1 /* 2 * sfereg.h: SiS900/DP83815 register definition 3 * 4 * Copyright (c) 2002-2007 Masayuki Murayama. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3. Neither the name of the author nor the names of its contributors may be 17 * used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 24 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 31 * DAMAGE. 32 */ 33 34 #pragma ident "%Z%%M% %I% %E% SMI" /* sfe device driver */ 35 36 #ifndef _SFEREG_H_ 37 #define _SFEREG_H_ 38 /* 39 * Tx/Rx descriptor 40 */ 41 struct sfe_desc { 42 volatile uint32_t d_link; /* link to the next */ 43 volatile uint32_t d_cmdsts; /* command/status field */ 44 volatile uint32_t d_bufptr; /* ptr to the first fragment */ 45 }; 46 47 /* CMDSTS common Bit Definition */ 48 #define CMDSTS_OWN 0x80000000U /* 1: data consumer owns */ 49 #define CMDSTS_MORE 0x40000000U /* Not the last descriptor */ 50 #define CMDSTS_INTR 0x20000000U 51 #define CMDSTS_SUPCRC 0x10000000U 52 #define CMDSTS_INCCRC CMDSTS_SUPCRC 53 #define CMDSTS_OK 0x08000000U /* Packet is OK */ 54 #define CMDSTS_SIZE 0x00000fffU /* Descriptor byte count */ 55 56 /* Transmit Status Bit Definition */ 57 #define CMDSTS_TXA 0x04000000U /* Transmit abort */ 58 #define CMDSTS_TFU 0x02000000U /* Transmit FIFO Underrun */ 59 #define CMDSTS_CRS 0x01000000U /* Carrier sense lost */ 60 #define CMDSTS_TD 0x00800000U /* Transmit deferred */ 61 #define CMDSTS_ED 0x00400000U /* Exessive deferrral */ 62 #define CMDSTS_OWC 0x00200000U /* Out of window collision */ 63 #define CMDSTS_EC 0x00100000U /* Excessive collision */ 64 #define CMDSTS_CCNT 0x000f0000U /* Collision count */ 65 #define CMDSTS_CCNT_SHIFT (16) 66 #define CCNT_MASK 0xfU /* Collision count mask */ 67 68 #define TXSTAT_BITS \ 69 "\020" \ 70 "\040Own" \ 71 "\037More" \ 72 "\036Intr" \ 73 "\035SupCrc" \ 74 "\034Ok" \ 75 "\033Abort" \ 76 "\032UnderRun" \ 77 "\031NoCarrier" \ 78 "\030Deferd" \ 79 "\027ExcDefer" \ 80 "\026OWColl" \ 81 "\025ExcColl" 82 83 #define RXSTAT_BITS \ 84 "\020" \ 85 "\040Own" \ 86 "\037More" \ 87 "\036Intr" \ 88 "\035IncCrc" \ 89 "\034Ok" \ 90 "\032OverRun" \ 91 "\031MCast" \ 92 "\030UniMatch" \ 93 "\027TooLong" \ 94 "\026Runt" \ 95 "\025RxISErr" \ 96 "\024CrcErr" \ 97 "\023FaErr" \ 98 "\022LoopBk" \ 99 "\021RxCol" 100 101 102 /* Receive Status Bit Definitions */ 103 #define CMDSTS_RXA 0x04000000U /* Receive abort */ 104 #define CMDSTS_RXO 0x02000000U /* Receive overrun */ 105 #define CMDSTS_DEST 0x01800000U /* Destination class */ 106 #define CMDSTS_DEST_SHIFT 23 /* Destination class */ 107 #define DEST_REJECT 0U 108 #define DEST_NODE 1U 109 #define DEST_MULTI 2U 110 #define DEST_BROAD 3U 111 #define CMDSTS_LONG 0x00400000U /* Too long packet received */ 112 #define CMDSTS_RUNT 0x00200000U /* Runt packet received */ 113 #define CMDSTS_ISE 0x00100000U /* Invalid symbol error */ 114 #define CMDSTS_CRCE 0x00080000U /* CRC error */ 115 #define CMDSTS_FAE 0x00040000U /* Frame alignment */ 116 #define CMDSTS_LBP 0x00020000U /* Loopback packet */ 117 #define CMDSTS_COL 0x00010000U /* Collision activety */ 118 119 /* 120 * Offsets of MAC Operational Registers 121 */ 122 #define CR 0x00 /* Command register */ 123 #define CFG 0x04 /* Configuration register */ 124 #define EROMAR 0x08 /* EEPROM access register */ 125 #define MEAR 0x08 /* alias for MII access register (sis900) */ 126 #define PTSCR 0x0c /* PCI test control register */ 127 #define ISR 0x10 /* Interrupt status register */ 128 #define IMR 0x14 /* Interrupt mask register */ 129 #define IER 0x18 /* Interrupt enable register */ 130 #define ENPHY 0x1c /* Enhanced PHY access register */ 131 #define TXDP 0x20 /* Transmit descriptor pointer reg */ 132 #define TXCFG 0x24 /* Transmit configuration register */ 133 #define RXDP 0x30 /* Receive descriptor pointer reg */ 134 #define RXCFG 0x34 /* Receive configration register */ 135 #define FLOWCTL 0x38 /* Flow control register (sis900) */ 136 #define CCSR 0x3c /* Clock run status register (dp83815) */ 137 #define PCR 0x44 /* Pause control register (dp83815) */ 138 #define RFCR 0x48 /* Receive filter control register */ 139 #define RFDR 0x4c /* Receive filter data register */ 140 #define SRR 0x58 /* silicon revision register */ 141 #define MII_REGS_BASE 0x80 /* DP83815 only */ 142 #define PMCTL 0xb0 /* Power management control register */ 143 #define PMEVT 0xb4 /* Power management wake-up event reg */ 144 #define WAKECRC 0xbc /* Wake-up sample frame CRC register */ 145 #define WAKEMASK 0xc0 /* Wake-up sample frame mask register */ 146 147 148 /* Command register */ 149 #define CR_RELOAD 0x0400U /* reload mac address */ 150 #define CR_ACCESSMODE 0x0200U /* mii access mode */ 151 #define CR_RST 0x0100U /* Reset */ 152 #define CR_SWI 0x0080U /* Software interrupt */ 153 #define CR_RXR 0x0020U /* Receiver reset */ 154 #define CR_TXR 0x0010U /* Transmit reset */ 155 #define CR_RXD 0x0008U /* Receiver disable */ 156 #define CR_RXE 0x0004U /* Receiver enable */ 157 #define CR_TXD 0x0002U /* Transmit disable */ 158 #define CR_TXE 0x0001U /* Transmit enable */ 159 160 #define CR_BITS \ 161 "\020" \ 162 "\011Reset" \ 163 "\010SWI" \ 164 "\006RxReset" \ 165 "\005TxReset" \ 166 "\004RxDisable" \ 167 "\003RxEnable" \ 168 "\002TxDisable" \ 169 "\001TxEnable" 170 171 /* Configration register */ 172 #define CFG_LNKSTS 0x80000000U /* Link up (83815) */ 173 #define CFG_SPEED100 0x40000000U /* 100Mbps (83815) */ 174 #define CFG_FDUP 0x20000000U /* full duplex (83815) */ 175 #define CFG_POL 0x10000000U /* 10Mbps polarity indication (83815) */ 176 #define CFG_ANEG_DN 0x08000000U /* auto negotiation done (83815) */ 177 #define CFG_PHY_CFG 0x00fc0000U /* internal PHY configuration (83815) */ 178 #define CFG_PINT_ACEN 0x00020000U /* PHY interrupt auto clear (83815) */ 179 #define CFG_PAUSE_ADV 0x00010000U /* Advertise pause (83815) */ 180 #define CFG_ANEG_SEL 0x0000e000U /* Auto-nego default (83815) */ 181 #define CFG_EDB_MASTER 0x00002000U /* sis635, sis900B, sis96x */ 182 #define CFG_EXT_PHY 0x00001000U /* External PHY support (83815) */ 183 #define CFG_PHY_RST 0x00000400U /* Internal PHY reset (83815) */ 184 #define CFG_RND_CNT 0x00000400U /* sis635 & 900B */ 185 #define CFG_PHY_DIS 0x00000200U /* Internal PHY disable (83815) */ 186 #define CFG_FAIR_BCKOFF 0x00000200U /* sis635 & 900B */ 187 #define CFG_EUPHCOMP 0x00000100U /* DP83810 compatibility (83815) */ 188 #define CFG_DESCRFMT 0x00000100U /* sis7016 */ 189 #define CFG_REQALG 0x00000080U /* PCI Bus request algorithm */ 190 #define CFG_SB 0x00000040U /* Single backoff */ 191 #define CFG_POW 0x00000020U /* Program out of window timer */ 192 #define CFG_EXD 0x00000010U /* Excessive deferral timer disable */ 193 #define CFG_PESEL 0x00000008U /* Parity error detection action */ 194 #define CFG_BROM_DIS 0x00000004U /* BootRom disable (83815) */ 195 #define CFG_BEM 0x00000001U /* Big endian mode */ 196 197 #define CFG_BITS_DP83815 \ 198 "\020" \ 199 "\040CFG_LNKSTS" \ 200 "\037SPEED100" \ 201 "\036FDUP" \ 202 "\035POL" \ 203 "\034ANEG_DN" \ 204 "\022PINT_ACEN" \ 205 "\021PAUSE_ADV" \ 206 "\015EXT_PHY" \ 207 "\013PHY_RST" \ 208 "\012PHY_DIS" \ 209 "\011EUPHCOMP" \ 210 "\010REQALG" \ 211 "\007SB" \ 212 "\006POW" \ 213 "\005EXD" \ 214 "\004PESEL" \ 215 "\003BROM_DIS" \ 216 "\001BEM" 217 218 #define CFG_BITS_SIS900 \ 219 "\020" \ 220 "\016EDB_EN" \ 221 "\013RND_CNT" \ 222 "\010REQALG" \ 223 "\007SB" \ 224 "\006POW" \ 225 "\005EXD" \ 226 "\004PESEL" \ 227 "\001BEM" 228 229 /* Serial EEPROM access register */ 230 #define EROMAR_EECS 0x00000008U /* EEPROM chip select */ 231 #define EROMAR_EESK 0x00000004U /* EEPROM serial clock */ 232 #define EROMAR_EEDO 0x00000002U /* EEPROM data out */ 233 #define EROMAR_EEDO_SHIFT 1 234 #define EROMAR_EEDI 0x00000001U /* EEPROM data in + */ 235 #define EROMAR_EEDI_SHIFT 0 236 #define EROMAR_EEREQ 0x00000400U /* for sis963 eeprom mamagement */ 237 #define EROMAR_EEDONE 0x00000200U /* for sis963 eeprom mamagement */ 238 #define EROMAR_EEGNT 0x00000100U /* for sis963 eeprom mamagement */ 239 240 #define MEAR_MDC 0x00000040U 241 #define MEAR_MDDIR 0x00000020U 242 #define MEAR_MDIO 0x00000010U 243 #define MEAR_MDIO_SHIFT 4 244 245 /* PCI Test Control register */ 246 #define DISCARD_TEST 0x40000000U /* Discard timer test mode */ 247 248 /* Interrupt status register */ 249 #define ISR_WAKEEVT 0x10000000U /* sis900 */ 250 #define ISR_PAUSE_END 0x08000000U /* sis900 */ 251 #define ISR_PAUSE_ST 0x04000000U /* sis900 */ 252 #define ISR_TXRCMP 0x02000000U 253 #define ISR_RXRCMP 0x01000000U 254 #define ISR_DPERR 0x00800000U /* Detected parity error */ 255 #define ISR_SSERR 0x00400000U /* Signaled system error */ 256 #define ISR_RMABT 0x00200000U /* Received master abort */ 257 #define ISR_RTABT 0x00100000U /* Received target abort */ 258 #define ISR_RXSOVR 0x00010000U /* Received status FIFO overrun */ 259 #define ISR_HIBERR 0x00008000U 260 #define ISR_SWI 0x00001000U 261 #define ISR_TXURN 0x00000400U 262 #define ISR_TXIDLE 0x00000200U 263 #define ISR_TXERR 0x00000100U 264 #define ISR_TXDESC 0x00000080U 265 #define ISR_TXOK 0x00000040U 266 #define ISR_RXORN 0x00000020U 267 #define ISR_RXIDLE 0x00000010U 268 #define ISR_RXEARLY 0x00000008U 269 #define ISR_RXERR 0x00000004U 270 #define ISR_RXDESC 0x00000002U 271 #define ISR_RXOK 0x00000001U 272 273 #define INTR_BITS \ 274 "\020" \ 275 "\035WakeEvt" \ 276 "\034PauseEnd" \ 277 "\033PauseST" \ 278 "\032TXRCMP" \ 279 "\031RXRCMP" \ 280 "\030DPErr" \ 281 "\027SSErr" \ 282 "\026RMAbt" \ 283 "\025RTAbt" \ 284 "\021RxSOVR" \ 285 "\020HIBErr" \ 286 "\015SWI" \ 287 "\013TxUrn" \ 288 "\012TxIdle" \ 289 "\011TxErr" \ 290 "\010TxDesc" \ 291 "\007TxOk" \ 292 "\006RxORN" \ 293 "\005RxIdle" \ 294 "\004RxEarly" \ 295 "\003RxErr" \ 296 "\002RxDesc" \ 297 "\001RxOk" 298 299 300 /* Interrupt enable reigster */ 301 #define IER_IE 0x00000001 /* Interrupt enable */ 302 303 /* Enhanced PHY acces register */ 304 #define ENPHY_DATA 0xffff0000U /* data */ 305 #define ENPHY_DATA_SHIFT 16 306 #define ENPHY_ADDR 0x0000f800U /* phy address */ 307 #define ENPHY_ADDR_SHIFT 11 308 #define ENPHY_OFFSET 0x000007c0U /* offset */ 309 #define ENPHY_OFFSET_SHIFT 6 310 #define ENPHY_RDCMD 0x00000020U /* read */ 311 #define ENPHY_ACCESS 0x00000010U /* busy */ 312 313 314 /* Transmit configuration register */ 315 #define TXCFG_CSI 0x80000000U /* carrier sense ignore */ 316 #define TXCFG_HBI 0x40000000U /* heart beat ignore */ 317 #define TXCFG_MLB 0x20000000U /* MAC loop back */ 318 #define TXCFG_ATP 0x10000000U /* Automatic transmit padding */ 319 #define TXCFG_MXDMA 0x00700000U /* max dma burst size */ 320 #define TXCFG_MXDMA_SHIFT 20 321 #define TXCFG_MXDMA_512 (0U << TXCFG_MXDMA_SHIFT) 322 #define TXCFG_MXDMA_4 (1U << TXCFG_MXDMA_SHIFT) 323 #define TXCFG_MXDMA_8 (2U << TXCFG_MXDMA_SHIFT) 324 #define TXCFG_MXDMA_16 (3U << TXCFG_MXDMA_SHIFT) 325 #define TXCFG_MXDMA_32 (4U << TXCFG_MXDMA_SHIFT) 326 #define TXCFG_MXDMA_64 (5U << TXCFG_MXDMA_SHIFT) 327 #define TXCFG_MXDMA_128 (6U << TXCFG_MXDMA_SHIFT) 328 #define TXCFG_MXDMA_256 (7U << TXCFG_MXDMA_SHIFT) 329 #define TXCFG_FLTH 0x00003f00U /* Tx fill threshold */ 330 #define TXCFG_FLTH_SHIFT 8 331 #define TXCFG_DRTH 0x0000003fU /* Tx drain threshold */ 332 333 #define TXFIFOSIZE 2048U 334 #define TXCFG_FIFO_UNIT 32U 335 336 #define TXCFG_BITS "\020\040CSI\037HBI\036MLB\035ATP" 337 338 /* RXCFG:43 Reveive configuration register */ 339 #define RXCFG_AEP 0x80000000U /* accept error packets */ 340 #define RXCFG_ARP 0x40000000U /* accept runt packets */ 341 #define RXCFG_ATX 0x10000000U /* accept transmit packets */ 342 #define RXCFG_AJAB 0x08000000U /* accept jabber packets */ 343 #define RXCFG_ALP_DP83815 0x08000000U /* accept long pakets */ 344 #define RXCFG_MXDMA 0x00700000U /* max dma burst size */ 345 #define RXCFG_MXDMA_SHIFT (20) 346 #define RXCFG_MXDMA_512 (0U << RXCFG_MXDMA_SHIFT) 347 #define RXCFG_MXDMA_4 (1U << RXCFG_MXDMA_SHIFT) 348 #define RXCFG_MXDMA_8 (2U << RXCFG_MXDMA_SHIFT) 349 #define RXCFG_MXDMA_16 (3U << RXCFG_MXDMA_SHIFT) 350 #define RXCFG_MXDMA_32 (4U << RXCFG_MXDMA_SHIFT) 351 #define RXCFG_MXDMA_64 (5U << RXCFG_MXDMA_SHIFT) 352 #define RXCFG_MXDMA_128 (6U << RXCFG_MXDMA_SHIFT) 353 #define RXCFG_MXDMA_256 (7U << RXCFG_MXDMA_SHIFT) 354 #define RXCFG_DRTH 0x0000003eU /* Rx drain threshold */ 355 #define RXCFG_DRTH_SHIFT 1 356 357 #define RXFIFOSIZE 2048U 358 #define RXCFG_FIFO_UNIT 8U 359 360 #define RXCFG_BITS "\020\040AEP\037ARP\035ATX\034AJAB" 361 362 363 /* FLWCRL:0x38 Flow Control register */ 364 #define FLOWCTL_PAUSE 0x00000002U /* PAUSE flag */ 365 #define FLOWCTL_FLOWEN 0x00000001U /* flow control enable */ 366 367 #define FLOWCTL_BITS "\020\002PAUSE\001FLOWEN" 368 369 /* CCSR:0x3c Clock run Control status register */ 370 #define CCSR_PMESTS 0x00008000U 371 #define CCSR_PMEEN 0x00000100U 372 #define CCSR_CLKRUN_EN 0x00000001U 373 374 /* PCR:0x44 Pause control/status register (DP83815) */ 375 #define PCR_PSEN 0x80000000U /* Pause Enable */ 376 #define PCR_PS_MCAST 0x40000000U /* Pause on multicast */ 377 #define PCR_PS_DA 0x20000000U /* Pause on DA */ 378 #define PCR_PS_ACT 0x00800000U /* Pause active */ 379 #define PCR_PS_RCVD 0x00400000U /* Pause frame receved */ 380 #define PCR_PSNEG 0x00200000U /* Pause negotiated */ 381 #define PCR_MLD_EN 0x00010000U /* Manual load enable */ 382 #define PCR_PAUSE_CNT 0x0000ffffU /* Pause counter value */ 383 384 #define PCR_BITS \ 385 "\020" \ 386 "\040PCR_PSEN" \ 387 "\037PCR_PS_MCAST" \ 388 "\036PCR_PS_DA" \ 389 "\030PCR_PS_ACT" \ 390 "\027PCR_PS_RCVD" \ 391 "\026PCR_PSNEG" \ 392 "\021PCR_MLD_EN" 393 394 /* RFCR:0x48 Receive filter control register */ 395 #define RFCR_RFEN 0x80000000U /* receive filter enable */ 396 #define RFCR_AAB 0x40000000U /* accept all broadcast */ 397 #define RFCR_AAM 0x20000000U /* accept all multicast */ 398 #define RFCR_AAP 0x10000000U /* accept all physical */ 399 #define RFCR_APM_DP83815 0x08000000U /* accept perfect match */ 400 #define RFCR_APAT_DP83815 0x07800000U /* accept on pattern match */ 401 #define RFCR_APAT_SHIFT 23 /* pattern match base */ 402 #define RFCR_AARP_DP83815 0x00400000U /* accept arp packets */ 403 #define RFCR_MHEN_DP83815 0x00200000U /* multicast hash enable */ 404 #define RFCR_UHEN_DP83815 0x00100000U /* unicast hash enable */ 405 #define RFCR_ULM_DP83815 0x00080000U /* U/L bit mask */ 406 #define RFCR_RFADDR_SIS900 0x000f0000U /* receive filter address */ 407 #define RFCR_RFADDR_SHIFT_SIS900 16 408 #define RFCR_RFADDR_DP83815 0x000003ffU 409 #define RFCR_RFADDR_SHIFT_DP83815 0 410 411 /* Receive filter offset */ 412 #define RFADDR_MAC_SIS900 0U 413 #define RFADDR_MULTICAST_SIS900 4U 414 415 #define RFADDR_MAC_DP83815 0x000U 416 #define RFADDR_PCOUNT01_DP83815 0x006U 417 #define RFADDR_PCOUNT23_DP83815 0x008U 418 #define RFADDR_MULTICAST_DP83815 0x200U 419 #define RFADDR_PMATCH0_DP83815 0x280U 420 #define RFADDR_PMATCH1_DP83815 0x282U 421 #define RFADDR_PMATCH2_DP83815 0x300U 422 #define RFADDR_PMATCH3_DP83815 0x302U 423 424 /* Receive filter data register */ 425 426 /* dp83815 Silicon revision register */ 427 #define SRR_REV 0x0000ffffU 428 #define SRR_REV_DP83815CVNG 0x0302U 429 #define SRR_REV_DP83815DVNG 0x0403U 430 #define SRR_REV_DP83816AVNG 0x0505U 431 432 /* sis900 revisions */ 433 #define SIS630A_900_REV 0x80 434 #define SIS630E_900_REV 0x81 435 #define SIS630S_900_REV 0x82 436 #define SIS630EA1_900_REV 0x83 437 #define SIS630ET_900_REV 0x84 438 #define SIS635A_900_REV 0x90 439 #define SIS962_900_REV 0X91 440 #define SIS900B_900_REV 0x03 441 442 #define SIS630A0 0x00 443 #define SIS630A1 0x01 444 #define SIS630B0 0x10 445 #define SIS630B1 0x11 446 447 448 #endif /* _SFEREG_H_ */ 449