1 /* 2 * sfe_mii.h: mii header for gem 3 * 4 * Copyright (c) 2002-2007 Masayuki Murayama. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3. Neither the name of the author nor the names of its contributors may be 17 * used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 24 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 31 * DAMAGE. 32 */ 33 34 /* 35 * sfe_mii.h : MII registers 36 */ 37 #ifndef _SFE_MII_H_ 38 #define _SFE_MII_H_ 39 40 #include <sys/miiregs.h> 41 42 #define MII_AN_LPANXT 8 43 #define MII_MS_CONTROL 9 44 #define MII_MS_STATUS 10 45 #define MII_XSTATUS 15 46 47 /* for 1000BaseT support */ 48 #define MII_1000TC MII_MS_CONTROL 49 #define MII_1000TS MII_MS_STATUS 50 #define MII_CONTROL_SPEED 0x2040 51 52 #define MII_CONTROL_10MB 0x0000 53 #define MII_CONTROL_1000MB 0x0040 54 55 #define MII_CONTROL_BITS \ 56 "\020" \ 57 "\020RESET" \ 58 "\017LOOPBACK" \ 59 "\016100MB" \ 60 "\015ANE" \ 61 "\014PWRDN" \ 62 "\013ISOLATE" \ 63 "\012RSAN" \ 64 "\011FDUPLEX" \ 65 "\010COLTST" \ 66 "\0071000M" 67 #define MII_STATUS_XSTATUS 0x0100 68 #define MII_STATUS_100_BASE_T2_FD 0x0400 69 #define MII_STATUS_100_BASE_T2 0x0200 70 71 #define MII_STATUS_ABILITY_TECH \ 72 (MII_STATUS_100_BASE_T4 | \ 73 MII_STATUS_100_BASEX_FD | \ 74 MII_STATUS_100_BASEX | \ 75 MII_STATUS_10 | \ 76 MII_STATUS_10_FD) 77 78 79 #define MII_STATUS_BITS \ 80 "\020" \ 81 "\020100_BASE_T4" \ 82 "\017100_BASEX_FD" \ 83 "\016100_BASEX" \ 84 "\01510_BASE_FD" \ 85 "\01410_BASE" \ 86 "\013100_BASE_T2_FD" \ 87 "\012100_BASE_T2" \ 88 "\011XSTATUS" \ 89 "\007MFPRMBLSUPR" \ 90 "\006ANDONE" \ 91 "\005REMFAULT" \ 92 "\004CANAUTONEG" \ 93 "\003LINKUP" \ 94 "\002JABBERING" \ 95 "\001EXTENDED" 96 97 #define MII_ABILITY_ASM_DIR 0x0800 /* for annex 28B */ 98 #define MII_ABILITY_PAUSE 0x0400 /* for IEEE 802.3x */ 99 100 #define MII_AN_LPABLE_NP 0x8000 101 102 #define MII_ABILITY_TECH \ 103 (MII_ABILITY_100BASE_T4 | \ 104 MII_ABILITY_100BASE_TX_FD | \ 105 MII_ABILITY_100BASE_TX | \ 106 MII_ABILITY_10BASE_T | \ 107 MII_ABILITY_10BASE_T_FD) 108 109 #define MII_ABILITY_ALL \ 110 (MII_AN_ADVERT_REMFAULT | \ 111 MII_ABILITY_ASM_DIR | \ 112 MII_ABILITY_PAUSE | \ 113 MII_ABILITY_TECH) 114 115 116 #define MII_ABILITY_BITS \ 117 "\020" \ 118 "\016REMFAULT" \ 119 "\014ASM_DIR" \ 120 "\013PAUSE" \ 121 "\012100BASE_T4" \ 122 "\011100BASE_TX_FD" \ 123 "\010100BASE_TX" \ 124 "\00710BASE_T_FD" \ 125 "\00610BASE_T" 126 127 #define MII_AN_EXP_BITS \ 128 "\020" \ 129 "\005PARFAULT" \ 130 "\004LPCANNXTP" \ 131 "\003CANNXTPP" \ 132 "\002PAGERCVD" \ 133 "\001LPCANAN" 134 135 #define MII_1000TC_TESTMODE 0xe000 136 #define MII_1000TC_CFG_EN 0x1000 137 #define MII_1000TC_CFG_VAL 0x0800 138 #define MII_1000TC_PORTTYPE 0x0400 139 #define MII_1000TC_ADV_FULL 0x0200 140 #define MII_1000TC_ADV_HALF 0x0100 141 142 #define MII_1000TC_BITS \ 143 "\020" \ 144 "\015CFG_EN" \ 145 "\014CFG_VAL" \ 146 "\013PORTTYPE" \ 147 "\012FULL" \ 148 "\011HALF" 149 150 #define MII_1000TS_CFG_FAULT 0x8000 151 #define MII_1000TS_CFG_MASTER 0x4000 152 #define MII_1000TS_LOCALRXOK 0x2000 153 #define MII_1000TS_REMOTERXOK 0x1000 154 #define MII_1000TS_LP_FULL 0x0800 155 #define MII_1000TS_LP_HALF 0x0400 156 157 #define MII_1000TS_BITS \ 158 "\020" \ 159 "\020CFG_FAULT" \ 160 "\017CFG_MASTER" \ 161 "\014CFG_LOCALRXOK" \ 162 "\013CFG_REMOTERXOK" \ 163 "\012LP_FULL" \ 164 "\011LP_HALF" 165 166 #define MII_XSTATUS_1000BASEX_FD 0x8000 167 #define MII_XSTATUS_1000BASEX 0x4000 168 #define MII_XSTATUS_1000BASET_FD 0x2000 169 #define MII_XSTATUS_1000BASET 0x1000 170 171 #define MII_XSTATUS_BITS \ 172 "\020" \ 173 "\0201000BASEX_FD" \ 174 "\0171000BASEX" \ 175 "\0161000BASET_FD" \ 176 "\0151000BASET" 177 178 #define MII_READ_CMD(p, r) \ 179 ((6<<(18+5+5)) | ((p)<<(18+5)) | ((r)<<18)) 180 181 #define MII_WRITE_CMD(p, r, v) \ 182 ((5<<(18+5+5)) | ((p)<<(18+5)) | ((r)<<18) | (2 << 16) | (v)) 183 184 #endif /* _SFE_MII_H_ */ 185