1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * rtls -- REALTEK 8139-serials PCI Fast Ethernet Driver, Depends on the 29 * Generic LAN Driver utility functions in /kernel/misc/mac 30 * 31 * This product is covered by one or more of the following patents: 32 * US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and 33 * US6,327,625. 34 * 35 * Currently supports: 36 * RTL8139 37 */ 38 39 #include <sys/types.h> 40 #include <sys/debug.h> 41 #include <sys/errno.h> 42 43 #include <sys/stropts.h> 44 #include <sys/stream.h> 45 #include <sys/kmem.h> 46 #include <sys/conf.h> 47 #include <sys/ddi.h> 48 #include <sys/devops.h> 49 #include <sys/ksynch.h> 50 #include <sys/stat.h> 51 #include <sys/conf.h> 52 #include <sys/modctl.h> 53 #include <sys/dlpi.h> 54 #include <sys/ethernet.h> 55 #include <sys/vlan.h> 56 #include <sys/strsun.h> 57 #include <sys/pci.h> 58 #include <sys/sunddi.h> 59 #include <sys/mac_provider.h> 60 #include <sys/mac_ether.h> 61 62 #include "rtls.h" 63 64 /* 65 * Declarations and Module Linkage 66 */ 67 68 /* 69 * This is the string displayed by modinfo, etc. 70 */ 71 static char rtls_ident[] = "RealTek 8139 Ethernet driver"; 72 73 #ifdef RTLS_DEBUG 74 int rtls_debug = 0; 75 #endif 76 77 /* 78 * Required system entry points 79 */ 80 static int rtls_attach(dev_info_t *, ddi_attach_cmd_t); 81 static int rtls_detach(dev_info_t *, ddi_detach_cmd_t); 82 static int rtls_quiesce(dev_info_t *); 83 84 /* 85 * Required driver entry points for MAC 86 */ 87 static int rtls_m_start(void *); 88 static void rtls_m_stop(void *); 89 static int rtls_m_unicst(void *, const uint8_t *); 90 static int rtls_m_multicst(void *, boolean_t, const uint8_t *); 91 static int rtls_m_promisc(void *, boolean_t); 92 static mblk_t *rtls_m_tx(void *, mblk_t *); 93 static int rtls_m_stat(void *, uint_t, uint64_t *); 94 95 static uint_t rtls_intr(caddr_t); 96 97 /* 98 * Internal functions used by the above entry points 99 */ 100 static int rtls_chip_reset(rtls_t *, boolean_t); 101 static void rtls_chip_init(rtls_t *); 102 static void rtls_chip_stop(rtls_t *rtlsp); 103 static void rtls_chip_start(rtls_t *rtlsp); 104 static void rtls_chip_restart(rtls_t *rtlsp); 105 static void rtls_get_mac_addr(rtls_t *, uint8_t *); 106 static void rtls_set_mac_addr(rtls_t *, const uint8_t *); 107 static uint_t rtls_hash_index(const uint8_t *); 108 static boolean_t rtls_send(rtls_t *, mblk_t *); 109 static void rtls_receive(rtls_t *); 110 static void rtls_periodic(void *); 111 static uint_t rtls_reschedule(caddr_t arg); 112 static uint_t rtls_events(caddr_t arg); 113 static void rtls_chip_force_speed_duplex(rtls_t *); 114 115 /* 116 * Buffer Management Routines 117 */ 118 static int rtls_alloc_bufs(rtls_t *); 119 static void rtls_free_bufs(rtls_t *); 120 static int rtls_alloc_dma_mem(rtls_t *, size_t, ddi_device_acc_attr_t *, 121 uint_t, dma_area_t *); 122 static void rtls_free_dma_mem(dma_area_t *); 123 124 #ifdef RTLS_DEBUG 125 static void rtls_reg_print(rtls_t *); /* debug routine */ 126 #endif 127 128 #define RTLS_DRIVER_NAME "rtls" 129 130 /* 131 * Used for buffers allocated by ddi_dma_mem_alloc() 132 */ 133 static ddi_dma_attr_t dma_attr = { 134 DMA_ATTR_V0, /* dma_attr version */ 135 0, /* dma_attr_addr_lo */ 136 (uint_t)0xFFFFFFFF, /* dma_attr_addr_hi */ 137 0x7FFFFFFF, /* dma_attr_count_max */ 138 4, /* dma_attr_align */ 139 0x3F, /* dma_attr_burstsizes */ 140 1, /* dma_attr_minxfer */ 141 (uint_t)0xFFFFFFFF, /* dma_attr_maxxfer */ 142 (uint_t)0xFFFFFFFF, /* dma_attr_seg */ 143 1, /* dma_attr_sgllen */ 144 1, /* dma_attr_granular */ 145 0, /* dma_attr_flags */ 146 }; 147 148 /* 149 * PIO access attributes for registers 150 */ 151 static ddi_device_acc_attr_t rtls_reg_accattr = { 152 DDI_DEVICE_ATTR_V0, 153 DDI_STRUCTURE_LE_ACC, 154 DDI_STRICTORDER_ACC 155 }; 156 157 /* 158 * DMA access attributes for data 159 */ 160 static ddi_device_acc_attr_t rtls_buf_accattr = { 161 DDI_DEVICE_ATTR_V0, 162 DDI_NEVERSWAP_ACC, 163 DDI_STRICTORDER_ACC 164 }; 165 166 uchar_t rtls_broadcastaddr[] = { 167 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 168 }; 169 170 static mac_callbacks_t rtls_m_callbacks = { 171 0, 172 rtls_m_stat, 173 rtls_m_start, 174 rtls_m_stop, 175 rtls_m_promisc, 176 rtls_m_multicst, 177 rtls_m_unicst, 178 rtls_m_tx, 179 NULL, /* mc_resources */ 180 NULL, /* mc_ioctl */ 181 NULL /* mc_getcapab */ 182 }; 183 184 DDI_DEFINE_STREAM_OPS(rtls_dev_ops, nulldev, nulldev, rtls_attach, rtls_detach, 185 nodev, NULL, D_MP, NULL, rtls_quiesce); 186 187 /* 188 * Standard module linkage initialization for a MAC driver 189 */ 190 static struct modldrv rtls_modldrv = { 191 &mod_driverops, /* type of module. This one is a driver */ 192 rtls_ident, /* short description */ 193 &rtls_dev_ops /* driver specific ops */ 194 }; 195 196 static struct modlinkage modlinkage = { 197 MODREV_1, { (void *)&rtls_modldrv, NULL } 198 }; 199 200 /* Save ForceSpeedDuplex value for instances in rtls.conf file */ 201 #define RTLS_MAX_DEVICES 256 202 static uint_t rtls_link_mode[RTLS_MAX_DEVICES]; 203 204 /* 205 * ========== RealTek chip register access Routines ========== 206 */ 207 static uint8_t rtls_reg_get8(rtls_t *rtlsp, uint32_t reg); 208 #pragma inline(rtls_reg_get8) 209 static uint8_t 210 rtls_reg_get8(rtls_t *rtlsp, uint32_t reg) 211 { 212 uint8_t *addr; 213 214 addr = REG8(rtlsp->io_reg, reg); 215 return (ddi_get8(rtlsp->io_handle, addr)); 216 } 217 218 static uint16_t rtls_reg_get16(rtls_t *rtlsp, uint32_t reg); 219 #pragma inline(rtls_reg_get16) 220 static uint16_t 221 rtls_reg_get16(rtls_t *rtlsp, uint32_t reg) 222 { 223 uint16_t *addr; 224 225 addr = REG16(rtlsp->io_reg, reg); 226 return (ddi_get16(rtlsp->io_handle, addr)); 227 } 228 229 static uint32_t rtls_reg_get32(rtls_t *rtlsp, uint32_t reg); 230 #pragma inline(rtls_reg_get32) 231 static uint32_t 232 rtls_reg_get32(rtls_t *rtlsp, uint32_t reg) 233 { 234 uint32_t *addr; 235 236 addr = REG32(rtlsp->io_reg, reg); 237 return (ddi_get32(rtlsp->io_handle, addr)); 238 } 239 240 static void rtls_reg_set8(rtls_t *rtlsp, uint32_t reg, uint8_t value); 241 #pragma inline(rtls_reg_set8) 242 static void 243 rtls_reg_set8(rtls_t *rtlsp, uint32_t reg, uint8_t value) 244 { 245 uint8_t *addr; 246 247 addr = REG8(rtlsp->io_reg, reg); 248 ddi_put8(rtlsp->io_handle, addr, value); 249 } 250 251 static void rtls_reg_set16(rtls_t *rtlsp, uint32_t reg, uint16_t value); 252 #pragma inline(rtls_reg_set16) 253 static void 254 rtls_reg_set16(rtls_t *rtlsp, uint32_t reg, uint16_t value) 255 { 256 uint16_t *addr; 257 258 addr = REG16(rtlsp->io_reg, reg); 259 ddi_put16(rtlsp->io_handle, addr, value); 260 } 261 262 static void rtls_reg_set32(rtls_t *rtlsp, uint32_t reg, uint32_t value); 263 #pragma inline(rtls_reg_set32) 264 static void 265 rtls_reg_set32(rtls_t *rtlsp, uint32_t reg, uint32_t value) 266 { 267 uint32_t *addr; 268 269 addr = REG32(rtlsp->io_reg, reg); 270 ddi_put32(rtlsp->io_handle, addr, value); 271 } 272 273 /* 274 * ========== Module Loading Entry Points ========== 275 */ 276 int 277 _init(void) 278 { 279 int rv; 280 281 mac_init_ops(&rtls_dev_ops, RTLS_DRIVER_NAME); 282 if ((rv = mod_install(&modlinkage)) != DDI_SUCCESS) { 283 mac_fini_ops(&rtls_dev_ops); 284 } 285 return (rv); 286 } 287 288 int 289 _fini(void) 290 { 291 int rv; 292 293 if ((rv = mod_remove(&modlinkage)) == DDI_SUCCESS) { 294 mac_fini_ops(&rtls_dev_ops); 295 } 296 return (rv); 297 } 298 299 int 300 _info(struct modinfo *modinfop) 301 { 302 return (mod_info(&modlinkage, modinfop)); 303 } 304 305 306 /* 307 * ========== DDI Entry Points ========== 308 */ 309 310 /* 311 * attach(9E) -- Attach a device to the system 312 * 313 * Called once for each board successfully probed. 314 */ 315 static int 316 rtls_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 317 { 318 rtls_t *rtlsp; /* Our private device info */ 319 ddi_acc_handle_t pci_handle; 320 uint16_t pci_commond; 321 uint16_t vendorid; 322 uint16_t deviceid; 323 uint32_t device; 324 mac_register_t *macp; 325 int err; 326 327 switch (cmd) { 328 case DDI_ATTACH: 329 break; 330 case DDI_RESUME: 331 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) { 332 return (DDI_FAILURE); 333 } 334 mutex_enter(&rtlsp->rtls_io_lock); 335 mutex_enter(&rtlsp->rtls_rx_lock); 336 mutex_enter(&rtlsp->rtls_tx_lock); 337 /* 338 * Turn on Master Enable (DMA) and IO Enable bits. 339 * Enable PCI Memory Space accesses 340 * Disable Memory Write/Invalidate 341 */ 342 if (pci_config_setup(devinfo, &pci_handle) != DDI_SUCCESS) { 343 mutex_exit(&rtlsp->rtls_tx_lock); 344 mutex_exit(&rtlsp->rtls_rx_lock); 345 mutex_exit(&rtlsp->rtls_io_lock); 346 return (DDI_FAILURE); 347 } 348 pci_commond = pci_config_get16(pci_handle, PCI_CONF_COMM); 349 pci_commond &= ~PCI_COMM_MEMWR_INVAL; 350 pci_commond |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 351 pci_config_put32(pci_handle, PCI_CONF_COMM, pci_commond); 352 pci_config_teardown(&pci_handle); 353 354 rtls_chip_restart(rtlsp); 355 rtlsp->chip_error = B_FALSE; 356 rtlsp->tx_retry = 0; 357 rtlsp->rtls_suspended = B_FALSE; 358 mutex_exit(&rtlsp->rtls_tx_lock); 359 mutex_exit(&rtlsp->rtls_rx_lock); 360 mutex_exit(&rtlsp->rtls_io_lock); 361 362 mac_tx_update(rtlsp->mh); 363 return (DDI_SUCCESS); 364 default: 365 return (DDI_FAILURE); 366 } 367 368 /* 369 * we don't support high level interrupts in the driver 370 */ 371 if (ddi_intr_hilevel(devinfo, 0) != 0) { 372 cmn_err(CE_WARN, 373 "rtls_attach -- unsupported high level interrupt"); 374 return (DDI_FAILURE); 375 } 376 377 /* 378 * Get handle to access pci configuration space 379 */ 380 if (pci_config_setup(devinfo, &pci_handle) != DDI_SUCCESS) { 381 cmn_err(CE_WARN, "rtls_attach -- pci_config_setup fail."); 382 return (DDI_FAILURE); 383 } 384 385 /* 386 * Make sure we support this particular vendor/device 387 */ 388 vendorid = pci_config_get16(pci_handle, PCI_CONF_VENID); 389 deviceid = pci_config_get16(pci_handle, PCI_CONF_DEVID); 390 device = vendorid; 391 device = (device << 16) | deviceid; /* combine two id together */ 392 393 #ifdef RTLS_DEBUG 394 cmn_err(CE_NOTE, 395 "rtls_attach: vendorID = 0x%x, deviceID = 0x%x", 396 vendorid, deviceid); 397 #endif 398 399 /* 400 * See if we support this device 401 * We do not return for wrong device id. It's user risk. 402 */ 403 switch (device) { 404 default: 405 cmn_err(CE_WARN, 406 "RTLS don't support this device: " 407 "vendorID = 0x%x, deviceID = 0x%x", 408 vendorid, deviceid); 409 break; 410 case RTLS_SUPPORT_DEVICE_1: 411 case RTLS_SUPPORT_DEVICE_2: 412 case RTLS_SUPPORT_DEVICE_3: 413 break; 414 } 415 416 #ifdef RTLS_OEM 417 /* 418 * RealTek required macro 419 */ 420 if ((vendorid != RT_VENDOR_ID) || (deviceid != RT_DEVICE_8139)) { 421 cmn_err(CE_WARN, 422 "rtls_attach -- wrong OEM device: " 423 "vendorID = 0x%x, deviceID = 0x%x", 424 vendorid, deviceid); 425 pci_config_teardown(&pci_handle); 426 return (DDI_FAILURE); 427 } 428 #endif 429 /* 430 * Turn on Master Enable (DMA) and IO Enable bits. 431 * Enable PCI Memory Space accesses 432 * Disable Memory Write/Invalidate 433 */ 434 pci_commond = pci_config_get16(pci_handle, PCI_CONF_COMM); 435 pci_commond &= ~PCI_COMM_MEMWR_INVAL; 436 pci_commond |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 437 pci_config_put32(pci_handle, PCI_CONF_COMM, pci_commond); 438 439 /* 440 * Free handle to access pci configuration space 441 */ 442 pci_config_teardown(&pci_handle); 443 444 rtlsp = kmem_zalloc(sizeof (rtls_t), KM_SLEEP); 445 if (rtlsp == NULL) { 446 cmn_err(CE_WARN, "rtls_attach -- rtls_t alloc fail."); 447 return (DDI_FAILURE); 448 } 449 450 ddi_set_driver_private(devinfo, rtlsp); 451 rtlsp->devinfo = devinfo; 452 rtlsp->instance = ddi_get_instance(devinfo); 453 454 /* 455 * Map operating register 456 */ 457 err = ddi_regs_map_setup(devinfo, 1, &rtlsp->io_reg, 458 (offset_t)0, 0, &rtls_reg_accattr, &rtlsp->io_handle); 459 if (err != DDI_SUCCESS) { 460 kmem_free((caddr_t)rtlsp, sizeof (rtls_t)); 461 cmn_err(CE_WARN, "rtls_attach -- ddi_regs_map_setup fail."); 462 return (DDI_FAILURE); 463 } 464 465 /* 466 * Allocate the TX and RX descriptors/buffers 467 */ 468 if (rtls_alloc_bufs(rtlsp) == DDI_FAILURE) { 469 cmn_err(CE_WARN, "rtls_attach -- DMA buffer allocation fail."); 470 goto fail; 471 } 472 473 /* 474 * Reset the chip 475 */ 476 err = rtls_chip_reset(rtlsp, B_FALSE); 477 if (err != DDI_SUCCESS) 478 goto fail; 479 480 /* 481 * Init rtls_t structure 482 */ 483 rtls_get_mac_addr(rtlsp, rtlsp->netaddr); 484 485 /* 486 * Add the softint handlers: 487 * 488 * Both of these handlers are used to avoid restrictions on the 489 * context and/or mutexes required for some operations. In 490 * particular, the hardware interrupt handler and its subfunctions 491 * can detect a number of conditions that we don't want to handle 492 * in that context or with that set of mutexes held. So, these 493 * softints are triggered instead: 494 * 495 * the <rtls_reschedule> softint is triggered if we have previously 496 * had to refuse to send a packet because of resource shortage 497 * (we've run out of transmit descriptors),Its only purpose is to 498 * call mac_tx_update() to retry the pending transmits (we're not 499 * allowed to hold driver-defined mutexes across mac_tx_update()). 500 * 501 * the <rtls_events> is triggered if the h/w interrupt handler 502 * sees the <link state changed>. 503 */ 504 if (ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, &rtlsp->resched_id, 505 NULL, NULL, rtls_reschedule, (caddr_t)rtlsp) != DDI_SUCCESS) { 506 cmn_err(CE_WARN, "rtls_attach -- ddi_add_softintr 1 fail."); 507 goto fail; 508 } 509 510 if (ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, &rtlsp->events_id, 511 NULL, NULL, rtls_events, (caddr_t)rtlsp) != DDI_SUCCESS) { 512 cmn_err(CE_WARN, "rtls_attach -- ddi_add_softintr 2 fail."); 513 ddi_remove_softintr(rtlsp->resched_id); 514 goto fail; 515 } 516 517 /* 518 * Add the interrupt handler 519 * 520 * This will prevent receiving interrupts before device is ready, as 521 * we are initializing device after setting the interrupts. So we 522 * will not get our interrupt handler invoked by OS while our device 523 * is still coming up or timer routines will not start till we are 524 * all set to process... 525 */ 526 527 if (ddi_add_intr(devinfo, 0, &rtlsp->iblk, NULL, rtls_intr, 528 (caddr_t)rtlsp) != DDI_SUCCESS) { 529 cmn_err(CE_WARN, "rtls_attach -- ddi_add_intr fail."); 530 goto late_fail; 531 } 532 533 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 534 cmn_err(CE_WARN, "rtls_attach - mac_alloc fail."); 535 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 536 goto late_fail; 537 } 538 539 /* 540 * Init mutex 541 */ 542 mutex_init(&rtlsp->rtls_io_lock, NULL, MUTEX_DRIVER, rtlsp->iblk); 543 mutex_init(&rtlsp->rtls_tx_lock, NULL, MUTEX_DRIVER, rtlsp->iblk); 544 mutex_init(&rtlsp->rtls_rx_lock, NULL, MUTEX_DRIVER, rtlsp->iblk); 545 546 /* 547 * Initialize pointers to device specific functions which will be 548 * used by the generic layer. 549 */ 550 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 551 macp->m_driver = rtlsp; 552 macp->m_dip = devinfo; 553 macp->m_src_addr = rtlsp->netaddr; 554 macp->m_callbacks = &rtls_m_callbacks; 555 macp->m_min_sdu = 0; 556 macp->m_max_sdu = ETHERMTU; 557 macp->m_margin = VLAN_TAGSZ; 558 559 if (mac_register(macp, &rtlsp->mh) != 0) { 560 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 561 mutex_destroy(&rtlsp->rtls_io_lock); 562 mutex_destroy(&rtlsp->rtls_tx_lock); 563 mutex_destroy(&rtlsp->rtls_rx_lock); 564 goto late_fail; 565 } 566 567 mac_free(macp); 568 569 /* 570 * Add the periodic timer to check link state. We do this 571 * once a second, in case the link interrupt is missed (or not 572 * delivered -- qemu emulated 8139 devices don't deliver the 573 * link change interrupt.) This can run in ordinary kernel 574 * context. 575 */ 576 rtlsp->periodic_id = ddi_periodic_add(rtls_periodic, rtlsp, 577 1000000000U, 0); 578 ASSERT(rtlsp->periodic_id != NULL); /* API guarantee */ 579 580 return (DDI_SUCCESS); 581 582 late_fail: 583 if (macp) 584 mac_free(macp); 585 ddi_remove_softintr(rtlsp->resched_id); 586 ddi_remove_softintr(rtlsp->events_id); 587 588 fail: 589 ddi_regs_map_free(&rtlsp->io_handle); 590 rtls_free_bufs(rtlsp); 591 kmem_free(rtlsp, sizeof (rtls_t)); 592 593 return (DDI_FAILURE); 594 } 595 596 /* 597 * detach(9E) -- Detach a device from the system 598 */ 599 static int 600 rtls_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 601 { 602 rtls_t *rtlsp; /* our private device info */ 603 604 /* 605 * Get the driver private structure 606 */ 607 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) { 608 return (DDI_FAILURE); 609 } 610 611 switch (cmd) { 612 case DDI_DETACH: 613 break; 614 615 case DDI_SUSPEND: 616 mutex_enter(&rtlsp->rtls_io_lock); 617 mutex_enter(&rtlsp->rtls_rx_lock); 618 mutex_enter(&rtlsp->rtls_tx_lock); 619 620 rtlsp->rtls_suspended = B_TRUE; 621 rtls_chip_stop(rtlsp); 622 623 mutex_exit(&rtlsp->rtls_tx_lock); 624 mutex_exit(&rtlsp->rtls_rx_lock); 625 mutex_exit(&rtlsp->rtls_io_lock); 626 return (DDI_SUCCESS); 627 628 default: 629 return (DDI_FAILURE); 630 } 631 632 if (mac_unregister(rtlsp->mh) != 0) { 633 /* device busy */ 634 return (DDI_FAILURE); 635 } 636 637 ddi_periodic_delete(rtlsp->periodic_id); 638 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 639 640 ddi_remove_softintr(rtlsp->resched_id); 641 ddi_remove_softintr(rtlsp->events_id); 642 643 mutex_destroy(&rtlsp->rtls_io_lock); 644 mutex_destroy(&rtlsp->rtls_tx_lock); 645 mutex_destroy(&rtlsp->rtls_rx_lock); 646 647 ddi_regs_map_free(&rtlsp->io_handle); 648 rtls_free_bufs(rtlsp); 649 kmem_free(rtlsp, sizeof (rtls_t)); 650 651 return (DDI_SUCCESS); 652 } 653 654 /* 655 * quiesce(9E) entry point. 656 * 657 * This function is called when the system is single-threaded at high 658 * PIL with preemption disabled. Therefore, this function must not be 659 * blocked. 660 * 661 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 662 * DDI_FAILURE indicates an error condition and should almost never happen. 663 */ 664 static int 665 rtls_quiesce(dev_info_t *devinfo) 666 { 667 rtls_t *rtlsp; /* our private device info */ 668 669 /* 670 * Get the driver private structure 671 */ 672 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) { 673 return (DDI_FAILURE); 674 } 675 return (rtls_chip_reset(rtlsp, B_TRUE)); 676 } 677 678 /* 679 * ========== MAC Entry Points ========== 680 */ 681 682 /* 683 * rtls_m_start() -- start the board receiving and allow transmits 684 */ 685 static int 686 rtls_m_start(void *arg) 687 { 688 rtls_t *rtlsp = (rtls_t *)arg; 689 690 mutex_enter(&rtlsp->rtls_io_lock); 691 mutex_enter(&rtlsp->rtls_rx_lock); 692 mutex_enter(&rtlsp->rtls_tx_lock); 693 694 if (!rtlsp->rtls_suspended) 695 rtls_chip_restart(rtlsp); 696 697 rtlsp->rtls_running = B_TRUE; 698 699 mutex_exit(&rtlsp->rtls_tx_lock); 700 mutex_exit(&rtlsp->rtls_rx_lock); 701 mutex_exit(&rtlsp->rtls_io_lock); 702 703 return (0); 704 } 705 706 /* 707 * rtls_m_stop() -- stop board receiving and transmits 708 */ 709 static void 710 rtls_m_stop(void *arg) 711 { 712 rtls_t *rtlsp = (rtls_t *)arg; 713 714 mutex_enter(&rtlsp->rtls_io_lock); 715 716 if (!rtlsp->rtls_suspended) 717 rtls_chip_stop(rtlsp); 718 rtlsp->rtls_running = B_FALSE; 719 720 mutex_exit(&rtlsp->rtls_io_lock); 721 } 722 723 /* 724 * rtls_m_unicst() -- set the physical network address 725 * on the board 726 */ 727 static int 728 rtls_m_unicst(void *arg, const uint8_t *macaddr) 729 { 730 rtls_t *rtlsp = arg; 731 732 mutex_enter(&rtlsp->rtls_io_lock); 733 bcopy(macaddr, rtlsp->netaddr, ETHERADDRL); 734 if (!rtlsp->rtls_suspended) 735 rtls_set_mac_addr(rtlsp, rtlsp->netaddr); 736 mutex_exit(&rtlsp->rtls_io_lock); 737 return (0); 738 } 739 740 /* 741 * rtls_m_multicst() -- set(enable) or disable a multicast address 742 * 743 * Program the hardware to enable/disable the multicast address in "mcast". 744 */ 745 static int 746 rtls_m_multicst(void *arg, boolean_t enable, const uint8_t *mcast) 747 { 748 rtls_t *rtlsp = (rtls_t *)arg; 749 uint_t index; 750 uint32_t *hashp; 751 752 mutex_enter(&rtlsp->rtls_io_lock); 753 hashp = rtlsp->multi_hash; 754 index = rtls_hash_index(mcast); 755 /* index value is between 0 and 63 */ 756 757 #ifdef RTLS_DEBUG 758 if (rtls_debug & RTLS_REGCFG) { 759 cmn_err(CE_NOTE, 760 "%s: rtls_m_multicst: enable = %d, multi(%s), index=%d", 761 rtlsp->ifname, enable, ether_sprintf((void *)mcast), index); 762 } 763 #endif 764 if (enable) { 765 if (rtlsp->multicast_cnt[index]++) { 766 mutex_exit(&rtlsp->rtls_io_lock); 767 return (0); 768 } 769 hashp[index/32] |= 1<< (index % 32); 770 } else { 771 if (--rtlsp->multicast_cnt[index]) { 772 mutex_exit(&rtlsp->rtls_io_lock); 773 return (0); 774 } 775 hashp[index/32] &= ~(1<< (index % 32)); 776 } 777 778 /* 779 * Set multicast register 780 */ 781 if (!rtlsp->rtls_suspended) { 782 rtls_reg_set32(rtlsp, MULTICAST_0_REG, hashp[0]); 783 rtls_reg_set32(rtlsp, MULTICAST_4_REG, hashp[1]); 784 } 785 786 #ifdef RTLS_DEBUG 787 if (rtls_debug & RTLS_REGCFG) { 788 cmn_err(CE_NOTE, 789 "%s: rtls_m_multicst =>: hash0=0x%x, hash1=0x%x", 790 rtlsp->ifname, hashp[0], hashp[1]); 791 cmn_err(CE_NOTE, 792 "%s: rtls_m_multicst <=, hash0=0x%x, hash1=0x%x", 793 rtlsp->ifname, 794 rtls_reg_get32(rtlsp, MULTICAST_0_REG), 795 rtls_reg_get32(rtlsp, MULTICAST_4_REG)); 796 } 797 #endif 798 799 mutex_exit(&rtlsp->rtls_io_lock); 800 801 return (0); 802 } 803 804 /* 805 * rtls_hash_index() -- a hashing function used for setting the 806 * node address or a multicast address 807 */ 808 static uint_t 809 rtls_hash_index(const uint8_t *address) 810 { 811 uint32_t crc = (ulong_t)RTLS_HASH_CRC; 812 uint32_t const POLY = RTLS_HASH_POLY; 813 uint32_t msb; 814 int bytes; 815 uchar_t currentbyte; 816 uint_t index; 817 int bit; 818 819 for (bytes = 0; bytes < ETHERADDRL; bytes++) { 820 currentbyte = address[bytes]; 821 for (bit = 0; bit < 8; bit++) { 822 msb = crc >> 31; 823 crc <<= 1; 824 if (msb ^ (currentbyte & 1)) { 825 crc ^= POLY; 826 crc |= 0x00000001; 827 } 828 currentbyte >>= 1; 829 } 830 } 831 832 index = crc >> 26; 833 834 return (index); 835 } 836 837 /* 838 * rtls_m_promisc() -- set or reset promiscuous mode on the board 839 */ 840 static int 841 rtls_m_promisc(void *arg, boolean_t on) 842 { 843 rtls_t *rtlsp = arg; 844 845 #ifdef RTLS_DEBUG 846 if (rtls_debug & RTLS_REGCFG) { 847 cmn_err(CE_NOTE, "%s: rtls_m_promisc: on=%d", 848 rtlsp->ifname, on); 849 } 850 #endif 851 mutex_enter(&rtlsp->rtls_io_lock); 852 853 rtlsp->promisc = on; 854 if (!rtlsp->rtls_suspended) { 855 uint32_t val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG); 856 if (on) { 857 val32 |= RX_ACCEPT_ALL_PACKET; 858 } else { 859 val32 &= ~RX_ACCEPT_ALL_PACKET; 860 } 861 rtls_reg_set32(rtlsp, RX_CONFIG_REG, val32); 862 } 863 mutex_exit(&rtlsp->rtls_io_lock); 864 865 return (0); 866 } 867 868 /* 869 * rtls_m_stat() -- retrieve statistic 870 * 871 * MAC calls this routine just before it reads the driver's statistics 872 * structure. If your board maintains statistics, this is the time to 873 * read them in and update the values in the structure. If the driver 874 * maintains statistics continuously, this routine need do nothing. 875 */ 876 static int 877 rtls_m_stat(void *arg, uint_t stat, uint64_t *val) 878 { 879 rtls_t *rtlsp = arg; 880 881 uint16_t bmcr, bmsr, anar, anlpar, aner; 882 883 mutex_enter(&rtlsp->rtls_io_lock); 884 if (!rtlsp->rtls_suspended) { 885 bmcr = rtls_reg_get16(rtlsp, BASIC_MODE_CONTROL_REG); 886 bmsr = rtls_reg_get16(rtlsp, BASIC_MODE_STATUS_REG); 887 anar = rtls_reg_get16(rtlsp, AUTO_NEGO_AD_REG); 888 anlpar = rtls_reg_get16(rtlsp, AUTO_NEGO_LP_REG); 889 aner = rtls_reg_get16(rtlsp, AUTO_NEGO_EXP_REG); 890 } else { 891 bmcr = bmsr = anar = anlpar = aner = 0; 892 } 893 mutex_exit(&rtlsp->rtls_io_lock); 894 895 switch (stat) { 896 case MAC_STAT_IFSPEED: 897 *val = rtlsp->stats.speed; 898 break; 899 case MAC_STAT_IPACKETS: 900 *val = rtlsp->stats.ipackets; 901 break; 902 case MAC_STAT_RBYTES: 903 *val = rtlsp->stats.rbytes; 904 break; 905 case MAC_STAT_OPACKETS: 906 *val = rtlsp->stats.opackets; 907 break; 908 case MAC_STAT_OBYTES: 909 *val = rtlsp->stats.obytes; 910 break; 911 case MAC_STAT_IERRORS: 912 *val = rtlsp->stats.rcv_err; 913 break; 914 case MAC_STAT_OERRORS: 915 *val = rtlsp->stats.xmt_err; 916 break; 917 case MAC_STAT_MULTIRCV: 918 *val = rtlsp->stats.multi_rcv; 919 break; 920 case MAC_STAT_BRDCSTRCV: 921 *val = rtlsp->stats.brdcst_rcv; 922 break; 923 case MAC_STAT_MULTIXMT: 924 *val = rtlsp->stats.multi_xmt; 925 break; 926 case MAC_STAT_BRDCSTXMT: 927 *val = rtlsp->stats.brdcst_xmt; 928 break; 929 case MAC_STAT_UNDERFLOWS: 930 *val = rtlsp->stats.underflow; 931 break; 932 case MAC_STAT_OVERFLOWS: 933 *val = rtlsp->stats.overflow; 934 break; 935 case MAC_STAT_NORCVBUF: 936 *val = rtlsp->stats.no_rcvbuf; 937 break; 938 case MAC_STAT_COLLISIONS: 939 *val = rtlsp->stats.collisions; 940 break; 941 case ETHER_STAT_LINK_DUPLEX: 942 *val = rtlsp->stats.duplex; 943 break; 944 case ETHER_STAT_FCS_ERRORS: 945 *val = rtlsp->stats.crc_err; 946 break; 947 case ETHER_STAT_ALIGN_ERRORS: 948 *val = rtlsp->stats.frame_err; 949 break; 950 case ETHER_STAT_DEFER_XMTS: 951 *val = rtlsp->stats.defer; 952 break; 953 case ETHER_STAT_TX_LATE_COLLISIONS: 954 *val = rtlsp->stats.xmt_latecoll; 955 break; 956 case ETHER_STAT_TOOLONG_ERRORS: 957 *val = rtlsp->stats.too_long; 958 break; 959 case ETHER_STAT_TOOSHORT_ERRORS: 960 *val = rtlsp->stats.in_short; 961 break; 962 case ETHER_STAT_CARRIER_ERRORS: 963 *val = rtlsp->stats.no_carrier; 964 break; 965 case ETHER_STAT_FIRST_COLLISIONS: 966 *val = rtlsp->stats.firstcol; 967 break; 968 case ETHER_STAT_MULTI_COLLISIONS: 969 *val = rtlsp->stats.multicol; 970 break; 971 case ETHER_STAT_CAP_100FDX: 972 case ETHER_STAT_CAP_100HDX: 973 case ETHER_STAT_CAP_10FDX: 974 case ETHER_STAT_CAP_10HDX: 975 case ETHER_STAT_CAP_AUTONEG: 976 *val = 1; /* these are all true by default */ 977 break; 978 case ETHER_STAT_ADV_CAP_100FDX: 979 *val = anar & AUTO_NEGO_100FULL ? 1 : 0; 980 break; 981 case ETHER_STAT_ADV_CAP_100HDX: 982 *val = anar & AUTO_NEGO_100HALF ? 1 : 0; 983 break; 984 case ETHER_STAT_ADV_CAP_10FDX: 985 *val = anar & AUTO_NEGO_10FULL ? 1 : 0; 986 break; 987 case ETHER_STAT_ADV_CAP_10HDX: 988 *val = anar & AUTO_NEGO_10HALF ? 1 : 0; 989 break; 990 case ETHER_STAT_ADV_CAP_AUTONEG: 991 *val = bmcr & BASIC_MODE_AUTONEGO ? 1 : 0; 992 break; 993 case ETHER_STAT_LP_CAP_100FDX: 994 *val = anlpar & AUTO_NEGO_100FULL ? 1 : 0; 995 break; 996 case ETHER_STAT_LP_CAP_100HDX: 997 *val = anlpar & AUTO_NEGO_100HALF ? 1 : 0; 998 break; 999 case ETHER_STAT_LP_CAP_10FDX: 1000 *val = anlpar & AUTO_NEGO_10FULL ? 1 : 0; 1001 break; 1002 case ETHER_STAT_LP_CAP_10HDX: 1003 *val = anlpar & AUTO_NEGO_10HALF ? 1 : 0; 1004 break; 1005 case ETHER_STAT_LP_CAP_AUTONEG: 1006 *val = aner & AUTO_NEGO_EXP_LPCANAN ? 1 : 0; 1007 break; 1008 case ETHER_STAT_LINK_AUTONEG: 1009 *val = ((aner & AUTO_NEGO_EXP_LPCANAN) && 1010 (bmcr & BASIC_MODE_AUTONEGO) && 1011 (bmsr & BASIC_MODE_STATUS_AUTONEGO_DONE)) ? 1 : 0; 1012 break; 1013 default: 1014 return (ENOTSUP); 1015 } 1016 1017 /* 1018 * RTL8139 don't support MII statistics, 1019 * these values are maintained by the driver software. 1020 */ 1021 1022 #ifdef RTLS_DEBUG 1023 if (rtls_debug & RTLS_TRACE) 1024 rtls_reg_print(rtlsp); 1025 #endif 1026 1027 return (0); 1028 } 1029 1030 /* 1031 * rtls_send() -- send a packet 1032 * 1033 * Called when a packet is ready to be transmitted. A pointer to an 1034 * M_DATA message that contains the packet is passed to this routine. 1035 * The complete LLC header is contained in the message's first message 1036 * block, and the remainder of the packet is contained within 1037 * additional M_DATA message blocks linked to the first message block. 1038 * 1039 * Returns B_TRUE if the packet was properly disposed of, or B_FALSE if 1040 * if the packet is being deferred and should be tried again later. 1041 */ 1042 1043 static boolean_t 1044 rtls_send(rtls_t *rtlsp, mblk_t *mp) 1045 { 1046 int totlen; 1047 int ncc; 1048 uint16_t cur_desc; 1049 uint32_t tx_status; 1050 1051 ASSERT(mp != NULL); 1052 ASSERT(rtlsp->rtls_running); 1053 1054 mutex_enter(&rtlsp->rtls_tx_lock); 1055 1056 if (rtlsp->rtls_suspended) { 1057 mutex_exit(&rtlsp->rtls_tx_lock); 1058 return (B_FALSE); 1059 } 1060 1061 /* 1062 * If chip error ... 1063 */ 1064 if (rtlsp->chip_error) { 1065 #ifdef RTLS_DEBUG 1066 cmn_err(CE_WARN, 1067 "%s: send fail--CHIP ERROR!", 1068 rtlsp->ifname); 1069 #endif 1070 mutex_exit(&rtlsp->rtls_tx_lock); 1071 freemsg(mp); 1072 return (B_TRUE); 1073 } 1074 1075 /* 1076 * If chip link down ... 1077 */ 1078 if (rtlsp->link_state == LINK_STATE_DOWN) { 1079 #ifdef RTLS_DEBUG 1080 cmn_err(CE_WARN, 1081 "%s: send fail--LINK DOWN!", 1082 rtlsp->ifname); 1083 #endif 1084 rtlsp->stats.no_carrier++; 1085 mutex_exit(&rtlsp->rtls_tx_lock); 1086 freemsg(mp); 1087 return (B_TRUE); 1088 } 1089 1090 /* 1091 * Current transmit descriptor 1092 */ 1093 cur_desc = rtlsp->tx_current_desc; 1094 ASSERT(cur_desc < RTLS_MAX_TX_DESC); 1095 1096 /* 1097 * RealTek 8139 has 4 tx descriptor for transmit. In the first tx loop 1098 * of transmit,we needn't judge transmit status. 1099 */ 1100 if (rtlsp->tx_first_loop < RTLS_MAX_TX_DESC) { 1101 rtlsp->tx_first_loop++; 1102 goto tx_ready; 1103 } 1104 1105 /* 1106 * If it's not the first tx loop, we need judge whether the chip is 1107 * busy or not. Otherwise, we have to reschedule send and wait... 1108 */ 1109 tx_status = rtls_reg_get32(rtlsp, TX_STATUS_DESC0_REG + 4 * cur_desc); 1110 1111 /* 1112 * H/W doesn't complete packet transmit 1113 */ 1114 if (!(tx_status & TX_COMPLETE_FLAG)) { 1115 #ifdef RTLS_DEBUG 1116 if (rtls_debug & RTLS_SEND) { 1117 cmn_err(CE_NOTE, 1118 "%s: rtls_send: need_sched", rtlsp->ifname); 1119 } 1120 #endif 1121 /* 1122 * Through test, we find RTL8139 tx status might be 1123 * not-completing all along. We have to reset chip 1124 * to make RTL8139 tansmit re-work. 1125 */ 1126 if (rtlsp->tx_retry++ > RTLS_TX_RETRY_NUM) { 1127 1128 /* 1129 * Wait transmit h/w more time... 1130 */ 1131 RTLS_TX_WAIT_TIMEOUT; /* 100 ms */ 1132 1133 /* 1134 * Judge tx status again, if it remains not-completing, 1135 * we can confirm RTL8139 is in chip error state 1136 * and must reset it. 1137 */ 1138 tx_status = rtls_reg_get32(rtlsp, 1139 TX_STATUS_DESC0_REG + 4 * cur_desc); 1140 if (!(tx_status & TX_COMPLETE_FLAG)) { 1141 #ifdef RTLS_DEBUG 1142 cmn_err(CE_NOTE, "%s: tx chip_error = 0x%x", 1143 rtlsp->ifname, tx_status); 1144 #endif 1145 rtlsp->tx_retry = 0; 1146 rtlsp->chip_error = B_TRUE; 1147 rtlsp->stats.xmt_err++; 1148 rtlsp->stats.mac_xmt_err++; 1149 mutex_exit(&rtlsp->rtls_tx_lock); 1150 freemsg(mp); 1151 return (B_TRUE); 1152 } 1153 } else { 1154 rtlsp->stats.defer++; 1155 rtlsp->need_sched = B_TRUE; 1156 mutex_exit(&rtlsp->rtls_tx_lock); 1157 return (B_FALSE); 1158 } 1159 } 1160 1161 /* 1162 * Transmit error? 1163 */ 1164 if (tx_status & TX_ERR_FLAG) { 1165 #ifdef RTLS_DEBUG 1166 if (rtls_debug & RTLS_SEND) { 1167 cmn_err(CE_NOTE, "%s: transmit error, status = 0x%x", 1168 rtlsp->ifname, tx_status); 1169 } 1170 #endif 1171 rtlsp->stats.xmt_err++; 1172 if (tx_status & TX_STATUS_TX_UNDERRUN) 1173 rtlsp->stats.underflow++; 1174 if (tx_status & TX_STATUS_CS_LOST) 1175 rtlsp->stats.no_carrier++; 1176 if (tx_status & TX_STATUS_OWC) 1177 rtlsp->stats.xmt_latecoll++; 1178 } 1179 ncc = ((tx_status & TX_STATUS_NCC) >> TX_STATUS_NCC_SHIFT); 1180 if (ncc != 0) { 1181 rtlsp->stats.collisions += ncc; 1182 rtlsp->stats.firstcol++; 1183 rtlsp->stats.multicol += ncc - 1; 1184 } 1185 1186 tx_ready: 1187 /* 1188 * Initialize variable 1189 */ 1190 rtlsp->tx_retry = 0; 1191 totlen = 0; 1192 1193 /* 1194 * Copy packet to tx descriptor buffer 1195 */ 1196 totlen = msgsize(mp); 1197 if (totlen > (ETHERMAX + 4)) { /* 4 bytes for VLAN header */ 1198 cmn_err(CE_NOTE, 1199 "%s: rtls_send: try to send large %d packet", 1200 rtlsp->ifname, totlen); 1201 rtlsp->stats.mac_xmt_err++; 1202 rtlsp->stats.xmt_err++; 1203 freemsg(mp); 1204 mutex_exit(&rtlsp->rtls_tx_lock); 1205 return (B_TRUE); 1206 } 1207 1208 /* this will free the mblk */ 1209 mcopymsg(mp, rtlsp->tx_buf[cur_desc]); 1210 1211 /* update stats */ 1212 if (*rtlsp->tx_buf[cur_desc] & 0x1) { 1213 uint16_t *ptr = (void *)rtlsp->tx_buf[cur_desc]; 1214 if ((ptr[0] == 0xffff) && 1215 (ptr[1] == 0xffff) && 1216 (ptr[2] == 0xffff)) { 1217 rtlsp->stats.brdcst_xmt++; 1218 } else { 1219 rtlsp->stats.multi_xmt++; 1220 } 1221 } 1222 rtlsp->stats.opackets++; 1223 rtlsp->stats.obytes += totlen; 1224 1225 if (totlen < ETHERMIN) { 1226 bzero(rtlsp->tx_buf[cur_desc] + totlen, ETHERMIN - totlen); 1227 totlen = ETHERMIN; 1228 } 1229 1230 /* make sure caches are flushed */ 1231 (void) ddi_dma_sync(rtlsp->dma_area_tx[cur_desc].dma_hdl, 0, totlen, 1232 DDI_DMA_SYNC_FORDEV); 1233 1234 /* 1235 * Start transmit 1236 * set transmit FIFO threshhold to 0x30*32 = 1536 bytes 1237 * to avoid tx underrun. 1238 */ 1239 rtls_reg_set32(rtlsp, TX_STATUS_DESC0_REG + 4 * cur_desc, 1240 totlen | (0x30 << TX_STATUS_TX_THRESHOLD_SHIFT)); 1241 1242 /* 1243 * Update the value of current tx descriptor 1244 */ 1245 cur_desc++; 1246 cur_desc %= RTLS_MAX_TX_DESC; 1247 rtlsp->tx_current_desc = cur_desc; 1248 1249 mutex_exit(&rtlsp->rtls_tx_lock); 1250 1251 return (B_TRUE); 1252 } 1253 1254 /* 1255 * rtls_m_tx() -- send a chain of packets, linked by mp->b_next. 1256 */ 1257 static mblk_t * 1258 rtls_m_tx(void *arg, mblk_t *mp) 1259 { 1260 rtls_t *rtlsp = arg; 1261 mblk_t *next; 1262 1263 while (mp != NULL) { 1264 next = mp->b_next; 1265 mp->b_next = NULL; 1266 if (!rtls_send(rtlsp, mp)) { 1267 mp->b_next = next; 1268 break; 1269 } 1270 mp = next; 1271 } 1272 return (mp); 1273 } 1274 1275 /* 1276 * rtls_receive() -- receive packets 1277 * 1278 * Called when receive interrupts detected 1279 */ 1280 static void 1281 rtls_receive(rtls_t *rtlsp) 1282 { 1283 mblk_t *head = NULL; 1284 mblk_t **mpp; 1285 mblk_t *mp; 1286 uint16_t rx_status; 1287 uint16_t packet_len; 1288 int wrap_size; 1289 uint32_t cur_rx; 1290 uint8_t *rx_ptr; 1291 1292 mpp = &head; 1293 1294 mutex_enter(&rtlsp->rtls_rx_lock); 1295 1296 if (rtlsp->rtls_suspended) { 1297 mutex_exit(&rtlsp->rtls_rx_lock); 1298 return; 1299 } 1300 1301 while ((rtls_reg_get8(rtlsp, RT_COMMAND_REG) 1302 & RT_COMMAND_BUFF_EMPTY) == 0) { 1303 1304 /* 1305 * Chip error state 1306 */ 1307 if (rtlsp->chip_error) { 1308 #ifdef RTLS_DEBUG 1309 cmn_err(CE_WARN, 1310 "%s: receive fail--CHIP ERROR!", 1311 rtlsp->ifname); 1312 #endif 1313 break; 1314 } 1315 1316 cur_rx = rtlsp->cur_rx; 1317 rx_ptr = rtlsp->rx_ring + cur_rx; 1318 packet_len = (rx_ptr[3] << 8) | (rx_ptr[2]); 1319 rx_status = rx_ptr[0]; 1320 1321 /* 1322 * DMA still in progress 1323 */ 1324 if (packet_len == RX_STATUS_DMA_BUSY) { 1325 cmn_err(CE_NOTE, "%s: Rx DMA still in progress", 1326 rtlsp->ifname); 1327 break; 1328 } 1329 1330 /* 1331 * Check receive status 1332 */ 1333 if ((rx_status & RX_ERR_FLAGS) || 1334 (!(rx_status & RX_HEADER_STATUS_ROK)) || 1335 (packet_len < (ETHERMIN + ETHERFCSL)) || 1336 (packet_len > (ETHERMAX + ETHERFCSL + 4))) { 1337 #ifdef RTLS_DEBUG 1338 cmn_err(CE_NOTE, 1339 "%s: receive error, status = 0x%x, length = %d", 1340 rtlsp->ifname, rx_status, packet_len); 1341 #endif 1342 /* 1343 * Rx error statistics 1344 */ 1345 if ((rx_status & RX_HEADER_STATUS_RUNT) || 1346 (packet_len < (ETHERMIN + ETHERFCSL))) 1347 rtlsp->stats.in_short++; 1348 else if (packet_len > (ETHERMAX + ETHERFCSL + 4)) 1349 rtlsp->stats.too_long++; 1350 else if (rx_status & RX_HEADER_STATUS_CRC) 1351 rtlsp->stats.crc_err++; 1352 else if (rx_status & RX_HEADER_STATUS_FAE) 1353 rtlsp->stats.frame_err++; 1354 1355 /* 1356 * Set chip_error flag to reset chip: 1357 * (suggested in RealTek programming guide.) 1358 */ 1359 rtlsp->chip_error = B_TRUE; 1360 mutex_exit(&rtlsp->rtls_rx_lock); 1361 return; 1362 } 1363 1364 /* 1365 * We need not up-send ETHERFCSL bytes of receive packet 1366 */ 1367 packet_len -= ETHERFCSL; 1368 1369 /* 1370 * Allocate buffer to receive this good packet 1371 */ 1372 mp = allocb(packet_len, 0); 1373 1374 /* 1375 * Copy the data found into the new cluster, we have (+4) 1376 * to get us past the packet head data that the rtl chip 1377 * places at the start of the message 1378 */ 1379 if ((cur_rx + packet_len + RX_HEADER_SIZE) 1380 > RTLS_RX_BUF_RING) { 1381 wrap_size = cur_rx + packet_len + RX_HEADER_SIZE 1382 - RTLS_RX_BUF_RING; 1383 #ifdef RTLS_DEBUG 1384 if (rtls_debug & RTLS_RECV) { 1385 cmn_err(CE_NOTE, 1386 "%s: Rx: packet_len = %d, wrap_size = %d", 1387 rtlsp->ifname, packet_len, wrap_size); 1388 } 1389 #endif 1390 1391 if (mp != NULL) { 1392 /* Flush caches */ 1393 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl, 1394 cur_rx + RX_HEADER_SIZE, 1395 packet_len - wrap_size, 1396 DDI_DMA_SYNC_FORKERNEL); 1397 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl, 1398 0, wrap_size, 1399 DDI_DMA_SYNC_FORKERNEL); 1400 1401 /* 1402 * Copy in first section of message as stored 1403 * at the end of the ring buffer 1404 */ 1405 bcopy(rx_ptr + RX_HEADER_SIZE, 1406 mp->b_wptr, packet_len - wrap_size); 1407 mp->b_wptr += packet_len - wrap_size; 1408 bcopy(rtlsp->rx_ring, mp->b_wptr, wrap_size); 1409 mp->b_wptr += wrap_size; 1410 *mpp = mp; 1411 mpp = &mp->b_next; 1412 1413 rtlsp->stats.ipackets++; 1414 if (rx_status & RX_HEADER_STATUS_BCAST) 1415 rtlsp->stats.brdcst_rcv++; 1416 if (rx_status & RX_HEADER_STATUS_MULTI) 1417 rtlsp->stats.multi_rcv++; 1418 rtlsp->stats.rbytes += packet_len; 1419 } else { 1420 rtlsp->stats.no_rcvbuf++; 1421 } 1422 1423 cur_rx = RTLS_RX_ADDR_ALIGNED(wrap_size + ETHERFCSL); 1424 /* 4-byte aligned */ 1425 } else { 1426 1427 if (mp != NULL) { 1428 /* Flush caches */ 1429 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl, 1430 cur_rx + RX_HEADER_SIZE, packet_len, 1431 DDI_DMA_SYNC_FORKERNEL); 1432 bcopy(rx_ptr + RX_HEADER_SIZE, mp->b_wptr, 1433 packet_len); 1434 mp->b_wptr += packet_len; 1435 *mpp = mp; 1436 mpp = &mp->b_next; 1437 1438 rtlsp->stats.ipackets++; 1439 if (rx_status & RX_HEADER_STATUS_BCAST) 1440 rtlsp->stats.brdcst_rcv++; 1441 if (rx_status & RX_HEADER_STATUS_MULTI) 1442 rtlsp->stats.multi_rcv++; 1443 rtlsp->stats.rbytes += packet_len; 1444 } else { 1445 rtlsp->stats.no_rcvbuf++; 1446 } 1447 cur_rx += packet_len + RX_HEADER_SIZE + ETHERFCSL; 1448 1449 cur_rx = RTLS_RX_ADDR_ALIGNED(cur_rx); 1450 /* 4-byte aligned */ 1451 } 1452 1453 /* 1454 * Update rx buffer ring read pointer: 1455 * give us a little leeway to ensure no overflow 1456 */ 1457 rtlsp->cur_rx = cur_rx; 1458 rtls_reg_set16(rtlsp, RX_CURRENT_READ_ADDR_REG, 1459 cur_rx - READ_ADDR_GAP); 1460 } 1461 mutex_exit(&rtlsp->rtls_rx_lock); 1462 1463 /* 1464 * Upsend packet 1465 */ 1466 if (head) { 1467 mac_rx(rtlsp->mh, NULL, head); 1468 } 1469 } 1470 1471 /* 1472 * rtls_intr() -- interrupt from board to inform us that a receive or 1473 * link change. 1474 */ 1475 static uint_t 1476 rtls_intr(caddr_t arg) 1477 { 1478 rtls_t *rtlsp = (void *)arg; 1479 uint32_t int_status; 1480 uint8_t media_status; 1481 int32_t link; 1482 uint32_t val32; 1483 1484 mutex_enter(&rtlsp->rtls_io_lock); 1485 1486 /* 1487 * Was this interrupt caused by our device... 1488 */ 1489 int_status = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 1490 if (!(int_status & rtlsp->int_mask)) { 1491 mutex_exit(&rtlsp->rtls_io_lock); 1492 return (DDI_INTR_UNCLAIMED); 1493 /* indicate it wasn't our interrupt */ 1494 } 1495 1496 /* 1497 * Clear interrupt 1498 */ 1499 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, int_status); 1500 1501 /* 1502 * If chip error, restart chip... 1503 */ 1504 if (rtlsp->chip_error) { 1505 mutex_enter(&rtlsp->rtls_rx_lock); 1506 mutex_enter(&rtlsp->rtls_tx_lock); 1507 rtls_chip_restart(rtlsp); 1508 rtlsp->chip_error = B_FALSE; 1509 rtlsp->tx_retry = 0; 1510 mutex_exit(&rtlsp->rtls_tx_lock); 1511 mutex_exit(&rtlsp->rtls_rx_lock); 1512 mutex_exit(&rtlsp->rtls_io_lock); 1513 return (DDI_INTR_CLAIMED); 1514 /* no need to hand other interrupts */ 1515 } 1516 1517 /* 1518 * Transmit error interrupt 1519 */ 1520 if (int_status & TX_ERR_INT) { 1521 val32 = rtls_reg_get32(rtlsp, TX_CONFIG_REG); 1522 val32 |= TX_CLEAR_ABORT; 1523 rtls_reg_set32(rtlsp, TX_CONFIG_REG, val32); 1524 cmn_err(CE_WARN, "%s: transmit abort!!!", rtlsp->ifname); 1525 } 1526 1527 /* 1528 * Cable link change interrupt 1529 */ 1530 if (int_status & LINK_CHANGE_INT) { 1531 media_status = rtls_reg_get8(rtlsp, MEDIA_STATUS_REG); 1532 link = (media_status & MEDIA_STATUS_LINK) ? 1533 LINK_STATE_DOWN : LINK_STATE_UP; 1534 1535 if (rtlsp->link_state != link) { 1536 rtlsp->link_state = link; 1537 rtlsp->link_change = B_TRUE; 1538 /* 1539 * Trigger rtls_events 1540 */ 1541 ddi_trigger_softintr(rtlsp->events_id); 1542 } 1543 } 1544 1545 /* 1546 * Trigger mac_tx_update 1547 */ 1548 if (rtlsp->need_sched && !rtlsp->sched_running) { 1549 rtlsp->sched_running = B_TRUE; 1550 ddi_trigger_softintr(rtlsp->resched_id); 1551 } 1552 1553 mutex_exit(&rtlsp->rtls_io_lock); 1554 1555 /* 1556 * Receive interrupt 1557 */ 1558 if (int_status & RTLS_RX_INT) { 1559 if (int_status & RX_OVERFLOW_INT) { 1560 rtlsp->stats.overflow++; 1561 rtlsp->stats.rcv_err++; 1562 } 1563 rtls_receive(rtlsp); 1564 } 1565 1566 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */ 1567 } 1568 1569 static void 1570 rtls_periodic(void *arg) 1571 { 1572 rtls_t *rtlsp = (void *)arg; 1573 uint32_t link; 1574 uint8_t media_status; 1575 1576 mutex_enter(&rtlsp->rtls_io_lock); 1577 1578 if (rtlsp->rtls_suspended) { 1579 mutex_exit(&rtlsp->rtls_io_lock); 1580 return; 1581 } 1582 1583 media_status = rtls_reg_get8(rtlsp, MEDIA_STATUS_REG); 1584 link = (media_status & MEDIA_STATUS_LINK) ? 1585 LINK_STATE_DOWN : LINK_STATE_UP; 1586 1587 if (rtlsp->link_state != link) { 1588 rtlsp->link_state = link; 1589 rtlsp->link_change = B_TRUE; 1590 /* 1591 * Trigger rtls_events 1592 */ 1593 ddi_trigger_softintr(rtlsp->events_id); 1594 } 1595 mutex_exit(&rtlsp->rtls_io_lock); 1596 } 1597 1598 /* 1599 * rtls_reschedule() -- soft interrupt handler 1600 */ 1601 static uint_t 1602 rtls_reschedule(caddr_t arg) 1603 { 1604 rtls_t *rtlsp = (void *)arg; 1605 uint_t tmp; 1606 1607 tmp = DDI_INTR_UNCLAIMED; 1608 1609 if (rtlsp->need_sched && rtlsp->rtls_running) { 1610 #ifdef RTLS_DEBUG 1611 if (rtls_debug & RTLS_SEND) { 1612 cmn_err(CE_NOTE, "%s: rtls_reschedule", rtlsp->ifname); 1613 } 1614 #endif 1615 rtlsp->need_sched = B_FALSE; 1616 mac_tx_update(rtlsp->mh); 1617 rtlsp->sched_running = B_FALSE; 1618 tmp = DDI_INTR_CLAIMED; 1619 } 1620 return (tmp); 1621 } 1622 1623 /* 1624 * rtls_events() -- soft interrupt handler 1625 * 1626 * The rtls_events is woken up when there's something to do that we'd rather 1627 * not do from inside a hardware interrupt handler. 1628 * Its main task now is just: 1629 * notice mac the link status changed 1630 */ 1631 static uint_t 1632 rtls_events(caddr_t arg) 1633 { 1634 rtls_t *rtlsp = (void *)arg; 1635 uint_t tmp = DDI_INTR_UNCLAIMED; 1636 uint8_t media_status; 1637 uint16_t duplex_mode; 1638 1639 /* 1640 * If the link state changed, tell the world about it. 1641 * Note: can't do this while still holding the mutex. 1642 */ 1643 if (rtlsp->link_change) { 1644 rtlsp->link_change = B_FALSE; 1645 1646 if (rtlsp->link_state == LINK_STATE_UP) { 1647 media_status = 1648 rtls_reg_get8(rtlsp, MEDIA_STATUS_REG); 1649 rtlsp->stats.speed = 1650 (media_status & MEDIA_STATUS_SPEED) ? 1651 RTLS_SPEED_10M : RTLS_SPEED_100M; 1652 duplex_mode = rtls_reg_get16(rtlsp, 1653 BASIC_MODE_CONTROL_REG); 1654 rtlsp->stats.duplex = 1655 (duplex_mode & BASIC_MODE_DUPLEX) ? 1656 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF; 1657 } 1658 mac_link_update(rtlsp->mh, rtlsp->link_state); 1659 1660 tmp = DDI_INTR_CLAIMED; 1661 } 1662 1663 return (tmp); 1664 } 1665 1666 /* 1667 * ========== Buffer Management Routines ========== 1668 */ 1669 1670 /* 1671 * rtls_alloc_dma_mem() -- allocate an area of memory and a DMA handle 1672 * for accessing it 1673 */ 1674 static int 1675 rtls_alloc_dma_mem(rtls_t *rtlsp, size_t memsize, 1676 ddi_device_acc_attr_t *attr_p, uint_t dma_flags, dma_area_t *dma_p) 1677 { 1678 caddr_t vaddr; 1679 int err; 1680 1681 /* 1682 * Allocate handle 1683 */ 1684 err = ddi_dma_alloc_handle(rtlsp->devinfo, &dma_attr, 1685 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl); 1686 if (err != DDI_SUCCESS) { 1687 cmn_err(CE_WARN, 1688 "%s: rtls_alloc_dma_mem: ddi_dma_alloc_handle failed: %d", 1689 rtlsp->ifname, err); 1690 dma_p->dma_hdl = NULL; 1691 return (DDI_FAILURE); 1692 } 1693 1694 /* 1695 * Allocate memory 1696 */ 1697 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p, 1698 dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING), 1699 DDI_DMA_SLEEP, NULL, &vaddr, &dma_p->alength, &dma_p->acc_hdl); 1700 if (err != DDI_SUCCESS) { 1701 cmn_err(CE_WARN, 1702 "%s: rtls_alloc_dma_mem: ddi_dma_mem_alloc failed: %d", 1703 rtlsp->ifname, err); 1704 ddi_dma_free_handle(&dma_p->dma_hdl); 1705 dma_p->dma_hdl = NULL; 1706 dma_p->acc_hdl = NULL; 1707 return (DDI_FAILURE); 1708 } 1709 1710 /* 1711 * Bind the two together 1712 */ 1713 dma_p->mem_va = vaddr; 1714 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 1715 vaddr, dma_p->alength, dma_flags, DDI_DMA_SLEEP, NULL, 1716 &dma_p->cookie, &dma_p->ncookies); 1717 if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1) { 1718 cmn_err(CE_WARN, 1719 "%s: rtls_alloc_dma_mem: " 1720 "ddi_dma_addr_bind_handle failed: %d", 1721 rtlsp->ifname, err); 1722 ddi_dma_mem_free(&dma_p->acc_hdl); 1723 ddi_dma_free_handle(&dma_p->dma_hdl); 1724 dma_p->acc_hdl = NULL; 1725 dma_p->dma_hdl = NULL; 1726 return (DDI_FAILURE); 1727 } 1728 1729 return (DDI_SUCCESS); 1730 } 1731 1732 /* 1733 * rtls_free_dma_mem() -- free one allocated area of DMAable memory 1734 */ 1735 static void 1736 rtls_free_dma_mem(dma_area_t *dma_p) 1737 { 1738 if (dma_p->dma_hdl != NULL) { 1739 if (dma_p->ncookies) { 1740 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 1741 dma_p->ncookies = 0; 1742 } 1743 ddi_dma_free_handle(&dma_p->dma_hdl); 1744 dma_p->dma_hdl = NULL; 1745 } 1746 1747 if (dma_p->acc_hdl != NULL) { 1748 ddi_dma_mem_free(&dma_p->acc_hdl); 1749 dma_p->acc_hdl = NULL; 1750 } 1751 } 1752 1753 /* 1754 * rtls_alloc_bufs() -- allocate descriptors/buffers for this device instance 1755 */ 1756 static int 1757 rtls_alloc_bufs(rtls_t *rtlsp) 1758 { 1759 int i; 1760 int err; 1761 1762 /* 1763 * Allocate memory & handle for Tx buffers 1764 */ 1765 for (i = 0; i < RTLS_MAX_TX_DESC; i++) { 1766 err = rtls_alloc_dma_mem(rtlsp, 1767 RTLS_TX_BUF_SIZE, 1768 &rtls_buf_accattr, 1769 DDI_DMA_WRITE | DDI_DMA_STREAMING, 1770 &rtlsp->dma_area_tx[i]); 1771 1772 if (err != DDI_SUCCESS) 1773 return (DDI_FAILURE); 1774 1775 rtlsp->tx_buf[i] = (uint8_t *)rtlsp->dma_area_tx[i].mem_va; 1776 } 1777 1778 /* 1779 * Allocate memory & handle for Rx buffers 1780 */ 1781 err = rtls_alloc_dma_mem(rtlsp, 1782 RTLS_RX_BUF_SIZE, 1783 &rtls_buf_accattr, 1784 DDI_DMA_READ | DDI_DMA_STREAMING, 1785 &rtlsp->dma_area_rx); 1786 1787 if (err != DDI_SUCCESS) 1788 return (DDI_FAILURE); 1789 1790 rtlsp->rx_ring = (uint8_t *)rtlsp->dma_area_rx.mem_va; 1791 1792 return (DDI_SUCCESS); 1793 } 1794 1795 /* 1796 * rtls_free_bufs() -- free descriptors/buffers allocated for this 1797 * device instance. 1798 */ 1799 static void 1800 rtls_free_bufs(rtls_t *rtlsp) 1801 { 1802 int i; 1803 1804 for (i = 0; i < RTLS_MAX_TX_DESC; i++) { 1805 rtls_free_dma_mem(&rtlsp->dma_area_tx[i]); 1806 rtlsp->tx_buf[i] = NULL; 1807 } 1808 1809 rtls_free_dma_mem(&rtlsp->dma_area_rx); 1810 rtlsp->rx_ring = NULL; 1811 } 1812 1813 /* 1814 * ========== Chip H/W Operation Routines ========== 1815 */ 1816 1817 /* 1818 * rtls_chip_reset() -- reset chip 1819 */ 1820 static int 1821 rtls_chip_reset(rtls_t *rtlsp, boolean_t quiesce) 1822 { 1823 int i; 1824 uint16_t val16; 1825 uint8_t val8; 1826 1827 /* 1828 * Chip should be in STOP state 1829 */ 1830 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1831 val8 &= ~(RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1832 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8); 1833 1834 /* 1835 * Disable interrupt 1836 */ 1837 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 1838 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 & (~RTLS_INT_MASK_ALL)); 1839 rtlsp->int_mask = RTLS_INT_MASK_NONE; 1840 1841 /* 1842 * Clear pended interrupt 1843 */ 1844 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 1845 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, val16); 1846 1847 /* 1848 * Reset chip 1849 */ 1850 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1851 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8 | RT_COMMAND_RESET); 1852 1853 /* 1854 * Wait for reset success 1855 */ 1856 i = 0; 1857 while (rtls_reg_get8(rtlsp, RT_COMMAND_REG) & RT_COMMAND_RESET) { 1858 if (++i > RTLS_RESET_WAIT_NUM) { 1859 /* 1860 * At quiesce path we can't call cmn_err(), as 1861 * it might block 1862 */ 1863 if (!quiesce) 1864 cmn_err(CE_WARN, 1865 "%s: chip reset fail.", rtlsp->ifname); 1866 return (DDI_FAILURE); 1867 } 1868 RTLS_RESET_WAIT_INTERVAL; 1869 } 1870 1871 return (DDI_SUCCESS); 1872 } 1873 1874 /* 1875 * rtls_chip_init() -- initialize the specified network board short of 1876 * actually starting the board. Call after rtls_chip_reset(). 1877 */ 1878 static void 1879 rtls_chip_init(rtls_t *rtlsp) 1880 { 1881 static boolean_t first_time = B_TRUE; 1882 int *forced_speed_and_duplex; 1883 uint_t item_num; 1884 uint32_t val32; 1885 uint16_t val16; 1886 uint8_t val8; 1887 int err; 1888 int i; 1889 1890 /* 1891 * Initialize internal data structures 1892 */ 1893 rtlsp->cur_rx = 0; 1894 rtlsp->tx_current_desc = 0; 1895 rtlsp->tx_first_loop = 0; 1896 1897 /* 1898 * Read ForceSpeedDuplex from rtls.conf file 1899 */ 1900 if (first_time) { 1901 first_time = B_FALSE; 1902 /* 1903 * Set ForceSpeedDuplex array default value 1904 * to 5:Anto-Negotiation 1905 */ 1906 for (i = 0; i < RTLS_MAX_DEVICES; i++) 1907 rtls_link_mode[i] = FORCE_AUTO_NEGO; 1908 1909 /* Read ForceSpeedDuplex value */ 1910 err = ddi_prop_lookup_int_array( 1911 DDI_DEV_T_ANY, 1912 rtlsp->devinfo, 1913 DDI_PROP_DONTPASS, 1914 "ForceSpeedDuplex", 1915 &forced_speed_and_duplex, 1916 &item_num); 1917 if (err == DDI_PROP_SUCCESS) { 1918 for (i = 0; i <= item_num; i++) { 1919 rtls_link_mode[i] = 1920 forced_speed_and_duplex[i]; 1921 } 1922 ddi_prop_free(forced_speed_and_duplex); 1923 } 1924 #ifdef RTLS_DEBUG 1925 if (err == DDI_PROP_SUCCESS) { 1926 for (i = 0; i < item_num; i++) 1927 cmn_err(CE_NOTE, 1928 "rtls.conf: rtls%d, ForceSpeedDuplex = %d", 1929 i, rtls_link_mode[i]); 1930 } else { 1931 cmn_err(CE_NOTE, 1932 "rtls: read ForceSpeedDuplex in rtls.conf fail."); 1933 } 1934 #endif 1935 } 1936 rtlsp->force_speed_duplex = 1937 rtls_link_mode[rtlsp->instance]; 1938 1939 /* 1940 * Set duplex and speed 1941 */ 1942 rtls_chip_force_speed_duplex(rtlsp); 1943 1944 /* 1945 * Set DMA physical rx/tx buffer address to register 1946 */ 1947 rtls_reg_set32(rtlsp, RX_BUFF_ADDR_REG, 1948 (ulong_t)rtlsp->dma_area_rx.cookie.dmac_address); 1949 rtls_reg_set32(rtlsp, TX_ADDR_DESC0_REG, 1950 (ulong_t)rtlsp->dma_area_tx[0].cookie.dmac_address); 1951 rtls_reg_set32(rtlsp, TX_ADDR_DESC1_REG, 1952 (ulong_t)rtlsp->dma_area_tx[1].cookie.dmac_address); 1953 rtls_reg_set32(rtlsp, TX_ADDR_DESC2_REG, 1954 (ulong_t)rtlsp->dma_area_tx[2].cookie.dmac_address); 1955 rtls_reg_set32(rtlsp, TX_ADDR_DESC3_REG, 1956 (ulong_t)rtlsp->dma_area_tx[3].cookie.dmac_address); 1957 1958 /* 1959 * Start transmit/receive before set tx/rx configuration register 1960 */ 1961 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1962 rtls_reg_set8(rtlsp, RT_COMMAND_REG, 1963 val8 | RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1964 1965 /* 1966 * Set transmit configuration register 1967 */ 1968 val32 = rtls_reg_get32(rtlsp, TX_CONFIG_REG); 1969 val32 &= TX_CONSIG_REG_RESERVE; 1970 rtls_reg_set32(rtlsp, TX_CONFIG_REG, val32 | TX_CONFIG_DEFAULT); 1971 1972 /* 1973 * Set receive configuration register 1974 */ 1975 val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG); 1976 val32 &= RX_CONSIG_REG_RESERVE; 1977 if (rtlsp->promisc) 1978 val32 |= RX_ACCEPT_ALL_PACKET; 1979 rtls_reg_set32(rtlsp, RX_CONFIG_REG, val32 | RX_CONFIG_DEFAULT); 1980 1981 /* 1982 * Set multicast register 1983 */ 1984 rtls_reg_set32(rtlsp, MULTICAST_0_REG, rtlsp->multi_hash[0]); 1985 rtls_reg_set32(rtlsp, MULTICAST_4_REG, rtlsp->multi_hash[1]); 1986 1987 /* 1988 * Set unicast address 1989 */ 1990 rtls_set_mac_addr(rtlsp, rtlsp->netaddr); 1991 1992 /* 1993 * Set current address of packet read 1994 */ 1995 rtls_reg_set16(rtlsp, RX_CURRENT_READ_ADDR_REG, RX_READ_RESET_VAL); 1996 1997 /* 1998 * No early-rx interrupts 1999 */ 2000 val16 = rtls_reg_get16(rtlsp, RT_MUL_INTSEL_REG); 2001 val16 &= ~RT_MUL_INTSEL_BITS; 2002 rtls_reg_set16(rtlsp, RT_MUL_INTSEL_REG, val16); 2003 } 2004 2005 /* 2006 * rtls_chip_start() -- start chip 2007 */ 2008 static void 2009 rtls_chip_start(rtls_t *rtlsp) 2010 { 2011 uint16_t val16; 2012 uint8_t val8; 2013 2014 /* 2015 * Start transmit/receive 2016 */ 2017 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 2018 rtls_reg_set8(rtlsp, RT_COMMAND_REG, 2019 val8 | RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 2020 2021 /* 2022 * Enable interrupt 2023 */ 2024 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 2025 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 | RTLS_INT_MASK); 2026 rtlsp->int_mask = RTLS_INT_MASK; 2027 } 2028 2029 /* 2030 * rtls_chip_restart() -- restart chip 2031 */ 2032 static void 2033 rtls_chip_restart(rtls_t *rtlsp) 2034 { 2035 (void) rtls_chip_reset(rtlsp, B_FALSE); 2036 rtls_chip_init(rtlsp); 2037 rtls_chip_start(rtlsp); 2038 } 2039 2040 /* 2041 * rtls_chip_stop() -- stop board receiving 2042 */ 2043 static void 2044 rtls_chip_stop(rtls_t *rtlsp) 2045 { 2046 uint16_t val16; 2047 uint8_t val8; 2048 2049 /* 2050 * Disable interrupt 2051 */ 2052 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 2053 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 & (~RTLS_INT_MASK_ALL)); 2054 rtlsp->int_mask = RTLS_INT_MASK_NONE; 2055 2056 /* 2057 * Clear pended interrupt 2058 */ 2059 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 2060 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, val16); 2061 2062 /* 2063 * Stop the board and disable transmit/receive 2064 */ 2065 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 2066 val8 &= ~(RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 2067 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8); 2068 } 2069 2070 /* 2071 * rtls_get_mac_addr() -- get the physical network address on the board 2072 */ 2073 static void 2074 rtls_get_mac_addr(rtls_t *rtlsp, uint8_t *macaddr) 2075 { 2076 uint32_t val32; 2077 2078 /* 2079 * Read first 4-byte of mac address 2080 */ 2081 val32 = rtls_reg_get32(rtlsp, ID_0_REG); 2082 macaddr[0] = val32 & 0xff; 2083 val32 = val32 >> 8; 2084 macaddr[1] = val32 & 0xff; 2085 val32 = val32 >> 8; 2086 macaddr[2] = val32 & 0xff; 2087 val32 = val32 >> 8; 2088 macaddr[3] = val32 & 0xff; 2089 2090 /* 2091 * Read last 2-byte of mac address 2092 */ 2093 val32 = rtls_reg_get32(rtlsp, ID_4_REG); 2094 macaddr[4] = val32 & 0xff; 2095 val32 = val32 >> 8; 2096 macaddr[5] = val32 & 0xff; 2097 } 2098 2099 static void 2100 rtls_set_mac_addr(rtls_t *rtlsp, const uint8_t *macaddr) 2101 { 2102 uint32_t val32; 2103 uint8_t val8; 2104 2105 #ifdef RTLS_DEBUG 2106 if (rtls_debug & RTLS_REGCFG) { 2107 cmn_err(CE_NOTE, "%s:rtls_set_mac_addr(%s)", 2108 rtlsp->ifname, ether_sprintf((void *)macaddr)); 2109 } 2110 #endif 2111 /* 2112 * Change to config register write enable mode 2113 */ 2114 val8 = rtls_reg_get8(rtlsp, RT_93c46_COMMOND_REG); 2115 val8 |= RT_93c46_MODE_CONFIG; 2116 rtls_reg_set8(rtlsp, RT_93c46_COMMOND_REG, val8); 2117 2118 /* 2119 * Get first 4 bytes of mac address 2120 */ 2121 val32 = macaddr[3]; 2122 val32 = val32 << 8; 2123 val32 |= macaddr[2]; 2124 val32 = val32 << 8; 2125 val32 |= macaddr[1]; 2126 val32 = val32 << 8; 2127 val32 |= macaddr[0]; 2128 2129 /* 2130 * Set first 4 bytes of mac address 2131 */ 2132 rtls_reg_set32(rtlsp, ID_0_REG, val32); 2133 2134 #ifdef RTLS_DEBUG 2135 if (rtls_debug & RTLS_REGCFG) { 2136 cmn_err(CE_NOTE, "%s: rtls_m_unicst 0 => 0x%x", 2137 rtlsp->ifname, val32); 2138 val32 = rtls_reg_get32(rtlsp, ID_0_REG); 2139 cmn_err(CE_NOTE, "%s: rtls_m_unicst 0 <= 0x%x", 2140 rtlsp->ifname, val32); 2141 } 2142 #endif 2143 /* 2144 * Get last 2 bytes of mac address 2145 */ 2146 val32 = macaddr[5]; 2147 val32 = val32 << 8; 2148 val32 |= macaddr[4]; 2149 2150 /* 2151 * Set last 2 bytes of mac address 2152 */ 2153 val32 |= rtls_reg_get32(rtlsp, ID_4_REG) & ~0xffff; 2154 rtls_reg_set32(rtlsp, ID_4_REG, val32); 2155 2156 #ifdef RTLS_DEBUG 2157 if (rtls_debug & RTLS_REGCFG) { 2158 cmn_err(CE_NOTE, "%s: rtls_m_unicst 1 => 0x%x", 2159 rtlsp->ifname, val32); 2160 val32 = rtls_reg_get32(rtlsp, ID_4_REG); 2161 cmn_err(CE_NOTE, "%s: rtls_m_unicst 1 <= 0x%x", 2162 rtlsp->ifname, val32); 2163 } 2164 #endif 2165 /* 2166 * Return to normal network/host communication mode 2167 */ 2168 val8 &= ~RT_93c46_MODE_CONFIG; 2169 rtls_reg_set8(rtlsp, RT_93c46_COMMOND_REG, val8); 2170 } 2171 2172 /* 2173 * rtls_chip_force_speed_duplex() -- set chip speed and duplex mode 2174 */ 2175 static void 2176 rtls_chip_force_speed_duplex(rtls_t *rtlsp) 2177 { 2178 uint16_t control; 2179 uint16_t ad_mode; 2180 uint8_t val8; 2181 2182 control = rtls_reg_get16(rtlsp, BASIC_MODE_CONTROL_REG); 2183 control &= ~BASIC_MODE_CONTROL_BITS; 2184 ad_mode = rtls_reg_get16(rtlsp, AUTO_NEGO_AD_REG); 2185 ad_mode &= ~AUTO_NEGO_MODE_BITS; 2186 2187 #ifdef RTLS_DEBUG 2188 if (rtls_debug & RTLS_TRACE) { 2189 cmn_err(CE_NOTE, "%s:rtls_chip_force_speed_duplex = %d", 2190 rtlsp->ifname, rtlsp->force_speed_duplex); 2191 } 2192 #endif 2193 switch (rtlsp->force_speed_duplex) { 2194 default: 2195 cmn_err(CE_WARN, 2196 "%s: Bad ForceSpeedDuplex = %d value, " 2197 "will use its default value 5: Anto-Negotiation", 2198 rtlsp->ifname, rtlsp->force_speed_duplex); 2199 rtlsp->force_speed_duplex = FORCE_AUTO_NEGO; 2200 control |= BASIC_MODE_AUTONEGO | BASIC_MODE_RESTAR_AUTONEGO; 2201 ad_mode |= AUTO_NEGO_100FULL | AUTO_NEGO_100HALF | 2202 AUTO_NEGO_10FULL | AUTO_NEGO_10HALF; 2203 rtlsp->stats.speed = RTLS_SPEED_UNKNOWN; 2204 rtlsp->stats.duplex = LINK_DUPLEX_UNKNOWN; 2205 break; 2206 case FORCE_AUTO_NEGO: 2207 control |= BASIC_MODE_AUTONEGO | BASIC_MODE_RESTAR_AUTONEGO; 2208 ad_mode |= AUTO_NEGO_100FULL | AUTO_NEGO_100HALF | 2209 AUTO_NEGO_10FULL | AUTO_NEGO_10HALF; 2210 if (!rtlsp->chip_error) { 2211 rtlsp->stats.speed = RTLS_SPEED_UNKNOWN; 2212 rtlsp->stats.duplex = LINK_DUPLEX_UNKNOWN; 2213 } 2214 break; 2215 case FORCE_100_FDX: 2216 /* 2217 * RTL8139 can't establish link correctly on this force mode 2218 * if the other side is not the same force mode. So We have to 2219 * realize this force mode in auto-negotiation mode advertising 2220 * 100M/Full ability only 2221 */ 2222 control |= BASIC_MODE_AUTONEGO | BASIC_MODE_RESTAR_AUTONEGO; 2223 ad_mode |= AUTO_NEGO_100FULL; 2224 rtlsp->stats.speed = RTLS_SPEED_100M; 2225 rtlsp->stats.duplex = LINK_DUPLEX_FULL; 2226 break; 2227 case FORCE_100_HDX: 2228 control |= BASIC_MODE_SPEED_100; 2229 ad_mode |= AUTO_NEGO_100HALF; 2230 rtlsp->stats.speed = RTLS_SPEED_100M; 2231 rtlsp->stats.duplex = LINK_DUPLEX_HALF; 2232 break; 2233 case FORCE_10_FDX: 2234 /* 2235 * RTL8139 can't establish link correctly on this force mode 2236 * if the other side is not the same force mode. So We have to 2237 * realize this force mode in auto-negotiation mode advertising 2238 * 10M/Full ability only 2239 */ 2240 control |= BASIC_MODE_AUTONEGO | BASIC_MODE_RESTAR_AUTONEGO; 2241 ad_mode |= AUTO_NEGO_10FULL; 2242 rtlsp->stats.speed = RTLS_SPEED_10M; 2243 rtlsp->stats.duplex = LINK_DUPLEX_FULL; 2244 break; 2245 case FORCE_10_HDX: 2246 ad_mode |= AUTO_NEGO_10HALF; 2247 rtlsp->stats.speed = RTLS_SPEED_10M; 2248 rtlsp->stats.duplex = LINK_DUPLEX_HALF; 2249 break; 2250 } 2251 2252 /* 2253 * Set auto-negotiation advertisement ability register 2254 */ 2255 rtls_reg_set16(rtlsp, AUTO_NEGO_AD_REG, ad_mode); 2256 2257 /* 2258 * Change to config register write enable mode 2259 */ 2260 val8 = rtls_reg_get8(rtlsp, RT_93c46_COMMOND_REG); 2261 val8 |= RT_93c46_MODE_CONFIG; 2262 rtls_reg_set8(rtlsp, RT_93c46_COMMOND_REG, val8); 2263 2264 /* 2265 * Set MII control register 2266 */ 2267 rtls_reg_set16(rtlsp, BASIC_MODE_CONTROL_REG, control); 2268 2269 /* 2270 * Return to normal network/host communication mode 2271 */ 2272 val8 &= ~RT_93c46_MODE_CONFIG; 2273 rtls_reg_set8(rtlsp, RT_93c46_COMMOND_REG, val8); 2274 } 2275 2276 #ifdef RTLS_DEBUG 2277 /* 2278 * rtls_reg_print() -- print out reg value(for debug use only) 2279 */ 2280 static void 2281 rtls_reg_print(rtls_t *rtlsp) 2282 { 2283 uint8_t val8; 2284 uint16_t val16; 2285 uint32_t val32; 2286 2287 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 2288 cmn_err(CE_NOTE, "%s: RT_COMMAND_REG = 0x%x", 2289 rtlsp->ifname, val8); 2290 delay(drv_usectohz(1000)); 2291 2292 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 2293 cmn_err(CE_NOTE, "%s: RT_INT_STATUS_REG = 0x%x", 2294 rtlsp->ifname, val16); 2295 delay(drv_usectohz(1000)); 2296 2297 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 2298 cmn_err(CE_NOTE, "%s: RT_INT_MASK_REG = 0x%x", 2299 rtlsp->ifname, val16); 2300 delay(drv_usectohz(1000)); 2301 2302 val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG); 2303 cmn_err(CE_NOTE, "%s: RX_CONFIG_REG = 0x%x", 2304 rtlsp->ifname, val32); 2305 delay(drv_usectohz(1000)); 2306 2307 val16 = rtls_reg_get16(rtlsp, TX_DESC_STAUS_REG); 2308 cmn_err(CE_NOTE, 2309 "%s: TX_DESC_STAUS_REG = 0x%x, cur_desc = %d", 2310 rtlsp->ifname, val16, rtlsp->tx_current_desc); 2311 delay(drv_usectohz(1000)); 2312 2313 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC0_REG); 2314 cmn_err(CE_NOTE, 2315 "%s: TX_STATUS_DESC0_REG = 0x%x", 2316 rtlsp->ifname, val32); 2317 delay(drv_usectohz(1000)); 2318 2319 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC1_REG); 2320 cmn_err(CE_NOTE, 2321 "%s: TX_STATUS_DESC1_REG = 0x%x", 2322 rtlsp->ifname, val32); 2323 delay(drv_usectohz(1000)); 2324 2325 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC2_REG); 2326 cmn_err(CE_NOTE, 2327 "%s: TX_STATUS_DESC2_REG = 0x%x", 2328 rtlsp->ifname, val32); 2329 delay(drv_usectohz(1000)); 2330 2331 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC3_REG); 2332 cmn_err(CE_NOTE, 2333 "%s: TX_STATUS_DESC3_REG = 0x%x", 2334 rtlsp->ifname, val32); 2335 delay(drv_usectohz(1000)); 2336 2337 cmn_err(CE_NOTE, 2338 "%s: in = %llu, multicast = %llu, broadcast = %llu", 2339 rtlsp->ifname, 2340 (unsigned long long)rtlsp->stats.ipackets, 2341 (unsigned long long)rtlsp->stats.multi_rcv, 2342 (unsigned long long)rtlsp->stats.brdcst_rcv); 2343 delay(drv_usectohz(1000)); 2344 } 2345 #endif 2346