xref: /titanic_51/usr/src/uts/common/io/rge/rge_chip.c (revision c4800545504378963d9f2eeb253f06899664f9f6)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 #include "rge.h"
29 
30 #define	REG32(rgep, reg)	((uint32_t *)(rgep->io_regs+(reg)))
31 #define	REG16(rgep, reg)	((uint16_t *)(rgep->io_regs+(reg)))
32 #define	REG8(rgep, reg)		((uint8_t *)(rgep->io_regs+(reg)))
33 #define	PIO_ADDR(rgep, offset)	((void *)(rgep->io_regs+(offset)))
34 
35 /*
36  * Patchable globals:
37  *
38  *	rge_autorecover
39  *		Enables/disables automatic recovery after fault detection
40  */
41 static uint32_t rge_autorecover = 1;
42 
43 /*
44  * globals:
45  */
46 #define	RGE_DBG		RGE_DBG_REGS	/* debug flag for this code	*/
47 static uint32_t rge_watchdog_count	= 1 << 16;
48 
49 /*
50  * Operating register get/set access routines
51  */
52 
53 static uint32_t rge_reg_get32(rge_t *rgep, uintptr_t regno);
54 #pragma	inline(rge_reg_get32)
55 
56 static uint32_t
57 rge_reg_get32(rge_t *rgep, uintptr_t regno)
58 {
59 	RGE_TRACE(("rge_reg_get32($%p, 0x%lx)",
60 	    (void *)rgep, regno));
61 
62 	return (ddi_get32(rgep->io_handle, REG32(rgep, regno)));
63 }
64 
65 static void rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data);
66 #pragma	inline(rge_reg_put32)
67 
68 static void
69 rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data)
70 {
71 	RGE_TRACE(("rge_reg_put32($%p, 0x%lx, 0x%x)",
72 	    (void *)rgep, regno, data));
73 
74 	ddi_put32(rgep->io_handle, REG32(rgep, regno), data);
75 }
76 
77 static void rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits);
78 #pragma	inline(rge_reg_set32)
79 
80 static void
81 rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits)
82 {
83 	uint32_t regval;
84 
85 	RGE_TRACE(("rge_reg_set32($%p, 0x%lx, 0x%x)",
86 	    (void *)rgep, regno, bits));
87 
88 	regval = rge_reg_get32(rgep, regno);
89 	regval |= bits;
90 	rge_reg_put32(rgep, regno, regval);
91 }
92 
93 static void rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits);
94 #pragma	inline(rge_reg_clr32)
95 
96 static void
97 rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits)
98 {
99 	uint32_t regval;
100 
101 	RGE_TRACE(("rge_reg_clr32($%p, 0x%lx, 0x%x)",
102 	    (void *)rgep, regno, bits));
103 
104 	regval = rge_reg_get32(rgep, regno);
105 	regval &= ~bits;
106 	rge_reg_put32(rgep, regno, regval);
107 }
108 
109 static uint16_t rge_reg_get16(rge_t *rgep, uintptr_t regno);
110 #pragma	inline(rge_reg_get16)
111 
112 static uint16_t
113 rge_reg_get16(rge_t *rgep, uintptr_t regno)
114 {
115 	RGE_TRACE(("rge_reg_get16($%p, 0x%lx)",
116 	    (void *)rgep, regno));
117 
118 	return (ddi_get16(rgep->io_handle, REG16(rgep, regno)));
119 }
120 
121 static void rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data);
122 #pragma	inline(rge_reg_put16)
123 
124 static void
125 rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data)
126 {
127 	RGE_TRACE(("rge_reg_put16($%p, 0x%lx, 0x%x)",
128 	    (void *)rgep, regno, data));
129 
130 	ddi_put16(rgep->io_handle, REG16(rgep, regno), data);
131 }
132 
133 static void rge_reg_set16(rge_t *rgep, uintptr_t regno, uint16_t bits);
134 #pragma	inline(rge_reg_set16)
135 
136 static void
137 rge_reg_set16(rge_t *rgep, uintptr_t regno, uint16_t bits)
138 {
139 	uint16_t regval;
140 
141 	RGE_TRACE(("rge_reg_set16($%p, 0x%lx, 0x%x)",
142 	    (void *)rgep, regno, bits));
143 
144 	regval = rge_reg_get16(rgep, regno);
145 	regval |= bits;
146 	rge_reg_put16(rgep, regno, regval);
147 }
148 
149 static void rge_reg_clr16(rge_t *rgep, uintptr_t regno, uint16_t bits);
150 #pragma	inline(rge_reg_clr16)
151 
152 static void
153 rge_reg_clr16(rge_t *rgep, uintptr_t regno, uint16_t bits)
154 {
155 	uint16_t regval;
156 
157 	RGE_TRACE(("rge_reg_clr16($%p, 0x%lx, 0x%x)",
158 	    (void *)rgep, regno, bits));
159 
160 	regval = rge_reg_get16(rgep, regno);
161 	regval &= ~bits;
162 	rge_reg_put16(rgep, regno, regval);
163 }
164 
165 static uint8_t rge_reg_get8(rge_t *rgep, uintptr_t regno);
166 #pragma	inline(rge_reg_get8)
167 
168 static uint8_t
169 rge_reg_get8(rge_t *rgep, uintptr_t regno)
170 {
171 	RGE_TRACE(("rge_reg_get8($%p, 0x%lx)",
172 	    (void *)rgep, regno));
173 
174 	return (ddi_get8(rgep->io_handle, REG8(rgep, regno)));
175 }
176 
177 static void rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data);
178 #pragma	inline(rge_reg_put8)
179 
180 static void
181 rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data)
182 {
183 	RGE_TRACE(("rge_reg_put8($%p, 0x%lx, 0x%x)",
184 	    (void *)rgep, regno, data));
185 
186 	ddi_put8(rgep->io_handle, REG8(rgep, regno), data);
187 }
188 
189 static void rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits);
190 #pragma	inline(rge_reg_set8)
191 
192 static void
193 rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits)
194 {
195 	uint8_t regval;
196 
197 	RGE_TRACE(("rge_reg_set8($%p, 0x%lx, 0x%x)",
198 	    (void *)rgep, regno, bits));
199 
200 	regval = rge_reg_get8(rgep, regno);
201 	regval |= bits;
202 	rge_reg_put8(rgep, regno, regval);
203 }
204 
205 static void rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits);
206 #pragma	inline(rge_reg_clr8)
207 
208 static void
209 rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits)
210 {
211 	uint8_t regval;
212 
213 	RGE_TRACE(("rge_reg_clr8($%p, 0x%lx, 0x%x)",
214 	    (void *)rgep, regno, bits));
215 
216 	regval = rge_reg_get8(rgep, regno);
217 	regval &= ~bits;
218 	rge_reg_put8(rgep, regno, regval);
219 }
220 
221 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii);
222 #pragma	no_inline(rge_mii_get16)
223 
224 uint16_t
225 rge_mii_get16(rge_t *rgep, uintptr_t mii)
226 {
227 	uint32_t regval;
228 	uint32_t val32;
229 	uint32_t i;
230 
231 	regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT;
232 	rge_reg_put32(rgep, PHY_ACCESS_REG, regval);
233 
234 	/*
235 	 * Waiting for PHY reading OK
236 	 */
237 	for (i = 0; i < PHY_RESET_LOOP; i++) {
238 		drv_usecwait(1000);
239 		val32 = rge_reg_get32(rgep, PHY_ACCESS_REG);
240 		if (val32 & PHY_ACCESS_WR_FLAG)
241 			return ((uint16_t)(val32 & 0xffff));
242 	}
243 
244 	RGE_REPORT((rgep, "rge_mii_get16(0x%x) fail, val = %x", mii, val32));
245 	return ((uint16_t)~0u);
246 }
247 
248 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data);
249 #pragma	no_inline(rge_mii_put16)
250 
251 void
252 rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data)
253 {
254 	uint32_t regval;
255 	uint32_t val32;
256 	uint32_t i;
257 
258 	regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT;
259 	regval |= data & PHY_DATA_MASK;
260 	regval |= PHY_ACCESS_WR_FLAG;
261 	rge_reg_put32(rgep, PHY_ACCESS_REG, regval);
262 
263 	/*
264 	 * Waiting for PHY writing OK
265 	 */
266 	for (i = 0; i < PHY_RESET_LOOP; i++) {
267 		drv_usecwait(1000);
268 		val32 = rge_reg_get32(rgep, PHY_ACCESS_REG);
269 		if (!(val32 & PHY_ACCESS_WR_FLAG))
270 			return;
271 	}
272 	RGE_REPORT((rgep, "rge_mii_put16(0x%lx, 0x%x) fail",
273 	    mii, data));
274 }
275 
276 void rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data);
277 #pragma	no_inline(rge_ephy_put16)
278 
279 void
280 rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data)
281 {
282 	uint32_t regval;
283 	uint32_t val32;
284 	uint32_t i;
285 
286 	regval = (emii & EPHY_REG_MASK) << EPHY_REG_SHIFT;
287 	regval |= data & EPHY_DATA_MASK;
288 	regval |= EPHY_ACCESS_WR_FLAG;
289 	rge_reg_put32(rgep, EPHY_ACCESS_REG, regval);
290 
291 	/*
292 	 * Waiting for PHY writing OK
293 	 */
294 	for (i = 0; i < PHY_RESET_LOOP; i++) {
295 		drv_usecwait(1000);
296 		val32 = rge_reg_get32(rgep, EPHY_ACCESS_REG);
297 		if (!(val32 & EPHY_ACCESS_WR_FLAG))
298 			return;
299 	}
300 	RGE_REPORT((rgep, "rge_ephy_put16(0x%lx, 0x%x) fail",
301 	    emii, data));
302 }
303 
304 /*
305  * Atomically shift a 32-bit word left, returning
306  * the value it had *before* the shift was applied
307  */
308 static uint32_t rge_atomic_shl32(uint32_t *sp, uint_t count);
309 #pragma	inline(rge_mii_put16)
310 
311 static uint32_t
312 rge_atomic_shl32(uint32_t *sp, uint_t count)
313 {
314 	uint32_t oldval;
315 	uint32_t newval;
316 
317 	/* ATOMICALLY */
318 	do {
319 		oldval = *sp;
320 		newval = oldval << count;
321 	} while (cas32(sp, oldval, newval) != oldval);
322 
323 	return (oldval);
324 }
325 
326 /*
327  * PHY operation routines
328  */
329 #if	RGE_DEBUGGING
330 
331 static void
332 rge_phydump(rge_t *rgep)
333 {
334 	uint16_t regs[32];
335 	int i;
336 
337 	ASSERT(mutex_owned(rgep->genlock));
338 
339 	for (i = 0; i < 32; ++i) {
340 		regs[i] = rge_mii_get16(rgep, i);
341 	}
342 
343 	for (i = 0; i < 32; i += 8)
344 		RGE_DEBUG(("rge_phydump: "
345 		    "0x%04x %04x %04x %04x %04x %04x %04x %04x",
346 		    regs[i+0], regs[i+1], regs[i+2], regs[i+3],
347 		    regs[i+4], regs[i+5], regs[i+6], regs[i+7]));
348 }
349 
350 #endif	/* RGE_DEBUGGING */
351 
352 /*
353  * Basic low-level function to probe for a PHY
354  *
355  * Returns TRUE if the PHY responds with valid data, FALSE otherwise
356  */
357 static boolean_t
358 rge_phy_probe(rge_t *rgep)
359 {
360 	uint16_t phy_status;
361 
362 	ASSERT(mutex_owned(rgep->genlock));
363 
364 	/*
365 	 * Read the MII_STATUS register twice, in
366 	 * order to clear any sticky bits (but they should
367 	 * have been cleared by the RESET, I think).
368 	 */
369 	phy_status = rge_mii_get16(rgep, MII_STATUS);
370 	phy_status = rge_mii_get16(rgep, MII_STATUS);
371 	RGE_DEBUG(("rge_phy_probe: status 0x%x", phy_status));
372 
373 	/*
374 	 * Now check the value read; it should have at least one bit set
375 	 * (for the device capabilities) and at least one clear (one of
376 	 * the error bits). So if we see all 0s or all 1s, there's a
377 	 * problem.  In particular, rge_mii_get16() returns all 1s if
378 	 * communications fails ...
379 	 */
380 	switch (phy_status) {
381 	case 0x0000:
382 	case 0xffff:
383 		return (B_FALSE);
384 
385 	default :
386 		return (B_TRUE);
387 	}
388 }
389 
390 static void
391 rge_phy_check(rge_t *rgep)
392 {
393 	uint16_t gig_ctl;
394 
395 	if (rgep->param_link_up  == LINK_STATE_DOWN) {
396 		/*
397 		 * RTL8169S/8110S PHY has the "PCS bug".  Need reset PHY
398 		 * every 15 seconds whin link down & advertise is 1000.
399 		 */
400 		if (rgep->chipid.phy_ver == PHY_VER_S) {
401 			gig_ctl = rge_mii_get16(rgep, MII_1000BASE_T_CONTROL);
402 			if (gig_ctl & MII_1000BT_CTL_ADV_FDX) {
403 				rgep->link_down_count++;
404 				if (rgep->link_down_count > 15) {
405 					(void) rge_phy_reset(rgep);
406 					rgep->stats.phy_reset++;
407 					rgep->link_down_count = 0;
408 				}
409 			}
410 		}
411 	} else {
412 		rgep->link_down_count = 0;
413 	}
414 }
415 
416 /*
417  * Basic low-level function to reset the PHY.
418  * Doesn't incorporate any special-case workarounds.
419  *
420  * Returns TRUE on success, FALSE if the RESET bit doesn't clear
421  */
422 boolean_t
423 rge_phy_reset(rge_t *rgep)
424 {
425 	uint16_t control;
426 	uint_t count;
427 
428 	/*
429 	 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear
430 	 */
431 	control = rge_mii_get16(rgep, MII_CONTROL);
432 	rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET);
433 	for (count = 0; count < 5; count++) {
434 		drv_usecwait(100);
435 		control = rge_mii_get16(rgep, MII_CONTROL);
436 		if (BIC(control, MII_CONTROL_RESET))
437 			return (B_TRUE);
438 	}
439 
440 	RGE_REPORT((rgep, "rge_phy_reset: FAILED, control now 0x%x", control));
441 	return (B_FALSE);
442 }
443 
444 /*
445  * Synchronise the PHY's speed/duplex/autonegotiation capabilities
446  * and advertisements with the required settings as specified by the various
447  * param_* variables that can be poked via the NDD interface.
448  *
449  * We always reset the PHY and reprogram *all* the relevant registers,
450  * not just those changed.  This should cause the link to go down, and then
451  * back up again once the link is stable and autonegotiation (if enabled)
452  * is complete.  We should get a link state change interrupt somewhere along
453  * the way ...
454  *
455  * NOTE: <genlock> must already be held by the caller
456  */
457 void
458 rge_phy_update(rge_t *rgep)
459 {
460 	boolean_t adv_autoneg;
461 	boolean_t adv_pause;
462 	boolean_t adv_asym_pause;
463 	boolean_t adv_1000fdx;
464 	boolean_t adv_1000hdx;
465 	boolean_t adv_100fdx;
466 	boolean_t adv_100hdx;
467 	boolean_t adv_10fdx;
468 	boolean_t adv_10hdx;
469 
470 	uint16_t control;
471 	uint16_t gigctrl;
472 	uint16_t anar;
473 
474 	ASSERT(mutex_owned(rgep->genlock));
475 
476 	RGE_DEBUG(("rge_phy_update: autoneg %d "
477 	    "pause %d asym_pause %d "
478 	    "1000fdx %d 1000hdx %d "
479 	    "100fdx %d 100hdx %d "
480 	    "10fdx %d 10hdx %d ",
481 	    rgep->param_adv_autoneg,
482 	    rgep->param_adv_pause, rgep->param_adv_asym_pause,
483 	    rgep->param_adv_1000fdx, rgep->param_adv_1000hdx,
484 	    rgep->param_adv_100fdx, rgep->param_adv_100hdx,
485 	    rgep->param_adv_10fdx, rgep->param_adv_10hdx));
486 
487 	control = gigctrl = anar = 0;
488 
489 	/*
490 	 * PHY settings are normally based on the param_* variables,
491 	 * but if any loopback mode is in effect, that takes precedence.
492 	 *
493 	 * RGE supports MAC-internal loopback, PHY-internal loopback,
494 	 * and External loopback at a variety of speeds (with a special
495 	 * cable).  In all cases, autoneg is turned OFF, full-duplex
496 	 * is turned ON, and the speed/mastership is forced.
497 	 */
498 	switch (rgep->param_loop_mode) {
499 	case RGE_LOOP_NONE:
500 	default:
501 		adv_autoneg = rgep->param_adv_autoneg;
502 		adv_pause = rgep->param_adv_pause;
503 		adv_asym_pause = rgep->param_adv_asym_pause;
504 		adv_1000fdx = rgep->param_adv_1000fdx;
505 		adv_1000hdx = rgep->param_adv_1000hdx;
506 		adv_100fdx = rgep->param_adv_100fdx;
507 		adv_100hdx = rgep->param_adv_100hdx;
508 		adv_10fdx = rgep->param_adv_10fdx;
509 		adv_10hdx = rgep->param_adv_10hdx;
510 		break;
511 
512 	case RGE_LOOP_INTERNAL_PHY:
513 	case RGE_LOOP_INTERNAL_MAC:
514 		adv_autoneg = adv_pause = adv_asym_pause = B_FALSE;
515 		adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE;
516 		adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE;
517 		rgep->param_link_duplex = LINK_DUPLEX_FULL;
518 
519 		switch (rgep->param_loop_mode) {
520 		case RGE_LOOP_INTERNAL_PHY:
521 			if (rgep->chipid.mac_ver != MAC_VER_8101E) {
522 				rgep->param_link_speed = 1000;
523 				adv_1000fdx = B_TRUE;
524 			} else {
525 				rgep->param_link_speed = 100;
526 				adv_100fdx = B_TRUE;
527 			}
528 			control = MII_CONTROL_LOOPBACK;
529 			break;
530 
531 		case RGE_LOOP_INTERNAL_MAC:
532 			if (rgep->chipid.mac_ver != MAC_VER_8101E) {
533 				rgep->param_link_speed = 1000;
534 				adv_1000fdx = B_TRUE;
535 			} else {
536 				rgep->param_link_speed = 100;
537 				adv_100fdx = B_TRUE;
538 			break;
539 		}
540 	}
541 
542 	RGE_DEBUG(("rge_phy_update: autoneg %d "
543 	    "pause %d asym_pause %d "
544 	    "1000fdx %d 1000hdx %d "
545 	    "100fdx %d 100hdx %d "
546 	    "10fdx %d 10hdx %d ",
547 	    adv_autoneg,
548 	    adv_pause, adv_asym_pause,
549 	    adv_1000fdx, adv_1000hdx,
550 	    adv_100fdx, adv_100hdx,
551 	    adv_10fdx, adv_10hdx));
552 
553 	/*
554 	 * We should have at least one technology capability set;
555 	 * if not, we select a default of 1000Mb/s full-duplex
556 	 */
557 	if (!adv_1000fdx && !adv_100fdx && !adv_10fdx &&
558 	    !adv_1000hdx && !adv_100hdx && !adv_10hdx) {
559 		if (rgep->chipid.mac_ver != MAC_VER_8101E)
560 			adv_1000fdx = B_TRUE;
561 		} else {
562 			adv_1000fdx = B_FALSE;
563 			adv_100fdx = B_TRUE;
564 		}
565 	}
566 
567 	/*
568 	 * Now transform the adv_* variables into the proper settings
569 	 * of the PHY registers ...
570 	 *
571 	 * If autonegotiation is (now) enabled, we want to trigger
572 	 * a new autonegotiation cycle once the PHY has been
573 	 * programmed with the capabilities to be advertised.
574 	 *
575 	 * RTL8169/8110 doesn't support 1000Mb/s half-duplex.
576 	 */
577 	if (adv_autoneg)
578 		control |= MII_CONTROL_ANE|MII_CONTROL_RSAN;
579 
580 	if (adv_1000fdx)
581 		control |= MII_CONTROL_1000MB|MII_CONTROL_FDUPLEX;
582 	else if (adv_1000hdx)
583 		control |= MII_CONTROL_1000MB;
584 	else if (adv_100fdx)
585 		control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX;
586 	else if (adv_100hdx)
587 		control |= MII_CONTROL_100MB;
588 	else if (adv_10fdx)
589 		control |= MII_CONTROL_FDUPLEX;
590 	else if (adv_10hdx)
591 		control |= 0;
592 	else
593 		{ _NOTE(EMPTY); }	/* Can't get here anyway ...	*/
594 
595 	if (adv_1000fdx) {
596 		gigctrl |= MII_1000BT_CTL_ADV_FDX;
597 		/*
598 		 * Chipset limitation: need set other capabilities to true
599 		 */
600 		if (rgep->chipid.is_pcie)
601 			adv_1000hdx = B_TRUE;
602 		adv_100fdx = B_TRUE;
603 		adv_100hdx  = B_TRUE;
604 		adv_10fdx = B_TRUE;
605 		adv_10hdx = B_TRUE;
606 	}
607 
608 	if (adv_1000hdx)
609 		gigctrl |= MII_1000BT_CTL_ADV_HDX;
610 
611 	if (adv_100fdx)
612 		anar |= MII_ABILITY_100BASE_TX_FD;
613 	if (adv_100hdx)
614 		anar |= MII_ABILITY_100BASE_TX;
615 	if (adv_10fdx)
616 		anar |= MII_ABILITY_10BASE_T_FD;
617 	if (adv_10hdx)
618 		anar |= MII_ABILITY_10BASE_T;
619 
620 	if (adv_pause)
621 		anar |= MII_ABILITY_PAUSE;
622 	if (adv_asym_pause)
623 		anar |= MII_ABILITY_ASYM_PAUSE;
624 
625 	/*
626 	 * Munge in any other fixed bits we require ...
627 	 */
628 	anar |= MII_AN_SELECTOR_8023;
629 
630 	/*
631 	 * Restart the PHY and write the new values.  Note the
632 	 * time, so that we can say whether subsequent link state
633 	 * changes can be attributed to our reprogramming the PHY
634 	 */
635 	rge_phy_init(rgep);
636 	rge_mii_put16(rgep, MII_AN_ADVERT, anar);
637 	rge_mii_put16(rgep, MII_1000BASE_T_CONTROL, gigctrl);
638 	rge_mii_put16(rgep, MII_CONTROL, control);
639 
640 	RGE_DEBUG(("rge_phy_update: anar <- 0x%x", anar));
641 	RGE_DEBUG(("rge_phy_update: control <- 0x%x", control));
642 	RGE_DEBUG(("rge_phy_update: gigctrl <- 0x%x", gigctrl));
643 }
644 
645 void rge_phy_init(rge_t *rgep);
646 #pragma	no_inline(rge_phy_init)
647 
648 void
649 rge_phy_init(rge_t *rgep)
650 {
651 	rgep->phy_mii_addr = 1;
652 
653 	/*
654 	 * Below phy config steps are copied from the Programming Guide
655 	 * (there's no detail comments for these steps.)
656 	 */
657 	switch (rgep->chipid.mac_ver) {
658 	case MAC_VER_8169S_D:
659 	case MAC_VER_8169S_E :
660 		rge_mii_put16(rgep, PHY_1F_REG, 0x0001);
661 		rge_mii_put16(rgep, PHY_15_REG, 0x1000);
662 		rge_mii_put16(rgep, PHY_18_REG, 0x65c7);
663 		rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000);
664 		rge_mii_put16(rgep, PHY_ID_REG_2, 0x00a1);
665 		rge_mii_put16(rgep, PHY_ID_REG_1, 0x0008);
666 		rge_mii_put16(rgep, PHY_BMSR_REG, 0x1020);
667 		rge_mii_put16(rgep, PHY_BMCR_REG, 0x1000);
668 		rge_mii_put16(rgep, PHY_ANAR_REG, 0x0800);
669 		rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000);
670 		rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000);
671 		rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41);
672 		rge_mii_put16(rgep, PHY_ID_REG_1, 0xde60);
673 		rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140);
674 		rge_mii_put16(rgep, PHY_BMCR_REG, 0x0077);
675 		rge_mii_put16(rgep, PHY_ANAR_REG, 0x7800);
676 		rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000);
677 		rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000);
678 		rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01);
679 		rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20);
680 		rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95);
681 		rge_mii_put16(rgep, PHY_BMCR_REG, 0xfa00);
682 		rge_mii_put16(rgep, PHY_ANAR_REG, 0xa800);
683 		rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000);
684 		rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000);
685 		rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41);
686 		rge_mii_put16(rgep, PHY_ID_REG_1, 0xde20);
687 		rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140);
688 		rge_mii_put16(rgep, PHY_BMCR_REG, 0x00bb);
689 		rge_mii_put16(rgep, PHY_ANAR_REG, 0xb800);
690 		rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000);
691 		rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000);
692 		rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01);
693 		rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20);
694 		rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95);
695 		rge_mii_put16(rgep, PHY_BMCR_REG, 0xbf00);
696 		rge_mii_put16(rgep, PHY_ANAR_REG, 0xf800);
697 		rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000);
698 		rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000);
699 		rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
700 		rge_mii_put16(rgep, PHY_0B_REG, 0x0000);
701 		break;
702 
703 	case MAC_VER_8169SB:
704 		rge_mii_put16(rgep, PHY_1F_REG, 0x0001);
705 		rge_mii_put16(rgep, PHY_1B_REG, 0xD41E);
706 		rge_mii_put16(rgep, PHY_0E_REG, 0x7bff);
707 		rge_mii_put16(rgep, PHY_GBCR_REG, GBCR_DEFAULT);
708 		rge_mii_put16(rgep, PHY_1F_REG, 0x0002);
709 		rge_mii_put16(rgep, PHY_BMSR_REG, 0x90D0);
710 		rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
711 		break;
712 
713 	case MAC_VER_8169SC:
714 		rge_mii_put16(rgep, PHY_1F_REG, 0x0001);
715 		rge_mii_put16(rgep, PHY_ANER_REG, 0x0078);
716 		rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x05dc);
717 		rge_mii_put16(rgep, PHY_GBCR_REG, 0x2672);
718 		rge_mii_put16(rgep, PHY_GBSR_REG, 0x6a14);
719 		rge_mii_put16(rgep, PHY_0B_REG, 0x7cb0);
720 		rge_mii_put16(rgep, PHY_0C_REG, 0xdb80);
721 		rge_mii_put16(rgep, PHY_1B_REG, 0xc414);
722 		rge_mii_put16(rgep, PHY_1C_REG, 0xef03);
723 		rge_mii_put16(rgep, PHY_1D_REG, 0x3dc8);
724 		rge_mii_put16(rgep, PHY_1F_REG, 0x0003);
725 		rge_mii_put16(rgep, PHY_13_REG, 0x0600);
726 		rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
727 		break;
728 
729 	case MAC_VER_8168:
730 		rge_mii_put16(rgep, PHY_1F_REG, 0x0001);
731 		rge_mii_put16(rgep, PHY_ANER_REG, 0x00aa);
732 		rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x3173);
733 		rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x08fc);
734 		rge_mii_put16(rgep, PHY_GBCR_REG, 0xe2d0);
735 		rge_mii_put16(rgep, PHY_0B_REG, 0x941a);
736 		rge_mii_put16(rgep, PHY_18_REG, 0x65fe);
737 		rge_mii_put16(rgep, PHY_1C_REG, 0x1e02);
738 		rge_mii_put16(rgep, PHY_1F_REG, 0x0002);
739 		rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x103e);
740 		rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
741 		break;
742 
743 	case MAC_VER_8168B_B:
744 	case MAC_VER_8168B_C:
745 		rge_mii_put16(rgep, PHY_1F_REG, 0x0001);
746 		rge_mii_put16(rgep, PHY_0B_REG, 0x94b0);
747 		rge_mii_put16(rgep, PHY_1B_REG, 0xc416);
748 		rge_mii_put16(rgep, PHY_1F_REG, 0x0003);
749 		rge_mii_put16(rgep, PHY_12_REG, 0x6096);
750 		rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
751 		break;
752 	}
753 }
754 
755 void rge_chip_ident(rge_t *rgep);
756 #pragma	no_inline(rge_chip_ident)
757 
758 void
759 rge_chip_ident(rge_t *rgep)
760 {
761 	chip_id_t *chip = &rgep->chipid;
762 	uint32_t val32;
763 	uint16_t val16;
764 
765 	/*
766 	 * Read and record MAC version
767 	 */
768 	val32 = rge_reg_get32(rgep, TX_CONFIG_REG);
769 	val32 &= HW_VERSION_ID_0 | HW_VERSION_ID_1;
770 	chip->mac_ver = val32;
771 	switch (chip->mac_ver) {
772 	case MAC_VER_8168:
773 	case MAC_VER_8168B_B:
774 	case MAC_VER_8168B_C:
775 	case MAC_VER_8101E:
776 		chip->is_pcie = B_TRUE;
777 		break;
778 
779 	default:
780 		chip->is_pcie = B_FALSE;
781 		break;
782 	}
783 
784 	/*
785 	 * Read and record PHY version
786 	 */
787 	val16 = rge_mii_get16(rgep, PHY_ID_REG_2);
788 	val16 &= PHY_VER_MASK;
789 	chip->phy_ver = val16;
790 
791 	/* set pci latency timer */
792 	if (chip->mac_ver == MAC_VER_8169 ||
793 	    chip->mac_ver == MAC_VER_8169S_D ||
794 	    chip->mac_ver == MAC_VER_8169SC)
795 		pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40);
796 
797 	if (chip->mac_ver == MAC_VER_8169SC) {
798 		val16 = rge_reg_get16(rgep, RT_CONFIG_1_REG);
799 		val16 &= 0x0300;
800 		if (val16 == 0x1)	/* 66Mhz PCI */
801 			pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ff00ff);
802 		else if (val16 == 0x0) /* 33Mhz PCI */
803 			pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ffff00);
804 	}
805 
806 	/*
807 	 * PCIE chipset require the Rx buffer start address must be
808 	 * 8-byte alignment and the Rx buffer size must be multiple of 8.
809 	 * We'll just use bcopy in receive procedure for the PCIE chipset.
810 	 */
811 	if (chip->is_pcie) {
812 		rgep->chip_flags |= CHIP_FLAG_FORCE_BCOPY;
813 		if (rgep->default_mtu > ETHERMTU) {
814 			rge_notice(rgep, "Jumbo packets not supported "
815 			    "for this PCIE chipset");
816 			rgep->default_mtu = ETHERMTU;
817 		}
818 	}
819 	if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY)
820 		rgep->head_room = 0;
821 	else
822 		rgep->head_room = RGE_HEADROOM;
823 
824 	/*
825 	 * Initialize other variables.
826 	 */
827 	if (rgep->default_mtu < ETHERMTU || rgep->default_mtu > RGE_JUMBO_MTU)
828 		rgep->default_mtu = ETHERMTU;
829 	if (rgep->default_mtu > ETHERMTU) {
830 		rgep->rxbuf_size = RGE_BUFF_SIZE_JUMBO;
831 		rgep->txbuf_size = RGE_BUFF_SIZE_JUMBO;
832 		rgep->ethmax_size = RGE_JUMBO_SIZE;
833 	} else {
834 		rgep->rxbuf_size = RGE_BUFF_SIZE_STD;
835 		rgep->txbuf_size = RGE_BUFF_SIZE_STD;
836 		rgep->ethmax_size = ETHERMAX;
837 	}
838 	chip->rxconfig = RX_CONFIG_DEFAULT;
839 	chip->txconfig = TX_CONFIG_DEFAULT;
840 
841 	RGE_TRACE(("%s: MAC version = %x, PHY version = %x",
842 	    rgep->ifname, chip->mac_ver, chip->phy_ver));
843 }
844 
845 /*
846  * Perform first-stage chip (re-)initialisation, using only config-space
847  * accesses:
848  *
849  * + Read the vendor/device/revision/subsystem/cache-line-size registers,
850  *   returning the data in the structure pointed to by <idp>.
851  * + Enable Memory Space accesses.
852  * + Enable Bus Mastering according.
853  */
854 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp);
855 #pragma	no_inline(rge_chip_cfg_init)
856 
857 void
858 rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp)
859 {
860 	ddi_acc_handle_t handle;
861 	uint16_t commd;
862 
863 	handle = rgep->cfg_handle;
864 
865 	/*
866 	 * Save PCI cache line size and subsystem vendor ID
867 	 */
868 	cidp->command = pci_config_get16(handle, PCI_CONF_COMM);
869 	cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID);
870 	cidp->device = pci_config_get16(handle, PCI_CONF_DEVID);
871 	cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID);
872 	cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID);
873 	cidp->revision = pci_config_get8(handle, PCI_CONF_REVID);
874 	cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ);
875 	cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER);
876 
877 	/*
878 	 * Turn on Master Enable (DMA) and IO Enable bits.
879 	 * Enable PCI Memory Space accesses
880 	 */
881 	commd = cidp->command;
882 	commd |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO;
883 	pci_config_put16(handle, PCI_CONF_COMM, commd);
884 
885 	RGE_DEBUG(("rge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x",
886 	    cidp->vendor, cidp->device, cidp->revision));
887 	RGE_DEBUG(("rge_chip_cfg_init: subven 0x%x subdev 0x%x",
888 	    cidp->subven, cidp->subdev));
889 	RGE_DEBUG(("rge_chip_cfg_init: clsize %d latency %d command 0x%x",
890 	    cidp->clsize, cidp->latency, cidp->command));
891 }
892 
893 int rge_chip_reset(rge_t *rgep);
894 #pragma	no_inline(rge_chip_reset)
895 
896 int
897 rge_chip_reset(rge_t *rgep)
898 {
899 	int i;
900 	uint8_t val8;
901 
902 	/*
903 	 * Chip should be in STOP state
904 	 */
905 	rge_reg_clr8(rgep, RT_COMMAND_REG,
906 	    RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
907 
908 	/*
909 	 * Disable interrupt
910 	 */
911 	rgep->int_mask = INT_MASK_NONE;
912 	rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask);
913 
914 	/*
915 	 * Clear pended interrupt
916 	 */
917 	rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL);
918 
919 	/*
920 	 * Reset chip
921 	 */
922 	rge_reg_set8(rgep, RT_COMMAND_REG, RT_COMMAND_RESET);
923 
924 	/*
925 	 * Wait for reset success
926 	 */
927 	for (i = 0; i < CHIP_RESET_LOOP; i++) {
928 		drv_usecwait(10);
929 		val8 = rge_reg_get8(rgep, RT_COMMAND_REG);
930 		if (!(val8 & RT_COMMAND_RESET)) {
931 			rgep->rge_chip_state = RGE_CHIP_RESET;
932 			return (0);
933 		}
934 	}
935 	RGE_REPORT((rgep, "rge_chip_reset fail."));
936 	return (-1);
937 }
938 
939 void rge_chip_init(rge_t *rgep);
940 #pragma	no_inline(rge_chip_init)
941 
942 void
943 rge_chip_init(rge_t *rgep)
944 {
945 	uint32_t val32;
946 	uint32_t val16;
947 	uint32_t *hashp;
948 	chip_id_t *chip = &rgep->chipid;
949 
950 	if (chip->is_pcie) {
951 		/*
952 		 * Increase the threshold voltage of RX sensitivity
953 		 */
954 		if (chip->mac_ver != MAC_VER_8168)
955 			rge_ephy_put16(rgep, 0x01, 0x1bd3);
956 
957 		val16 = rge_reg_get8(rgep, PHY_STATUS_REG);
958 		val16 = 0x12<<8 | val16;
959 		if (rgep->chipid.mac_ver != MAC_VER_8101E &&
960 		    rgep->chipid.mac_ver != MAC_VER_8168B_C) {
961 			rge_reg_put16(rgep, PHY_STATUS_REG, val16);
962 			rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00021c01);
963 			rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f088);
964 			rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00004000);
965 			rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f0b0);
966 			rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x0000f068);
967 			val32 = rge_reg_get32(rgep, RT_CSI_DATA_REG);
968 			val32 |= 0x7000;
969 			val32 &= 0xffff5fff;
970 			rge_reg_put32(rgep, RT_CSI_DATA_REG, val32);
971 			rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f068);
972 		}
973 	}
974 
975 	/*
976 	 * Config MII register
977 	 */
978 	rgep->param_link_up = LINK_STATE_DOWN;
979 	rge_phy_update(rgep);
980 
981 	/*
982 	 * Enable Rx checksum offload.
983 	 *  Then for vlan support, we must enable receive vlan de-tagging.
984 	 *  Otherwise, there'll be checksum error.
985 	 */
986 	val16 = rge_reg_get16(rgep, CPLUS_COMMAND_REG);
987 	val16 |= RX_CKSM_OFFLOAD | RX_VLAN_DETAG;
988 	if (chip->mac_ver == MAC_VER_8169S_D) {
989 		val16 |= CPLUS_BIT14 | MUL_PCI_RW_ENABLE;
990 		rge_reg_put8(rgep, RESV_82_REG, 0x01);
991 	}
992 	rge_reg_put16(rgep, CPLUS_COMMAND_REG, val16 & (~0x03));
993 
994 	/*
995 	 * Start transmit/receive before set tx/rx configuration register
996 	 */
997 	if (!chip->is_pcie)
998 		rge_reg_set8(rgep, RT_COMMAND_REG,
999 		    RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
1000 
1001 	/*
1002 	 * Set dump tally counter register
1003 	 */
1004 	val32 = rgep->dma_area_stats.cookie.dmac_laddress >> 32;
1005 	rge_reg_put32(rgep, DUMP_COUNTER_REG_1, val32);
1006 	val32 = rge_reg_get32(rgep, DUMP_COUNTER_REG_0);
1007 	val32 &= DUMP_COUNTER_REG_RESV;
1008 	val32 |= rgep->dma_area_stats.cookie.dmac_laddress;
1009 	rge_reg_put32(rgep, DUMP_COUNTER_REG_0, val32);
1010 
1011 	/*
1012 	 * Change to config register write enable mode
1013 	 */
1014 	rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1015 
1016 	/*
1017 	 * Set Tx/Rx maximum packet size
1018 	 */
1019 	if (rgep->default_mtu > ETHERMTU) {
1020 		rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_JUMBO);
1021 		rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_JUMBO);
1022 	} else if (rgep->chipid.mac_ver != MAC_VER_8101E) {
1023 		rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD);
1024 		rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD);
1025 	} else {
1026 		rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD_8101E);
1027 		rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD_8101E);
1028 	}
1029 
1030 	/*
1031 	 * Set receive configuration register
1032 	 */
1033 	val32 = rge_reg_get32(rgep, RX_CONFIG_REG);
1034 	val32 &= RX_CONFIG_REG_RESV;
1035 	if (rgep->promisc)
1036 		val32 |= RX_ACCEPT_ALL_PKT;
1037 	rge_reg_put32(rgep, RX_CONFIG_REG, val32 | chip->rxconfig);
1038 
1039 	/*
1040 	 * Set transmit configuration register
1041 	 */
1042 	val32 = rge_reg_get32(rgep, TX_CONFIG_REG);
1043 	val32 &= TX_CONFIG_REG_RESV;
1044 	rge_reg_put32(rgep, TX_CONFIG_REG, val32 | chip->txconfig);
1045 
1046 	/*
1047 	 * Set Tx/Rx descriptor register
1048 	 */
1049 	val32 = rgep->tx_desc.cookie.dmac_laddress;
1050 	rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_LO_REG, val32);
1051 	val32 = rgep->tx_desc.cookie.dmac_laddress >> 32;
1052 	rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_HI_REG, val32);
1053 	rge_reg_put32(rgep, HIGH_TX_RING_ADDR_LO_REG, 0);
1054 	rge_reg_put32(rgep, HIGH_TX_RING_ADDR_HI_REG, 0);
1055 	val32 = rgep->rx_desc.cookie.dmac_laddress;
1056 	rge_reg_put32(rgep, RX_RING_ADDR_LO_REG, val32);
1057 	val32 = rgep->rx_desc.cookie.dmac_laddress >> 32;
1058 	rge_reg_put32(rgep, RX_RING_ADDR_HI_REG, val32);
1059 
1060 	/*
1061 	 * Suggested setting from Realtek
1062 	 */
1063 	if (rgep->chipid.mac_ver != MAC_VER_8101E)
1064 		rge_reg_put16(rgep, RESV_E2_REG, 0x282a);
1065 	else
1066 		rge_reg_put16(rgep, RESV_E2_REG, 0x0000);
1067 
1068 	/*
1069 	 * Set multicast register
1070 	 */
1071 	hashp = (uint32_t *)rgep->mcast_hash;
1072 	rge_reg_put32(rgep, MULTICAST_0_REG, hashp[0]);
1073 	rge_reg_put32(rgep, MULTICAST_4_REG, hashp[1]);
1074 
1075 	/*
1076 	 * Msic register setting:
1077 	 *   -- Missed packet counter: clear it
1078 	 *   -- TimerInt Register
1079 	 *   -- Timer count register
1080 	 */
1081 	rge_reg_put32(rgep, RX_PKT_MISS_COUNT_REG, 0);
1082 	rge_reg_put32(rgep, TIMER_INT_REG, TIMER_INT_NONE);
1083 	rge_reg_put32(rgep, TIMER_COUNT_REG, 0);
1084 
1085 	/*
1086 	 * Return to normal network/host communication mode
1087 	 */
1088 	rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1089 	drv_usecwait(20);
1090 }
1091 
1092 /*
1093  * rge_chip_start() -- start the chip transmitting and/or receiving,
1094  * including enabling interrupts
1095  */
1096 void rge_chip_start(rge_t *rgep);
1097 #pragma	no_inline(rge_chip_start)
1098 
1099 void
1100 rge_chip_start(rge_t *rgep)
1101 {
1102 	/*
1103 	 * Clear statistics
1104 	 */
1105 	bzero(&rgep->stats, sizeof (rge_stats_t));
1106 	DMA_ZERO(rgep->dma_area_stats);
1107 
1108 	/*
1109 	 * Start transmit/receive
1110 	 */
1111 	rge_reg_set8(rgep, RT_COMMAND_REG,
1112 	    RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
1113 
1114 	/*
1115 	 * Enable interrupt
1116 	 */
1117 	rgep->int_mask = RGE_INT_MASK;
1118 	rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask);
1119 
1120 	/*
1121 	 * All done!
1122 	 */
1123 	rgep->rge_chip_state = RGE_CHIP_RUNNING;
1124 }
1125 
1126 /*
1127  * rge_chip_stop() -- stop board receiving
1128  */
1129 void rge_chip_stop(rge_t *rgep, boolean_t fault);
1130 #pragma	no_inline(rge_chip_stop)
1131 
1132 void
1133 rge_chip_stop(rge_t *rgep, boolean_t fault)
1134 {
1135 	/*
1136 	 * Disable interrupt
1137 	 */
1138 	rgep->int_mask = INT_MASK_NONE;
1139 	rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask);
1140 
1141 	/*
1142 	 * Clear pended interrupt
1143 	 */
1144 	if (!rgep->suspended) {
1145 		rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL);
1146 	}
1147 
1148 	/*
1149 	 * Stop the board and disable transmit/receive
1150 	 */
1151 	rge_reg_clr8(rgep, RT_COMMAND_REG,
1152 	    RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
1153 
1154 	if (fault)
1155 		rgep->rge_chip_state = RGE_CHIP_FAULT;
1156 	else
1157 		rgep->rge_chip_state = RGE_CHIP_STOPPED;
1158 }
1159 
1160 /*
1161  * rge_get_mac_addr() -- get the MAC address on NIC
1162  */
1163 static void rge_get_mac_addr(rge_t *rgep);
1164 #pragma	inline(rge_get_mac_addr)
1165 
1166 static void
1167 rge_get_mac_addr(rge_t *rgep)
1168 {
1169 	uint8_t *macaddr = rgep->netaddr;
1170 	uint32_t val32;
1171 
1172 	/*
1173 	 * Read first 4-byte of mac address
1174 	 */
1175 	val32 = rge_reg_get32(rgep, ID_0_REG);
1176 	macaddr[0] = val32 & 0xff;
1177 	val32 = val32 >> 8;
1178 	macaddr[1] = val32 & 0xff;
1179 	val32 = val32 >> 8;
1180 	macaddr[2] = val32 & 0xff;
1181 	val32 = val32 >> 8;
1182 	macaddr[3] = val32 & 0xff;
1183 
1184 	/*
1185 	 * Read last 2-byte of mac address
1186 	 */
1187 	val32 = rge_reg_get32(rgep, ID_4_REG);
1188 	macaddr[4] = val32 & 0xff;
1189 	val32 = val32 >> 8;
1190 	macaddr[5] = val32 & 0xff;
1191 }
1192 
1193 static void rge_set_mac_addr(rge_t *rgep);
1194 #pragma	inline(rge_set_mac_addr)
1195 
1196 static void
1197 rge_set_mac_addr(rge_t *rgep)
1198 {
1199 	uint8_t *p = rgep->netaddr;
1200 	uint32_t val32;
1201 
1202 	/*
1203 	 * Change to config register write enable mode
1204 	 */
1205 	rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1206 
1207 	/*
1208 	 * Get first 4 bytes of mac address
1209 	 */
1210 	val32 = p[3];
1211 	val32 = val32 << 8;
1212 	val32 |= p[2];
1213 	val32 = val32 << 8;
1214 	val32 |= p[1];
1215 	val32 = val32 << 8;
1216 	val32 |= p[0];
1217 
1218 	/*
1219 	 * Set first 4 bytes of mac address
1220 	 */
1221 	rge_reg_put32(rgep, ID_0_REG, val32);
1222 
1223 	/*
1224 	 * Get last 2 bytes of mac address
1225 	 */
1226 	val32 = p[5];
1227 	val32 = val32 << 8;
1228 	val32 |= p[4];
1229 
1230 	/*
1231 	 * Set last 2 bytes of mac address
1232 	 */
1233 	val32 |= rge_reg_get32(rgep, ID_4_REG) & ~0xffff;
1234 	rge_reg_put32(rgep, ID_4_REG, val32);
1235 
1236 	/*
1237 	 * Return to normal network/host communication mode
1238 	 */
1239 	rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1240 }
1241 
1242 static void rge_set_multi_addr(rge_t *rgep);
1243 #pragma	inline(rge_set_multi_addr)
1244 
1245 static void
1246 rge_set_multi_addr(rge_t *rgep)
1247 {
1248 	uint32_t *hashp;
1249 
1250 	hashp = (uint32_t *)rgep->mcast_hash;
1251 
1252 	/*
1253 	 * Change to config register write enable mode
1254 	 */
1255 	if (rgep->chipid.mac_ver == MAC_VER_8169SC)
1256 		rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1257 
1258 	rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0]));
1259 	rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1]));
1260 
1261 	/*
1262 	 * Return to normal network/host communication mode
1263 	 */
1264 	if (rgep->chipid.mac_ver == MAC_VER_8169SC)
1265 		rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1266 }
1267 
1268 static void rge_set_promisc(rge_t *rgep);
1269 #pragma	inline(rge_set_promisc)
1270 
1271 static void
1272 rge_set_promisc(rge_t *rgep)
1273 {
1274 	if (rgep->promisc)
1275 		rge_reg_set32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT);
1276 	else
1277 		rge_reg_clr32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT);
1278 }
1279 
1280 /*
1281  * rge_chip_sync() -- program the chip with the unicast MAC address,
1282  * the multicast hash table, the required level of promiscuity, and
1283  * the current loopback mode ...
1284  */
1285 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo);
1286 #pragma	no_inline(rge_chip_sync)
1287 
1288 void
1289 rge_chip_sync(rge_t *rgep, enum rge_sync_op todo)
1290 {
1291 	switch (todo) {
1292 	case RGE_GET_MAC:
1293 		rge_get_mac_addr(rgep);
1294 		break;
1295 	case RGE_SET_MAC:
1296 		/* Reprogram the unicast MAC address(es) ... */
1297 		rge_set_mac_addr(rgep);
1298 		break;
1299 	case RGE_SET_MUL:
1300 		/* Reprogram the hashed multicast address table ... */
1301 		rge_set_multi_addr(rgep);
1302 		break;
1303 	case RGE_SET_PROMISC:
1304 		/* Set or clear the PROMISCUOUS mode bit */
1305 		rge_set_promisc(rgep);
1306 		break;
1307 	default:
1308 		break;
1309 	}
1310 }
1311 
1312 void rge_chip_blank(void *arg, time_t ticks, uint_t count);
1313 #pragma	no_inline(rge_chip_blank)
1314 
1315 void
1316 rge_chip_blank(void *arg, time_t ticks, uint_t count)
1317 {
1318 	_NOTE(ARGUNUSED(arg, ticks, count));
1319 }
1320 
1321 void rge_tx_trigger(rge_t *rgep);
1322 #pragma	no_inline(rge_tx_trigger)
1323 
1324 void
1325 rge_tx_trigger(rge_t *rgep)
1326 {
1327 	rge_reg_set8(rgep, TX_RINGS_POLL_REG, NORMAL_TX_RING_POLL);
1328 }
1329 
1330 void rge_hw_stats_dump(rge_t *rgep);
1331 #pragma	no_inline(rge_tx_trigger)
1332 
1333 void
1334 rge_hw_stats_dump(rge_t *rgep)
1335 {
1336 	int i = 0;
1337 
1338 	while (rge_reg_get32(rgep, DUMP_COUNTER_REG_0) & DUMP_START) {
1339 		drv_usecwait(100);
1340 		if (++i > STATS_DUMP_LOOP) {
1341 			RGE_DEBUG(("rge h/w statistics dump fail!"));
1342 			rgep->rge_chip_state = RGE_CHIP_ERROR;
1343 			return;
1344 		}
1345 	}
1346 	DMA_SYNC(rgep->dma_area_stats, DDI_DMA_SYNC_FORKERNEL);
1347 
1348 	/*
1349 	 * Start H/W statistics dump for RTL8169 chip
1350 	 */
1351 	rge_reg_set32(rgep, DUMP_COUNTER_REG_0, DUMP_START);
1352 }
1353 
1354 /*
1355  * ========== Hardware interrupt handler ==========
1356  */
1357 
1358 #undef	RGE_DBG
1359 #define	RGE_DBG		RGE_DBG_INT	/* debug flag for this code	*/
1360 
1361 static void rge_wake_factotum(rge_t *rgep);
1362 #pragma	inline(rge_wake_factotum)
1363 
1364 static void
1365 rge_wake_factotum(rge_t *rgep)
1366 {
1367 	if (rgep->factotum_flag == 0) {
1368 		rgep->factotum_flag = 1;
1369 		(void) ddi_intr_trigger_softint(rgep->factotum_hdl, NULL);
1370 	}
1371 }
1372 
1373 /*
1374  *	rge_intr() -- handle chip interrupts
1375  */
1376 uint_t rge_intr(caddr_t arg1, caddr_t arg2);
1377 #pragma	no_inline(rge_intr)
1378 
1379 uint_t
1380 rge_intr(caddr_t arg1, caddr_t arg2)
1381 {
1382 	rge_t *rgep = (rge_t *)arg1;
1383 	uint16_t int_status;
1384 
1385 	_NOTE(ARGUNUSED(arg2))
1386 
1387 	mutex_enter(rgep->genlock);
1388 
1389 	if (rgep->suspended) {
1390 		mutex_exit(rgep->genlock);
1391 		return (DDI_INTR_UNCLAIMED);
1392 	}
1393 
1394 	/*
1395 	 * Was this interrupt caused by our device...
1396 	 */
1397 	int_status = rge_reg_get16(rgep, INT_STATUS_REG);
1398 	if (!(int_status & rgep->int_mask)) {
1399 		mutex_exit(rgep->genlock);
1400 		return (DDI_INTR_UNCLAIMED);
1401 				/* indicate it wasn't our interrupt */
1402 	}
1403 	rgep->stats.intr++;
1404 
1405 	/*
1406 	 * Clear interrupt
1407 	 *	For PCIE chipset, we need disable interrupt first.
1408 	 */
1409 	if (rgep->chipid.is_pcie)
1410 		rge_reg_put16(rgep, INT_MASK_REG, INT_MASK_NONE);
1411 	rge_reg_put16(rgep, INT_STATUS_REG, int_status);
1412 
1413 	/*
1414 	 * Cable link change interrupt
1415 	 */
1416 	if (int_status & LINK_CHANGE_INT) {
1417 		rge_chip_cyclic(rgep);
1418 	}
1419 
1420 	mutex_exit(rgep->genlock);
1421 
1422 	/*
1423 	 * Receive interrupt
1424 	 */
1425 	if (int_status & RGE_RX_INT)
1426 		rge_receive(rgep);
1427 
1428 	/*
1429 	 * Re-enable interrupt for PCIE chipset
1430 	 */
1431 	if (rgep->chipid.is_pcie)
1432 		rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask);
1433 
1434 	return (DDI_INTR_CLAIMED);	/* indicate it was our interrupt */
1435 }
1436 
1437 /*
1438  * ========== Factotum, implemented as a softint handler ==========
1439  */
1440 
1441 #undef	RGE_DBG
1442 #define	RGE_DBG		RGE_DBG_FACT	/* debug flag for this code	*/
1443 
1444 static boolean_t rge_factotum_link_check(rge_t *rgep);
1445 #pragma	no_inline(rge_factotum_link_check)
1446 
1447 static boolean_t
1448 rge_factotum_link_check(rge_t *rgep)
1449 {
1450 	uint8_t media_status;
1451 	int32_t link;
1452 
1453 	media_status = rge_reg_get8(rgep, PHY_STATUS_REG);
1454 	link = (media_status & PHY_STATUS_LINK_UP) ?
1455 	    LINK_STATE_UP : LINK_STATE_DOWN;
1456 	if (rgep->param_link_up != link) {
1457 		/*
1458 		 * Link change.
1459 		 */
1460 		rgep->param_link_up = link;
1461 
1462 		if (link == LINK_STATE_UP) {
1463 			if (media_status & PHY_STATUS_1000MF) {
1464 				rgep->param_link_speed = RGE_SPEED_1000M;
1465 				rgep->param_link_duplex = LINK_DUPLEX_FULL;
1466 			} else {
1467 				rgep->param_link_speed =
1468 				    (media_status & PHY_STATUS_100M) ?
1469 				    RGE_SPEED_100M : RGE_SPEED_10M;
1470 				rgep->param_link_duplex =
1471 				    (media_status & PHY_STATUS_DUPLEX_FULL) ?
1472 				    LINK_DUPLEX_FULL : LINK_DUPLEX_HALF;
1473 			}
1474 		}
1475 		return (B_TRUE);
1476 	}
1477 	return (B_FALSE);
1478 }
1479 
1480 /*
1481  * Factotum routine to check for Tx stall, using the 'watchdog' counter
1482  */
1483 static boolean_t rge_factotum_stall_check(rge_t *rgep);
1484 #pragma	no_inline(rge_factotum_stall_check)
1485 
1486 static boolean_t
1487 rge_factotum_stall_check(rge_t *rgep)
1488 {
1489 	uint32_t dogval;
1490 
1491 	ASSERT(mutex_owned(rgep->genlock));
1492 
1493 	/*
1494 	 * Specific check for Tx stall ...
1495 	 *
1496 	 * The 'watchdog' counter is incremented whenever a packet
1497 	 * is queued, reset to 1 when some (but not all) buffers
1498 	 * are reclaimed, reset to 0 (disabled) when all buffers
1499 	 * are reclaimed, and shifted left here.  If it exceeds the
1500 	 * threshold value, the chip is assumed to have stalled and
1501 	 * is put into the ERROR state.  The factotum will then reset
1502 	 * it on the next pass.
1503 	 *
1504 	 * All of which should ensure that we don't get into a state
1505 	 * where packets are left pending indefinitely!
1506 	 */
1507 	if (rgep->resched_needed)
1508 		(void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL);
1509 	dogval = rge_atomic_shl32(&rgep->watchdog, 1);
1510 	if (dogval < rge_watchdog_count)
1511 		return (B_FALSE);
1512 
1513 	RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval));
1514 	return (B_TRUE);
1515 
1516 }
1517 
1518 /*
1519  * The factotum is woken up when there's something to do that we'd rather
1520  * not do from inside a hardware interrupt handler or high-level cyclic.
1521  * Its two main tasks are:
1522  *	reset & restart the chip after an error
1523  *	check the link status whenever necessary
1524  */
1525 uint_t rge_chip_factotum(caddr_t arg1, caddr_t arg2);
1526 #pragma	no_inline(rge_chip_factotum)
1527 
1528 uint_t
1529 rge_chip_factotum(caddr_t arg1, caddr_t arg2)
1530 {
1531 	rge_t *rgep;
1532 	uint_t result;
1533 	boolean_t error;
1534 	boolean_t linkchg;
1535 
1536 	rgep = (rge_t *)arg1;
1537 	_NOTE(ARGUNUSED(arg2))
1538 
1539 	if (rgep->factotum_flag == 0)
1540 		return (DDI_INTR_UNCLAIMED);
1541 
1542 	rgep->factotum_flag = 0;
1543 	result = DDI_INTR_CLAIMED;
1544 	error = B_FALSE;
1545 	linkchg = B_FALSE;
1546 
1547 	mutex_enter(rgep->genlock);
1548 	switch (rgep->rge_chip_state) {
1549 	default:
1550 		break;
1551 
1552 	case RGE_CHIP_RUNNING:
1553 		linkchg = rge_factotum_link_check(rgep);
1554 		error = rge_factotum_stall_check(rgep);
1555 		break;
1556 
1557 	case RGE_CHIP_ERROR:
1558 		error = B_TRUE;
1559 		break;
1560 
1561 	case RGE_CHIP_FAULT:
1562 		/*
1563 		 * Fault detected, time to reset ...
1564 		 */
1565 		if (rge_autorecover) {
1566 			RGE_REPORT((rgep, "automatic recovery activated"));
1567 			rge_restart(rgep);
1568 		}
1569 		break;
1570 	}
1571 
1572 	/*
1573 	 * If an error is detected, stop the chip now, marking it as
1574 	 * faulty, so that it will be reset next time through ...
1575 	 */
1576 	if (error)
1577 		rge_chip_stop(rgep, B_TRUE);
1578 	mutex_exit(rgep->genlock);
1579 
1580 	/*
1581 	 * If the link state changed, tell the world about it.
1582 	 * Note: can't do this while still holding the mutex.
1583 	 */
1584 	if (linkchg)
1585 		mac_link_update(rgep->mh, rgep->param_link_up);
1586 
1587 	return (result);
1588 }
1589 
1590 /*
1591  * High-level cyclic handler
1592  *
1593  * This routine schedules a (low-level) softint callback to the
1594  * factotum, and prods the chip to update the status block (which
1595  * will cause a hardware interrupt when complete).
1596  */
1597 void rge_chip_cyclic(void *arg);
1598 #pragma	no_inline(rge_chip_cyclic)
1599 
1600 void
1601 rge_chip_cyclic(void *arg)
1602 {
1603 	rge_t *rgep;
1604 
1605 	rgep = arg;
1606 
1607 	switch (rgep->rge_chip_state) {
1608 	default:
1609 		return;
1610 
1611 	case RGE_CHIP_RUNNING:
1612 		rge_phy_check(rgep);
1613 		break;
1614 
1615 	case RGE_CHIP_FAULT:
1616 	case RGE_CHIP_ERROR:
1617 		break;
1618 	}
1619 
1620 	rge_wake_factotum(rgep);
1621 }
1622 
1623 
1624 /*
1625  * ========== Ioctl subfunctions ==========
1626  */
1627 
1628 #undef	RGE_DBG
1629 #define	RGE_DBG		RGE_DBG_PPIO	/* debug flag for this code	*/
1630 
1631 #if	RGE_DEBUGGING || RGE_DO_PPIO
1632 
1633 static void rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd);
1634 #pragma	no_inline(rge_chip_peek_cfg)
1635 
1636 static void
1637 rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd)
1638 {
1639 	uint64_t regval;
1640 	uint64_t regno;
1641 
1642 	RGE_TRACE(("rge_chip_peek_cfg($%p, $%p)",
1643 	    (void *)rgep, (void *)ppd));
1644 
1645 	regno = ppd->pp_acc_offset;
1646 
1647 	switch (ppd->pp_acc_size) {
1648 	case 1:
1649 		regval = pci_config_get8(rgep->cfg_handle, regno);
1650 		break;
1651 
1652 	case 2:
1653 		regval = pci_config_get16(rgep->cfg_handle, regno);
1654 		break;
1655 
1656 	case 4:
1657 		regval = pci_config_get32(rgep->cfg_handle, regno);
1658 		break;
1659 
1660 	case 8:
1661 		regval = pci_config_get64(rgep->cfg_handle, regno);
1662 		break;
1663 	}
1664 
1665 	ppd->pp_acc_data = regval;
1666 }
1667 
1668 static void rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd);
1669 #pragma	no_inline(rge_chip_poke_cfg)
1670 
1671 static void
1672 rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd)
1673 {
1674 	uint64_t regval;
1675 	uint64_t regno;
1676 
1677 	RGE_TRACE(("rge_chip_poke_cfg($%p, $%p)",
1678 	    (void *)rgep, (void *)ppd));
1679 
1680 	regno = ppd->pp_acc_offset;
1681 	regval = ppd->pp_acc_data;
1682 
1683 	switch (ppd->pp_acc_size) {
1684 	case 1:
1685 		pci_config_put8(rgep->cfg_handle, regno, regval);
1686 		break;
1687 
1688 	case 2:
1689 		pci_config_put16(rgep->cfg_handle, regno, regval);
1690 		break;
1691 
1692 	case 4:
1693 		pci_config_put32(rgep->cfg_handle, regno, regval);
1694 		break;
1695 
1696 	case 8:
1697 		pci_config_put64(rgep->cfg_handle, regno, regval);
1698 		break;
1699 	}
1700 }
1701 
1702 static void rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd);
1703 #pragma	no_inline(rge_chip_peek_reg)
1704 
1705 static void
1706 rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd)
1707 {
1708 	uint64_t regval;
1709 	void *regaddr;
1710 
1711 	RGE_TRACE(("rge_chip_peek_reg($%p, $%p)",
1712 	    (void *)rgep, (void *)ppd));
1713 
1714 	regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset);
1715 
1716 	switch (ppd->pp_acc_size) {
1717 	case 1:
1718 		regval = ddi_get8(rgep->io_handle, regaddr);
1719 		break;
1720 
1721 	case 2:
1722 		regval = ddi_get16(rgep->io_handle, regaddr);
1723 		break;
1724 
1725 	case 4:
1726 		regval = ddi_get32(rgep->io_handle, regaddr);
1727 		break;
1728 
1729 	case 8:
1730 		regval = ddi_get64(rgep->io_handle, regaddr);
1731 		break;
1732 	}
1733 
1734 	ppd->pp_acc_data = regval;
1735 }
1736 
1737 static void rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd);
1738 #pragma	no_inline(rge_chip_peek_reg)
1739 
1740 static void
1741 rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd)
1742 {
1743 	uint64_t regval;
1744 	void *regaddr;
1745 
1746 	RGE_TRACE(("rge_chip_poke_reg($%p, $%p)",
1747 	    (void *)rgep, (void *)ppd));
1748 
1749 	regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset);
1750 	regval = ppd->pp_acc_data;
1751 
1752 	switch (ppd->pp_acc_size) {
1753 	case 1:
1754 		ddi_put8(rgep->io_handle, regaddr, regval);
1755 		break;
1756 
1757 	case 2:
1758 		ddi_put16(rgep->io_handle, regaddr, regval);
1759 		break;
1760 
1761 	case 4:
1762 		ddi_put32(rgep->io_handle, regaddr, regval);
1763 		break;
1764 
1765 	case 8:
1766 		ddi_put64(rgep->io_handle, regaddr, regval);
1767 		break;
1768 	}
1769 }
1770 
1771 static void rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd);
1772 #pragma	no_inline(rge_chip_peek_mii)
1773 
1774 static void
1775 rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd)
1776 {
1777 	RGE_TRACE(("rge_chip_peek_mii($%p, $%p)",
1778 	    (void *)rgep, (void *)ppd));
1779 
1780 	ppd->pp_acc_data = rge_mii_get16(rgep, ppd->pp_acc_offset/2);
1781 }
1782 
1783 static void rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd);
1784 #pragma	no_inline(rge_chip_poke_mii)
1785 
1786 static void
1787 rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd)
1788 {
1789 	RGE_TRACE(("rge_chip_poke_mii($%p, $%p)",
1790 	    (void *)rgep, (void *)ppd));
1791 
1792 	rge_mii_put16(rgep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
1793 }
1794 
1795 static void rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd);
1796 #pragma	no_inline(rge_chip_peek_mem)
1797 
1798 static void
1799 rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd)
1800 {
1801 	uint64_t regval;
1802 	void *vaddr;
1803 
1804 	RGE_TRACE(("rge_chip_peek_rge($%p, $%p)",
1805 	    (void *)rgep, (void *)ppd));
1806 
1807 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
1808 
1809 	switch (ppd->pp_acc_size) {
1810 	case 1:
1811 		regval = *(uint8_t *)vaddr;
1812 		break;
1813 
1814 	case 2:
1815 		regval = *(uint16_t *)vaddr;
1816 		break;
1817 
1818 	case 4:
1819 		regval = *(uint32_t *)vaddr;
1820 		break;
1821 
1822 	case 8:
1823 		regval = *(uint64_t *)vaddr;
1824 		break;
1825 	}
1826 
1827 	RGE_DEBUG(("rge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p",
1828 	    (void *)rgep, (void *)ppd, regval, vaddr));
1829 
1830 	ppd->pp_acc_data = regval;
1831 }
1832 
1833 static void rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd);
1834 #pragma	no_inline(rge_chip_poke_mem)
1835 
1836 static void
1837 rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd)
1838 {
1839 	uint64_t regval;
1840 	void *vaddr;
1841 
1842 	RGE_TRACE(("rge_chip_poke_mem($%p, $%p)",
1843 	    (void *)rgep, (void *)ppd));
1844 
1845 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
1846 	regval = ppd->pp_acc_data;
1847 
1848 	RGE_DEBUG(("rge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p",
1849 	    (void *)rgep, (void *)ppd, regval, vaddr));
1850 
1851 	switch (ppd->pp_acc_size) {
1852 	case 1:
1853 		*(uint8_t *)vaddr = (uint8_t)regval;
1854 		break;
1855 
1856 	case 2:
1857 		*(uint16_t *)vaddr = (uint16_t)regval;
1858 		break;
1859 
1860 	case 4:
1861 		*(uint32_t *)vaddr = (uint32_t)regval;
1862 		break;
1863 
1864 	case 8:
1865 		*(uint64_t *)vaddr = (uint64_t)regval;
1866 		break;
1867 	}
1868 }
1869 
1870 static enum ioc_reply rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp,
1871 					struct iocblk *iocp);
1872 #pragma	no_inline(rge_pp_ioctl)
1873 
1874 static enum ioc_reply
1875 rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp)
1876 {
1877 	void (*ppfn)(rge_t *rgep, rge_peekpoke_t *ppd);
1878 	rge_peekpoke_t *ppd;
1879 	dma_area_t *areap;
1880 	uint64_t sizemask;
1881 	uint64_t mem_va;
1882 	uint64_t maxoff;
1883 	boolean_t peek;
1884 
1885 	switch (cmd) {
1886 	default:
1887 		/* NOTREACHED */
1888 		rge_error(rgep, "rge_pp_ioctl: invalid cmd 0x%x", cmd);
1889 		return (IOC_INVAL);
1890 
1891 	case RGE_PEEK:
1892 		peek = B_TRUE;
1893 		break;
1894 
1895 	case RGE_POKE:
1896 		peek = B_FALSE;
1897 		break;
1898 	}
1899 
1900 	/*
1901 	 * Validate format of ioctl
1902 	 */
1903 	if (iocp->ioc_count != sizeof (rge_peekpoke_t))
1904 		return (IOC_INVAL);
1905 	if (mp->b_cont == NULL)
1906 		return (IOC_INVAL);
1907 	ppd = (rge_peekpoke_t *)mp->b_cont->b_rptr;
1908 
1909 	/*
1910 	 * Validate request parameters
1911 	 */
1912 	switch (ppd->pp_acc_space) {
1913 	default:
1914 		return (IOC_INVAL);
1915 
1916 	case RGE_PP_SPACE_CFG:
1917 		/*
1918 		 * Config space
1919 		 */
1920 		sizemask = 8|4|2|1;
1921 		mem_va = 0;
1922 		maxoff = PCI_CONF_HDR_SIZE;
1923 		ppfn = peek ? rge_chip_peek_cfg : rge_chip_poke_cfg;
1924 		break;
1925 
1926 	case RGE_PP_SPACE_REG:
1927 		/*
1928 		 * Memory-mapped I/O space
1929 		 */
1930 		sizemask = 8|4|2|1;
1931 		mem_va = 0;
1932 		maxoff = RGE_REGISTER_MAX;
1933 		ppfn = peek ? rge_chip_peek_reg : rge_chip_poke_reg;
1934 		break;
1935 
1936 	case RGE_PP_SPACE_MII:
1937 		/*
1938 		 * PHY's MII registers
1939 		 * NB: all PHY registers are two bytes, but the
1940 		 * addresses increment in ones (word addressing).
1941 		 * So we scale the address here, then undo the
1942 		 * transformation inside the peek/poke functions.
1943 		 */
1944 		ppd->pp_acc_offset *= 2;
1945 		sizemask = 2;
1946 		mem_va = 0;
1947 		maxoff = (MII_MAXREG+1)*2;
1948 		ppfn = peek ? rge_chip_peek_mii : rge_chip_poke_mii;
1949 		break;
1950 
1951 	case RGE_PP_SPACE_RGE:
1952 		/*
1953 		 * RGE data structure!
1954 		 */
1955 		sizemask = 8|4|2|1;
1956 		mem_va = (uintptr_t)rgep;
1957 		maxoff = sizeof (*rgep);
1958 		ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem;
1959 		break;
1960 
1961 	case RGE_PP_SPACE_STATISTICS:
1962 	case RGE_PP_SPACE_TXDESC:
1963 	case RGE_PP_SPACE_TXBUFF:
1964 	case RGE_PP_SPACE_RXDESC:
1965 	case RGE_PP_SPACE_RXBUFF:
1966 		/*
1967 		 * Various DMA_AREAs
1968 		 */
1969 		switch (ppd->pp_acc_space) {
1970 		case RGE_PP_SPACE_TXDESC:
1971 			areap = &rgep->dma_area_txdesc;
1972 			break;
1973 		case RGE_PP_SPACE_RXDESC:
1974 			areap = &rgep->dma_area_rxdesc;
1975 			break;
1976 		case RGE_PP_SPACE_STATISTICS:
1977 			areap = &rgep->dma_area_stats;
1978 			break;
1979 		}
1980 
1981 		sizemask = 8|4|2|1;
1982 		mem_va = (uintptr_t)areap->mem_va;
1983 		maxoff = areap->alength;
1984 		ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem;
1985 		break;
1986 	}
1987 
1988 	switch (ppd->pp_acc_size) {
1989 	default:
1990 		return (IOC_INVAL);
1991 
1992 	case 8:
1993 	case 4:
1994 	case 2:
1995 	case 1:
1996 		if ((ppd->pp_acc_size & sizemask) == 0)
1997 			return (IOC_INVAL);
1998 		break;
1999 	}
2000 
2001 	if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
2002 		return (IOC_INVAL);
2003 
2004 	if (ppd->pp_acc_offset >= maxoff)
2005 		return (IOC_INVAL);
2006 
2007 	if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff)
2008 		return (IOC_INVAL);
2009 
2010 	/*
2011 	 * All OK - go do it!
2012 	 */
2013 	ppd->pp_acc_offset += mem_va;
2014 	(*ppfn)(rgep, ppd);
2015 	return (peek ? IOC_REPLY : IOC_ACK);
2016 }
2017 
2018 static enum ioc_reply rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp,
2019 					struct iocblk *iocp);
2020 #pragma	no_inline(rge_diag_ioctl)
2021 
2022 static enum ioc_reply
2023 rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp)
2024 {
2025 	ASSERT(mutex_owned(rgep->genlock));
2026 
2027 	switch (cmd) {
2028 	default:
2029 		/* NOTREACHED */
2030 		rge_error(rgep, "rge_diag_ioctl: invalid cmd 0x%x", cmd);
2031 		return (IOC_INVAL);
2032 
2033 	case RGE_DIAG:
2034 		/*
2035 		 * Currently a no-op
2036 		 */
2037 		return (IOC_ACK);
2038 
2039 	case RGE_PEEK:
2040 	case RGE_POKE:
2041 		return (rge_pp_ioctl(rgep, cmd, mp, iocp));
2042 
2043 	case RGE_PHY_RESET:
2044 		return (IOC_RESTART_ACK);
2045 
2046 	case RGE_SOFT_RESET:
2047 	case RGE_HARD_RESET:
2048 		/*
2049 		 * Reset and reinitialise the 570x hardware
2050 		 */
2051 		rge_restart(rgep);
2052 		return (IOC_ACK);
2053 	}
2054 
2055 	/* NOTREACHED */
2056 }
2057 
2058 #endif	/* RGE_DEBUGGING || RGE_DO_PPIO */
2059 
2060 static enum ioc_reply rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp,
2061 				    struct iocblk *iocp);
2062 #pragma	no_inline(rge_mii_ioctl)
2063 
2064 static enum ioc_reply
2065 rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp)
2066 {
2067 	struct rge_mii_rw *miirwp;
2068 
2069 	/*
2070 	 * Validate format of ioctl
2071 	 */
2072 	if (iocp->ioc_count != sizeof (struct rge_mii_rw))
2073 		return (IOC_INVAL);
2074 	if (mp->b_cont == NULL)
2075 		return (IOC_INVAL);
2076 	miirwp = (struct rge_mii_rw *)mp->b_cont->b_rptr;
2077 
2078 	/*
2079 	 * Validate request parameters ...
2080 	 */
2081 	if (miirwp->mii_reg > MII_MAXREG)
2082 		return (IOC_INVAL);
2083 
2084 	switch (cmd) {
2085 	default:
2086 		/* NOTREACHED */
2087 		rge_error(rgep, "rge_mii_ioctl: invalid cmd 0x%x", cmd);
2088 		return (IOC_INVAL);
2089 
2090 	case RGE_MII_READ:
2091 		miirwp->mii_data = rge_mii_get16(rgep, miirwp->mii_reg);
2092 		return (IOC_REPLY);
2093 
2094 	case RGE_MII_WRITE:
2095 		rge_mii_put16(rgep, miirwp->mii_reg, miirwp->mii_data);
2096 		return (IOC_ACK);
2097 	}
2098 
2099 	/* NOTREACHED */
2100 }
2101 
2102 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp,
2103 				struct iocblk *iocp);
2104 #pragma	no_inline(rge_chip_ioctl)
2105 
2106 enum ioc_reply
2107 rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
2108 {
2109 	int cmd;
2110 
2111 	RGE_TRACE(("rge_chip_ioctl($%p, $%p, $%p, $%p)",
2112 	    (void *)rgep, (void *)wq, (void *)mp, (void *)iocp));
2113 
2114 	ASSERT(mutex_owned(rgep->genlock));
2115 
2116 	cmd = iocp->ioc_cmd;
2117 	switch (cmd) {
2118 	default:
2119 		/* NOTREACHED */
2120 		rge_error(rgep, "rge_chip_ioctl: invalid cmd 0x%x", cmd);
2121 		return (IOC_INVAL);
2122 
2123 	case RGE_DIAG:
2124 	case RGE_PEEK:
2125 	case RGE_POKE:
2126 	case RGE_PHY_RESET:
2127 	case RGE_SOFT_RESET:
2128 	case RGE_HARD_RESET:
2129 #if	RGE_DEBUGGING || RGE_DO_PPIO
2130 		return (rge_diag_ioctl(rgep, cmd, mp, iocp));
2131 #else
2132 		return (IOC_INVAL);
2133 #endif	/* RGE_DEBUGGING || RGE_DO_PPIO */
2134 
2135 	case RGE_MII_READ:
2136 	case RGE_MII_WRITE:
2137 		return (rge_mii_ioctl(rgep, cmd, mp, iocp));
2138 
2139 	}
2140 
2141 	/* NOTREACHED */
2142 }
2143