1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include "rge.h" 29 30 #define REG32(rgep, reg) ((uint32_t *)(rgep->io_regs+(reg))) 31 #define REG16(rgep, reg) ((uint16_t *)(rgep->io_regs+(reg))) 32 #define REG8(rgep, reg) ((uint8_t *)(rgep->io_regs+(reg))) 33 #define PIO_ADDR(rgep, offset) ((void *)(rgep->io_regs+(offset))) 34 35 /* 36 * Patchable globals: 37 * 38 * rge_autorecover 39 * Enables/disables automatic recovery after fault detection 40 */ 41 static uint32_t rge_autorecover = 1; 42 43 /* 44 * globals: 45 */ 46 #define RGE_DBG RGE_DBG_REGS /* debug flag for this code */ 47 static uint32_t rge_watchdog_count = 1 << 16; 48 49 /* 50 * Operating register get/set access routines 51 */ 52 53 static uint32_t rge_reg_get32(rge_t *rgep, uintptr_t regno); 54 #pragma inline(rge_reg_get32) 55 56 static uint32_t 57 rge_reg_get32(rge_t *rgep, uintptr_t regno) 58 { 59 RGE_TRACE(("rge_reg_get32($%p, 0x%lx)", 60 (void *)rgep, regno)); 61 62 return (ddi_get32(rgep->io_handle, REG32(rgep, regno))); 63 } 64 65 static void rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data); 66 #pragma inline(rge_reg_put32) 67 68 static void 69 rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data) 70 { 71 RGE_TRACE(("rge_reg_put32($%p, 0x%lx, 0x%x)", 72 (void *)rgep, regno, data)); 73 74 ddi_put32(rgep->io_handle, REG32(rgep, regno), data); 75 } 76 77 static void rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits); 78 #pragma inline(rge_reg_set32) 79 80 static void 81 rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits) 82 { 83 uint32_t regval; 84 85 RGE_TRACE(("rge_reg_set32($%p, 0x%lx, 0x%x)", 86 (void *)rgep, regno, bits)); 87 88 regval = rge_reg_get32(rgep, regno); 89 regval |= bits; 90 rge_reg_put32(rgep, regno, regval); 91 } 92 93 static void rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits); 94 #pragma inline(rge_reg_clr32) 95 96 static void 97 rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits) 98 { 99 uint32_t regval; 100 101 RGE_TRACE(("rge_reg_clr32($%p, 0x%lx, 0x%x)", 102 (void *)rgep, regno, bits)); 103 104 regval = rge_reg_get32(rgep, regno); 105 regval &= ~bits; 106 rge_reg_put32(rgep, regno, regval); 107 } 108 109 static uint16_t rge_reg_get16(rge_t *rgep, uintptr_t regno); 110 #pragma inline(rge_reg_get16) 111 112 static uint16_t 113 rge_reg_get16(rge_t *rgep, uintptr_t regno) 114 { 115 RGE_TRACE(("rge_reg_get16($%p, 0x%lx)", 116 (void *)rgep, regno)); 117 118 return (ddi_get16(rgep->io_handle, REG16(rgep, regno))); 119 } 120 121 static void rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data); 122 #pragma inline(rge_reg_put16) 123 124 static void 125 rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data) 126 { 127 RGE_TRACE(("rge_reg_put16($%p, 0x%lx, 0x%x)", 128 (void *)rgep, regno, data)); 129 130 ddi_put16(rgep->io_handle, REG16(rgep, regno), data); 131 } 132 133 static void rge_reg_set16(rge_t *rgep, uintptr_t regno, uint16_t bits); 134 #pragma inline(rge_reg_set16) 135 136 static void 137 rge_reg_set16(rge_t *rgep, uintptr_t regno, uint16_t bits) 138 { 139 uint16_t regval; 140 141 RGE_TRACE(("rge_reg_set16($%p, 0x%lx, 0x%x)", 142 (void *)rgep, regno, bits)); 143 144 regval = rge_reg_get16(rgep, regno); 145 regval |= bits; 146 rge_reg_put16(rgep, regno, regval); 147 } 148 149 static void rge_reg_clr16(rge_t *rgep, uintptr_t regno, uint16_t bits); 150 #pragma inline(rge_reg_clr16) 151 152 static void 153 rge_reg_clr16(rge_t *rgep, uintptr_t regno, uint16_t bits) 154 { 155 uint16_t regval; 156 157 RGE_TRACE(("rge_reg_clr16($%p, 0x%lx, 0x%x)", 158 (void *)rgep, regno, bits)); 159 160 regval = rge_reg_get16(rgep, regno); 161 regval &= ~bits; 162 rge_reg_put16(rgep, regno, regval); 163 } 164 165 static uint8_t rge_reg_get8(rge_t *rgep, uintptr_t regno); 166 #pragma inline(rge_reg_get8) 167 168 static uint8_t 169 rge_reg_get8(rge_t *rgep, uintptr_t regno) 170 { 171 RGE_TRACE(("rge_reg_get8($%p, 0x%lx)", 172 (void *)rgep, regno)); 173 174 return (ddi_get8(rgep->io_handle, REG8(rgep, regno))); 175 } 176 177 static void rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data); 178 #pragma inline(rge_reg_put8) 179 180 static void 181 rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data) 182 { 183 RGE_TRACE(("rge_reg_put8($%p, 0x%lx, 0x%x)", 184 (void *)rgep, regno, data)); 185 186 ddi_put8(rgep->io_handle, REG8(rgep, regno), data); 187 } 188 189 static void rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits); 190 #pragma inline(rge_reg_set8) 191 192 static void 193 rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits) 194 { 195 uint8_t regval; 196 197 RGE_TRACE(("rge_reg_set8($%p, 0x%lx, 0x%x)", 198 (void *)rgep, regno, bits)); 199 200 regval = rge_reg_get8(rgep, regno); 201 regval |= bits; 202 rge_reg_put8(rgep, regno, regval); 203 } 204 205 static void rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits); 206 #pragma inline(rge_reg_clr8) 207 208 static void 209 rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits) 210 { 211 uint8_t regval; 212 213 RGE_TRACE(("rge_reg_clr8($%p, 0x%lx, 0x%x)", 214 (void *)rgep, regno, bits)); 215 216 regval = rge_reg_get8(rgep, regno); 217 regval &= ~bits; 218 rge_reg_put8(rgep, regno, regval); 219 } 220 221 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii); 222 #pragma no_inline(rge_mii_get16) 223 224 uint16_t 225 rge_mii_get16(rge_t *rgep, uintptr_t mii) 226 { 227 uint32_t regval; 228 uint32_t val32; 229 uint32_t i; 230 231 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 232 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 233 234 /* 235 * Waiting for PHY reading OK 236 */ 237 for (i = 0; i < PHY_RESET_LOOP; i++) { 238 drv_usecwait(1000); 239 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 240 if (val32 & PHY_ACCESS_WR_FLAG) 241 return ((uint16_t)(val32 & 0xffff)); 242 } 243 244 RGE_REPORT((rgep, "rge_mii_get16(0x%x) fail, val = %x", mii, val32)); 245 return ((uint16_t)~0u); 246 } 247 248 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data); 249 #pragma no_inline(rge_mii_put16) 250 251 void 252 rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data) 253 { 254 uint32_t regval; 255 uint32_t val32; 256 uint32_t i; 257 258 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 259 regval |= data & PHY_DATA_MASK; 260 regval |= PHY_ACCESS_WR_FLAG; 261 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 262 263 /* 264 * Waiting for PHY writing OK 265 */ 266 for (i = 0; i < PHY_RESET_LOOP; i++) { 267 drv_usecwait(1000); 268 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 269 if (!(val32 & PHY_ACCESS_WR_FLAG)) 270 return; 271 } 272 RGE_REPORT((rgep, "rge_mii_put16(0x%lx, 0x%x) fail", 273 mii, data)); 274 } 275 276 void rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data); 277 #pragma no_inline(rge_ephy_put16) 278 279 void 280 rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data) 281 { 282 uint32_t regval; 283 uint32_t val32; 284 uint32_t i; 285 286 regval = (emii & EPHY_REG_MASK) << EPHY_REG_SHIFT; 287 regval |= data & EPHY_DATA_MASK; 288 regval |= EPHY_ACCESS_WR_FLAG; 289 rge_reg_put32(rgep, EPHY_ACCESS_REG, regval); 290 291 /* 292 * Waiting for PHY writing OK 293 */ 294 for (i = 0; i < PHY_RESET_LOOP; i++) { 295 drv_usecwait(1000); 296 val32 = rge_reg_get32(rgep, EPHY_ACCESS_REG); 297 if (!(val32 & EPHY_ACCESS_WR_FLAG)) 298 return; 299 } 300 RGE_REPORT((rgep, "rge_ephy_put16(0x%lx, 0x%x) fail", 301 emii, data)); 302 } 303 304 /* 305 * Atomically shift a 32-bit word left, returning 306 * the value it had *before* the shift was applied 307 */ 308 static uint32_t rge_atomic_shl32(uint32_t *sp, uint_t count); 309 #pragma inline(rge_mii_put16) 310 311 static uint32_t 312 rge_atomic_shl32(uint32_t *sp, uint_t count) 313 { 314 uint32_t oldval; 315 uint32_t newval; 316 317 /* ATOMICALLY */ 318 do { 319 oldval = *sp; 320 newval = oldval << count; 321 } while (cas32(sp, oldval, newval) != oldval); 322 323 return (oldval); 324 } 325 326 /* 327 * PHY operation routines 328 */ 329 #if RGE_DEBUGGING 330 331 static void 332 rge_phydump(rge_t *rgep) 333 { 334 uint16_t regs[32]; 335 int i; 336 337 ASSERT(mutex_owned(rgep->genlock)); 338 339 for (i = 0; i < 32; ++i) { 340 regs[i] = rge_mii_get16(rgep, i); 341 } 342 343 for (i = 0; i < 32; i += 8) 344 RGE_DEBUG(("rge_phydump: " 345 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 346 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 347 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 348 } 349 350 #endif /* RGE_DEBUGGING */ 351 352 /* 353 * Basic low-level function to probe for a PHY 354 * 355 * Returns TRUE if the PHY responds with valid data, FALSE otherwise 356 */ 357 static boolean_t 358 rge_phy_probe(rge_t *rgep) 359 { 360 uint16_t phy_status; 361 362 ASSERT(mutex_owned(rgep->genlock)); 363 364 /* 365 * Read the MII_STATUS register twice, in 366 * order to clear any sticky bits (but they should 367 * have been cleared by the RESET, I think). 368 */ 369 phy_status = rge_mii_get16(rgep, MII_STATUS); 370 phy_status = rge_mii_get16(rgep, MII_STATUS); 371 RGE_DEBUG(("rge_phy_probe: status 0x%x", phy_status)); 372 373 /* 374 * Now check the value read; it should have at least one bit set 375 * (for the device capabilities) and at least one clear (one of 376 * the error bits). So if we see all 0s or all 1s, there's a 377 * problem. In particular, rge_mii_get16() returns all 1s if 378 * communications fails ... 379 */ 380 switch (phy_status) { 381 case 0x0000: 382 case 0xffff: 383 return (B_FALSE); 384 385 default : 386 return (B_TRUE); 387 } 388 } 389 390 static void 391 rge_phy_check(rge_t *rgep) 392 { 393 uint16_t gig_ctl; 394 395 if (rgep->param_link_up == LINK_STATE_DOWN) { 396 /* 397 * RTL8169S/8110S PHY has the "PCS bug". Need reset PHY 398 * every 15 seconds whin link down & advertise is 1000. 399 */ 400 if (rgep->chipid.phy_ver == PHY_VER_S) { 401 gig_ctl = rge_mii_get16(rgep, MII_1000BASE_T_CONTROL); 402 if (gig_ctl & MII_1000BT_CTL_ADV_FDX) { 403 rgep->link_down_count++; 404 if (rgep->link_down_count > 15) { 405 (void) rge_phy_reset(rgep); 406 rgep->stats.phy_reset++; 407 rgep->link_down_count = 0; 408 } 409 } 410 } 411 } else { 412 rgep->link_down_count = 0; 413 } 414 } 415 416 /* 417 * Basic low-level function to reset the PHY. 418 * Doesn't incorporate any special-case workarounds. 419 * 420 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 421 */ 422 boolean_t 423 rge_phy_reset(rge_t *rgep) 424 { 425 uint16_t control; 426 uint_t count; 427 428 /* 429 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 430 */ 431 control = rge_mii_get16(rgep, MII_CONTROL); 432 rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET); 433 for (count = 0; count < 5; count++) { 434 drv_usecwait(100); 435 control = rge_mii_get16(rgep, MII_CONTROL); 436 if (BIC(control, MII_CONTROL_RESET)) 437 return (B_TRUE); 438 } 439 440 RGE_REPORT((rgep, "rge_phy_reset: FAILED, control now 0x%x", control)); 441 return (B_FALSE); 442 } 443 444 /* 445 * Synchronise the PHY's speed/duplex/autonegotiation capabilities 446 * and advertisements with the required settings as specified by the various 447 * param_* variables that can be poked via the NDD interface. 448 * 449 * We always reset the PHY and reprogram *all* the relevant registers, 450 * not just those changed. This should cause the link to go down, and then 451 * back up again once the link is stable and autonegotiation (if enabled) 452 * is complete. We should get a link state change interrupt somewhere along 453 * the way ... 454 * 455 * NOTE: <genlock> must already be held by the caller 456 */ 457 void 458 rge_phy_update(rge_t *rgep) 459 { 460 boolean_t adv_autoneg; 461 boolean_t adv_pause; 462 boolean_t adv_asym_pause; 463 boolean_t adv_1000fdx; 464 boolean_t adv_1000hdx; 465 boolean_t adv_100fdx; 466 boolean_t adv_100hdx; 467 boolean_t adv_10fdx; 468 boolean_t adv_10hdx; 469 470 uint16_t control; 471 uint16_t gigctrl; 472 uint16_t anar; 473 474 ASSERT(mutex_owned(rgep->genlock)); 475 476 RGE_DEBUG(("rge_phy_update: autoneg %d " 477 "pause %d asym_pause %d " 478 "1000fdx %d 1000hdx %d " 479 "100fdx %d 100hdx %d " 480 "10fdx %d 10hdx %d ", 481 rgep->param_adv_autoneg, 482 rgep->param_adv_pause, rgep->param_adv_asym_pause, 483 rgep->param_adv_1000fdx, rgep->param_adv_1000hdx, 484 rgep->param_adv_100fdx, rgep->param_adv_100hdx, 485 rgep->param_adv_10fdx, rgep->param_adv_10hdx)); 486 487 control = gigctrl = anar = 0; 488 489 /* 490 * PHY settings are normally based on the param_* variables, 491 * but if any loopback mode is in effect, that takes precedence. 492 * 493 * RGE supports MAC-internal loopback, PHY-internal loopback, 494 * and External loopback at a variety of speeds (with a special 495 * cable). In all cases, autoneg is turned OFF, full-duplex 496 * is turned ON, and the speed/mastership is forced. 497 */ 498 switch (rgep->param_loop_mode) { 499 case RGE_LOOP_NONE: 500 default: 501 adv_autoneg = rgep->param_adv_autoneg; 502 adv_pause = rgep->param_adv_pause; 503 adv_asym_pause = rgep->param_adv_asym_pause; 504 adv_1000fdx = rgep->param_adv_1000fdx; 505 adv_1000hdx = rgep->param_adv_1000hdx; 506 adv_100fdx = rgep->param_adv_100fdx; 507 adv_100hdx = rgep->param_adv_100hdx; 508 adv_10fdx = rgep->param_adv_10fdx; 509 adv_10hdx = rgep->param_adv_10hdx; 510 break; 511 512 case RGE_LOOP_INTERNAL_PHY: 513 case RGE_LOOP_INTERNAL_MAC: 514 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 515 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 516 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 517 rgep->param_link_duplex = LINK_DUPLEX_FULL; 518 519 switch (rgep->param_loop_mode) { 520 case RGE_LOOP_INTERNAL_PHY: 521 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 522 rgep->param_link_speed = 1000; 523 adv_1000fdx = B_TRUE; 524 } else { 525 rgep->param_link_speed = 100; 526 adv_100fdx = B_TRUE; 527 } 528 control = MII_CONTROL_LOOPBACK; 529 break; 530 531 case RGE_LOOP_INTERNAL_MAC: 532 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 533 rgep->param_link_speed = 1000; 534 adv_1000fdx = B_TRUE; 535 } else { 536 rgep->param_link_speed = 100; 537 adv_100fdx = B_TRUE; 538 break; 539 } 540 } 541 542 RGE_DEBUG(("rge_phy_update: autoneg %d " 543 "pause %d asym_pause %d " 544 "1000fdx %d 1000hdx %d " 545 "100fdx %d 100hdx %d " 546 "10fdx %d 10hdx %d ", 547 adv_autoneg, 548 adv_pause, adv_asym_pause, 549 adv_1000fdx, adv_1000hdx, 550 adv_100fdx, adv_100hdx, 551 adv_10fdx, adv_10hdx)); 552 553 /* 554 * We should have at least one technology capability set; 555 * if not, we select a default of 1000Mb/s full-duplex 556 */ 557 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 558 !adv_1000hdx && !adv_100hdx && !adv_10hdx) { 559 if (rgep->chipid.mac_ver != MAC_VER_8101E) 560 adv_1000fdx = B_TRUE; 561 } else { 562 adv_1000fdx = B_FALSE; 563 adv_100fdx = B_TRUE; 564 } 565 } 566 567 /* 568 * Now transform the adv_* variables into the proper settings 569 * of the PHY registers ... 570 * 571 * If autonegotiation is (now) enabled, we want to trigger 572 * a new autonegotiation cycle once the PHY has been 573 * programmed with the capabilities to be advertised. 574 * 575 * RTL8169/8110 doesn't support 1000Mb/s half-duplex. 576 */ 577 if (adv_autoneg) 578 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 579 580 if (adv_1000fdx) 581 control |= MII_CONTROL_1000MB|MII_CONTROL_FDUPLEX; 582 else if (adv_1000hdx) 583 control |= MII_CONTROL_1000MB; 584 else if (adv_100fdx) 585 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 586 else if (adv_100hdx) 587 control |= MII_CONTROL_100MB; 588 else if (adv_10fdx) 589 control |= MII_CONTROL_FDUPLEX; 590 else if (adv_10hdx) 591 control |= 0; 592 else 593 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 594 595 if (adv_1000fdx) { 596 gigctrl |= MII_1000BT_CTL_ADV_FDX; 597 /* 598 * Chipset limitation: need set other capabilities to true 599 */ 600 if (rgep->chipid.is_pcie) 601 adv_1000hdx = B_TRUE; 602 adv_100fdx = B_TRUE; 603 adv_100hdx = B_TRUE; 604 adv_10fdx = B_TRUE; 605 adv_10hdx = B_TRUE; 606 } 607 608 if (adv_1000hdx) 609 gigctrl |= MII_1000BT_CTL_ADV_HDX; 610 611 if (adv_100fdx) 612 anar |= MII_ABILITY_100BASE_TX_FD; 613 if (adv_100hdx) 614 anar |= MII_ABILITY_100BASE_TX; 615 if (adv_10fdx) 616 anar |= MII_ABILITY_10BASE_T_FD; 617 if (adv_10hdx) 618 anar |= MII_ABILITY_10BASE_T; 619 620 if (adv_pause) 621 anar |= MII_ABILITY_PAUSE; 622 if (adv_asym_pause) 623 anar |= MII_ABILITY_ASYM_PAUSE; 624 625 /* 626 * Munge in any other fixed bits we require ... 627 */ 628 anar |= MII_AN_SELECTOR_8023; 629 630 /* 631 * Restart the PHY and write the new values. Note the 632 * time, so that we can say whether subsequent link state 633 * changes can be attributed to our reprogramming the PHY 634 */ 635 rge_phy_init(rgep); 636 rge_mii_put16(rgep, MII_AN_ADVERT, anar); 637 rge_mii_put16(rgep, MII_1000BASE_T_CONTROL, gigctrl); 638 rge_mii_put16(rgep, MII_CONTROL, control); 639 640 RGE_DEBUG(("rge_phy_update: anar <- 0x%x", anar)); 641 RGE_DEBUG(("rge_phy_update: control <- 0x%x", control)); 642 RGE_DEBUG(("rge_phy_update: gigctrl <- 0x%x", gigctrl)); 643 } 644 645 void rge_phy_init(rge_t *rgep); 646 #pragma no_inline(rge_phy_init) 647 648 void 649 rge_phy_init(rge_t *rgep) 650 { 651 rgep->phy_mii_addr = 1; 652 653 /* 654 * Below phy config steps are copied from the Programming Guide 655 * (there's no detail comments for these steps.) 656 */ 657 switch (rgep->chipid.mac_ver) { 658 case MAC_VER_8169S_D: 659 case MAC_VER_8169S_E : 660 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 661 rge_mii_put16(rgep, PHY_15_REG, 0x1000); 662 rge_mii_put16(rgep, PHY_18_REG, 0x65c7); 663 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 664 rge_mii_put16(rgep, PHY_ID_REG_2, 0x00a1); 665 rge_mii_put16(rgep, PHY_ID_REG_1, 0x0008); 666 rge_mii_put16(rgep, PHY_BMSR_REG, 0x1020); 667 rge_mii_put16(rgep, PHY_BMCR_REG, 0x1000); 668 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0800); 669 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 670 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 671 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 672 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde60); 673 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 674 rge_mii_put16(rgep, PHY_BMCR_REG, 0x0077); 675 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7800); 676 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 677 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 678 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 679 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 680 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 681 rge_mii_put16(rgep, PHY_BMCR_REG, 0xfa00); 682 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa800); 683 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 684 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 685 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 686 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde20); 687 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 688 rge_mii_put16(rgep, PHY_BMCR_REG, 0x00bb); 689 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb800); 690 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 691 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 692 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 693 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 694 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 695 rge_mii_put16(rgep, PHY_BMCR_REG, 0xbf00); 696 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf800); 697 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 698 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 699 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 700 rge_mii_put16(rgep, PHY_0B_REG, 0x0000); 701 break; 702 703 case MAC_VER_8169SB: 704 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 705 rge_mii_put16(rgep, PHY_1B_REG, 0xD41E); 706 rge_mii_put16(rgep, PHY_0E_REG, 0x7bff); 707 rge_mii_put16(rgep, PHY_GBCR_REG, GBCR_DEFAULT); 708 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 709 rge_mii_put16(rgep, PHY_BMSR_REG, 0x90D0); 710 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 711 break; 712 713 case MAC_VER_8169SC: 714 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 715 rge_mii_put16(rgep, PHY_ANER_REG, 0x0078); 716 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x05dc); 717 rge_mii_put16(rgep, PHY_GBCR_REG, 0x2672); 718 rge_mii_put16(rgep, PHY_GBSR_REG, 0x6a14); 719 rge_mii_put16(rgep, PHY_0B_REG, 0x7cb0); 720 rge_mii_put16(rgep, PHY_0C_REG, 0xdb80); 721 rge_mii_put16(rgep, PHY_1B_REG, 0xc414); 722 rge_mii_put16(rgep, PHY_1C_REG, 0xef03); 723 rge_mii_put16(rgep, PHY_1D_REG, 0x3dc8); 724 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 725 rge_mii_put16(rgep, PHY_13_REG, 0x0600); 726 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 727 break; 728 729 case MAC_VER_8168: 730 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 731 rge_mii_put16(rgep, PHY_ANER_REG, 0x00aa); 732 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x3173); 733 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x08fc); 734 rge_mii_put16(rgep, PHY_GBCR_REG, 0xe2d0); 735 rge_mii_put16(rgep, PHY_0B_REG, 0x941a); 736 rge_mii_put16(rgep, PHY_18_REG, 0x65fe); 737 rge_mii_put16(rgep, PHY_1C_REG, 0x1e02); 738 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 739 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x103e); 740 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 741 break; 742 743 case MAC_VER_8168B_B: 744 case MAC_VER_8168B_C: 745 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 746 rge_mii_put16(rgep, PHY_0B_REG, 0x94b0); 747 rge_mii_put16(rgep, PHY_1B_REG, 0xc416); 748 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 749 rge_mii_put16(rgep, PHY_12_REG, 0x6096); 750 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 751 break; 752 } 753 } 754 755 void rge_chip_ident(rge_t *rgep); 756 #pragma no_inline(rge_chip_ident) 757 758 void 759 rge_chip_ident(rge_t *rgep) 760 { 761 chip_id_t *chip = &rgep->chipid; 762 uint32_t val32; 763 uint16_t val16; 764 765 /* 766 * Read and record MAC version 767 */ 768 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 769 val32 &= HW_VERSION_ID_0 | HW_VERSION_ID_1; 770 chip->mac_ver = val32; 771 switch (chip->mac_ver) { 772 case MAC_VER_8168: 773 case MAC_VER_8168B_B: 774 case MAC_VER_8168B_C: 775 case MAC_VER_8101E: 776 chip->is_pcie = B_TRUE; 777 break; 778 779 default: 780 chip->is_pcie = B_FALSE; 781 break; 782 } 783 784 /* 785 * Read and record PHY version 786 */ 787 val16 = rge_mii_get16(rgep, PHY_ID_REG_2); 788 val16 &= PHY_VER_MASK; 789 chip->phy_ver = val16; 790 791 /* set pci latency timer */ 792 if (chip->mac_ver == MAC_VER_8169 || 793 chip->mac_ver == MAC_VER_8169S_D || 794 chip->mac_ver == MAC_VER_8169SC) 795 pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40); 796 797 if (chip->mac_ver == MAC_VER_8169SC) { 798 val16 = rge_reg_get16(rgep, RT_CONFIG_1_REG); 799 val16 &= 0x0300; 800 if (val16 == 0x1) /* 66Mhz PCI */ 801 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ff00ff); 802 else if (val16 == 0x0) /* 33Mhz PCI */ 803 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ffff00); 804 } 805 806 /* 807 * PCIE chipset require the Rx buffer start address must be 808 * 8-byte alignment and the Rx buffer size must be multiple of 8. 809 * We'll just use bcopy in receive procedure for the PCIE chipset. 810 */ 811 if (chip->is_pcie) { 812 rgep->chip_flags |= CHIP_FLAG_FORCE_BCOPY; 813 if (rgep->default_mtu > ETHERMTU) { 814 rge_notice(rgep, "Jumbo packets not supported " 815 "for this PCIE chipset"); 816 rgep->default_mtu = ETHERMTU; 817 } 818 } 819 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY) 820 rgep->head_room = 0; 821 else 822 rgep->head_room = RGE_HEADROOM; 823 824 /* 825 * Initialize other variables. 826 */ 827 if (rgep->default_mtu < ETHERMTU || rgep->default_mtu > RGE_JUMBO_MTU) 828 rgep->default_mtu = ETHERMTU; 829 if (rgep->default_mtu > ETHERMTU) { 830 rgep->rxbuf_size = RGE_BUFF_SIZE_JUMBO; 831 rgep->txbuf_size = RGE_BUFF_SIZE_JUMBO; 832 rgep->ethmax_size = RGE_JUMBO_SIZE; 833 } else { 834 rgep->rxbuf_size = RGE_BUFF_SIZE_STD; 835 rgep->txbuf_size = RGE_BUFF_SIZE_STD; 836 rgep->ethmax_size = ETHERMAX; 837 } 838 chip->rxconfig = RX_CONFIG_DEFAULT; 839 chip->txconfig = TX_CONFIG_DEFAULT; 840 841 RGE_TRACE(("%s: MAC version = %x, PHY version = %x", 842 rgep->ifname, chip->mac_ver, chip->phy_ver)); 843 } 844 845 /* 846 * Perform first-stage chip (re-)initialisation, using only config-space 847 * accesses: 848 * 849 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 850 * returning the data in the structure pointed to by <idp>. 851 * + Enable Memory Space accesses. 852 * + Enable Bus Mastering according. 853 */ 854 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp); 855 #pragma no_inline(rge_chip_cfg_init) 856 857 void 858 rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp) 859 { 860 ddi_acc_handle_t handle; 861 uint16_t commd; 862 863 handle = rgep->cfg_handle; 864 865 /* 866 * Save PCI cache line size and subsystem vendor ID 867 */ 868 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 869 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 870 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 871 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 872 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 873 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 874 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 875 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 876 877 /* 878 * Turn on Master Enable (DMA) and IO Enable bits. 879 * Enable PCI Memory Space accesses 880 */ 881 commd = cidp->command; 882 commd |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 883 pci_config_put16(handle, PCI_CONF_COMM, commd); 884 885 RGE_DEBUG(("rge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 886 cidp->vendor, cidp->device, cidp->revision)); 887 RGE_DEBUG(("rge_chip_cfg_init: subven 0x%x subdev 0x%x", 888 cidp->subven, cidp->subdev)); 889 RGE_DEBUG(("rge_chip_cfg_init: clsize %d latency %d command 0x%x", 890 cidp->clsize, cidp->latency, cidp->command)); 891 } 892 893 int rge_chip_reset(rge_t *rgep); 894 #pragma no_inline(rge_chip_reset) 895 896 int 897 rge_chip_reset(rge_t *rgep) 898 { 899 int i; 900 uint8_t val8; 901 902 /* 903 * Chip should be in STOP state 904 */ 905 rge_reg_clr8(rgep, RT_COMMAND_REG, 906 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 907 908 /* 909 * Disable interrupt 910 */ 911 rgep->int_mask = INT_MASK_NONE; 912 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 913 914 /* 915 * Clear pended interrupt 916 */ 917 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 918 919 /* 920 * Reset chip 921 */ 922 rge_reg_set8(rgep, RT_COMMAND_REG, RT_COMMAND_RESET); 923 924 /* 925 * Wait for reset success 926 */ 927 for (i = 0; i < CHIP_RESET_LOOP; i++) { 928 drv_usecwait(10); 929 val8 = rge_reg_get8(rgep, RT_COMMAND_REG); 930 if (!(val8 & RT_COMMAND_RESET)) { 931 rgep->rge_chip_state = RGE_CHIP_RESET; 932 return (0); 933 } 934 } 935 RGE_REPORT((rgep, "rge_chip_reset fail.")); 936 return (-1); 937 } 938 939 void rge_chip_init(rge_t *rgep); 940 #pragma no_inline(rge_chip_init) 941 942 void 943 rge_chip_init(rge_t *rgep) 944 { 945 uint32_t val32; 946 uint32_t val16; 947 uint32_t *hashp; 948 chip_id_t *chip = &rgep->chipid; 949 950 if (chip->is_pcie) { 951 /* 952 * Increase the threshold voltage of RX sensitivity 953 */ 954 if (chip->mac_ver != MAC_VER_8168) 955 rge_ephy_put16(rgep, 0x01, 0x1bd3); 956 957 val16 = rge_reg_get8(rgep, PHY_STATUS_REG); 958 val16 = 0x12<<8 | val16; 959 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 960 rge_reg_put16(rgep, PHY_STATUS_REG, val16); 961 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00021c01); 962 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f088); 963 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00004000); 964 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f0b0); 965 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x0000f068); 966 val32 = rge_reg_get32(rgep, RT_CSI_DATA_REG); 967 val32 |= 0x7000; 968 val32 &= 0xffff5fff; 969 rge_reg_put32(rgep, RT_CSI_DATA_REG, val32); 970 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f068); 971 } 972 } 973 974 /* 975 * Config MII register 976 */ 977 rgep->param_link_up = LINK_STATE_DOWN; 978 rge_phy_update(rgep); 979 980 /* 981 * Enable Rx checksum offload. 982 * Then for vlan support, we must enable receive vlan de-tagging. 983 * Otherwise, there'll be checksum error. 984 */ 985 val16 = rge_reg_get16(rgep, CPLUS_COMMAND_REG); 986 val16 |= RX_CKSM_OFFLOAD | RX_VLAN_DETAG; 987 if (chip->mac_ver == MAC_VER_8169S_D) { 988 val16 |= CPLUS_BIT14 | MUL_PCI_RW_ENABLE; 989 rge_reg_put8(rgep, RESV_82_REG, 0x01); 990 } 991 rge_reg_put16(rgep, CPLUS_COMMAND_REG, val16 & (~0x03)); 992 993 /* 994 * Start transmit/receive before set tx/rx configuration register 995 */ 996 if (!chip->is_pcie) 997 rge_reg_set8(rgep, RT_COMMAND_REG, 998 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 999 1000 /* 1001 * Set dump tally counter register 1002 */ 1003 val32 = rgep->dma_area_stats.cookie.dmac_laddress >> 32; 1004 rge_reg_put32(rgep, DUMP_COUNTER_REG_1, val32); 1005 val32 = rge_reg_get32(rgep, DUMP_COUNTER_REG_0); 1006 val32 &= DUMP_COUNTER_REG_RESV; 1007 val32 |= rgep->dma_area_stats.cookie.dmac_laddress; 1008 rge_reg_put32(rgep, DUMP_COUNTER_REG_0, val32); 1009 1010 /* 1011 * Change to config register write enable mode 1012 */ 1013 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1014 1015 /* 1016 * Set Tx/Rx maximum packet size 1017 */ 1018 if (rgep->default_mtu > ETHERMTU) { 1019 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_JUMBO); 1020 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_JUMBO); 1021 } else if (rgep->chipid.mac_ver != MAC_VER_8101E) { 1022 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD); 1023 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD); 1024 } else { 1025 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD_8101E); 1026 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD_8101E); 1027 } 1028 1029 /* 1030 * Set receive configuration register 1031 */ 1032 val32 = rge_reg_get32(rgep, RX_CONFIG_REG); 1033 val32 &= RX_CONFIG_REG_RESV; 1034 if (rgep->promisc) 1035 val32 |= RX_ACCEPT_ALL_PKT; 1036 rge_reg_put32(rgep, RX_CONFIG_REG, val32 | chip->rxconfig); 1037 1038 /* 1039 * Set transmit configuration register 1040 */ 1041 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 1042 val32 &= TX_CONFIG_REG_RESV; 1043 rge_reg_put32(rgep, TX_CONFIG_REG, val32 | chip->txconfig); 1044 1045 /* 1046 * Set Tx/Rx descriptor register 1047 */ 1048 val32 = rgep->tx_desc.cookie.dmac_laddress; 1049 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_LO_REG, val32); 1050 val32 = rgep->tx_desc.cookie.dmac_laddress >> 32; 1051 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_HI_REG, val32); 1052 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_LO_REG, 0); 1053 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_HI_REG, 0); 1054 val32 = rgep->rx_desc.cookie.dmac_laddress; 1055 rge_reg_put32(rgep, RX_RING_ADDR_LO_REG, val32); 1056 val32 = rgep->rx_desc.cookie.dmac_laddress >> 32; 1057 rge_reg_put32(rgep, RX_RING_ADDR_HI_REG, val32); 1058 1059 /* 1060 * Suggested setting from Realtek 1061 */ 1062 if (rgep->chipid.mac_ver != MAC_VER_8101E) 1063 rge_reg_put16(rgep, RESV_E2_REG, 0x282a); 1064 else 1065 rge_reg_put16(rgep, RESV_E2_REG, 0x0000); 1066 1067 /* 1068 * Set multicast register 1069 */ 1070 hashp = (uint32_t *)rgep->mcast_hash; 1071 rge_reg_put32(rgep, MULTICAST_0_REG, hashp[0]); 1072 rge_reg_put32(rgep, MULTICAST_4_REG, hashp[1]); 1073 1074 /* 1075 * Msic register setting: 1076 * -- Missed packet counter: clear it 1077 * -- TimerInt Register 1078 * -- Timer count register 1079 */ 1080 rge_reg_put32(rgep, RX_PKT_MISS_COUNT_REG, 0); 1081 rge_reg_put32(rgep, TIMER_INT_REG, TIMER_INT_NONE); 1082 rge_reg_put32(rgep, TIMER_COUNT_REG, 0); 1083 1084 /* 1085 * Return to normal network/host communication mode 1086 */ 1087 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1088 drv_usecwait(20); 1089 } 1090 1091 /* 1092 * rge_chip_start() -- start the chip transmitting and/or receiving, 1093 * including enabling interrupts 1094 */ 1095 void rge_chip_start(rge_t *rgep); 1096 #pragma no_inline(rge_chip_start) 1097 1098 void 1099 rge_chip_start(rge_t *rgep) 1100 { 1101 /* 1102 * Clear statistics 1103 */ 1104 bzero(&rgep->stats, sizeof (rge_stats_t)); 1105 DMA_ZERO(rgep->dma_area_stats); 1106 1107 /* 1108 * Start transmit/receive 1109 */ 1110 rge_reg_set8(rgep, RT_COMMAND_REG, 1111 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1112 1113 /* 1114 * Enable interrupt 1115 */ 1116 rgep->int_mask = RGE_INT_MASK; 1117 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1118 1119 /* 1120 * All done! 1121 */ 1122 rgep->rge_chip_state = RGE_CHIP_RUNNING; 1123 } 1124 1125 /* 1126 * rge_chip_stop() -- stop board receiving 1127 */ 1128 void rge_chip_stop(rge_t *rgep, boolean_t fault); 1129 #pragma no_inline(rge_chip_stop) 1130 1131 void 1132 rge_chip_stop(rge_t *rgep, boolean_t fault) 1133 { 1134 /* 1135 * Disable interrupt 1136 */ 1137 rgep->int_mask = INT_MASK_NONE; 1138 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1139 1140 /* 1141 * Clear pended interrupt 1142 */ 1143 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 1144 1145 /* 1146 * Stop the board and disable transmit/receive 1147 */ 1148 rge_reg_clr8(rgep, RT_COMMAND_REG, 1149 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1150 1151 if (fault) 1152 rgep->rge_chip_state = RGE_CHIP_FAULT; 1153 else 1154 rgep->rge_chip_state = RGE_CHIP_STOPPED; 1155 } 1156 1157 /* 1158 * rge_get_mac_addr() -- get the MAC address on NIC 1159 */ 1160 static void rge_get_mac_addr(rge_t *rgep); 1161 #pragma inline(rge_get_mac_addr) 1162 1163 static void 1164 rge_get_mac_addr(rge_t *rgep) 1165 { 1166 uint8_t *macaddr = rgep->netaddr; 1167 uint32_t val32; 1168 1169 /* 1170 * Read first 4-byte of mac address 1171 */ 1172 val32 = rge_reg_get32(rgep, ID_0_REG); 1173 macaddr[0] = val32 & 0xff; 1174 val32 = val32 >> 8; 1175 macaddr[1] = val32 & 0xff; 1176 val32 = val32 >> 8; 1177 macaddr[2] = val32 & 0xff; 1178 val32 = val32 >> 8; 1179 macaddr[3] = val32 & 0xff; 1180 1181 /* 1182 * Read last 2-byte of mac address 1183 */ 1184 val32 = rge_reg_get32(rgep, ID_4_REG); 1185 macaddr[4] = val32 & 0xff; 1186 val32 = val32 >> 8; 1187 macaddr[5] = val32 & 0xff; 1188 } 1189 1190 static void rge_set_mac_addr(rge_t *rgep); 1191 #pragma inline(rge_set_mac_addr) 1192 1193 static void 1194 rge_set_mac_addr(rge_t *rgep) 1195 { 1196 uint8_t *p = rgep->netaddr; 1197 uint32_t val32; 1198 1199 /* 1200 * Change to config register write enable mode 1201 */ 1202 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1203 1204 /* 1205 * Get first 4 bytes of mac address 1206 */ 1207 val32 = p[3]; 1208 val32 = val32 << 8; 1209 val32 |= p[2]; 1210 val32 = val32 << 8; 1211 val32 |= p[1]; 1212 val32 = val32 << 8; 1213 val32 |= p[0]; 1214 1215 /* 1216 * Set first 4 bytes of mac address 1217 */ 1218 rge_reg_put32(rgep, ID_0_REG, val32); 1219 1220 /* 1221 * Get last 2 bytes of mac address 1222 */ 1223 val32 = p[5]; 1224 val32 = val32 << 8; 1225 val32 |= p[4]; 1226 1227 /* 1228 * Set last 2 bytes of mac address 1229 */ 1230 val32 |= rge_reg_get32(rgep, ID_4_REG) & ~0xffff; 1231 rge_reg_put32(rgep, ID_4_REG, val32); 1232 1233 /* 1234 * Return to normal network/host communication mode 1235 */ 1236 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1237 } 1238 1239 static void rge_set_multi_addr(rge_t *rgep); 1240 #pragma inline(rge_set_multi_addr) 1241 1242 static void 1243 rge_set_multi_addr(rge_t *rgep) 1244 { 1245 uint32_t *hashp; 1246 1247 hashp = (uint32_t *)rgep->mcast_hash; 1248 1249 /* 1250 * Change to config register write enable mode 1251 */ 1252 if (rgep->chipid.mac_ver == MAC_VER_8169SC) 1253 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1254 1255 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0])); 1256 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1])); 1257 1258 /* 1259 * Return to normal network/host communication mode 1260 */ 1261 if (rgep->chipid.mac_ver == MAC_VER_8169SC) 1262 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1263 } 1264 1265 static void rge_set_promisc(rge_t *rgep); 1266 #pragma inline(rge_set_promisc) 1267 1268 static void 1269 rge_set_promisc(rge_t *rgep) 1270 { 1271 if (rgep->promisc) 1272 rge_reg_set32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1273 else 1274 rge_reg_clr32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1275 } 1276 1277 /* 1278 * rge_chip_sync() -- program the chip with the unicast MAC address, 1279 * the multicast hash table, the required level of promiscuity, and 1280 * the current loopback mode ... 1281 */ 1282 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo); 1283 #pragma no_inline(rge_chip_sync) 1284 1285 void 1286 rge_chip_sync(rge_t *rgep, enum rge_sync_op todo) 1287 { 1288 switch (todo) { 1289 case RGE_GET_MAC: 1290 rge_get_mac_addr(rgep); 1291 break; 1292 case RGE_SET_MAC: 1293 /* Reprogram the unicast MAC address(es) ... */ 1294 rge_set_mac_addr(rgep); 1295 break; 1296 case RGE_SET_MUL: 1297 /* Reprogram the hashed multicast address table ... */ 1298 rge_set_multi_addr(rgep); 1299 break; 1300 case RGE_SET_PROMISC: 1301 /* Set or clear the PROMISCUOUS mode bit */ 1302 rge_set_promisc(rgep); 1303 break; 1304 default: 1305 break; 1306 } 1307 } 1308 1309 void rge_chip_blank(void *arg, time_t ticks, uint_t count); 1310 #pragma no_inline(rge_chip_blank) 1311 1312 void 1313 rge_chip_blank(void *arg, time_t ticks, uint_t count) 1314 { 1315 _NOTE(ARGUNUSED(arg, ticks, count)); 1316 } 1317 1318 void rge_tx_trigger(rge_t *rgep); 1319 #pragma no_inline(rge_tx_trigger) 1320 1321 void 1322 rge_tx_trigger(rge_t *rgep) 1323 { 1324 rge_reg_set8(rgep, TX_RINGS_POLL_REG, NORMAL_TX_RING_POLL); 1325 } 1326 1327 void rge_hw_stats_dump(rge_t *rgep); 1328 #pragma no_inline(rge_tx_trigger) 1329 1330 void 1331 rge_hw_stats_dump(rge_t *rgep) 1332 { 1333 int i = 0; 1334 1335 while (rge_reg_get32(rgep, DUMP_COUNTER_REG_0) & DUMP_START) { 1336 drv_usecwait(100); 1337 if (++i > STATS_DUMP_LOOP) { 1338 RGE_DEBUG(("rge h/w statistics dump fail!")); 1339 rgep->rge_chip_state = RGE_CHIP_ERROR; 1340 return; 1341 } 1342 } 1343 DMA_SYNC(rgep->dma_area_stats, DDI_DMA_SYNC_FORKERNEL); 1344 1345 /* 1346 * Start H/W statistics dump for RTL8169 chip 1347 */ 1348 rge_reg_set32(rgep, DUMP_COUNTER_REG_0, DUMP_START); 1349 } 1350 1351 /* 1352 * ========== Hardware interrupt handler ========== 1353 */ 1354 1355 #undef RGE_DBG 1356 #define RGE_DBG RGE_DBG_INT /* debug flag for this code */ 1357 1358 static void rge_wake_factotum(rge_t *rgep); 1359 #pragma inline(rge_wake_factotum) 1360 1361 static void 1362 rge_wake_factotum(rge_t *rgep) 1363 { 1364 if (rgep->factotum_flag == 0) { 1365 rgep->factotum_flag = 1; 1366 (void) ddi_intr_trigger_softint(rgep->factotum_hdl, NULL); 1367 } 1368 } 1369 1370 /* 1371 * rge_intr() -- handle chip interrupts 1372 */ 1373 uint_t rge_intr(caddr_t arg1, caddr_t arg2); 1374 #pragma no_inline(rge_intr) 1375 1376 uint_t 1377 rge_intr(caddr_t arg1, caddr_t arg2) 1378 { 1379 rge_t *rgep = (rge_t *)arg1; 1380 uint16_t int_status; 1381 1382 _NOTE(ARGUNUSED(arg2)) 1383 1384 mutex_enter(rgep->genlock); 1385 /* 1386 * Was this interrupt caused by our device... 1387 */ 1388 int_status = rge_reg_get16(rgep, INT_STATUS_REG); 1389 if (!(int_status & rgep->int_mask)) { 1390 mutex_exit(rgep->genlock); 1391 return (DDI_INTR_UNCLAIMED); 1392 /* indicate it wasn't our interrupt */ 1393 } 1394 rgep->stats.intr++; 1395 1396 /* 1397 * Clear interrupt 1398 * For PCIE chipset, we need disable interrupt first. 1399 */ 1400 if (rgep->chipid.is_pcie) 1401 rge_reg_put16(rgep, INT_MASK_REG, INT_MASK_NONE); 1402 rge_reg_put16(rgep, INT_STATUS_REG, int_status); 1403 1404 /* 1405 * Cable link change interrupt 1406 */ 1407 if (int_status & LINK_CHANGE_INT) { 1408 rge_chip_cyclic(rgep); 1409 } 1410 1411 mutex_exit(rgep->genlock); 1412 1413 /* 1414 * Receive interrupt 1415 */ 1416 if (int_status & RGE_RX_INT) 1417 rge_receive(rgep); 1418 1419 /* 1420 * Re-enable interrupt for PCIE chipset 1421 */ 1422 if (rgep->chipid.is_pcie) 1423 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1424 1425 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */ 1426 } 1427 1428 /* 1429 * ========== Factotum, implemented as a softint handler ========== 1430 */ 1431 1432 #undef RGE_DBG 1433 #define RGE_DBG RGE_DBG_FACT /* debug flag for this code */ 1434 1435 static boolean_t rge_factotum_link_check(rge_t *rgep); 1436 #pragma no_inline(rge_factotum_link_check) 1437 1438 static boolean_t 1439 rge_factotum_link_check(rge_t *rgep) 1440 { 1441 uint8_t media_status; 1442 int32_t link; 1443 1444 media_status = rge_reg_get8(rgep, PHY_STATUS_REG); 1445 link = (media_status & PHY_STATUS_LINK_UP) ? 1446 LINK_STATE_UP : LINK_STATE_DOWN; 1447 if (rgep->param_link_up != link) { 1448 /* 1449 * Link change. 1450 */ 1451 rgep->param_link_up = link; 1452 1453 if (link == LINK_STATE_UP) { 1454 if (media_status & PHY_STATUS_1000MF) { 1455 rgep->param_link_speed = RGE_SPEED_1000M; 1456 rgep->param_link_duplex = LINK_DUPLEX_FULL; 1457 } else { 1458 rgep->param_link_speed = 1459 (media_status & PHY_STATUS_100M) ? 1460 RGE_SPEED_100M : RGE_SPEED_10M; 1461 rgep->param_link_duplex = 1462 (media_status & PHY_STATUS_DUPLEX_FULL) ? 1463 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF; 1464 } 1465 } 1466 return (B_TRUE); 1467 } 1468 return (B_FALSE); 1469 } 1470 1471 /* 1472 * Factotum routine to check for Tx stall, using the 'watchdog' counter 1473 */ 1474 static boolean_t rge_factotum_stall_check(rge_t *rgep); 1475 #pragma no_inline(rge_factotum_stall_check) 1476 1477 static boolean_t 1478 rge_factotum_stall_check(rge_t *rgep) 1479 { 1480 uint32_t dogval; 1481 1482 ASSERT(mutex_owned(rgep->genlock)); 1483 1484 /* 1485 * Specific check for Tx stall ... 1486 * 1487 * The 'watchdog' counter is incremented whenever a packet 1488 * is queued, reset to 1 when some (but not all) buffers 1489 * are reclaimed, reset to 0 (disabled) when all buffers 1490 * are reclaimed, and shifted left here. If it exceeds the 1491 * threshold value, the chip is assumed to have stalled and 1492 * is put into the ERROR state. The factotum will then reset 1493 * it on the next pass. 1494 * 1495 * All of which should ensure that we don't get into a state 1496 * where packets are left pending indefinitely! 1497 */ 1498 if (rgep->resched_needed) 1499 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL); 1500 dogval = rge_atomic_shl32(&rgep->watchdog, 1); 1501 if (dogval < rge_watchdog_count) 1502 return (B_FALSE); 1503 1504 RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval)); 1505 return (B_TRUE); 1506 1507 } 1508 1509 /* 1510 * The factotum is woken up when there's something to do that we'd rather 1511 * not do from inside a hardware interrupt handler or high-level cyclic. 1512 * Its two main tasks are: 1513 * reset & restart the chip after an error 1514 * check the link status whenever necessary 1515 */ 1516 uint_t rge_chip_factotum(caddr_t arg1, caddr_t arg2); 1517 #pragma no_inline(rge_chip_factotum) 1518 1519 uint_t 1520 rge_chip_factotum(caddr_t arg1, caddr_t arg2) 1521 { 1522 rge_t *rgep; 1523 uint_t result; 1524 boolean_t error; 1525 boolean_t linkchg; 1526 1527 rgep = (rge_t *)arg1; 1528 _NOTE(ARGUNUSED(arg2)) 1529 1530 if (rgep->factotum_flag == 0) 1531 return (DDI_INTR_UNCLAIMED); 1532 1533 rgep->factotum_flag = 0; 1534 result = DDI_INTR_CLAIMED; 1535 error = B_FALSE; 1536 linkchg = B_FALSE; 1537 1538 mutex_enter(rgep->genlock); 1539 switch (rgep->rge_chip_state) { 1540 default: 1541 break; 1542 1543 case RGE_CHIP_RUNNING: 1544 linkchg = rge_factotum_link_check(rgep); 1545 error = rge_factotum_stall_check(rgep); 1546 break; 1547 1548 case RGE_CHIP_ERROR: 1549 error = B_TRUE; 1550 break; 1551 1552 case RGE_CHIP_FAULT: 1553 /* 1554 * Fault detected, time to reset ... 1555 */ 1556 if (rge_autorecover) { 1557 RGE_REPORT((rgep, "automatic recovery activated")); 1558 rge_restart(rgep); 1559 } 1560 break; 1561 } 1562 1563 /* 1564 * If an error is detected, stop the chip now, marking it as 1565 * faulty, so that it will be reset next time through ... 1566 */ 1567 if (error) 1568 rge_chip_stop(rgep, B_TRUE); 1569 mutex_exit(rgep->genlock); 1570 1571 /* 1572 * If the link state changed, tell the world about it. 1573 * Note: can't do this while still holding the mutex. 1574 */ 1575 if (linkchg) 1576 mac_link_update(rgep->mh, rgep->param_link_up); 1577 1578 return (result); 1579 } 1580 1581 /* 1582 * High-level cyclic handler 1583 * 1584 * This routine schedules a (low-level) softint callback to the 1585 * factotum, and prods the chip to update the status block (which 1586 * will cause a hardware interrupt when complete). 1587 */ 1588 void rge_chip_cyclic(void *arg); 1589 #pragma no_inline(rge_chip_cyclic) 1590 1591 void 1592 rge_chip_cyclic(void *arg) 1593 { 1594 rge_t *rgep; 1595 1596 rgep = arg; 1597 1598 switch (rgep->rge_chip_state) { 1599 default: 1600 return; 1601 1602 case RGE_CHIP_RUNNING: 1603 rge_phy_check(rgep); 1604 break; 1605 1606 case RGE_CHIP_FAULT: 1607 case RGE_CHIP_ERROR: 1608 break; 1609 } 1610 1611 rge_wake_factotum(rgep); 1612 } 1613 1614 1615 /* 1616 * ========== Ioctl subfunctions ========== 1617 */ 1618 1619 #undef RGE_DBG 1620 #define RGE_DBG RGE_DBG_PPIO /* debug flag for this code */ 1621 1622 #if RGE_DEBUGGING || RGE_DO_PPIO 1623 1624 static void rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1625 #pragma no_inline(rge_chip_peek_cfg) 1626 1627 static void 1628 rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1629 { 1630 uint64_t regval; 1631 uint64_t regno; 1632 1633 RGE_TRACE(("rge_chip_peek_cfg($%p, $%p)", 1634 (void *)rgep, (void *)ppd)); 1635 1636 regno = ppd->pp_acc_offset; 1637 1638 switch (ppd->pp_acc_size) { 1639 case 1: 1640 regval = pci_config_get8(rgep->cfg_handle, regno); 1641 break; 1642 1643 case 2: 1644 regval = pci_config_get16(rgep->cfg_handle, regno); 1645 break; 1646 1647 case 4: 1648 regval = pci_config_get32(rgep->cfg_handle, regno); 1649 break; 1650 1651 case 8: 1652 regval = pci_config_get64(rgep->cfg_handle, regno); 1653 break; 1654 } 1655 1656 ppd->pp_acc_data = regval; 1657 } 1658 1659 static void rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1660 #pragma no_inline(rge_chip_poke_cfg) 1661 1662 static void 1663 rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1664 { 1665 uint64_t regval; 1666 uint64_t regno; 1667 1668 RGE_TRACE(("rge_chip_poke_cfg($%p, $%p)", 1669 (void *)rgep, (void *)ppd)); 1670 1671 regno = ppd->pp_acc_offset; 1672 regval = ppd->pp_acc_data; 1673 1674 switch (ppd->pp_acc_size) { 1675 case 1: 1676 pci_config_put8(rgep->cfg_handle, regno, regval); 1677 break; 1678 1679 case 2: 1680 pci_config_put16(rgep->cfg_handle, regno, regval); 1681 break; 1682 1683 case 4: 1684 pci_config_put32(rgep->cfg_handle, regno, regval); 1685 break; 1686 1687 case 8: 1688 pci_config_put64(rgep->cfg_handle, regno, regval); 1689 break; 1690 } 1691 } 1692 1693 static void rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1694 #pragma no_inline(rge_chip_peek_reg) 1695 1696 static void 1697 rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1698 { 1699 uint64_t regval; 1700 void *regaddr; 1701 1702 RGE_TRACE(("rge_chip_peek_reg($%p, $%p)", 1703 (void *)rgep, (void *)ppd)); 1704 1705 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1706 1707 switch (ppd->pp_acc_size) { 1708 case 1: 1709 regval = ddi_get8(rgep->io_handle, regaddr); 1710 break; 1711 1712 case 2: 1713 regval = ddi_get16(rgep->io_handle, regaddr); 1714 break; 1715 1716 case 4: 1717 regval = ddi_get32(rgep->io_handle, regaddr); 1718 break; 1719 1720 case 8: 1721 regval = ddi_get64(rgep->io_handle, regaddr); 1722 break; 1723 } 1724 1725 ppd->pp_acc_data = regval; 1726 } 1727 1728 static void rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1729 #pragma no_inline(rge_chip_peek_reg) 1730 1731 static void 1732 rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1733 { 1734 uint64_t regval; 1735 void *regaddr; 1736 1737 RGE_TRACE(("rge_chip_poke_reg($%p, $%p)", 1738 (void *)rgep, (void *)ppd)); 1739 1740 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1741 regval = ppd->pp_acc_data; 1742 1743 switch (ppd->pp_acc_size) { 1744 case 1: 1745 ddi_put8(rgep->io_handle, regaddr, regval); 1746 break; 1747 1748 case 2: 1749 ddi_put16(rgep->io_handle, regaddr, regval); 1750 break; 1751 1752 case 4: 1753 ddi_put32(rgep->io_handle, regaddr, regval); 1754 break; 1755 1756 case 8: 1757 ddi_put64(rgep->io_handle, regaddr, regval); 1758 break; 1759 } 1760 } 1761 1762 static void rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1763 #pragma no_inline(rge_chip_peek_mii) 1764 1765 static void 1766 rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1767 { 1768 RGE_TRACE(("rge_chip_peek_mii($%p, $%p)", 1769 (void *)rgep, (void *)ppd)); 1770 1771 ppd->pp_acc_data = rge_mii_get16(rgep, ppd->pp_acc_offset/2); 1772 } 1773 1774 static void rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1775 #pragma no_inline(rge_chip_poke_mii) 1776 1777 static void 1778 rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1779 { 1780 RGE_TRACE(("rge_chip_poke_mii($%p, $%p)", 1781 (void *)rgep, (void *)ppd)); 1782 1783 rge_mii_put16(rgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 1784 } 1785 1786 static void rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1787 #pragma no_inline(rge_chip_peek_mem) 1788 1789 static void 1790 rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1791 { 1792 uint64_t regval; 1793 void *vaddr; 1794 1795 RGE_TRACE(("rge_chip_peek_rge($%p, $%p)", 1796 (void *)rgep, (void *)ppd)); 1797 1798 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1799 1800 switch (ppd->pp_acc_size) { 1801 case 1: 1802 regval = *(uint8_t *)vaddr; 1803 break; 1804 1805 case 2: 1806 regval = *(uint16_t *)vaddr; 1807 break; 1808 1809 case 4: 1810 regval = *(uint32_t *)vaddr; 1811 break; 1812 1813 case 8: 1814 regval = *(uint64_t *)vaddr; 1815 break; 1816 } 1817 1818 RGE_DEBUG(("rge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 1819 (void *)rgep, (void *)ppd, regval, vaddr)); 1820 1821 ppd->pp_acc_data = regval; 1822 } 1823 1824 static void rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1825 #pragma no_inline(rge_chip_poke_mem) 1826 1827 static void 1828 rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1829 { 1830 uint64_t regval; 1831 void *vaddr; 1832 1833 RGE_TRACE(("rge_chip_poke_mem($%p, $%p)", 1834 (void *)rgep, (void *)ppd)); 1835 1836 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1837 regval = ppd->pp_acc_data; 1838 1839 RGE_DEBUG(("rge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 1840 (void *)rgep, (void *)ppd, regval, vaddr)); 1841 1842 switch (ppd->pp_acc_size) { 1843 case 1: 1844 *(uint8_t *)vaddr = (uint8_t)regval; 1845 break; 1846 1847 case 2: 1848 *(uint16_t *)vaddr = (uint16_t)regval; 1849 break; 1850 1851 case 4: 1852 *(uint32_t *)vaddr = (uint32_t)regval; 1853 break; 1854 1855 case 8: 1856 *(uint64_t *)vaddr = (uint64_t)regval; 1857 break; 1858 } 1859 } 1860 1861 static enum ioc_reply rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1862 struct iocblk *iocp); 1863 #pragma no_inline(rge_pp_ioctl) 1864 1865 static enum ioc_reply 1866 rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1867 { 1868 void (*ppfn)(rge_t *rgep, rge_peekpoke_t *ppd); 1869 rge_peekpoke_t *ppd; 1870 dma_area_t *areap; 1871 uint64_t sizemask; 1872 uint64_t mem_va; 1873 uint64_t maxoff; 1874 boolean_t peek; 1875 1876 switch (cmd) { 1877 default: 1878 /* NOTREACHED */ 1879 rge_error(rgep, "rge_pp_ioctl: invalid cmd 0x%x", cmd); 1880 return (IOC_INVAL); 1881 1882 case RGE_PEEK: 1883 peek = B_TRUE; 1884 break; 1885 1886 case RGE_POKE: 1887 peek = B_FALSE; 1888 break; 1889 } 1890 1891 /* 1892 * Validate format of ioctl 1893 */ 1894 if (iocp->ioc_count != sizeof (rge_peekpoke_t)) 1895 return (IOC_INVAL); 1896 if (mp->b_cont == NULL) 1897 return (IOC_INVAL); 1898 ppd = (rge_peekpoke_t *)mp->b_cont->b_rptr; 1899 1900 /* 1901 * Validate request parameters 1902 */ 1903 switch (ppd->pp_acc_space) { 1904 default: 1905 return (IOC_INVAL); 1906 1907 case RGE_PP_SPACE_CFG: 1908 /* 1909 * Config space 1910 */ 1911 sizemask = 8|4|2|1; 1912 mem_va = 0; 1913 maxoff = PCI_CONF_HDR_SIZE; 1914 ppfn = peek ? rge_chip_peek_cfg : rge_chip_poke_cfg; 1915 break; 1916 1917 case RGE_PP_SPACE_REG: 1918 /* 1919 * Memory-mapped I/O space 1920 */ 1921 sizemask = 8|4|2|1; 1922 mem_va = 0; 1923 maxoff = RGE_REGISTER_MAX; 1924 ppfn = peek ? rge_chip_peek_reg : rge_chip_poke_reg; 1925 break; 1926 1927 case RGE_PP_SPACE_MII: 1928 /* 1929 * PHY's MII registers 1930 * NB: all PHY registers are two bytes, but the 1931 * addresses increment in ones (word addressing). 1932 * So we scale the address here, then undo the 1933 * transformation inside the peek/poke functions. 1934 */ 1935 ppd->pp_acc_offset *= 2; 1936 sizemask = 2; 1937 mem_va = 0; 1938 maxoff = (MII_MAXREG+1)*2; 1939 ppfn = peek ? rge_chip_peek_mii : rge_chip_poke_mii; 1940 break; 1941 1942 case RGE_PP_SPACE_RGE: 1943 /* 1944 * RGE data structure! 1945 */ 1946 sizemask = 8|4|2|1; 1947 mem_va = (uintptr_t)rgep; 1948 maxoff = sizeof (*rgep); 1949 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1950 break; 1951 1952 case RGE_PP_SPACE_STATISTICS: 1953 case RGE_PP_SPACE_TXDESC: 1954 case RGE_PP_SPACE_TXBUFF: 1955 case RGE_PP_SPACE_RXDESC: 1956 case RGE_PP_SPACE_RXBUFF: 1957 /* 1958 * Various DMA_AREAs 1959 */ 1960 switch (ppd->pp_acc_space) { 1961 case RGE_PP_SPACE_TXDESC: 1962 areap = &rgep->dma_area_txdesc; 1963 break; 1964 case RGE_PP_SPACE_RXDESC: 1965 areap = &rgep->dma_area_rxdesc; 1966 break; 1967 case RGE_PP_SPACE_STATISTICS: 1968 areap = &rgep->dma_area_stats; 1969 break; 1970 } 1971 1972 sizemask = 8|4|2|1; 1973 mem_va = (uintptr_t)areap->mem_va; 1974 maxoff = areap->alength; 1975 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1976 break; 1977 } 1978 1979 switch (ppd->pp_acc_size) { 1980 default: 1981 return (IOC_INVAL); 1982 1983 case 8: 1984 case 4: 1985 case 2: 1986 case 1: 1987 if ((ppd->pp_acc_size & sizemask) == 0) 1988 return (IOC_INVAL); 1989 break; 1990 } 1991 1992 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 1993 return (IOC_INVAL); 1994 1995 if (ppd->pp_acc_offset >= maxoff) 1996 return (IOC_INVAL); 1997 1998 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 1999 return (IOC_INVAL); 2000 2001 /* 2002 * All OK - go do it! 2003 */ 2004 ppd->pp_acc_offset += mem_va; 2005 (*ppfn)(rgep, ppd); 2006 return (peek ? IOC_REPLY : IOC_ACK); 2007 } 2008 2009 static enum ioc_reply rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 2010 struct iocblk *iocp); 2011 #pragma no_inline(rge_diag_ioctl) 2012 2013 static enum ioc_reply 2014 rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 2015 { 2016 ASSERT(mutex_owned(rgep->genlock)); 2017 2018 switch (cmd) { 2019 default: 2020 /* NOTREACHED */ 2021 rge_error(rgep, "rge_diag_ioctl: invalid cmd 0x%x", cmd); 2022 return (IOC_INVAL); 2023 2024 case RGE_DIAG: 2025 /* 2026 * Currently a no-op 2027 */ 2028 return (IOC_ACK); 2029 2030 case RGE_PEEK: 2031 case RGE_POKE: 2032 return (rge_pp_ioctl(rgep, cmd, mp, iocp)); 2033 2034 case RGE_PHY_RESET: 2035 return (IOC_RESTART_ACK); 2036 2037 case RGE_SOFT_RESET: 2038 case RGE_HARD_RESET: 2039 /* 2040 * Reset and reinitialise the 570x hardware 2041 */ 2042 rge_restart(rgep); 2043 return (IOC_ACK); 2044 } 2045 2046 /* NOTREACHED */ 2047 } 2048 2049 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2050 2051 static enum ioc_reply rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 2052 struct iocblk *iocp); 2053 #pragma no_inline(rge_mii_ioctl) 2054 2055 static enum ioc_reply 2056 rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 2057 { 2058 struct rge_mii_rw *miirwp; 2059 2060 /* 2061 * Validate format of ioctl 2062 */ 2063 if (iocp->ioc_count != sizeof (struct rge_mii_rw)) 2064 return (IOC_INVAL); 2065 if (mp->b_cont == NULL) 2066 return (IOC_INVAL); 2067 miirwp = (struct rge_mii_rw *)mp->b_cont->b_rptr; 2068 2069 /* 2070 * Validate request parameters ... 2071 */ 2072 if (miirwp->mii_reg > MII_MAXREG) 2073 return (IOC_INVAL); 2074 2075 switch (cmd) { 2076 default: 2077 /* NOTREACHED */ 2078 rge_error(rgep, "rge_mii_ioctl: invalid cmd 0x%x", cmd); 2079 return (IOC_INVAL); 2080 2081 case RGE_MII_READ: 2082 miirwp->mii_data = rge_mii_get16(rgep, miirwp->mii_reg); 2083 return (IOC_REPLY); 2084 2085 case RGE_MII_WRITE: 2086 rge_mii_put16(rgep, miirwp->mii_reg, miirwp->mii_data); 2087 return (IOC_ACK); 2088 } 2089 2090 /* NOTREACHED */ 2091 } 2092 2093 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, 2094 struct iocblk *iocp); 2095 #pragma no_inline(rge_chip_ioctl) 2096 2097 enum ioc_reply 2098 rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2099 { 2100 int cmd; 2101 2102 RGE_TRACE(("rge_chip_ioctl($%p, $%p, $%p, $%p)", 2103 (void *)rgep, (void *)wq, (void *)mp, (void *)iocp)); 2104 2105 ASSERT(mutex_owned(rgep->genlock)); 2106 2107 cmd = iocp->ioc_cmd; 2108 switch (cmd) { 2109 default: 2110 /* NOTREACHED */ 2111 rge_error(rgep, "rge_chip_ioctl: invalid cmd 0x%x", cmd); 2112 return (IOC_INVAL); 2113 2114 case RGE_DIAG: 2115 case RGE_PEEK: 2116 case RGE_POKE: 2117 case RGE_PHY_RESET: 2118 case RGE_SOFT_RESET: 2119 case RGE_HARD_RESET: 2120 #if RGE_DEBUGGING || RGE_DO_PPIO 2121 return (rge_diag_ioctl(rgep, cmd, mp, iocp)); 2122 #else 2123 return (IOC_INVAL); 2124 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2125 2126 case RGE_MII_READ: 2127 case RGE_MII_WRITE: 2128 return (rge_mii_ioctl(rgep, cmd, mp, iocp)); 2129 2130 } 2131 2132 /* NOTREACHED */ 2133 } 2134