xref: /titanic_51/usr/src/uts/common/io/rge/rge.h (revision 651c0131ccc65381cbda174bee44a4fd7a518d6b)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _RGE_H
27 #define	_RGE_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34 
35 #include <sys/types.h>
36 #include <sys/stream.h>
37 #include <sys/strsun.h>
38 #include <sys/strsubr.h>
39 #include <sys/stat.h>
40 #include <sys/pci.h>
41 #include <sys/note.h>
42 #include <sys/modctl.h>
43 #include <sys/kstat.h>
44 #include <sys/ethernet.h>
45 #include <sys/vlan.h>
46 #include <sys/errno.h>
47 #include <sys/dlpi.h>
48 #include <sys/devops.h>
49 #include <sys/debug.h>
50 #include <sys/cyclic.h>
51 #include <sys/conf.h>
52 
53 #include <netinet/ip6.h>
54 #include <inet/common.h>
55 #include <inet/ip.h>
56 #include <inet/mi.h>
57 #include <inet/nd.h>
58 #include <sys/pattr.h>
59 
60 #include <sys/dditypes.h>
61 #include <sys/ddi.h>
62 #include <sys/sunddi.h>
63 
64 #include <sys/mac.h>
65 #include <sys/mac_ether.h>
66 
67 /*
68  * Reconfiguring the network devices requires the net_config privilege
69  * in Solaris 10+.
70  */
71 extern int secpolicy_net_config(const cred_t *, boolean_t);
72 
73 #include <sys/netlb.h>			/* originally from cassini	*/
74 #include <sys/miiregs.h>		/* by fjlite out of intel 	*/
75 
76 #include "rge_hw.h"
77 
78 /*
79  * Name of the driver
80  */
81 #define	RGE_DRIVER_NAME		"rge"
82 
83 /*
84  * The driver supports the NDD ioctls ND_GET/ND_SET, and the loopback
85  * ioctls LB_GET_INFO_SIZE/LB_GET_INFO/LB_GET_MODE/LB_SET_MODE
86  *
87  * These are the values to use with LD_SET_MODE.
88  */
89 #define	RGE_LOOP_NONE		0
90 #define	RGE_LOOP_INTERNAL_PHY	1
91 #define	RGE_LOOP_INTERNAL_MAC	2
92 
93 /*
94  * RGE-specific ioctls ...
95  */
96 #define	RGE_IOC			((((('R' << 8) + 'G') << 8) + 'E') << 8)
97 
98 /*
99  * PHY register read/write ioctls, used by cable test software
100  */
101 #define	RGE_MII_READ		(RGE_IOC|1)
102 #define	RGE_MII_WRITE		(RGE_IOC|2)
103 
104 struct rge_mii_rw {
105 	uint32_t	mii_reg;	/* PHY register number [0..31]	*/
106 	uint32_t	mii_data;	/* data to write/data read	*/
107 };
108 
109 /*
110  * These diagnostic IOCTLS are enabled only in DEBUG drivers
111  */
112 #define	RGE_DIAG		(RGE_IOC|10)	/* currently a no-op	*/
113 #define	RGE_PEEK		(RGE_IOC|11)
114 #define	RGE_POKE		(RGE_IOC|12)
115 #define	RGE_PHY_RESET		(RGE_IOC|13)
116 #define	RGE_SOFT_RESET		(RGE_IOC|14)
117 #define	RGE_HARD_RESET		(RGE_IOC|15)
118 
119 typedef struct {
120 	uint64_t		pp_acc_size;	/* in bytes: 1,2,4,8	*/
121 	uint64_t		pp_acc_space;	/* See #defines below	*/
122 	uint64_t		pp_acc_offset;
123 	uint64_t		pp_acc_data;	/* output for peek	*/
124 						/* input for poke	*/
125 } rge_peekpoke_t;
126 
127 #define	RGE_PP_SPACE_CFG	0		/* PCI config space	*/
128 #define	RGE_PP_SPACE_REG	1		/* PCI memory space	*/
129 #define	RGE_PP_SPACE_MII	2		/* PHY's MII registers	*/
130 #define	RGE_PP_SPACE_RGE	3		/* driver's soft state	*/
131 #define	RGE_PP_SPACE_TXDESC	4		/* TX descriptors	*/
132 #define	RGE_PP_SPACE_TXBUFF	5		/* TX buffers		*/
133 #define	RGE_PP_SPACE_RXDESC	6		/* RX descriptors	*/
134 #define	RGE_PP_SPACE_RXBUFF	7		/* RX buffers		*/
135 #define	RGE_PP_SPACE_STATISTICS	8		/* statistics block	*/
136 
137 /*
138  * RTL8169 CRC poly
139  */
140 #define	RGE_HASH_POLY		0x04C11DB7	/* 0x04C11DB6 */
141 #define	RGE_HASH_CRC		0xFFFFFFFFU
142 #define	RGE_MCAST_BUF_SIZE	64	/* multicast hash table size in bits */
143 
144 /*
145  * Rx/Tx buffer parameters
146  */
147 #define	RGE_BUF_SLOTS		2048
148 #define	RGE_RECV_COPY_SIZE	256
149 #define	RGE_HEADROOM		6
150 
151 /*
152  * Driver chip operation parameters
153  */
154 #define	RGE_CYCLIC_PERIOD	(1000000000)	/* ~1s */
155 #define	CHIP_RESET_LOOP		1000
156 #define	PHY_RESET_LOOP		10
157 #define	STATS_DUMP_LOOP		1000
158 #define	RXBUFF_FREE_LOOP	1000
159 #define	RGE_RX_INT_TIME		128
160 #define	RGE_RX_INT_PKTS		8
161 
162 /*
163  * Named Data (ND) Parameter Management Structure
164  */
165 typedef struct {
166 	int			ndp_info;
167 	int			ndp_min;
168 	int			ndp_max;
169 	int			ndp_val;
170 	char			*ndp_name;
171 } nd_param_t;				/* 0x18 (24) bytes	*/
172 
173 /*
174  * NDD parameter indexes, divided into:
175  *
176  *	read-only parameters describing the hardware's capabilities
177  *	read-write parameters controlling the advertised capabilities
178  *	read-only parameters describing the partner's capabilities
179  *	read-only parameters describing the link state
180  */
181 enum {
182 	PARAM_AUTONEG_CAP = 0,
183 	PARAM_PAUSE_CAP,
184 	PARAM_ASYM_PAUSE_CAP,
185 	PARAM_1000FDX_CAP,
186 	PARAM_1000HDX_CAP,
187 	PARAM_100T4_CAP,
188 	PARAM_100FDX_CAP,
189 	PARAM_100HDX_CAP,
190 	PARAM_10FDX_CAP,
191 	PARAM_10HDX_CAP,
192 
193 	PARAM_ADV_AUTONEG_CAP,
194 	PARAM_ADV_PAUSE_CAP,
195 	PARAM_ADV_ASYM_PAUSE_CAP,
196 	PARAM_ADV_1000FDX_CAP,
197 	PARAM_ADV_1000HDX_CAP,
198 	PARAM_ADV_100T4_CAP,
199 	PARAM_ADV_100FDX_CAP,
200 	PARAM_ADV_100HDX_CAP,
201 	PARAM_ADV_10FDX_CAP,
202 	PARAM_ADV_10HDX_CAP,
203 
204 	PARAM_LINK_STATUS,
205 	PARAM_LINK_SPEED,
206 	PARAM_LINK_DUPLEX,
207 
208 	PARAM_LOOP_MODE,
209 
210 	PARAM_COUNT
211 };
212 
213 enum rge_chip_state {
214 	RGE_CHIP_FAULT = -2,			/* fault, need reset	*/
215 	RGE_CHIP_ERROR,				/* error, want reset	*/
216 	RGE_CHIP_INITIAL,			/* Initial state only	*/
217 	RGE_CHIP_RESET,				/* reset, need init	*/
218 	RGE_CHIP_STOPPED,			/* Tx/Rx stopped	*/
219 	RGE_CHIP_RUNNING			/* with interrupts	*/
220 };
221 
222 enum rge_mac_state {
223 	RGE_MAC_ATTACH = 0,
224 	RGE_MAC_STOPPED,
225 	RGE_MAC_STARTED,
226 	RGE_MAC_UNATTACH
227 };
228 
229 enum rge_sync_op {
230 	RGE_OP_NULL,
231 	RGE_GET_MAC,				/* get mac address operation */
232 	RGE_SET_MAC,				/* set mac address operation */
233 	RGE_SET_MUL,				/* set multicast address op */
234 	RGE_SET_PROMISC				/* set promisc mode */
235 };
236 
237 /*
238  * (Internal) return values from ioctl subroutines
239  */
240 enum ioc_reply {
241 	IOC_INVAL = -1,				/* bad, NAK with EINVAL	*/
242 	IOC_DONE,				/* OK, reply sent	*/
243 	IOC_ACK,				/* OK, just send ACK	*/
244 	IOC_REPLY,				/* OK, just send reply	*/
245 	IOC_RESTART_ACK,			/* OK, restart & ACK	*/
246 	IOC_RESTART_REPLY			/* OK, restart & reply	*/
247 };
248 
249 /*
250  * (Internal) enumeration of this driver's kstats
251  */
252 enum {
253 	RGE_KSTAT_DRIVER = 0,
254 	RGE_KSTAT_COUNT
255 };
256 
257 /*
258  * Basic data types, for clarity in distinguishing 'numbers'
259  * used for different purposes ...
260  *
261  * A <rge_regno_t> is a register 'address' (offset) in any one of
262  * various address spaces (PCI config space, PCI memory-mapped I/O
263  * register space, MII registers, etc).  None of these exceeds 64K,
264  * so we could use a 16-bit representation but pointer-sized objects
265  * are more "natural" in most architectures; they seem to be handled
266  * more efficiently on SPARC and no worse on x86.
267  *
268  * RGE_REGNO_NONE represents the non-existent value in this space.
269  */
270 typedef uintptr_t rge_regno_t;			/* register # (offset)	*/
271 #define	RGE_REGNO_NONE		(~(uintptr_t)0u)
272 
273 /*
274  * Describes one chunk of allocated DMA-able memory
275  *
276  * In some cases, this is a single chunk as allocated from the system;
277  * but we also use this structure to represent slices carved off such
278  * a chunk.  Even when we don't really need all the information, we
279  * use this structure as a convenient way of correlating the various
280  * ways of looking at a piece of memory (kernel VA, IO space DVMA,
281  * handle+offset, etc).
282  */
283 typedef struct {
284 	ddi_acc_handle_t	acc_hdl;	/* handle for memory	*/
285 	void			*mem_va;	/* CPU VA of memory	*/
286 	uint32_t		nslots;		/* number of slots	*/
287 	uint32_t		size;		/* size per slot	*/
288 	size_t			alength;	/* allocated size */
289 	ddi_dma_handle_t	dma_hdl;	/* DMA handle */
290 	offset_t		offset;		/* relative to handle	*/
291 	ddi_dma_cookie_t	cookie;		/* associated cookie */
292 	uint32_t		ncookies;	/* must be 1 */
293 	uint32_t		token;		/* arbitrary identifier	*/
294 } dma_area_t;
295 
296 /*
297  * Software version of the Receive Buffer Descriptor
298  */
299 typedef struct {
300 	caddr_t			private;	/* pointer to rge */
301 	dma_area_t		pbuf;		/* (const) related	*/
302 						/* buffer area		*/
303 	frtn_t			rx_recycle;	/* recycle function */
304 	mblk_t			*mp;
305 } dma_buf_t;
306 
307 typedef struct sw_rbd {
308 	dma_buf_t		*rx_buf;
309 	uint8_t			flags;
310 } sw_rbd_t;
311 
312 /*
313  * Software version of the Send Buffer Descriptor
314  */
315 typedef struct sw_sbd {
316 	dma_area_t		desc;		/* (const) related h/w	*/
317 						/* descriptor area	*/
318 	dma_area_t		pbuf;		/* (const) related	*/
319 						/* buffer area		*/
320 } sw_sbd_t;
321 
322 
323 #define	HW_RBD_INIT(rbd, slot)					\
324 	rbd->flags_len |= RGE_BSWAP_32(BD_FLAG_HW_OWN);		\
325 	rbd->vlan_tag = 0;					\
326 	if (slot == (RGE_RECV_SLOTS -1))			\
327 		rbd->flags_len |= RGE_BSWAP_32(BD_FLAG_EOR);
328 #define	HW_SBD_INIT(sbd, slot)					\
329 	sbd->flags_len = 0;					\
330 	if (slot == (RGE_SEND_SLOTS -1))			\
331 		sbd->flags_len |= RGE_BSWAP_32(BD_FLAG_EOR);
332 #define	HW_SBD_SET(sbd, slot)					\
333 	sbd->flags_len |= RGE_BSWAP_32(SBD_FLAG_TX_PKT);	\
334 	if (slot == (RGE_SEND_SLOTS -1))			\
335 		sbd->flags_len |= RGE_BSWAP_32(BD_FLAG_EOR);
336 
337 /*
338  * Describes the characteristics of a specific chip
339  */
340 typedef struct {
341 	uint16_t		command;	/* saved during attach	*/
342 	uint16_t		vendor;		/* vendor-id		*/
343 	uint16_t		device;		/* device-id		*/
344 	uint16_t		subven;		/* subsystem-vendor-id	*/
345 	uint16_t		subdev;		/* subsystem-id		*/
346 	uint8_t			revision;	/* revision-id		*/
347 	uint8_t			clsize;		/* cache-line-size	*/
348 	uint8_t			latency;	/* latency-timer	*/
349 	boolean_t		is_pcie;
350 	uint32_t		mac_ver;
351 	uint32_t		phy_ver;
352 	uint32_t		rxconfig;
353 	uint32_t		txconfig;
354 } chip_id_t;
355 
356 typedef struct rge_stats {
357 	uint64_t	rbytes;
358 	uint64_t	obytes;
359 	uint32_t	overflow;
360 	uint32_t	defer;		/* dot3StatsDeferredTransmissions */
361 	uint32_t	crc_err;	/* dot3StatsFCSErrors */
362 	uint32_t	in_short;
363 	uint32_t	no_rcvbuf;	/* ifInDiscards */
364 	uint32_t	intr;		/* interrupt count */
365 	uint16_t	chip_reset;
366 	uint16_t	phy_reset;
367 } rge_stats_t;
368 
369 /*
370  * Per-instance soft-state structure
371  */
372 typedef struct rge {
373 	dev_info_t		*devinfo;	/* device instance	*/
374 	mac_handle_t		mh;		/* mac module handle	*/
375 	ddi_acc_handle_t	cfg_handle;	/* DDI I/O handle	*/
376 	ddi_acc_handle_t	io_handle;	/* DDI I/O handle	*/
377 	caddr_t			io_regs;	/* mapped registers	*/
378 	cyclic_id_t		cyclic_id;	/* cyclic callback	*/
379 	ddi_softint_handle_t	resched_hdl;	/* reschedule callback	*/
380 	ddi_softint_handle_t	factotum_hdl;	/* factotum callback	*/
381 	uint_t			soft_pri;
382 	ddi_intr_handle_t 	*htable;	/* For array of interrupts */
383 	int			intr_type;	/* What type of interrupt */
384 	int			intr_rqst;	/* # of request intrs count */
385 	int			intr_cnt;	/* # of intrs count returned */
386 	uint_t			intr_pri;	/* Interrupt priority	*/
387 	int			intr_cap;	/* Interrupt capabilities */
388 	boolean_t		msi_enable;
389 
390 	uint32_t		ethmax_size;
391 	uint32_t		default_mtu;
392 	uint32_t		rxbuf_size;
393 	uint32_t		txbuf_size;
394 	uint32_t		chip_flags;
395 	uint32_t		head_room;
396 	char			ifname[8];	/* "rge0" ... "rge999"	*/
397 	int32_t			instance;
398 	uint32_t		progress;	/* attach tracking	*/
399 	uint32_t		debug;		/* per-instance debug	*/
400 	chip_id_t		chipid;
401 
402 	/*
403 	 * These structures describe the blocks of memory allocated during
404 	 * attach().  They remain unchanged thereafter, although the memory
405 	 * they describe is carved up into various separate regions and may
406 	 * therefore be described by other structures as well.
407 	 */
408 	dma_area_t		dma_area_rxdesc;
409 	dma_area_t		dma_area_txdesc;
410 	dma_area_t		dma_area_stats;
411 				/* describes hardware statistics area	*/
412 
413 	uint8_t			netaddr[ETHERADDRL];	/* mac address	*/
414 	uint16_t		int_mask;	/* interrupt mask	*/
415 
416 	/* used for multicast/promisc mode set */
417 	char			mcast_refs[RGE_MCAST_BUF_SIZE];
418 	uint8_t			mcast_hash[RGE_MCAST_NUM];
419 	boolean_t		promisc;	/* promisc state flag	*/
420 
421 	/* used for recv */
422 	rge_bd_t		*rx_ring;
423 	dma_area_t		rx_desc;
424 	boolean_t		rx_bcopy;
425 	uint32_t		rx_next;	/* current rx bd index	*/
426 	sw_rbd_t		*sw_rbds;
427 	sw_rbd_t		*free_srbds;
428 	uint32_t		rf_next;	/* current free buf index */
429 	uint32_t		rc_next;	/* current recycle buf index */
430 	uint32_t		rx_free;	/* number of rx free buf */
431 	mac_resource_handle_t	handle;
432 
433 	/* used for send */
434 	rge_bd_t		*tx_ring;
435 	dma_area_t		tx_desc;
436 	uint32_t		tx_free;	/* number of free tx bd */
437 	uint32_t		tx_next;	/* current tx bd index	*/
438 	uint32_t		tc_next;	/* current tx recycle index */
439 	uint32_t		tx_flow;
440 	uint32_t		tc_tail;
441 	sw_sbd_t		*sw_sbds;
442 
443 	/* mutex */
444 	kmutex_t		genlock[1];	/* i/o reg access	*/
445 	krwlock_t		errlock[1];	/* rge restart */
446 	kmutex_t		tx_lock[1];	/* send access		*/
447 	kmutex_t		tc_lock[1];	/* send recycle access */
448 	kmutex_t		rx_lock[1];	/* receive access	*/
449 	kmutex_t		rc_lock[1];	/* receive recycle access */
450 
451 	/*
452 	 * Miscellaneous operating variables (not synchronised)
453 	 */
454 	uint32_t		watchdog;	/* watches for Tx stall	*/
455 	boolean_t		resched_needed;
456 	uint32_t		factotum_flag;	/* softint pending	*/
457 
458 	/*
459 	 * Physical layer
460 	 */
461 	rge_regno_t		phy_mii_addr;	/* should be (const) 1!	*/
462 	uint16_t		link_down_count;
463 
464 	/*
465 	 * NDD parameters (protected by genlock)
466 	 */
467 	caddr_t			nd_data_p;
468 	nd_param_t		nd_params[PARAM_COUNT];
469 
470 	/*
471 	 * Driver kstats, protected by <genlock> where necessary
472 	 */
473 	kstat_t			*rge_kstats[RGE_KSTAT_COUNT];
474 
475 	/* H/W statistics */
476 	rge_hw_stats_t		*hw_stats;
477 	rge_stats_t		stats;
478 	enum rge_mac_state	rge_mac_state;	/* definitions above	*/
479 	enum rge_chip_state	rge_chip_state;	/* definitions above	*/
480 } rge_t;
481 
482 /*
483  * 'Progress' bit flags ...
484  */
485 #define	PROGRESS_CFG		0x0001	/* config space mapped		*/
486 #define	PROGRESS_REGS		0x0002	/* registers mapped		*/
487 #define	PROGRESS_RESCHED	0x0010	/* resched softint registered	*/
488 #define	PROGRESS_FACTOTUM	0x0020	/* factotum softint registered	*/
489 #define	PROGRESS_INTR		0X0040	/* h/w interrupt registered	*/
490 					/* and mutexen initialised	*/
491 #define	PROGRESS_INIT		0x0080	/* rx/buf/tx ring initialised	*/
492 #define	PROGRESS_PHY		0x0100	/* PHY initialised		*/
493 #define	PROGRESS_NDD		0x1000	/* NDD parameters set up	*/
494 #define	PROGRESS_KSTATS		0x2000	/* kstats created		*/
495 #define	PROGRESS_READY		0x8000	/* ready for work		*/
496 
497 /*
498  * Special chip flags
499  */
500 #define	CHIP_FLAG_FORCE_BCOPY	0x10000000
501 
502 /*
503  * Shorthand for the NDD parameters
504  */
505 #define	param_adv_autoneg	nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val
506 #define	param_adv_pause		nd_params[PARAM_ADV_PAUSE_CAP].ndp_val
507 #define	param_adv_asym_pause	nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val
508 #define	param_adv_1000fdx	nd_params[PARAM_ADV_1000FDX_CAP].ndp_val
509 #define	param_adv_1000hdx	nd_params[PARAM_ADV_1000HDX_CAP].ndp_val
510 #define	param_adv_100fdx	nd_params[PARAM_ADV_100FDX_CAP].ndp_val
511 #define	param_adv_100hdx	nd_params[PARAM_ADV_100HDX_CAP].ndp_val
512 #define	param_adv_10fdx		nd_params[PARAM_ADV_10FDX_CAP].ndp_val
513 #define	param_adv_10hdx		nd_params[PARAM_ADV_10HDX_CAP].ndp_val
514 
515 #define	param_link_up		nd_params[PARAM_LINK_STATUS].ndp_val
516 #define	param_link_speed	nd_params[PARAM_LINK_SPEED].ndp_val
517 #define	param_link_duplex	nd_params[PARAM_LINK_DUPLEX].ndp_val
518 
519 #define	param_loop_mode		nd_params[PARAM_LOOP_MODE].ndp_val
520 
521 /*
522  * Sync a DMA area described by a dma_area_t
523  */
524 #define	DMA_SYNC(area, flag)	((void) ddi_dma_sync((area).dma_hdl,	\
525 				    (area).offset, (area).alength, (flag)))
526 
527 /*
528  * Find the (kernel virtual) address of block of memory
529  * described by a dma_area_t
530  */
531 #define	DMA_VPTR(area)		((area).mem_va)
532 
533 /*
534  * Zero a block of memory described by a dma_area_t
535  */
536 #define	DMA_ZERO(area)		bzero(DMA_VPTR(area), (area).alength)
537 
538 /*
539  * Next/Last value of a cyclic index
540  */
541 #define	NEXT(index, limit)	((index)+1 < (limit) ? (index)+1 : 0);
542 #define	LAST(index, limit)	((index) ? (index)-1 : (limit - 1));
543 /*
544  * Property lookups
545  */
546 #define	RGE_PROP_EXISTS(d, n)	ddi_prop_exists(DDI_DEV_T_ANY, (d),	\
547 					DDI_PROP_DONTPASS, (n))
548 #define	RGE_PROP_GET_INT(d, n)	ddi_prop_get_int(DDI_DEV_T_ANY, (d),	\
549 					DDI_PROP_DONTPASS, (n), -1)
550 
551 /*
552  * Endian swap
553  */
554 #ifdef	_BIG_ENDIAN
555 #define	RGE_BSWAP_16(x)		((((x) & 0xff00) >> 8)	|		\
556 				    (((x) & 0x00ff) << 8))
557 #define	RGE_BSWAP_32(x)		((((x) & 0xff000000) >> 24)	|	\
558 				    (((x) & 0x00ff0000) >> 8)	|	\
559 				    (((x) & 0x0000ff00) << 8)	|	\
560 				    (((x) & 0x000000ff) << 24))
561 #define	RGE_BSWAP_64(x)		(RGE_BSWAP_32((x) >> 32)	|	\
562 				    (RGE_BSWAP_32(x) << 32))
563 #else
564 #define	RGE_BSWAP_16(x)		(x)
565 #define	RGE_BSWAP_32(x)		(x)
566 #define	RGE_BSWAP_64(x)		(x)
567 #endif
568 
569 /*
570  * Bit test macros, returning boolean_t values
571  */
572 #define	BIS(w, b)	(((w) & (b)) ? B_TRUE : B_FALSE)
573 #define	BIC(w, b)	(((w) & (b)) ? B_FALSE : B_TRUE)
574 #define	UPORDOWN(x)	((x) ? "up" : "down")
575 
576 /*
577  * Bit flags in the 'debug' word ...
578  */
579 #define	RGE_DBG_STOP		0x00000001	/* early debug_enter()	*/
580 #define	RGE_DBG_TRACE		0x00000002	/* general flow tracing	*/
581 
582 #define	RGE_DBG_REGS		0x00000010	/* low-level accesses	*/
583 #define	RGE_DBG_MII		0x00000020	/* low-level MII access	*/
584 #define	RGE_DBG_SEEPROM		0x00000040	/* low-level SEEPROM IO	*/
585 #define	RGE_DBG_CHIP		0x00000080	/* low(ish)-level code	*/
586 
587 #define	RGE_DBG_RECV		0x00000100	/* receive-side code	*/
588 #define	RGE_DBG_SEND		0x00000200	/* packet-send code	*/
589 
590 #define	RGE_DBG_INT		0x00001000	/* interrupt handler	*/
591 #define	RGE_DBG_FACT		0x00002000	/* factotum (softint)	*/
592 
593 #define	RGE_DBG_PHY		0x00010000	/* Copper PHY code	*/
594 #define	RGE_DBG_SERDES		0x00020000	/* SerDes code		*/
595 #define	RGE_DBG_PHYS		0x00040000	/* Physical layer code	*/
596 #define	RGE_DBG_LINK		0x00080000	/* Link status check	*/
597 
598 #define	RGE_DBG_INIT		0x00100000	/* initialisation	*/
599 #define	RGE_DBG_NEMO		0x00200000	/* nemo interaction	*/
600 #define	RGE_DBG_ADDR		0x00400000	/* address-setting code	*/
601 #define	RGE_DBG_STATS		0x00800000	/* statistics		*/
602 
603 #define	RGE_DBG_IOCTL		0x01000000	/* ioctl handling	*/
604 #define	RGE_DBG_LOOP		0x02000000	/* loopback ioctl code	*/
605 #define	RGE_DBG_PPIO		0x04000000	/* Peek/poke ioctls	*/
606 #define	RGE_DBG_BADIOC		0x08000000	/* unknown ioctls	*/
607 
608 #define	RGE_DBG_MCTL		0x10000000	/* mctl (csum) code	*/
609 #define	RGE_DBG_NDD		0x20000000	/* NDD operations	*/
610 
611 /*
612  * Debugging ...
613  */
614 #ifdef	DEBUG
615 #define	RGE_DEBUGGING		1
616 #else
617 #define	RGE_DEBUGGING		0
618 #endif	/* DEBUG */
619 
620 
621 /*
622  * 'Do-if-debugging' macro.  The parameter <command> should be one or more
623  * C statements (but without the *final* semicolon), which will either be
624  * compiled inline or completely ignored, depending on the RGE_DEBUGGING
625  * compile-time flag.
626  *
627  * You should get a compile-time error (at least on a DEBUG build) if
628  * your statement isn't actually a statement, rather than unexpected
629  * run-time behaviour caused by unintended matching of if-then-elses etc.
630  *
631  * Note that the RGE_DDB() macro itself can only be used as a statement,
632  * not an expression, and should always be followed by a semicolon.
633  */
634 #if	RGE_DEBUGGING
635 #define	RGE_DDB(command)	do {					\
636 					{ command; }			\
637 					_NOTE(CONSTANTCONDITION)	\
638 				} while (0)
639 #else 	/* RGE_DEBUGGING */
640 #define	RGE_DDB(command)	do {					\
641 					{ _NOTE(EMPTY); }		\
642 					_NOTE(CONSTANTCONDITION)	\
643 				} while (0)
644 #endif	/* RGE_DEBUGGING */
645 
646 /*
647  * 'Internal' macros used to construct the TRACE/DEBUG macros below.
648  * These provide the primitive conditional-call capability required.
649  * Note: the parameter <args> is a parenthesised list of the actual
650  * printf-style arguments to be passed to the debug function ...
651  */
652 #define	RGE_XDB(b, w, f, args)	RGE_DDB(if ((b) & (w)) f args)
653 #define	RGE_GDB(b, args)	RGE_XDB(b, rge_debug, (*rge_gdb()), args)
654 #define	RGE_LDB(b, args)	RGE_XDB(b, rgep->debug, (*rge_db(rgep)), args)
655 #define	RGE_CDB(f, args)	RGE_XDB(RGE_DBG, rgep->debug, f, args)
656 
657 /*
658  * Conditional-print macros.
659  *
660  * Define RGE_DBG to be the relevant member of the set of RGE_DBG_* values
661  * above before using the RGE_GDEBUG() or RGE_DEBUG() macros.  The 'G'
662  * versions look at the Global debug flag word (rge_debug); the non-G
663  * versions look in the per-instance data (rgep->debug) and so require a
664  * variable called 'rgep' to be in scope (and initialised!) before use.
665  *
666  * You could redefine RGE_TRC too if you really need two different
667  * flavours of debugging output in the same area of code, but I don't
668  * really recommend it.
669  *
670  * Note: the parameter <args> is a parenthesised list of the actual
671  * arguments to be passed to the debug function, usually a printf-style
672  * format string and corresponding values to be formatted.
673  */
674 
675 #define	RGE_TRC			RGE_DBG_TRACE	/* default 'trace' bit	*/
676 #define	RGE_GTRACE(args)	RGE_GDB(RGE_TRC, args)
677 #define	RGE_GDEBUG(args)	RGE_GDB(RGE_DBG, args)
678 #define	RGE_TRACE(args)		RGE_LDB(RGE_TRC, args)
679 #define	RGE_DEBUG(args)		RGE_LDB(RGE_DBG, args)
680 
681 /*
682  * Debug-only action macros
683  */
684 #define	RGE_BRKPT(rgep, s)	RGE_DDB(rge_dbg_enter(rgep, s))
685 #define	RGE_MARK(rgep)		RGE_DDB(rge_led_mark(rgep))
686 #define	RGE_PCICHK(rgep)	RGE_DDB(rge_pci_check(rgep))
687 #define	RGE_PKTDUMP(args)	RGE_DDB(rge_pkt_dump args)
688 #define	RGE_REPORT(args)	RGE_DDB(rge_log args)
689 
690 /*
691  * Inter-source-file linkage ...
692  */
693 
694 /* rge_chip.c */
695 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii);
696 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data);
697 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp);
698 void rge_chip_ident(rge_t *rgep);
699 int rge_chip_reset(rge_t *rgep);
700 void rge_chip_init(rge_t *rgep);
701 void rge_chip_start(rge_t *rgep);
702 void rge_chip_stop(rge_t *rgep, boolean_t fault);
703 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo);
704 void rge_chip_blank(void *arg, time_t ticks, uint_t count);
705 void rge_tx_trigger(rge_t *rgep);
706 void rge_hw_stats_dump(rge_t *rgep);
707 uint_t rge_intr(caddr_t arg1, caddr_t arg2);
708 uint_t rge_chip_factotum(caddr_t arg1, caddr_t arg2);
709 void rge_chip_cyclic(void *arg);
710 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp,
711 	struct iocblk *iocp);
712 boolean_t rge_phy_reset(rge_t *rgep);
713 void rge_phy_init(rge_t *rgep);
714 void rge_phy_update(rge_t *rgep);
715 
716 /* rge_kstats.c */
717 void rge_init_kstats(rge_t *rgep, int instance);
718 void rge_fini_kstats(rge_t *rgep);
719 int rge_m_stat(void *arg, uint_t stat, uint64_t *val);
720 
721 /* rge_log.c */
722 #if	RGE_DEBUGGING
723 void (*rge_db(rge_t *rgep))(const char *fmt, ...);
724 void (*rge_gdb(void))(const char *fmt, ...);
725 void rge_pkt_dump(rge_t *rgep, rge_bd_t *hbp, sw_rbd_t *sdp, const char *msg);
726 void rge_dbg_enter(rge_t *rgep, const char *msg);
727 #endif	/* RGE_DEBUGGING */
728 void rge_problem(rge_t *rgep, const char *fmt, ...);
729 void rge_notice(rge_t *rgep, const char *fmt, ...);
730 void rge_log(rge_t *rgep, const char *fmt, ...);
731 void rge_error(rge_t *rgep, const char *fmt, ...);
732 extern kmutex_t rge_log_mutex[1];
733 extern uint32_t rge_debug;
734 
735 /* rge_main.c */
736 void rge_restart(rge_t *rgep);
737 
738 /* rge_ndd.c */
739 int rge_nd_init(rge_t *rgep);
740 enum ioc_reply rge_nd_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp,
741 	struct iocblk *iocp);
742 void rge_nd_cleanup(rge_t *rgep);
743 
744 /* rge_rxtx.c */
745 void rge_rx_recycle(caddr_t arg);
746 void rge_receive(rge_t *rgep);
747 mblk_t *rge_m_tx(void *arg, mblk_t *mp);
748 uint_t rge_reschedule(caddr_t arg1, caddr_t arg2);
749 
750 #ifdef __cplusplus
751 }
752 #endif
753 
754 #endif	/* _RGE_H */
755