1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _RGE_H 27 #define _RGE_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <sys/types.h> 34 #include <sys/stream.h> 35 #include <sys/strsun.h> 36 #include <sys/strsubr.h> 37 #include <sys/stat.h> 38 #include <sys/pci.h> 39 #include <sys/pci_cap.h> 40 #include <sys/note.h> 41 #include <sys/modctl.h> 42 #include <sys/kstat.h> 43 #include <sys/ethernet.h> 44 #include <sys/vlan.h> 45 #include <sys/errno.h> 46 #include <sys/dlpi.h> 47 #include <sys/devops.h> 48 #include <sys/debug.h> 49 #include <sys/conf.h> 50 51 #include <netinet/ip6.h> 52 #include <inet/common.h> 53 #include <inet/ip.h> 54 #include <inet/mi.h> 55 #include <inet/nd.h> 56 #include <sys/pattr.h> 57 58 #include <sys/ddi.h> 59 #include <sys/sunddi.h> 60 61 #include <sys/mac_provider.h> 62 #include <sys/mac_ether.h> 63 64 /* 65 * Reconfiguring the network devices requires the net_config privilege 66 * in Solaris 10+. 67 */ 68 extern int secpolicy_net_config(const cred_t *, boolean_t); 69 70 #include <sys/netlb.h> /* originally from cassini */ 71 #include <sys/miiregs.h> /* by fjlite out of intel */ 72 73 #include "rge_hw.h" 74 75 /* 76 * Name of the driver 77 */ 78 #define RGE_DRIVER_NAME "rge" 79 80 /* 81 * The driver supports the NDD ioctls ND_GET/ND_SET, and the loopback 82 * ioctls LB_GET_INFO_SIZE/LB_GET_INFO/LB_GET_MODE/LB_SET_MODE 83 * 84 * These are the values to use with LD_SET_MODE. 85 */ 86 #define RGE_LOOP_NONE 0 87 #define RGE_LOOP_INTERNAL_PHY 1 88 #define RGE_LOOP_INTERNAL_MAC 2 89 90 /* 91 * RGE-specific ioctls ... 92 */ 93 #define RGE_IOC ((((('R' << 8) + 'G') << 8) + 'E') << 8) 94 95 /* 96 * PHY register read/write ioctls, used by cable test software 97 */ 98 #define RGE_MII_READ (RGE_IOC|1) 99 #define RGE_MII_WRITE (RGE_IOC|2) 100 101 struct rge_mii_rw { 102 uint32_t mii_reg; /* PHY register number [0..31] */ 103 uint32_t mii_data; /* data to write/data read */ 104 }; 105 106 /* 107 * These diagnostic IOCTLS are enabled only in DEBUG drivers 108 */ 109 #define RGE_DIAG (RGE_IOC|10) /* currently a no-op */ 110 #define RGE_PEEK (RGE_IOC|11) 111 #define RGE_POKE (RGE_IOC|12) 112 #define RGE_PHY_RESET (RGE_IOC|13) 113 #define RGE_SOFT_RESET (RGE_IOC|14) 114 #define RGE_HARD_RESET (RGE_IOC|15) 115 116 typedef struct { 117 uint64_t pp_acc_size; /* in bytes: 1,2,4,8 */ 118 uint64_t pp_acc_space; /* See #defines below */ 119 uint64_t pp_acc_offset; 120 uint64_t pp_acc_data; /* output for peek */ 121 /* input for poke */ 122 } rge_peekpoke_t; 123 124 #define RGE_PP_SPACE_CFG 0 /* PCI config space */ 125 #define RGE_PP_SPACE_REG 1 /* PCI memory space */ 126 #define RGE_PP_SPACE_MII 2 /* PHY's MII registers */ 127 #define RGE_PP_SPACE_RGE 3 /* driver's soft state */ 128 #define RGE_PP_SPACE_TXDESC 4 /* TX descriptors */ 129 #define RGE_PP_SPACE_TXBUFF 5 /* TX buffers */ 130 #define RGE_PP_SPACE_RXDESC 6 /* RX descriptors */ 131 #define RGE_PP_SPACE_RXBUFF 7 /* RX buffers */ 132 #define RGE_PP_SPACE_STATISTICS 8 /* statistics block */ 133 134 /* 135 * RTL8169 CRC poly 136 */ 137 #define RGE_HASH_POLY 0x04C11DB7 /* 0x04C11DB6 */ 138 #define RGE_HASH_CRC 0xFFFFFFFFU 139 #define RGE_MCAST_BUF_SIZE 64 /* multicast hash table size in bits */ 140 141 /* 142 * Rx/Tx buffer parameters 143 */ 144 #define RGE_BUF_SLOTS 2048 145 #define RGE_RECV_COPY_SIZE 256 146 #define RGE_HEADROOM 6 147 148 /* 149 * Driver chip operation parameters 150 */ 151 #define RGE_CYCLIC_PERIOD (1000000000) /* ~1s */ 152 #define CHIP_RESET_LOOP 1000 153 #define PHY_RESET_LOOP 10 154 #define STATS_DUMP_LOOP 1000 155 #define RXBUFF_FREE_LOOP 1000 156 #define RGE_RX_INT_TIME 128 157 #define RGE_RX_INT_PKTS 8 158 159 /* 160 * Named Data (ND) Parameter Management Structure 161 */ 162 typedef struct { 163 int ndp_info; 164 int ndp_min; 165 int ndp_max; 166 int ndp_val; 167 char *ndp_name; 168 } nd_param_t; /* 0x18 (24) bytes */ 169 170 /* 171 * NDD parameter indexes, divided into: 172 * 173 * read-only parameters describing the hardware's capabilities 174 * read-write parameters controlling the advertised capabilities 175 * read-only parameters describing the partner's capabilities 176 * read-only parameters describing the link state 177 */ 178 enum { 179 PARAM_AUTONEG_CAP = 0, 180 PARAM_PAUSE_CAP, 181 PARAM_ASYM_PAUSE_CAP, 182 PARAM_1000FDX_CAP, 183 PARAM_1000HDX_CAP, 184 PARAM_100T4_CAP, 185 PARAM_100FDX_CAP, 186 PARAM_100HDX_CAP, 187 PARAM_10FDX_CAP, 188 PARAM_10HDX_CAP, 189 190 PARAM_ADV_AUTONEG_CAP, 191 PARAM_ADV_PAUSE_CAP, 192 PARAM_ADV_ASYM_PAUSE_CAP, 193 PARAM_ADV_1000FDX_CAP, 194 PARAM_ADV_1000HDX_CAP, 195 PARAM_ADV_100T4_CAP, 196 PARAM_ADV_100FDX_CAP, 197 PARAM_ADV_100HDX_CAP, 198 PARAM_ADV_10FDX_CAP, 199 PARAM_ADV_10HDX_CAP, 200 201 PARAM_LINK_STATUS, 202 PARAM_LINK_SPEED, 203 PARAM_LINK_DUPLEX, 204 205 PARAM_LOOP_MODE, 206 207 PARAM_COUNT 208 }; 209 210 enum rge_chip_state { 211 RGE_CHIP_FAULT = -2, /* fault, need reset */ 212 RGE_CHIP_ERROR, /* error, want reset */ 213 RGE_CHIP_INITIAL, /* Initial state only */ 214 RGE_CHIP_RESET, /* reset, need init */ 215 RGE_CHIP_STOPPED, /* Tx/Rx stopped */ 216 RGE_CHIP_RUNNING /* with interrupts */ 217 }; 218 219 enum rge_mac_state { 220 RGE_MAC_ATTACH = 0, 221 RGE_MAC_STOPPED, 222 RGE_MAC_STARTED, 223 RGE_MAC_UNATTACH 224 }; 225 226 enum rge_sync_op { 227 RGE_OP_NULL, 228 RGE_GET_MAC, /* get mac address operation */ 229 RGE_SET_MAC, /* set mac address operation */ 230 RGE_SET_MUL, /* set multicast address op */ 231 RGE_SET_PROMISC /* set promisc mode */ 232 }; 233 234 /* 235 * (Internal) return values from ioctl subroutines 236 */ 237 enum ioc_reply { 238 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 239 IOC_DONE, /* OK, reply sent */ 240 IOC_ACK, /* OK, just send ACK */ 241 IOC_REPLY, /* OK, just send reply */ 242 IOC_RESTART_ACK, /* OK, restart & ACK */ 243 IOC_RESTART_REPLY /* OK, restart & reply */ 244 }; 245 246 /* 247 * (Internal) enumeration of this driver's kstats 248 */ 249 enum { 250 RGE_KSTAT_DRIVER = 0, 251 RGE_KSTAT_COUNT 252 }; 253 254 /* 255 * Basic data types, for clarity in distinguishing 'numbers' 256 * used for different purposes ... 257 * 258 * A <rge_regno_t> is a register 'address' (offset) in any one of 259 * various address spaces (PCI config space, PCI memory-mapped I/O 260 * register space, MII registers, etc). None of these exceeds 64K, 261 * so we could use a 16-bit representation but pointer-sized objects 262 * are more "natural" in most architectures; they seem to be handled 263 * more efficiently on SPARC and no worse on x86. 264 * 265 * RGE_REGNO_NONE represents the non-existent value in this space. 266 */ 267 typedef uintptr_t rge_regno_t; /* register # (offset) */ 268 #define RGE_REGNO_NONE (~(uintptr_t)0u) 269 270 /* 271 * Describes one chunk of allocated DMA-able memory 272 * 273 * In some cases, this is a single chunk as allocated from the system; 274 * but we also use this structure to represent slices carved off such 275 * a chunk. Even when we don't really need all the information, we 276 * use this structure as a convenient way of correlating the various 277 * ways of looking at a piece of memory (kernel VA, IO space DVMA, 278 * handle+offset, etc). 279 */ 280 typedef struct { 281 ddi_acc_handle_t acc_hdl; /* handle for memory */ 282 void *mem_va; /* CPU VA of memory */ 283 uint32_t nslots; /* number of slots */ 284 uint32_t size; /* size per slot */ 285 size_t alength; /* allocated size */ 286 ddi_dma_handle_t dma_hdl; /* DMA handle */ 287 offset_t offset; /* relative to handle */ 288 ddi_dma_cookie_t cookie; /* associated cookie */ 289 uint32_t ncookies; /* must be 1 */ 290 uint32_t token; /* arbitrary identifier */ 291 } dma_area_t; 292 293 /* 294 * Software version of the Receive Buffer Descriptor 295 */ 296 typedef struct { 297 caddr_t private; /* pointer to rge */ 298 dma_area_t pbuf; /* (const) related */ 299 /* buffer area */ 300 frtn_t rx_recycle; /* recycle function */ 301 mblk_t *mp; 302 } dma_buf_t; 303 304 typedef struct sw_rbd { 305 dma_buf_t *rx_buf; 306 uint8_t flags; 307 } sw_rbd_t; 308 309 /* 310 * Software version of the Send Buffer Descriptor 311 */ 312 typedef struct sw_sbd { 313 dma_area_t desc; /* (const) related h/w */ 314 /* descriptor area */ 315 dma_area_t pbuf; /* (const) related */ 316 /* buffer area */ 317 } sw_sbd_t; 318 319 320 #define HW_RBD_INIT(rbd, slot) { \ 321 (rbd)->vlan_tag = 0; \ 322 if ((slot) == (RGE_RECV_SLOTS -1)) { \ 323 (rbd)->flags_len |= \ 324 RGE_BSWAP_32(BD_FLAG_EOR | BD_FLAG_HW_OWN); \ 325 } else { \ 326 (rbd)->flags_len |= RGE_BSWAP_32(BD_FLAG_HW_OWN); \ 327 } \ 328 } 329 #define HW_SBD_SET(sbd, slot) { \ 330 if ((slot) == (RGE_SEND_SLOTS -1)) { \ 331 (sbd)->flags_len |= \ 332 RGE_BSWAP_32(BD_FLAG_EOR | SBD_FLAG_TX_PKT); \ 333 } else { \ 334 (sbd)->flags_len |= RGE_BSWAP_32(SBD_FLAG_TX_PKT); \ 335 } \ 336 } 337 338 /* 339 * Describes the characteristics of a specific chip 340 */ 341 typedef struct { 342 uint16_t command; /* saved during attach */ 343 uint16_t vendor; /* vendor-id */ 344 uint16_t device; /* device-id */ 345 uint16_t subven; /* subsystem-vendor-id */ 346 uint16_t subdev; /* subsystem-id */ 347 uint8_t revision; /* revision-id */ 348 uint8_t clsize; /* cache-line-size */ 349 uint8_t latency; /* latency-timer */ 350 boolean_t is_pcie; 351 uint32_t mac_ver; 352 uint32_t phy_ver; 353 uint32_t rxconfig; 354 uint32_t txconfig; 355 } chip_id_t; 356 357 typedef struct rge_stats { 358 uint64_t rpackets; 359 uint64_t rbytes; 360 uint64_t opackets; 361 uint64_t obytes; 362 uint32_t overflow; 363 uint32_t defer; /* dot3StatsDeferredTransmissions */ 364 uint32_t crc_err; /* dot3StatsFCSErrors */ 365 uint32_t in_short; 366 uint32_t no_rcvbuf; /* ifInDiscards */ 367 uint32_t intr; /* interrupt count */ 368 uint16_t chip_reset; 369 uint16_t phy_reset; 370 boolean_t tx_pre_ismax; 371 boolean_t tx_cur_ismax; 372 } rge_stats_t; 373 374 /* 375 * Per-instance soft-state structure 376 */ 377 typedef struct rge { 378 dev_info_t *devinfo; /* device instance */ 379 mac_handle_t mh; /* mac module handle */ 380 ddi_acc_handle_t cfg_handle; /* DDI I/O handle */ 381 ddi_acc_handle_t io_handle; /* DDI I/O handle */ 382 caddr_t io_regs; /* mapped registers */ 383 ddi_periodic_t periodic_id; /* periodical callback */ 384 ddi_softint_handle_t resched_hdl; /* reschedule callback */ 385 ddi_softint_handle_t factotum_hdl; /* factotum callback */ 386 uint_t soft_pri; 387 ddi_intr_handle_t *htable; /* For array of interrupts */ 388 int intr_type; /* What type of interrupt */ 389 int intr_rqst; /* # of request intrs count */ 390 int intr_cnt; /* # of intrs count returned */ 391 uint_t intr_pri; /* Interrupt priority */ 392 int intr_cap; /* Interrupt capabilities */ 393 boolean_t msi_enable; 394 395 uint32_t ethmax_size; 396 uint32_t default_mtu; 397 uint32_t rxbuf_size; 398 uint32_t txbuf_size; 399 uint32_t chip_flags; 400 uint32_t head_room; 401 char ifname[8]; /* "rge0" ... "rge999" */ 402 int32_t instance; 403 uint32_t progress; /* attach tracking */ 404 uint32_t debug; /* per-instance debug */ 405 chip_id_t chipid; 406 407 /* 408 * These structures describe the blocks of memory allocated during 409 * attach(). They remain unchanged thereafter, although the memory 410 * they describe is carved up into various separate regions and may 411 * therefore be described by other structures as well. 412 */ 413 dma_area_t dma_area_rxdesc; 414 dma_area_t dma_area_txdesc; 415 dma_area_t dma_area_stats; 416 /* describes hardware statistics area */ 417 418 uint8_t netaddr[ETHERADDRL]; /* mac address */ 419 uint16_t int_mask; /* interrupt mask */ 420 421 /* used for multicast/promisc mode set */ 422 char mcast_refs[RGE_MCAST_BUF_SIZE]; 423 uint8_t mcast_hash[RGE_MCAST_NUM]; 424 boolean_t promisc; /* promisc state flag */ 425 426 /* used for recv */ 427 rge_bd_t *rx_ring; 428 dma_area_t rx_desc; 429 boolean_t rx_bcopy; 430 uint32_t rx_next; /* current rx bd index */ 431 sw_rbd_t *sw_rbds; 432 sw_rbd_t *free_srbds; 433 uint32_t rf_next; /* current free buf index */ 434 uint32_t rc_next; /* current recycle buf index */ 435 uint32_t rx_free; /* number of rx free buf */ 436 437 /* used for send */ 438 rge_bd_t *tx_ring; 439 dma_area_t tx_desc; 440 uint32_t tx_free; /* number of free tx bd */ 441 uint32_t tx_next; /* current tx bd index */ 442 uint32_t tc_next; /* current tx recycle index */ 443 uint32_t tx_flow; 444 uint32_t tc_tail; 445 sw_sbd_t *sw_sbds; 446 447 /* mutex */ 448 kmutex_t genlock[1]; /* i/o reg access */ 449 krwlock_t errlock[1]; /* rge restart */ 450 kmutex_t tx_lock[1]; /* send access */ 451 kmutex_t tc_lock[1]; /* send recycle access */ 452 kmutex_t rx_lock[1]; /* receive access */ 453 kmutex_t rc_lock[1]; /* receive recycle access */ 454 455 /* 456 * Miscellaneous operating variables (not synchronised) 457 */ 458 uint32_t watchdog; /* watches for Tx stall */ 459 boolean_t resched_needed; 460 uint32_t factotum_flag; /* softint pending */ 461 462 /* 463 * Physical layer 464 */ 465 rge_regno_t phy_mii_addr; /* should be (const) 1! */ 466 uint16_t link_down_count; 467 468 /* 469 * NDD parameters (protected by genlock) 470 */ 471 caddr_t nd_data_p; 472 nd_param_t nd_params[PARAM_COUNT]; 473 474 /* 475 * Driver kstats, protected by <genlock> where necessary 476 */ 477 kstat_t *rge_kstats[RGE_KSTAT_COUNT]; 478 479 /* H/W statistics */ 480 rge_hw_stats_t *hw_stats; 481 rge_stats_t stats; 482 enum rge_mac_state rge_mac_state; /* definitions above */ 483 enum rge_chip_state rge_chip_state; /* definitions above */ 484 485 boolean_t suspended; 486 487 /* 488 * Polling 489 */ 490 #define TX_COALESC max(RGE_BUF_SLOTS/32LL, 8) 491 #define RX_COALESC 8LL 492 #define CLK_TICK 100 493 clock_t curr_tick; 494 clock_t tick_delta; 495 uint64_t last_opackets; 496 uint64_t last_rpackets; 497 } rge_t; 498 499 /* 500 * 'Progress' bit flags ... 501 */ 502 #define PROGRESS_CFG 0x0001 /* config space mapped */ 503 #define PROGRESS_REGS 0x0002 /* registers mapped */ 504 #define PROGRESS_RESCHED 0x0010 /* resched softint registered */ 505 #define PROGRESS_FACTOTUM 0x0020 /* factotum softint registered */ 506 #define PROGRESS_INTR 0X0040 /* h/w interrupt registered */ 507 /* and mutexen initialised */ 508 #define PROGRESS_INIT 0x0080 /* rx/buf/tx ring initialised */ 509 #define PROGRESS_PHY 0x0100 /* PHY initialised */ 510 #define PROGRESS_NDD 0x1000 /* NDD parameters set up */ 511 #define PROGRESS_KSTATS 0x2000 /* kstats created */ 512 #define PROGRESS_READY 0x8000 /* ready for work */ 513 514 /* 515 * Special chip flags 516 */ 517 #define CHIP_FLAG_FORCE_BCOPY 0x10000000 518 519 /* 520 * Shorthand for the NDD parameters 521 */ 522 #define param_adv_autoneg nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val 523 #define param_adv_pause nd_params[PARAM_ADV_PAUSE_CAP].ndp_val 524 #define param_adv_asym_pause nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val 525 #define param_adv_1000fdx nd_params[PARAM_ADV_1000FDX_CAP].ndp_val 526 #define param_adv_1000hdx nd_params[PARAM_ADV_1000HDX_CAP].ndp_val 527 #define param_adv_100fdx nd_params[PARAM_ADV_100FDX_CAP].ndp_val 528 #define param_adv_100hdx nd_params[PARAM_ADV_100HDX_CAP].ndp_val 529 #define param_adv_10fdx nd_params[PARAM_ADV_10FDX_CAP].ndp_val 530 #define param_adv_10hdx nd_params[PARAM_ADV_10HDX_CAP].ndp_val 531 532 #define param_link_up nd_params[PARAM_LINK_STATUS].ndp_val 533 #define param_link_speed nd_params[PARAM_LINK_SPEED].ndp_val 534 #define param_link_duplex nd_params[PARAM_LINK_DUPLEX].ndp_val 535 536 #define param_loop_mode nd_params[PARAM_LOOP_MODE].ndp_val 537 538 /* 539 * Sync a DMA area described by a dma_area_t 540 */ 541 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \ 542 (area).offset, (area).alength, (flag))) 543 544 /* 545 * Find the (kernel virtual) address of block of memory 546 * described by a dma_area_t 547 */ 548 #define DMA_VPTR(area) ((area).mem_va) 549 550 /* 551 * Zero a block of memory described by a dma_area_t 552 */ 553 #define DMA_ZERO(area) bzero(DMA_VPTR(area), (area).alength) 554 555 /* 556 * Next/Last value of a cyclic index 557 */ 558 #define NEXT(index, limit) ((index)+1 < (limit) ? (index)+1 : 0); 559 #define LAST(index, limit) ((index) ? (index)-1 : (limit - 1)); 560 /* 561 * Property lookups 562 */ 563 #define RGE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 564 DDI_PROP_DONTPASS, (n)) 565 #define RGE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 566 DDI_PROP_DONTPASS, (n), -1) 567 568 /* 569 * Endian swap 570 */ 571 #ifdef _BIG_ENDIAN 572 #define RGE_BSWAP_16(x) ((((x) & 0xff00) >> 8) | \ 573 (((x) & 0x00ff) << 8)) 574 #define RGE_BSWAP_32(x) ((((x) & 0xff000000) >> 24) | \ 575 (((x) & 0x00ff0000) >> 8) | \ 576 (((x) & 0x0000ff00) << 8) | \ 577 (((x) & 0x000000ff) << 24)) 578 #define RGE_BSWAP_64(x) (RGE_BSWAP_32((x) >> 32) | \ 579 (RGE_BSWAP_32(x) << 32)) 580 #else 581 #define RGE_BSWAP_16(x) (x) 582 #define RGE_BSWAP_32(x) (x) 583 #define RGE_BSWAP_64(x) (x) 584 #endif 585 586 /* 587 * Bit test macros, returning boolean_t values 588 */ 589 #define BIS(w, b) (((w) & (b)) ? B_TRUE : B_FALSE) 590 #define BIC(w, b) (((w) & (b)) ? B_FALSE : B_TRUE) 591 #define UPORDOWN(x) ((x) ? "up" : "down") 592 593 /* 594 * Bit flags in the 'debug' word ... 595 */ 596 #define RGE_DBG_STOP 0x00000001 /* early debug_enter() */ 597 #define RGE_DBG_TRACE 0x00000002 /* general flow tracing */ 598 599 #define RGE_DBG_REGS 0x00000010 /* low-level accesses */ 600 #define RGE_DBG_MII 0x00000020 /* low-level MII access */ 601 #define RGE_DBG_SEEPROM 0x00000040 /* low-level SEEPROM IO */ 602 #define RGE_DBG_CHIP 0x00000080 /* low(ish)-level code */ 603 604 #define RGE_DBG_RECV 0x00000100 /* receive-side code */ 605 #define RGE_DBG_SEND 0x00000200 /* packet-send code */ 606 607 #define RGE_DBG_INT 0x00001000 /* interrupt handler */ 608 #define RGE_DBG_FACT 0x00002000 /* factotum (softint) */ 609 610 #define RGE_DBG_PHY 0x00010000 /* Copper PHY code */ 611 #define RGE_DBG_SERDES 0x00020000 /* SerDes code */ 612 #define RGE_DBG_PHYS 0x00040000 /* Physical layer code */ 613 #define RGE_DBG_LINK 0x00080000 /* Link status check */ 614 615 #define RGE_DBG_INIT 0x00100000 /* initialisation */ 616 #define RGE_DBG_NEMO 0x00200000 /* nemo interaction */ 617 #define RGE_DBG_ADDR 0x00400000 /* address-setting code */ 618 #define RGE_DBG_STATS 0x00800000 /* statistics */ 619 620 #define RGE_DBG_IOCTL 0x01000000 /* ioctl handling */ 621 #define RGE_DBG_LOOP 0x02000000 /* loopback ioctl code */ 622 #define RGE_DBG_PPIO 0x04000000 /* Peek/poke ioctls */ 623 #define RGE_DBG_BADIOC 0x08000000 /* unknown ioctls */ 624 625 #define RGE_DBG_MCTL 0x10000000 /* mctl (csum) code */ 626 #define RGE_DBG_NDD 0x20000000 /* NDD operations */ 627 628 /* 629 * Debugging ... 630 */ 631 #ifdef DEBUG 632 #define RGE_DEBUGGING 1 633 #else 634 #define RGE_DEBUGGING 0 635 #endif /* DEBUG */ 636 637 638 /* 639 * 'Do-if-debugging' macro. The parameter <command> should be one or more 640 * C statements (but without the *final* semicolon), which will either be 641 * compiled inline or completely ignored, depending on the RGE_DEBUGGING 642 * compile-time flag. 643 * 644 * You should get a compile-time error (at least on a DEBUG build) if 645 * your statement isn't actually a statement, rather than unexpected 646 * run-time behaviour caused by unintended matching of if-then-elses etc. 647 * 648 * Note that the RGE_DDB() macro itself can only be used as a statement, 649 * not an expression, and should always be followed by a semicolon. 650 */ 651 #if RGE_DEBUGGING 652 #define RGE_DDB(command) do { \ 653 { command; } \ 654 _NOTE(CONSTANTCONDITION) \ 655 } while (0) 656 #else /* RGE_DEBUGGING */ 657 #define RGE_DDB(command) do { \ 658 { _NOTE(EMPTY); } \ 659 _NOTE(CONSTANTCONDITION) \ 660 } while (0) 661 #endif /* RGE_DEBUGGING */ 662 663 /* 664 * 'Internal' macros used to construct the TRACE/DEBUG macros below. 665 * These provide the primitive conditional-call capability required. 666 * Note: the parameter <args> is a parenthesised list of the actual 667 * printf-style arguments to be passed to the debug function ... 668 */ 669 #define RGE_XDB(b, w, f, args) RGE_DDB(if ((b) & (w)) f args) 670 #define RGE_GDB(b, args) RGE_XDB(b, rge_debug, (*rge_gdb()), args) 671 #define RGE_LDB(b, args) RGE_XDB(b, rgep->debug, (*rge_db(rgep)), args) 672 #define RGE_CDB(f, args) RGE_XDB(RGE_DBG, rgep->debug, f, args) 673 674 /* 675 * Conditional-print macros. 676 * 677 * Define RGE_DBG to be the relevant member of the set of RGE_DBG_* values 678 * above before using the RGE_GDEBUG() or RGE_DEBUG() macros. The 'G' 679 * versions look at the Global debug flag word (rge_debug); the non-G 680 * versions look in the per-instance data (rgep->debug) and so require a 681 * variable called 'rgep' to be in scope (and initialised!) before use. 682 * 683 * You could redefine RGE_TRC too if you really need two different 684 * flavours of debugging output in the same area of code, but I don't 685 * really recommend it. 686 * 687 * Note: the parameter <args> is a parenthesised list of the actual 688 * arguments to be passed to the debug function, usually a printf-style 689 * format string and corresponding values to be formatted. 690 */ 691 692 #define RGE_TRC RGE_DBG_TRACE /* default 'trace' bit */ 693 #define RGE_GTRACE(args) RGE_GDB(RGE_TRC, args) 694 #define RGE_GDEBUG(args) RGE_GDB(RGE_DBG, args) 695 #define RGE_TRACE(args) RGE_LDB(RGE_TRC, args) 696 #define RGE_DEBUG(args) RGE_LDB(RGE_DBG, args) 697 698 /* 699 * Debug-only action macros 700 */ 701 #define RGE_BRKPT(rgep, s) RGE_DDB(rge_dbg_enter(rgep, s)) 702 #define RGE_MARK(rgep) RGE_DDB(rge_led_mark(rgep)) 703 #define RGE_PCICHK(rgep) RGE_DDB(rge_pci_check(rgep)) 704 #define RGE_PKTDUMP(args) RGE_DDB(rge_pkt_dump args) 705 #define RGE_REPORT(args) RGE_DDB(rge_log args) 706 707 /* 708 * Inter-source-file linkage ... 709 */ 710 711 /* rge_chip.c */ 712 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii); 713 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data); 714 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp); 715 void rge_chip_ident(rge_t *rgep); 716 int rge_chip_reset(rge_t *rgep); 717 void rge_chip_init(rge_t *rgep); 718 void rge_chip_start(rge_t *rgep); 719 void rge_chip_stop(rge_t *rgep, boolean_t fault); 720 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo); 721 void rge_chip_blank(void *arg, time_t ticks, uint_t count, int flag); 722 void rge_tx_trigger(rge_t *rgep); 723 void rge_hw_stats_dump(rge_t *rgep); 724 uint_t rge_intr(caddr_t arg1, caddr_t arg2); 725 uint_t rge_chip_factotum(caddr_t arg1, caddr_t arg2); 726 void rge_chip_cyclic(void *arg); 727 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, 728 struct iocblk *iocp); 729 boolean_t rge_phy_reset(rge_t *rgep); 730 void rge_phy_init(rge_t *rgep); 731 void rge_phy_update(rge_t *rgep); 732 733 /* rge_kstats.c */ 734 void rge_init_kstats(rge_t *rgep, int instance); 735 void rge_fini_kstats(rge_t *rgep); 736 int rge_m_stat(void *arg, uint_t stat, uint64_t *val); 737 738 /* rge_log.c */ 739 #if RGE_DEBUGGING 740 void (*rge_db(rge_t *rgep))(const char *fmt, ...); 741 void (*rge_gdb(void))(const char *fmt, ...); 742 void rge_pkt_dump(rge_t *rgep, rge_bd_t *hbp, sw_rbd_t *sdp, const char *msg); 743 void rge_dbg_enter(rge_t *rgep, const char *msg); 744 #endif /* RGE_DEBUGGING */ 745 void rge_problem(rge_t *rgep, const char *fmt, ...); 746 void rge_notice(rge_t *rgep, const char *fmt, ...); 747 void rge_log(rge_t *rgep, const char *fmt, ...); 748 void rge_error(rge_t *rgep, const char *fmt, ...); 749 extern kmutex_t rge_log_mutex[1]; 750 extern uint32_t rge_debug; 751 752 /* rge_main.c */ 753 void rge_restart(rge_t *rgep); 754 755 /* rge_ndd.c */ 756 int rge_nd_init(rge_t *rgep); 757 enum ioc_reply rge_nd_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, 758 struct iocblk *iocp); 759 void rge_nd_cleanup(rge_t *rgep); 760 761 /* rge_rxtx.c */ 762 void rge_rx_recycle(caddr_t arg); 763 void rge_receive(rge_t *rgep); 764 mblk_t *rge_m_tx(void *arg, mblk_t *mp); 765 uint_t rge_reschedule(caddr_t arg1, caddr_t arg2); 766 767 #ifdef __cplusplus 768 } 769 #endif 770 771 #endif /* _RGE_H */ 772