1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 27 /* 28 * PCI-IDE bus nexus driver 29 */ 30 31 #include <sys/types.h> 32 #include <sys/cmn_err.h> 33 #include <sys/conf.h> 34 #include <sys/errno.h> 35 #include <sys/debug.h> 36 #include <sys/ddidmareq.h> 37 #include <sys/ddi_impldefs.h> 38 #include <sys/dma_engine.h> 39 #include <sys/modctl.h> 40 #include <sys/ddi.h> 41 #include <sys/sunddi.h> 42 #include <sys/sunndi.h> 43 #include <sys/mach_intr.h> 44 #include <sys/kmem.h> 45 #include <sys/pci.h> 46 #include <sys/promif.h> 47 #include <sys/pci_intr_lib.h> 48 49 int pciide_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 50 int pciide_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 51 52 #define PCIIDE_NATIVE_MODE(dip) \ 53 (!ddi_prop_exists(DDI_DEV_T_ANY, (dip), DDI_PROP_DONTPASS, \ 54 "compatibility-mode")) 55 56 #define PCIIDE_PRE26(dip) \ 57 ddi_prop_exists(DDI_DEV_T_ANY, (dip), 0, "ignore-hardware-nodes") 58 59 #define PCI_IDE_IF_BM_CAP_MASK 0x80 60 61 #define PCIIDE_PDSIZE (sizeof (struct ddi_parent_private_data) + \ 62 sizeof (struct intrspec)) 63 64 #ifdef DEBUG 65 static int pci_ide_debug = 0; 66 #define PDBG(fmt) \ 67 if (pci_ide_debug) { \ 68 prom_printf fmt; \ 69 } 70 #else 71 #define PDBG(fmt) 72 #endif 73 74 #ifndef TRUE 75 #define TRUE 1 76 #endif 77 #ifndef FALSE 78 #define FALSE 0 79 #endif 80 81 /* 82 * bus_ops functions 83 */ 84 85 static int pciide_bus_map(dev_info_t *dip, dev_info_t *rdip, 86 ddi_map_req_t *mp, off_t offset, off_t len, 87 caddr_t *vaddrp); 88 89 static int pciide_ddi_ctlops(dev_info_t *dip, dev_info_t *rdip, 90 ddi_ctl_enum_t ctlop, void *arg, 91 void *result); 92 93 static int pciide_get_pri(dev_info_t *dip, dev_info_t *rdip, 94 ddi_intr_handle_impl_t *hdlp, int *pri); 95 96 static int pciide_intr_ops(dev_info_t *dip, dev_info_t *rdip, 97 ddi_intr_op_t intr_op, 98 ddi_intr_handle_impl_t *hdlp, void *result); 99 100 static struct intrspec *pciide_get_ispec(dev_info_t *dip, dev_info_t *rdip, 101 int inum); 102 103 /* 104 * Local Functions 105 */ 106 static int pciide_initchild(dev_info_t *mydip, dev_info_t *cdip); 107 108 static void pciide_compat_setup(dev_info_t *mydip, dev_info_t *cdip, 109 int dev); 110 static int pciide_pre26_rnumber_map(dev_info_t *mydip, int rnumber); 111 static int pciide_map_rnumber(int canonical_rnumber, int pri_native, 112 int sec_native); 113 114 115 /* 116 * Config information 117 */ 118 119 struct bus_ops pciide_bus_ops = { 120 BUSO_REV, 121 pciide_bus_map, 122 0, 123 0, 124 0, 125 i_ddi_map_fault, 126 ddi_dma_map, 127 ddi_dma_allochdl, 128 ddi_dma_freehdl, 129 ddi_dma_bindhdl, 130 ddi_dma_unbindhdl, 131 ddi_dma_flush, 132 ddi_dma_win, 133 ddi_dma_mctl, 134 pciide_ddi_ctlops, 135 ddi_bus_prop_op, 136 0, /* (*bus_get_eventcookie)(); */ 137 0, /* (*bus_add_eventcall)(); */ 138 0, /* (*bus_remove_eventcall)(); */ 139 0, /* (*bus_post_event)(); */ 140 0, 141 0, 142 0, 143 0, 144 0, 145 0, 146 0, 147 0, 148 pciide_intr_ops 149 }; 150 151 struct dev_ops pciide_ops = { 152 DEVO_REV, /* devo_rev, */ 153 0, /* refcnt */ 154 ddi_no_info, /* info */ 155 nulldev, /* identify */ 156 nulldev, /* probe */ 157 pciide_attach, /* attach */ 158 pciide_detach, /* detach */ 159 nodev, /* reset */ 160 (struct cb_ops *)0, /* driver operations */ 161 &pciide_bus_ops, /* bus operations */ 162 NULL, /* power */ 163 ddi_quiesce_not_needed, /* quiesce */ 164 }; 165 166 /* 167 * Module linkage information for the kernel. 168 */ 169 170 static struct modldrv modldrv = { 171 &mod_driverops, /* Type of module. This is PCI-IDE bus driver */ 172 "pciide nexus driver for 'PCI-IDE' 1.26", 173 &pciide_ops, /* driver ops */ 174 }; 175 176 static struct modlinkage modlinkage = { 177 MODREV_1, 178 &modldrv, 179 NULL 180 }; 181 182 183 int 184 _init(void) 185 { 186 return (mod_install(&modlinkage)); 187 } 188 189 int 190 _fini(void) 191 { 192 return (mod_remove(&modlinkage)); 193 } 194 195 int 196 _info(struct modinfo *modinfop) 197 { 198 return (mod_info(&modlinkage, modinfop)); 199 } 200 201 int 202 pciide_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 203 { 204 uint16_t cmdreg; 205 ddi_acc_handle_t conf_hdl = NULL; 206 int rc; 207 208 switch (cmd) { 209 case DDI_ATTACH: 210 /* 211 * Make sure bus-mastering is enabled, even if 212 * BIOS didn't. 213 */ 214 rc = pci_config_setup(dip, &conf_hdl); 215 216 /* 217 * In case of error, return SUCCESS. This is because 218 * bus-mastering could be already enabled by BIOS. 219 */ 220 if (rc != DDI_SUCCESS) 221 return (DDI_SUCCESS); 222 223 cmdreg = pci_config_get16(conf_hdl, PCI_CONF_COMM); 224 if ((cmdreg & PCI_COMM_ME) == 0) { 225 pci_config_put16(conf_hdl, PCI_CONF_COMM, 226 cmdreg | PCI_COMM_ME); 227 } 228 pci_config_teardown(&conf_hdl); 229 return (DDI_SUCCESS); 230 231 case DDI_RESUME: 232 /* Restore our PCI configuration header */ 233 if (pci_restore_config_regs(dip) != DDI_SUCCESS) { 234 /* 235 * XXXX 236 * This is a pretty bad thing. However, for some 237 * reason it always happens. To further complicate 238 * things, it appears if we just ignore this, we 239 * properly resume. For now, all I want to do is 240 * to generate this message so that it doesn't get 241 * forgotten. 242 */ 243 cmn_err(CE_WARN, 244 "Couldn't restore PCI config regs for %s(%p)", 245 ddi_node_name(dip), (void *) dip); 246 } 247 #ifdef DEBUG 248 /* Bus mastering should still be enabled */ 249 if (pci_config_setup(dip, &conf_hdl) != DDI_SUCCESS) 250 return (DDI_FAILURE); 251 cmdreg = pci_config_get16(conf_hdl, PCI_CONF_COMM); 252 ASSERT((cmdreg & PCI_COMM_ME) != 0); 253 pci_config_teardown(&conf_hdl); 254 #endif 255 return (DDI_SUCCESS); 256 } 257 258 return (DDI_FAILURE); 259 } 260 261 /*ARGSUSED*/ 262 int 263 pciide_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 264 { 265 switch (cmd) { 266 case DDI_DETACH: 267 return (DDI_SUCCESS); 268 case DDI_SUSPEND: 269 /* Save our PCI configuration header */ 270 if (pci_save_config_regs(dip) != DDI_SUCCESS) { 271 /* Don't suspend if we cannot save config regs */ 272 return (DDI_FAILURE); 273 } 274 return (DDI_SUCCESS); 275 } 276 return (DDI_FAILURE); 277 } 278 279 /*ARGSUSED*/ 280 static int 281 pciide_ddi_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t ctlop, 282 void *arg, void *result) 283 { 284 dev_info_t *cdip; 285 int controller; 286 void *pdptr; 287 int rnumber; 288 off_t tmp; 289 int rc; 290 291 PDBG(("pciide_bus_ctl\n")); 292 293 switch (ctlop) { 294 case DDI_CTLOPS_INITCHILD: 295 cdip = (dev_info_t *)arg; 296 return (pciide_initchild(dip, cdip)); 297 298 case DDI_CTLOPS_UNINITCHILD: 299 cdip = (dev_info_t *)arg; 300 pdptr = ddi_get_parent_data(cdip); 301 ddi_set_parent_data(cdip, NULL); 302 ddi_set_name_addr(cdip, NULL); 303 kmem_free(pdptr, PCIIDE_PDSIZE); 304 return (DDI_SUCCESS); 305 306 case DDI_CTLOPS_NREGS: 307 *(int *)result = 3; 308 return (DDI_SUCCESS); 309 310 case DDI_CTLOPS_REGSIZE: 311 /* 312 * Adjust the rnumbers based on which controller instance 313 * is requested; adjust for the 2 tuples per controller. 314 */ 315 if (strcmp("0", ddi_get_name_addr(rdip)) == 0) 316 controller = 0; 317 else 318 controller = 1; 319 320 321 switch (rnumber = *(int *)arg) { 322 case 0: 323 case 1: 324 rnumber += (2 * controller); 325 break; 326 case 2: 327 rnumber = 4; 328 break; 329 default: 330 PDBG(("pciide_ctlops invalid rnumber\n")); 331 return (DDI_FAILURE); 332 } 333 334 335 if (PCIIDE_PRE26(dip)) { 336 int old_rnumber; 337 int new_rnumber; 338 339 old_rnumber = rnumber; 340 new_rnumber 341 = pciide_pre26_rnumber_map(dip, old_rnumber); 342 PDBG(("pciide rnumber old %d new %d\n", 343 old_rnumber, new_rnumber)); 344 rnumber = new_rnumber; 345 } 346 347 /* 348 * Add 1 to skip over the PCI config space tuple 349 */ 350 rnumber++; 351 352 /* 353 * If it's not tuple #2 pass the adjusted request to my parent 354 */ 355 if (*(int *)arg != 2) { 356 return (ddi_ctlops(dip, dip, ctlop, &rnumber, result)); 357 } 358 359 /* 360 * Handle my child's reg-tuple #2 here by splitting my 16 byte 361 * reg-tuple #4 into two 8 byte ranges based on the 362 * the child's controller #. 363 */ 364 365 tmp = 8; 366 rc = ddi_ctlops(dip, dip, ctlop, &rnumber, &tmp); 367 368 /* 369 * Allow for the possibility of less than 16 bytes by 370 * by checking what's actually returned for my reg-tuple #4. 371 */ 372 if (controller == 1) { 373 if (tmp < 8) 374 tmp = 0; 375 else 376 tmp -= 8; 377 } 378 if (tmp > 8) 379 tmp = 8; 380 *(off_t *)result = tmp; 381 382 return (rc); 383 384 default: 385 return (ddi_ctlops(dip, rdip, ctlop, arg, result)); 386 } 387 } 388 389 /* 390 * IEEE 1275 Working Group Proposal #414 says that the Primary 391 * controller is "ata@0" and the Secondary controller "ata@1". 392 * 393 * By the time we get here, boot Bootconf (2.6+) has created devinfo 394 * nodes with the appropriate "reg", "assigned-addresses" and "interrupts" 395 * properites on the pci-ide node and both ide child nodes. 396 * 397 * In compatibility mode the "reg" and "assigned-addresses" properties 398 * of the pci-ide node are set up like this: 399 * 400 * 1. PCI-IDE Nexus 401 * 402 * interrupts=0 403 * (addr-hi addr-mid addr-low size-hi size-low) 404 * reg= assigned-addresses=00000000.00000000.00000000.00000000.00000000 405 * 81000000.00000000.000001f0.00000000.00000008 406 * 81000000.00000000.000003f4.00000000.00000004 407 * 81000000.00000000,00000170.00000000.00000008 408 * 81000000.00000000,00000374.00000000.00000004 409 * 01000020.00000000,-[BAR4]-.00000000.00000010 410 * 411 * In native PCI mode the "reg" and "assigned-addresses" properties 412 * would be set up like this: 413 * 414 * 2. PCI-IDE Nexus 415 * 416 * interrupts=0 417 * reg= assigned-addresses=00000000.00000000.00000000.00000000.00000000 418 * 01000010.00000000.-[BAR0]-.00000000.00000008 419 * 01000014,00000000.-[BAR1]-.00000000.00000004 420 * 01000018.00000000.-[BAR2]-.00000000.00000008 421 * 0100001c.00000000.-[BAR3]-.00000000.00000004 422 * 01000020.00000000.-[BAR4]-.00000000.00000010 423 * 424 * 425 * In both modes the child nodes simply have the following: 426 * 427 * 2. primary controller (compatibility mode) 428 * 429 * interrupts=14 430 * reg=00000000 431 * 432 * 3. secondary controller 433 * 434 * interrupts=15 435 * reg=00000001 436 * 437 * The pciide_bus_map() function is responsible for turning requests 438 * to map primary or secondary controller rnumbers into mapping requests 439 * of the appropriate regspec on the pci-ide node. 440 * 441 */ 442 443 static int 444 pciide_initchild(dev_info_t *mydip, dev_info_t *cdip) 445 { 446 struct ddi_parent_private_data *pdptr; 447 struct intrspec *ispecp; 448 int vec; 449 int *rp; 450 uint_t proplen; 451 char name[80]; 452 int dev; 453 454 PDBG(("pciide_initchild\n")); 455 456 /* 457 * Set the address portion of the node name based on 458 * the controller number (0 or 1) from the 'reg' property. 459 */ 460 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 461 "reg", &rp, (uint_t *)&proplen) != DDI_PROP_SUCCESS) { 462 PDBG(("pciide_intchild prop error\n")); 463 return (DDI_NOT_WELL_FORMED); 464 } 465 466 /* 467 * copy the controller number and 468 * free the memory allocated by ddi_prop_lookup_int_array 469 */ 470 dev = *rp; 471 ddi_prop_free(rp); 472 473 /* 474 * I only support two controllers per device, determine 475 * which this one is and set its unit address. 476 */ 477 if (dev > 1) { 478 PDBG(("pciide_initchild bad dev\n")); 479 return (DDI_NOT_WELL_FORMED); 480 } 481 (void) sprintf(name, "%d", dev); 482 ddi_set_name_addr(cdip, name); 483 484 /* 485 * determine if this instance is running in native or compat mode 486 */ 487 pciide_compat_setup(mydip, cdip, dev); 488 489 /* interrupts property is required */ 490 if (PCIIDE_NATIVE_MODE(cdip)) { 491 vec = 1; 492 } else { 493 /* 494 * In compatibility mode, dev 0 should always be 495 * IRQ 14 and dev 1 is IRQ 15. If for some reason 496 * this needs to be changed, do it via the interrupts 497 * property in the ata.conf file. 498 */ 499 vec = ddi_prop_get_int(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 500 "interrupts", -1); 501 if (vec == -1) { 502 /* setup compatibility mode interrupts */ 503 if (dev == 0) { 504 vec = 14; 505 } else if (dev == 1) { 506 vec = 15; 507 } else { 508 PDBG(("pciide_initchild bad intr\n")); 509 return (DDI_NOT_WELL_FORMED); 510 } 511 } 512 } 513 514 pdptr = kmem_zalloc(PCIIDE_PDSIZE, KM_SLEEP); 515 ispecp = (struct intrspec *)(pdptr + 1); 516 pdptr->par_nintr = 1; 517 pdptr->par_intr = ispecp; 518 ispecp->intrspec_vec = vec; 519 ddi_set_parent_data(cdip, pdptr); 520 521 PDBG(("pciide_initchild okay\n")); 522 return (DDI_SUCCESS); 523 } 524 525 static int 526 pciide_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 527 off_t offset, off_t len, caddr_t *vaddrp) 528 { 529 dev_info_t *pdip; 530 int rnumber = mp->map_obj.rnumber; 531 int controller; 532 int rc; 533 534 PDBG(("pciide_bus_map\n")); 535 536 if (strcmp("0", ddi_get_name_addr(rdip)) == 0) 537 controller = 0; 538 else 539 controller = 1; 540 541 /* 542 * Adjust the rnumbers based on which controller instance 543 * is being mapped; adjust for the 2 tuples per controller. 544 */ 545 546 switch (rnumber) { 547 case 0: 548 case 1: 549 mp->map_obj.rnumber += (controller * 2); 550 break; 551 case 2: 552 /* 553 * split the 16 I/O ports into two 8 port ranges 554 */ 555 mp->map_obj.rnumber = 4; 556 if (offset + len > 8) { 557 PDBG(("pciide_bus_map offset\n")); 558 return (DDI_FAILURE); 559 } 560 if (len == 0) 561 len = 8 - offset; 562 offset += 8 * controller; 563 break; 564 default: 565 PDBG(("pciide_bus_map default\n")); 566 return (DDI_FAILURE); 567 } 568 569 if (PCIIDE_PRE26(dip)) { 570 int old_rnumber; 571 int new_rnumber; 572 573 old_rnumber = mp->map_obj.rnumber; 574 new_rnumber = pciide_pre26_rnumber_map(dip, old_rnumber); 575 PDBG(("pciide rnumber old %d new %d\n", 576 old_rnumber, new_rnumber)); 577 mp->map_obj.rnumber = new_rnumber; 578 } 579 580 /* 581 * Add 1 to skip over the PCI config space tuple 582 */ 583 mp->map_obj.rnumber++; 584 585 586 /* 587 * pass the adjusted request to my parent 588 */ 589 pdip = ddi_get_parent(dip); 590 rc = ((*(DEVI(pdip)->devi_ops->devo_bus_ops->bus_map)) 591 (pdip, dip, mp, offset, len, vaddrp)); 592 593 PDBG(("pciide_bus_map %s\n", rc == DDI_SUCCESS ? "okay" : "!ok")); 594 595 return (rc); 596 } 597 598 599 static struct intrspec * 600 pciide_get_ispec(dev_info_t *dip, dev_info_t *rdip, int inumber) 601 { 602 struct ddi_parent_private_data *ppdptr; 603 604 PDBG(("pciide_get_ispec\n")); 605 606 /* 607 * Native mode PCI-IDE controllers share the parent's 608 * PCI interrupt line. 609 * 610 * Compatibility mode PCI-IDE controllers have their 611 * own intrspec which specifies ISA IRQ 14 or 15. 612 * 613 */ 614 if (PCIIDE_NATIVE_MODE(rdip)) { 615 ddi_intrspec_t is; 616 617 is = pci_intx_get_ispec(dip, dip, inumber); 618 PDBG(("pciide_get_ispec okay\n")); 619 return ((struct intrspec *)is); 620 } 621 622 /* Else compatibility mode, use the ISA IRQ */ 623 if ((ppdptr = ddi_get_parent_data(rdip)) == NULL) { 624 PDBG(("pciide_get_ispec null\n")); 625 return (NULL); 626 } 627 628 /* validate the interrupt number */ 629 if (inumber >= ppdptr->par_nintr) { 630 PDBG(("pciide_get_inum\n")); 631 return (NULL); 632 } 633 634 PDBG(("pciide_get_ispec ok\n")); 635 636 return ((struct intrspec *)&ppdptr->par_intr[inumber]); 637 } 638 639 static int 640 pciide_get_pri(dev_info_t *dip, dev_info_t *rdip, 641 ddi_intr_handle_impl_t *hdlp, int *pri) 642 { 643 struct intrspec *ispecp; 644 int *intpriorities; 645 uint_t num_intpriorities; 646 647 PDBG(("pciide_get_pri\n")); 648 649 if ((ispecp = pciide_get_ispec(dip, rdip, hdlp->ih_inum)) == NULL) { 650 PDBG(("pciide_get_pri null\n")); 651 return (DDI_FAILURE); 652 } 653 654 if (PCIIDE_NATIVE_MODE(rdip)) { 655 *pri = ispecp->intrspec_pri; 656 PDBG(("pciide_get_pri ok\n")); 657 return (DDI_SUCCESS); 658 } 659 660 /* check if the intrspec has been initialized */ 661 if (ispecp->intrspec_pri != 0) { 662 *pri = ispecp->intrspec_pri; 663 PDBG(("pciide_get_pri ok2\n")); 664 return (DDI_SUCCESS); 665 } 666 667 /* Use a default of level 5 */ 668 ispecp->intrspec_pri = 5; 669 670 /* 671 * If there's an interrupt-priorities property, use it to 672 * over-ride the default interrupt priority. 673 */ 674 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 675 "interrupt-priorities", &intpriorities, &num_intpriorities) == 676 DDI_PROP_SUCCESS) { 677 if (hdlp->ih_inum < num_intpriorities) 678 ispecp->intrspec_pri = intpriorities[hdlp->ih_inum]; 679 ddi_prop_free(intpriorities); 680 } 681 *pri = ispecp->intrspec_pri; 682 683 PDBG(("pciide_get_pri ok3\n")); 684 685 return (DDI_SUCCESS); 686 } 687 688 static int 689 pciide_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 690 ddi_intr_handle_impl_t *hdlp, void *result) 691 { 692 struct intrspec *ispecp; 693 int rc; 694 int pri = 0; 695 696 PDBG(("pciide_intr_ops: dip %p rdip %p op %x hdlp %p\n", 697 (void *)dip, (void *)rdip, intr_op, (void *)hdlp)); 698 699 switch (intr_op) { 700 case DDI_INTROP_SUPPORTED_TYPES: 701 *(int *)result = DDI_INTR_TYPE_FIXED; 702 break; 703 case DDI_INTROP_GETCAP: 704 *(int *)result = DDI_INTR_FLAG_LEVEL; 705 break; 706 case DDI_INTROP_NINTRS: 707 case DDI_INTROP_NAVAIL: 708 *(int *)result = (!PCIIDE_NATIVE_MODE(rdip)) ? 709 i_ddi_get_intx_nintrs(rdip) : 1; 710 break; 711 case DDI_INTROP_ALLOC: 712 if ((ispecp = pciide_get_ispec(dip, rdip, hdlp->ih_inum)) == 713 NULL) 714 return (DDI_FAILURE); 715 *(int *)result = hdlp->ih_scratch1; 716 break; 717 case DDI_INTROP_FREE: 718 break; 719 case DDI_INTROP_GETPRI: 720 if (pciide_get_pri(dip, rdip, hdlp, &pri) != DDI_SUCCESS) { 721 *(int *)result = 0; 722 return (DDI_FAILURE); 723 } 724 *(int *)result = pri; 725 break; 726 case DDI_INTROP_ADDISR: 727 if ((ispecp = pciide_get_ispec(dip, rdip, hdlp->ih_inum)) == 728 NULL) 729 return (DDI_FAILURE); 730 ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp = ispecp; 731 ispecp->intrspec_func = hdlp->ih_cb_func; 732 break; 733 case DDI_INTROP_REMISR: 734 if ((ispecp = pciide_get_ispec(dip, rdip, hdlp->ih_inum)) == 735 NULL) 736 return (DDI_FAILURE); 737 ispecp->intrspec_func = (uint_t (*)()) 0; 738 break; 739 case DDI_INTROP_ENABLE: 740 /* FALLTHRU */ 741 case DDI_INTROP_DISABLE: 742 if (PCIIDE_NATIVE_MODE(rdip)) { 743 rdip = dip; 744 dip = ddi_get_parent(dip); 745 } else { /* get ptr to the root node */ 746 dip = ddi_root_node(); 747 } 748 749 rc = (*(DEVI(dip)->devi_ops->devo_bus_ops->bus_intr_op))(dip, 750 rdip, intr_op, hdlp, result); 751 752 #ifdef DEBUG 753 if (intr_op == DDI_INTROP_ENABLE) { 754 PDBG(("pciide_enable rc=%d", rc)); 755 } else 756 PDBG(("pciide_disable rc=%d", rc)); 757 #endif /* DEBUG */ 758 return (rc); 759 default: 760 return (DDI_FAILURE); 761 } 762 763 return (DDI_SUCCESS); 764 } 765 766 /* 767 * This is one of the places where controller specific setup needs to be 768 * considered. 769 * At this point the controller was already pre-qualified as a known and 770 * supported pciide controller. 771 * Some controllers do not provide PCI_MASS_IDE sub-class code and IDE 772 * programming interface code but rather PCI_MASS_OTHER sub-class code 773 * without any additional data. 774 * For those controllers IDE programming interface cannot be extracted 775 * from PCI class - we assume that they are pci-native type and we fix 776 * the programming interface used by other functions. 777 * The programming interface byte is set to indicate pci-native mode 778 * for both controllers and the Bus Master DMA capabilitiy of the controller. 779 */ 780 static void 781 pciide_compat_setup(dev_info_t *mydip, dev_info_t *cdip, int dev) 782 { 783 int class_code; 784 int rc = DDI_PROP_SUCCESS; 785 786 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, mydip, 787 DDI_PROP_DONTPASS, "class-code", 0); 788 789 if (((class_code & 0x00FF00) >> 8) == PCI_MASS_IDE) { 790 /* 791 * Controller provides PCI_MASS_IDE sub-class code first 792 * (implied IDE programming interface) 793 */ 794 if ((dev == 0 && !(class_code & PCI_IDE_IF_NATIVE_PRI)) || 795 (dev == 1 && !(class_code & PCI_IDE_IF_NATIVE_SEC))) { 796 rc = ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 797 "compatibility-mode", 1); 798 if (rc != DDI_PROP_SUCCESS) 799 cmn_err(CE_WARN, 800 "pciide prop error %d compat-mode", rc); 801 } 802 } else { 803 /* 804 * Pci-ide controllers not providing PCI_MASS_IDE sub-class are 805 * assumed to be of pci-native type and bus master DMA capable. 806 * Programming interface part of the class-code property is 807 * fixed here. 808 */ 809 class_code &= 0x00ffff00; 810 class_code |= PCI_IDE_IF_BM_CAP_MASK | 811 PCI_IDE_IF_NATIVE_PRI | PCI_IDE_IF_NATIVE_SEC; 812 rc = ddi_prop_update_int(DDI_DEV_T_NONE, mydip, 813 "class-code", class_code); 814 if (rc != DDI_PROP_SUCCESS) 815 cmn_err(CE_WARN, 816 "pciide prop error %d class-code", rc); 817 } 818 } 819 820 821 static int 822 pciide_pre26_rnumber_map(dev_info_t *mydip, int rnumber) 823 { 824 int pri_native; 825 int sec_native; 826 int class_code; 827 828 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, mydip, DDI_PROP_DONTPASS, 829 "class-code", 0); 830 831 pri_native = (class_code & PCI_IDE_IF_NATIVE_PRI) ? TRUE : FALSE; 832 sec_native = (class_code & PCI_IDE_IF_NATIVE_SEC) ? TRUE : FALSE; 833 834 return (pciide_map_rnumber(rnumber, pri_native, sec_native)); 835 836 } 837 838 /* 839 * The canonical order of the reg property tuples for the 840 * Base Address Registers is supposed to be: 841 * 842 * primary controller (BAR 0) 843 * primary controller (BAR 1) 844 * secondary controller (BAR 2) 845 * secondary controller (BAR 3) 846 * bus mastering regs (BAR 4) 847 * 848 * For 2.6, bootconf has been fixed to always generate the 849 * reg property (and assigned-addresses property) tuples 850 * in the above order. 851 * 852 * But in releases prior to 2.6 the order varies depending 853 * on whether compatibility or native mode is being used for 854 * each controller. There ends up being four possible 855 * orders: 856 * 857 * BM, P0, P1, S0, S1 primary compatible, secondary compatible 858 * S0, S1, BM, P0, P1 primary compatible, secondary native 859 * P0, P1, BM, S0, S1 primary native, secondary compatible 860 * P0, P1, S0, S1, BM primary native, secondary native 861 * 862 * where: Px is the primary tuples, Sx the secondary tuples, and 863 * B the Bus Master tuple. 864 * 865 * Here's the results for each of the four states: 866 * 867 * 0, 1, 2, 3, 4 868 * 869 * CC 1, 2, 3, 4, 0 870 * CN 3, 4, 0, 1, 2 871 * NC 0, 1, 3, 4, 2 872 * NN 0, 1, 2, 3, 4 873 * 874 * C = compatible(!native) == 0 875 * N = native == 1 876 * 877 * Here's the transformation matrix: 878 */ 879 880 static int pciide_transform[2][2][5] = { 881 /* P S */ 882 /* [C][C] */ +1, +1, +1, +1, -4, 883 /* [C][N] */ +3, +3, -2, -2, -2, 884 /* [N][C] */ +0, +0, +1, +1, -2, 885 /* [N][N] */ +0, +0, +0, +0, +0 886 }; 887 888 889 static int 890 pciide_map_rnumber(int rnumber, int pri_native, int sec_native) 891 { 892 /* transform flags into indexes */ 893 pri_native = pri_native ? 1 : 0; 894 sec_native = sec_native ? 1 : 0; 895 896 rnumber += pciide_transform[pri_native][sec_native][rnumber]; 897 return (rnumber); 898 } 899