xref: /titanic_51/usr/src/uts/common/io/nxge/nxge_virtual.c (revision 7b3411b6ce9d5ba373d2e36a6c8db48b2dfb74b7)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #include <sys/nxge/nxge_impl.h>
27 #include <sys/nxge/nxge_mac.h>
28 #include <sys/nxge/nxge_hio.h>
29 
30 /*
31  * Local defines for FWARC 2006/556
32  */
33 #define	NXGE_NIU_TDMA_PROP_LEN		2
34 #define	NXGE_NIU_RDMA_PROP_LEN		2
35 #define	NXGE_NIU_0_INTR_PROP_LEN	19
36 #define	NXGE_NIU_1_INTR_PROP_LEN	17
37 
38 /*
39  * Local functions.
40  */
41 static void nxge_get_niu_property(dev_info_t *, niu_type_t *);
42 static nxge_status_t nxge_get_mac_addr_properties(p_nxge_t);
43 static nxge_status_t nxge_use_cfg_n2niu_properties(p_nxge_t);
44 static void nxge_use_cfg_neptune_properties(p_nxge_t);
45 static void nxge_use_cfg_dma_config(p_nxge_t);
46 static void nxge_use_cfg_vlan_class_config(p_nxge_t);
47 static void nxge_use_cfg_mac_class_config(p_nxge_t);
48 static void nxge_use_cfg_class_config(p_nxge_t);
49 static void nxge_use_cfg_link_cfg(p_nxge_t);
50 static void nxge_set_hw_dma_config(p_nxge_t);
51 static void nxge_set_hw_vlan_class_config(p_nxge_t);
52 static void nxge_set_hw_mac_class_config(p_nxge_t);
53 static void nxge_set_hw_class_config(p_nxge_t);
54 static nxge_status_t nxge_use_default_dma_config_n2(p_nxge_t);
55 static void nxge_ldgv_setup(p_nxge_ldg_t *, p_nxge_ldv_t *, uint8_t,
56 	uint8_t, int *);
57 static void nxge_init_mmac(p_nxge_t, boolean_t);
58 static void nxge_set_rdc_intr_property(p_nxge_t);
59 
60 uint32_t nxge_use_hw_property = 1;
61 uint32_t nxge_groups_per_port = 2;
62 
63 extern uint32_t nxge_use_partition;
64 extern uint32_t nxge_dma_obp_props_only;
65 
66 extern uint_t nxge_rx_intr(void *, void *);
67 extern uint_t nxge_tx_intr(void *, void *);
68 extern uint_t nxge_mif_intr(void *, void *);
69 extern uint_t nxge_mac_intr(void *, void *);
70 extern uint_t nxge_syserr_intr(void *, void *);
71 extern void *nxge_list;
72 
73 #define	NXGE_SHARED_REG_SW_SIM
74 
75 #ifdef NXGE_SHARED_REG_SW_SIM
76 uint64_t global_dev_ctrl = 0;
77 #endif
78 
79 #define	MAX_SIBLINGS	NXGE_MAX_PORTS
80 
81 extern uint32_t nxge_rbr_size;
82 extern uint32_t nxge_rcr_size;
83 extern uint32_t nxge_tx_ring_size;
84 extern uint32_t nxge_rbr_spare_size;
85 
86 extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t);
87 
88 static uint8_t p2_tx_fair[2] = {12, 12};
89 static uint8_t p2_tx_equal[2] = {12, 12};
90 static uint8_t p4_tx_fair[4] = {6, 6, 6, 6};
91 static uint8_t p4_tx_equal[4] = {6, 6, 6, 6};
92 static uint8_t p2_rx_fair[2] = {8, 8};
93 static uint8_t p2_rx_equal[2] = {8, 8};
94 static uint8_t p4_rx_fair[4] = {4, 4, 4, 4};
95 static uint8_t p4_rx_equal[4] = {4, 4, 4, 4};
96 
97 static uint8_t p2_rdcgrp_fair[2] = {4, 4};
98 static uint8_t p2_rdcgrp_equal[2] = {4, 4};
99 static uint8_t p4_rdcgrp_fair[4] = {2, 2, 1, 1};
100 static uint8_t p4_rdcgrp_equal[4] = {2, 2, 2, 2};
101 static uint8_t p2_rdcgrp_cls[2] = {1, 1};
102 static uint8_t p4_rdcgrp_cls[4] = {1, 1, 1, 1};
103 
104 static uint8_t rx_4_1G[4] = {4, 4, 4, 4};
105 static uint8_t rx_2_10G[2] = {8, 8};
106 static uint8_t rx_2_10G_2_1G[4] = {6, 6, 2, 2};
107 static uint8_t rx_1_10G_3_1G[4] = {10, 2, 2, 2};
108 static uint8_t rx_1_1G_1_10G_2_1G[4] = {2, 10, 2, 2};
109 
110 static uint8_t tx_4_1G[4] = {6, 6, 6, 6};
111 static uint8_t tx_2_10G[2] = {12, 12};
112 static uint8_t tx_2_10G_2_1G[4] = {10, 10, 2, 2};
113 static uint8_t tx_1_10G_3_1G[4] = {12, 4, 4, 4};
114 static uint8_t tx_1_1G_1_10G_2_1G[4] = {4, 12, 4, 4};
115 
116 typedef enum {
117 	DEFAULT = 0,
118 	EQUAL,
119 	FAIR,
120 	CUSTOM,
121 	CLASSIFY,
122 	L2_CLASSIFY,
123 	L3_DISTRIBUTE,
124 	L3_CLASSIFY,
125 	L3_TCAM,
126 	CONFIG_TOKEN_NONE
127 } config_token_t;
128 
129 static char *token_names[] = {
130 	"default",
131 	"equal",
132 	"fair",
133 	"custom",
134 	"classify",
135 	"l2_classify",
136 	"l3_distribute",
137 	"l3_classify",
138 	"l3_tcam",
139 	"none",
140 };
141 
142 void nxge_virint_regs_dump(p_nxge_t nxgep);
143 
144 void
145 nxge_virint_regs_dump(p_nxge_t nxgep)
146 {
147 	npi_handle_t handle;
148 
149 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_virint_regs_dump"));
150 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
151 	(void) npi_vir_dump_pio_fzc_regs_one(handle);
152 	(void) npi_vir_dump_ldgnum(handle);
153 	(void) npi_vir_dump_ldsv(handle);
154 	(void) npi_vir_dump_imask0(handle);
155 	(void) npi_vir_dump_sid(handle);
156 	(void) npi_mac_dump_regs(handle, nxgep->function_num);
157 	(void) npi_ipp_dump_regs(handle, nxgep->function_num);
158 	(void) npi_fflp_dump_regs(handle);
159 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_virint_regs_dump"));
160 }
161 
162 /*
163  * For now: we hard coded the DMA configurations.
164  *	    and assume for one partition only.
165  *
166  *       OBP. Then OBP will pass this partition's
167  *	 Neptune configurations to fcode to create
168  *	 properties for them.
169  *
170  *	Since Neptune(PCI-E) and NIU (Niagara-2) has
171  *	different bus interfaces, the driver needs
172  *	to know which bus it is connected to.
173  *  	Ravinder suggested: create a device property.
174  *	In partitioning environment, we cannot
175  *	use .conf file (need to check). If conf changes,
176  *	need to reboot the system.
177  *	The following function assumes that we will
178  *	retrieve its properties from a virtualized nexus driver.
179  */
180 
181 nxge_status_t
182 nxge_cntlops(dev_info_t *dip, nxge_ctl_enum_t ctlop, void *arg, void *result)
183 {
184 	nxge_status_t status = NXGE_OK;
185 	int instance;
186 	p_nxge_t nxgep;
187 
188 #ifndef NXGE_SHARED_REG_SW_SIM
189 	npi_handle_t handle;
190 	uint16_t sr16, cr16;
191 #endif
192 	instance = ddi_get_instance(dip);
193 	NXGE_DEBUG_MSG((NULL, VIR_CTL, "Instance %d ", instance));
194 
195 	if (nxge_list == NULL) {
196 		NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
197 		    "nxge_cntlops: nxge_list null"));
198 		return (NXGE_ERROR);
199 	}
200 	nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance);
201 	if (nxgep == NULL) {
202 		NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
203 		    "nxge_cntlops: nxgep null"));
204 		return (NXGE_ERROR);
205 	}
206 #ifndef NXGE_SHARED_REG_SW_SIM
207 	handle = nxgep->npi_reg_handle;
208 #endif
209 	switch (ctlop) {
210 	case NXGE_CTLOPS_NIUTYPE:
211 		nxge_get_niu_property(dip, (niu_type_t *)result);
212 		return (status);
213 
214 	case NXGE_CTLOPS_GET_SHARED_REG:
215 #ifdef NXGE_SHARED_REG_SW_SIM
216 		*(uint64_t *)result = global_dev_ctrl;
217 		return (0);
218 #else
219 		status = npi_dev_func_sr_sr_get(handle, &sr16);
220 		*(uint16_t *)result = sr16;
221 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
222 		    "nxge_cntlops: NXGE_CTLOPS_GET_SHARED_REG"));
223 		return (0);
224 #endif
225 
226 	case NXGE_CTLOPS_SET_SHARED_REG_LOCK:
227 #ifdef NXGE_SHARED_REG_SW_SIM
228 		global_dev_ctrl = *(uint64_t *)arg;
229 		return (0);
230 #else
231 		status = NPI_FAILURE;
232 		while (status != NPI_SUCCESS)
233 			status = npi_dev_func_sr_lock_enter(handle);
234 
235 		sr16 = *(uint16_t *)arg;
236 		status = npi_dev_func_sr_sr_set_only(handle, &sr16);
237 		status = npi_dev_func_sr_lock_free(handle);
238 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
239 		    "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
240 		return (0);
241 #endif
242 
243 	case NXGE_CTLOPS_UPDATE_SHARED_REG:
244 #ifdef NXGE_SHARED_REG_SW_SIM
245 		global_dev_ctrl |= *(uint64_t *)arg;
246 		return (0);
247 #else
248 		status = NPI_FAILURE;
249 		while (status != NPI_SUCCESS)
250 			status = npi_dev_func_sr_lock_enter(handle);
251 		status = npi_dev_func_sr_sr_get(handle, &sr16);
252 		sr16 |= *(uint16_t *)arg;
253 		status = npi_dev_func_sr_sr_set_only(handle, &sr16);
254 		status = npi_dev_func_sr_lock_free(handle);
255 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
256 		    "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
257 		return (0);
258 #endif
259 
260 	case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG_UL:
261 #ifdef NXGE_SHARED_REG_SW_SIM
262 		global_dev_ctrl |= *(uint64_t *)arg;
263 		return (0);
264 #else
265 		status = npi_dev_func_sr_sr_get(handle, &sr16);
266 		cr16 = *(uint16_t *)arg;
267 		sr16 &= ~cr16;
268 		status = npi_dev_func_sr_sr_set_only(handle, &sr16);
269 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
270 		    "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
271 		return (0);
272 #endif
273 
274 	case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG:
275 #ifdef NXGE_SHARED_REG_SW_SIM
276 		global_dev_ctrl |= *(uint64_t *)arg;
277 		return (0);
278 #else
279 		status = NPI_FAILURE;
280 		while (status != NPI_SUCCESS)
281 			status = npi_dev_func_sr_lock_enter(handle);
282 		status = npi_dev_func_sr_sr_get(handle, &sr16);
283 		cr16 = *(uint16_t *)arg;
284 		sr16 &= ~cr16;
285 		status = npi_dev_func_sr_sr_set_only(handle, &sr16);
286 		status = npi_dev_func_sr_lock_free(handle);
287 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
288 		    "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
289 		return (0);
290 #endif
291 
292 	case NXGE_CTLOPS_GET_LOCK_BLOCK:
293 #ifdef NXGE_SHARED_REG_SW_SIM
294 		global_dev_ctrl |= *(uint64_t *)arg;
295 		return (0);
296 #else
297 		status = NPI_FAILURE;
298 		while (status != NPI_SUCCESS)
299 			status = npi_dev_func_sr_lock_enter(handle);
300 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
301 		    "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_BLOCK"));
302 		return (0);
303 #endif
304 	case NXGE_CTLOPS_GET_LOCK_TRY:
305 #ifdef NXGE_SHARED_REG_SW_SIM
306 		global_dev_ctrl |= *(uint64_t *)arg;
307 		return (0);
308 #else
309 		status = npi_dev_func_sr_lock_enter(handle);
310 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
311 		    "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_TRY"));
312 		if (status == NPI_SUCCESS)
313 			return (NXGE_OK);
314 		else
315 			return (NXGE_ERROR);
316 #endif
317 	case NXGE_CTLOPS_FREE_LOCK:
318 #ifdef NXGE_SHARED_REG_SW_SIM
319 		global_dev_ctrl |= *(uint64_t *)arg;
320 		return (0);
321 #else
322 		status = npi_dev_func_sr_lock_free(handle);
323 		NXGE_DEBUG_MSG((NULL, VIR_CTL,
324 		    "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_FREE"));
325 		if (status == NPI_SUCCESS)
326 			return (NXGE_OK);
327 		else
328 			return (NXGE_ERROR);
329 #endif
330 
331 	default:
332 		status = NXGE_ERROR;
333 	}
334 
335 	return (status);
336 }
337 
338 void
339 nxge_common_lock_get(p_nxge_t nxgep)
340 {
341 	uint32_t status = NPI_FAILURE;
342 	npi_handle_t handle;
343 
344 #if	defined(NXGE_SHARE_REG_SW_SIM)
345 	return;
346 #endif
347 	handle = nxgep->npi_reg_handle;
348 	while (status != NPI_SUCCESS)
349 		status = npi_dev_func_sr_lock_enter(handle);
350 }
351 
352 void
353 nxge_common_lock_free(p_nxge_t nxgep)
354 {
355 	npi_handle_t handle;
356 
357 #if	defined(NXGE_SHARE_REG_SW_SIM)
358 	return;
359 #endif
360 	handle = nxgep->npi_reg_handle;
361 	(void) npi_dev_func_sr_lock_free(handle);
362 }
363 
364 
365 static void
366 nxge_get_niu_property(dev_info_t *dip, niu_type_t *niu_type)
367 {
368 	uchar_t *prop_val;
369 	uint_t prop_len;
370 
371 	*niu_type = NIU_TYPE_NONE;
372 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0,
373 	    "niu-type", (uchar_t **)&prop_val,
374 	    &prop_len) == DDI_PROP_SUCCESS) {
375 		if (strncmp("niu", (caddr_t)prop_val, (size_t)prop_len) == 0) {
376 			*niu_type = N2_NIU;
377 		}
378 		ddi_prop_free(prop_val);
379 	}
380 }
381 
382 static config_token_t
383 nxge_get_config_token(char *prop)
384 {
385 	config_token_t token = DEFAULT;
386 
387 	while (token < CONFIG_TOKEN_NONE) {
388 		if (strncmp(prop, token_names[token], 4) == 0)
389 			break;
390 		token++;
391 	}
392 	return (token);
393 }
394 
395 /* per port */
396 
397 static nxge_status_t
398 nxge_update_rxdma_grp_properties(p_nxge_t nxgep, config_token_t token,
399 	dev_info_t *s_dip[])
400 {
401 	nxge_status_t status = NXGE_OK;
402 	int ddi_status;
403 	int num_ports = nxgep->nports;
404 	int port, bits, j;
405 	uint8_t start_grp = 0, num_grps = 0;
406 	p_nxge_param_t param_arr;
407 	uint32_t grp_bitmap[MAX_SIBLINGS];
408 	int custom_start_grp[MAX_SIBLINGS];
409 	int custom_num_grp[MAX_SIBLINGS];
410 	uint8_t bad_config = B_FALSE;
411 	char *start_prop, *num_prop, *cfg_prop;
412 
413 	start_grp = 0;
414 	param_arr = nxgep->param_arr;
415 	start_prop = param_arr[param_rdc_grps_start].fcode_name;
416 	num_prop = param_arr[param_rx_rdc_grps].fcode_name;
417 
418 	switch (token) {
419 	case FAIR:
420 		cfg_prop = "fair";
421 		for (port = 0; port < num_ports; port++) {
422 			custom_num_grp[port] =
423 			    (num_ports == 4) ?
424 			    p4_rdcgrp_fair[port] :
425 			    p2_rdcgrp_fair[port];
426 			custom_start_grp[port] = start_grp;
427 			start_grp += custom_num_grp[port];
428 		}
429 		break;
430 
431 	case EQUAL:
432 		cfg_prop = "equal";
433 		for (port = 0; port < num_ports; port++) {
434 			custom_num_grp[port] =
435 			    (num_ports == 4) ?
436 			    p4_rdcgrp_equal[port] :
437 			    p2_rdcgrp_equal[port];
438 			custom_start_grp[port] = start_grp;
439 			start_grp += custom_num_grp[port];
440 		}
441 		break;
442 
443 
444 	case CLASSIFY:
445 		cfg_prop = "classify";
446 		for (port = 0; port < num_ports; port++) {
447 			custom_num_grp[port] = (num_ports == 4) ?
448 			    p4_rdcgrp_cls[port] : p2_rdcgrp_cls[port];
449 			custom_start_grp[port] = start_grp;
450 			start_grp += custom_num_grp[port];
451 		}
452 		break;
453 
454 	case CUSTOM:
455 		cfg_prop = "custom";
456 		/* See if it is good config */
457 		num_grps = 0;
458 		for (port = 0; port < num_ports; port++) {
459 			custom_start_grp[port] =
460 			    ddi_prop_get_int(DDI_DEV_T_NONE, s_dip[port],
461 			    DDI_PROP_DONTPASS, start_prop, -1);
462 			if ((custom_start_grp[port] == -1) ||
463 			    (custom_start_grp[port] >=
464 			    NXGE_MAX_RDC_GRPS)) {
465 				bad_config = B_TRUE;
466 				break;
467 			}
468 			custom_num_grp[port] = ddi_prop_get_int(
469 			    DDI_DEV_T_NONE,
470 			    s_dip[port],
471 			    DDI_PROP_DONTPASS,
472 			    num_prop, -1);
473 
474 			if ((custom_num_grp[port] == -1) ||
475 			    (custom_num_grp[port] >
476 			    NXGE_MAX_RDC_GRPS) ||
477 			    ((custom_num_grp[port] +
478 			    custom_start_grp[port]) >=
479 			    NXGE_MAX_RDC_GRPS)) {
480 				bad_config = B_TRUE;
481 				break;
482 			}
483 			num_grps += custom_num_grp[port];
484 			if (num_grps > NXGE_MAX_RDC_GRPS) {
485 				bad_config = B_TRUE;
486 				break;
487 			}
488 			grp_bitmap[port] = 0;
489 			for (bits = 0;
490 			    bits < custom_num_grp[port];
491 			    bits++) {
492 				grp_bitmap[port] |=
493 				    (1 << (bits + custom_start_grp[port]));
494 			}
495 
496 		}
497 
498 		if (bad_config == B_FALSE) {
499 			/* check for overlap */
500 			for (port = 0; port < num_ports - 1; port++) {
501 				for (j = port + 1; j < num_ports; j++) {
502 					if (grp_bitmap[port] &
503 					    grp_bitmap[j]) {
504 						bad_config = B_TRUE;
505 						break;
506 					}
507 				}
508 				if (bad_config == B_TRUE)
509 					break;
510 			}
511 		}
512 		if (bad_config == B_TRUE) {
513 			/* use default config */
514 			for (port = 0; port < num_ports; port++) {
515 				custom_num_grp[port] =
516 				    (num_ports == 4) ?
517 				    p4_rx_fair[port] : p2_rx_fair[port];
518 				custom_start_grp[port] = start_grp;
519 				start_grp += custom_num_grp[port];
520 			}
521 		}
522 		break;
523 
524 	default:
525 		/* use default config */
526 		cfg_prop = "fair";
527 		for (port = 0; port < num_ports; port++) {
528 			custom_num_grp[port] = (num_ports == 4) ?
529 			    p4_rx_fair[port] : p2_rx_fair[port];
530 			custom_start_grp[port] = start_grp;
531 			start_grp += custom_num_grp[port];
532 		}
533 		break;
534 	}
535 
536 	/* Now Update the rx properties */
537 	for (port = 0; port < num_ports; port++) {
538 		ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
539 		    "rxdma-grp-cfg", cfg_prop);
540 		if (ddi_status != DDI_PROP_SUCCESS) {
541 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
542 			    " property %s not updating",
543 			    cfg_prop));
544 			status |= NXGE_DDI_FAILED;
545 		}
546 		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
547 		    num_prop, custom_num_grp[port]);
548 
549 		if (ddi_status != DDI_PROP_SUCCESS) {
550 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
551 			    " property %s not updating",
552 			    num_prop));
553 			status |= NXGE_DDI_FAILED;
554 		}
555 		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
556 		    start_prop, custom_start_grp[port]);
557 
558 		if (ddi_status != DDI_PROP_SUCCESS) {
559 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
560 			    " property %s not updating",
561 			    start_prop));
562 			status |= NXGE_DDI_FAILED;
563 		}
564 	}
565 	if (status & NXGE_DDI_FAILED)
566 		status |= NXGE_ERROR;
567 
568 	return (status);
569 }
570 
571 static nxge_status_t
572 nxge_update_rxdma_properties(p_nxge_t nxgep, config_token_t token,
573 	dev_info_t *s_dip[])
574 {
575 	nxge_status_t status = NXGE_OK;
576 	int ddi_status;
577 	int num_ports = nxgep->nports;
578 	int port, bits, j;
579 	uint8_t start_rdc = 0, num_rdc = 0;
580 	p_nxge_param_t param_arr;
581 	uint32_t rdc_bitmap[MAX_SIBLINGS];
582 	int custom_start_rdc[MAX_SIBLINGS];
583 	int custom_num_rdc[MAX_SIBLINGS];
584 	uint8_t bad_config = B_FALSE;
585 	int *prop_val;
586 	uint_t prop_len;
587 	char *start_rdc_prop, *num_rdc_prop, *cfg_prop;
588 
589 	start_rdc = 0;
590 	param_arr = nxgep->param_arr;
591 	start_rdc_prop = param_arr[param_rxdma_channels_begin].fcode_name;
592 	num_rdc_prop = param_arr[param_rxdma_channels].fcode_name;
593 
594 	switch (token) {
595 	case FAIR:
596 		cfg_prop = "fair";
597 		for (port = 0; port < num_ports; port++) {
598 			custom_num_rdc[port] = (num_ports == 4) ?
599 			    p4_rx_fair[port] : p2_rx_fair[port];
600 			custom_start_rdc[port] = start_rdc;
601 			start_rdc += custom_num_rdc[port];
602 		}
603 		break;
604 
605 	case EQUAL:
606 		cfg_prop = "equal";
607 		for (port = 0; port < num_ports; port++) {
608 			custom_num_rdc[port] = (num_ports == 4) ?
609 			    p4_rx_equal[port] :
610 			    p2_rx_equal[port];
611 			custom_start_rdc[port] = start_rdc;
612 			start_rdc += custom_num_rdc[port];
613 		}
614 		break;
615 
616 	case CUSTOM:
617 		cfg_prop = "custom";
618 		/* See if it is good config */
619 		num_rdc = 0;
620 		for (port = 0; port < num_ports; port++) {
621 			ddi_status = ddi_prop_lookup_int_array(
622 			    DDI_DEV_T_ANY,
623 			    s_dip[port], 0,
624 			    start_rdc_prop,
625 			    &prop_val,
626 			    &prop_len);
627 			if (ddi_status == DDI_SUCCESS)
628 				custom_start_rdc[port] = *prop_val;
629 			else {
630 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
631 				    " %s custom start port %d"
632 				    " read failed ",
633 				    " rxdma-cfg", port));
634 				bad_config = B_TRUE;
635 				status |= NXGE_DDI_FAILED;
636 			}
637 			if ((custom_start_rdc[port] == -1) ||
638 			    (custom_start_rdc[port] >=
639 			    NXGE_MAX_RDCS)) {
640 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
641 				    " %s custom start %d"
642 				    " out of range %x ",
643 				    " rxdma-cfg",
644 				    port,
645 				    custom_start_rdc[port]));
646 				bad_config = B_TRUE;
647 				break;
648 			}
649 			ddi_status = ddi_prop_lookup_int_array(
650 			    DDI_DEV_T_ANY,
651 			    s_dip[port],
652 			    0,
653 			    num_rdc_prop,
654 			    &prop_val,
655 			    &prop_len);
656 
657 			if (ddi_status == DDI_SUCCESS)
658 				custom_num_rdc[port] = *prop_val;
659 			else {
660 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
661 				    " %s custom num port %d"
662 				    " read failed ",
663 				    "rxdma-cfg", port));
664 				bad_config = B_TRUE;
665 				status |= NXGE_DDI_FAILED;
666 			}
667 
668 			if ((custom_num_rdc[port] == -1) ||
669 			    (custom_num_rdc[port] >
670 			    NXGE_MAX_RDCS) ||
671 			    ((custom_num_rdc[port] +
672 			    custom_start_rdc[port]) >
673 			    NXGE_MAX_RDCS)) {
674 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
675 				    " %s custom num %d"
676 				    " out of range %x ",
677 				    " rxdma-cfg",
678 				    port, custom_num_rdc[port]));
679 				bad_config = B_TRUE;
680 				break;
681 			}
682 			num_rdc += custom_num_rdc[port];
683 			if (num_rdc > NXGE_MAX_RDCS) {
684 				bad_config = B_TRUE;
685 				break;
686 			}
687 			rdc_bitmap[port] = 0;
688 			for (bits = 0;
689 			    bits < custom_num_rdc[port]; bits++) {
690 				rdc_bitmap[port] |=
691 				    (1 << (bits + custom_start_rdc[port]));
692 			}
693 		}
694 
695 		if (bad_config == B_FALSE) {
696 			/* check for overlap */
697 			for (port = 0; port < num_ports - 1; port++) {
698 				for (j = port + 1; j < num_ports; j++) {
699 					if (rdc_bitmap[port] &
700 					    rdc_bitmap[j]) {
701 						NXGE_DEBUG_MSG((nxgep,
702 						    CFG_CTL,
703 						    " rxdma-cfg"
704 						    " property custom"
705 						    " bit overlap"
706 						    " %d %d ",
707 						    port, j));
708 						bad_config = B_TRUE;
709 						break;
710 					}
711 				}
712 				if (bad_config == B_TRUE)
713 					break;
714 			}
715 		}
716 		if (bad_config == B_TRUE) {
717 			/* use default config */
718 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
719 			    " rxdma-cfg property:"
720 			    " bad custom config:"
721 			    " use default"));
722 			for (port = 0; port < num_ports; port++) {
723 				custom_num_rdc[port] =
724 				    (num_ports == 4) ?
725 				    p4_rx_fair[port] :
726 				    p2_rx_fair[port];
727 				custom_start_rdc[port] = start_rdc;
728 				start_rdc += custom_num_rdc[port];
729 			}
730 		}
731 		break;
732 
733 	default:
734 		/* use default config */
735 		cfg_prop = "fair";
736 		for (port = 0; port < num_ports; port++) {
737 			custom_num_rdc[port] = (num_ports == 4) ?
738 			    p4_rx_fair[port] : p2_rx_fair[port];
739 			custom_start_rdc[port] = start_rdc;
740 			start_rdc += custom_num_rdc[port];
741 		}
742 		break;
743 	}
744 
745 	/* Now Update the rx properties */
746 	for (port = 0; port < num_ports; port++) {
747 		NXGE_DEBUG_MSG((nxgep, CFG_CTL,
748 		    " update property rxdma-cfg with %s ", cfg_prop));
749 		ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
750 		    "rxdma-cfg", cfg_prop);
751 		if (ddi_status != DDI_PROP_SUCCESS) {
752 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
753 			    " property rxdma-cfg is not updating to %s",
754 			    cfg_prop));
755 			status |= NXGE_DDI_FAILED;
756 		}
757 		NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
758 		    num_rdc_prop, custom_num_rdc[port]));
759 
760 		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
761 		    num_rdc_prop, custom_num_rdc[port]);
762 
763 		if (ddi_status != DDI_PROP_SUCCESS) {
764 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
765 			    " property %s not updating with %d",
766 			    num_rdc_prop, custom_num_rdc[port]));
767 			status |= NXGE_DDI_FAILED;
768 		}
769 		NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
770 		    start_rdc_prop, custom_start_rdc[port]));
771 		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
772 		    start_rdc_prop, custom_start_rdc[port]);
773 
774 		if (ddi_status != DDI_PROP_SUCCESS) {
775 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
776 			    " property %s not updating with %d ",
777 			    start_rdc_prop, custom_start_rdc[port]));
778 			status |= NXGE_DDI_FAILED;
779 		}
780 	}
781 	if (status & NXGE_DDI_FAILED)
782 		status |= NXGE_ERROR;
783 	return (status);
784 }
785 
786 static nxge_status_t
787 nxge_update_txdma_properties(p_nxge_t nxgep, config_token_t token,
788 	dev_info_t *s_dip[])
789 {
790 	nxge_status_t status = NXGE_OK;
791 	int ddi_status = DDI_SUCCESS;
792 	int num_ports = nxgep->nports;
793 	int port, bits, j;
794 	uint8_t  start_tdc, num_tdc = 0;
795 	p_nxge_param_t param_arr;
796 	uint32_t tdc_bitmap[MAX_SIBLINGS];
797 	int custom_start_tdc[MAX_SIBLINGS];
798 	int custom_num_tdc[MAX_SIBLINGS];
799 	uint8_t bad_config = B_FALSE;
800 	int *prop_val;
801 	uint_t prop_len;
802 	char *start_tdc_prop, *num_tdc_prop, *cfg_prop;
803 
804 	start_tdc = 0;
805 	param_arr = nxgep->param_arr;
806 	start_tdc_prop = param_arr[param_txdma_channels_begin].fcode_name;
807 	num_tdc_prop = param_arr[param_txdma_channels].fcode_name;
808 
809 	switch (token) {
810 	case FAIR:
811 		cfg_prop = "fair";
812 		for (port = 0; port < num_ports; port++) {
813 			custom_num_tdc[port] = (num_ports == 4) ?
814 			    p4_tx_fair[port] : p2_tx_fair[port];
815 			custom_start_tdc[port] = start_tdc;
816 			start_tdc += custom_num_tdc[port];
817 		}
818 		break;
819 
820 	case EQUAL:
821 		cfg_prop = "equal";
822 		for (port = 0; port < num_ports; port++) {
823 			custom_num_tdc[port] = (num_ports == 4) ?
824 			    p4_tx_equal[port] : p2_tx_equal[port];
825 			custom_start_tdc[port] = start_tdc;
826 			start_tdc += custom_num_tdc[port];
827 		}
828 		break;
829 
830 	case CUSTOM:
831 		cfg_prop = "custom";
832 		/* See if it is good config */
833 		num_tdc = 0;
834 		for (port = 0; port < num_ports; port++) {
835 			ddi_status = ddi_prop_lookup_int_array(
836 			    DDI_DEV_T_ANY, s_dip[port], 0, start_tdc_prop,
837 			    &prop_val, &prop_len);
838 			if (ddi_status == DDI_SUCCESS)
839 				custom_start_tdc[port] = *prop_val;
840 			else {
841 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
842 				    " %s custom start port %d"
843 				    " read failed ", " txdma-cfg", port));
844 				bad_config = B_TRUE;
845 				status |= NXGE_DDI_FAILED;
846 			}
847 
848 			if ((custom_start_tdc[port] == -1) ||
849 			    (custom_start_tdc[port] >=
850 			    NXGE_MAX_RDCS)) {
851 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
852 				    " %s custom start %d"
853 				    " out of range %x ", " txdma-cfg",
854 				    port, custom_start_tdc[port]));
855 				bad_config = B_TRUE;
856 				break;
857 			}
858 
859 			ddi_status = ddi_prop_lookup_int_array(
860 			    DDI_DEV_T_ANY, s_dip[port], 0, num_tdc_prop,
861 			    &prop_val, &prop_len);
862 			if (ddi_status == DDI_SUCCESS)
863 				custom_num_tdc[port] = *prop_val;
864 			else {
865 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
866 				    " %s custom num port %d"
867 				    " read failed ", " txdma-cfg", port));
868 				bad_config = B_TRUE;
869 				status |= NXGE_DDI_FAILED;
870 			}
871 
872 			if ((custom_num_tdc[port] == -1) ||
873 			    (custom_num_tdc[port] >
874 			    NXGE_MAX_TDCS) ||
875 			    ((custom_num_tdc[port] +
876 			    custom_start_tdc[port]) >
877 			    NXGE_MAX_TDCS)) {
878 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
879 				    " %s custom num %d"
880 				    " out of range %x ", " rxdma-cfg",
881 				    port, custom_num_tdc[port]));
882 				bad_config = B_TRUE;
883 				break;
884 			}
885 			num_tdc += custom_num_tdc[port];
886 			if (num_tdc > NXGE_MAX_TDCS) {
887 				bad_config = B_TRUE;
888 				break;
889 			}
890 			tdc_bitmap[port] = 0;
891 			for (bits = 0;
892 			    bits < custom_num_tdc[port]; bits++) {
893 				tdc_bitmap[port] |=
894 				    (1 <<
895 				    (bits + custom_start_tdc[port]));
896 			}
897 
898 		}
899 
900 		if (bad_config == B_FALSE) {
901 			/* check for overlap */
902 			for (port = 0; port < num_ports - 1; port++) {
903 				for (j = port + 1; j < num_ports; j++) {
904 					if (tdc_bitmap[port] &
905 					    tdc_bitmap[j]) {
906 						NXGE_DEBUG_MSG((nxgep, CFG_CTL,
907 						    " rxdma-cfg"
908 						    " property custom"
909 						    " bit overlap"
910 						    " %d %d ",
911 						    port, j));
912 						bad_config = B_TRUE;
913 						break;
914 					}
915 				}
916 				if (bad_config == B_TRUE)
917 					break;
918 			}
919 		}
920 		if (bad_config == B_TRUE) {
921 			/* use default config */
922 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
923 			    " txdma-cfg property:"
924 			    " bad custom config:" " use default"));
925 
926 			for (port = 0; port < num_ports; port++) {
927 				custom_num_tdc[port] = (num_ports == 4) ?
928 				    p4_tx_fair[port] : p2_tx_fair[port];
929 				custom_start_tdc[port] = start_tdc;
930 				start_tdc += custom_num_tdc[port];
931 			}
932 		}
933 		break;
934 
935 	default:
936 		/* use default config */
937 		cfg_prop = "fair";
938 		for (port = 0; port < num_ports; port++) {
939 			custom_num_tdc[port] = (num_ports == 4) ?
940 			    p4_tx_fair[port] : p2_tx_fair[port];
941 			custom_start_tdc[port] = start_tdc;
942 			start_tdc += custom_num_tdc[port];
943 		}
944 		break;
945 	}
946 
947 	/* Now Update the tx properties */
948 	for (port = 0; port < num_ports; port++) {
949 		NXGE_DEBUG_MSG((nxgep, CFG_CTL,
950 		    " update property txdma-cfg with %s ", cfg_prop));
951 		ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
952 		    "txdma-cfg", cfg_prop);
953 		if (ddi_status != DDI_PROP_SUCCESS) {
954 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
955 			    " property txdma-cfg is not updating to %s",
956 			    cfg_prop));
957 			status |= NXGE_DDI_FAILED;
958 		}
959 		NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
960 		    num_tdc_prop, custom_num_tdc[port]));
961 
962 		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
963 		    num_tdc_prop, custom_num_tdc[port]);
964 
965 		if (ddi_status != DDI_PROP_SUCCESS) {
966 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
967 			    " property %s not updating with %d",
968 			    num_tdc_prop,
969 			    custom_num_tdc[port]));
970 			status |= NXGE_DDI_FAILED;
971 		}
972 
973 		NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
974 		    start_tdc_prop, custom_start_tdc[port]));
975 
976 		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
977 		    start_tdc_prop, custom_start_tdc[port]);
978 		if (ddi_status != DDI_PROP_SUCCESS) {
979 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
980 			    " property %s not updating with %d ",
981 			    start_tdc_prop, custom_start_tdc[port]));
982 			status |= NXGE_DDI_FAILED;
983 		}
984 	}
985 	if (status & NXGE_DDI_FAILED)
986 		status |= NXGE_ERROR;
987 	return (status);
988 }
989 
990 static nxge_status_t
991 nxge_update_cfg_properties(p_nxge_t nxgep, uint32_t flags,
992 	config_token_t token, dev_info_t *s_dip[])
993 {
994 	nxge_status_t status = NXGE_OK;
995 
996 	switch (flags) {
997 	case COMMON_TXDMA_CFG:
998 		if (nxge_dma_obp_props_only == 0)
999 			status = nxge_update_txdma_properties(nxgep,
1000 			    token, s_dip);
1001 		break;
1002 	case COMMON_RXDMA_CFG:
1003 		if (nxge_dma_obp_props_only == 0)
1004 			status = nxge_update_rxdma_properties(nxgep,
1005 			    token, s_dip);
1006 
1007 		break;
1008 	case COMMON_RXDMA_GRP_CFG:
1009 		status = nxge_update_rxdma_grp_properties(nxgep,
1010 		    token, s_dip);
1011 		break;
1012 	default:
1013 		return (NXGE_ERROR);
1014 	}
1015 	return (status);
1016 }
1017 
1018 /*
1019  * verify consistence.
1020  * (May require publishing the properties on all the ports.
1021  *
1022  * What if properties are published on function 0 device only?
1023  *
1024  *
1025  * rxdma-cfg, txdma-cfg, rxdma-grp-cfg (required )
1026  * What about class configs?
1027  *
1028  * If consistent, update the property on all the siblings.
1029  * set  a flag on hardware shared register
1030  * The rest of the siblings will check the flag
1031  * if the flag is set, they will use the updated property
1032  * without doing any validation.
1033  */
1034 
1035 nxge_status_t
1036 nxge_cfg_verify_set_classify_prop(p_nxge_t nxgep, char *prop,
1037 	uint64_t known_cfg, uint32_t override, dev_info_t *c_dip[])
1038 {
1039 	nxge_status_t status = NXGE_OK;
1040 	int ddi_status = DDI_SUCCESS;
1041 	int i = 0, found = 0, update_prop = B_TRUE;
1042 	int *cfg_val;
1043 	uint_t new_value, cfg_value[MAX_SIBLINGS];
1044 	uint_t prop_len;
1045 	uint_t known_cfg_value;
1046 
1047 	known_cfg_value = (uint_t)known_cfg;
1048 
1049 	if (override == B_TRUE) {
1050 		new_value = known_cfg_value;
1051 		for (i = 0; i < nxgep->nports; i++) {
1052 			ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE,
1053 			    c_dip[i], prop, new_value);
1054 #ifdef NXGE_DEBUG_ERROR
1055 			if (ddi_status != DDI_PROP_SUCCESS)
1056 				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1057 				    " property %s failed update ", prop));
1058 #endif
1059 		}
1060 		if (ddi_status != DDI_PROP_SUCCESS)
1061 			return (NXGE_ERROR | NXGE_DDI_FAILED);
1062 	}
1063 	for (i = 0; i < nxgep->nports; i++) {
1064 		cfg_value[i] = known_cfg_value;
1065 		if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, c_dip[i], 0,
1066 		    prop, &cfg_val,
1067 		    &prop_len) == DDI_PROP_SUCCESS) {
1068 			cfg_value[i] = *cfg_val;
1069 			ddi_prop_free(cfg_val);
1070 			found++;
1071 		}
1072 	}
1073 
1074 	if (found != i) {
1075 		NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1076 		    " property %s not specified on all ports", prop));
1077 		if (found == 0) {
1078 			/* not specified: Use default */
1079 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1080 			    " property %s not specified on any port:"
1081 			    " Using default", prop));
1082 			new_value = known_cfg_value;
1083 		} else {
1084 			/* specified on some */
1085 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1086 			    " property %s not specified"
1087 			    " on some ports: Using default", prop));
1088 			/* ? use p0 value instead ? */
1089 			new_value = known_cfg_value;
1090 		}
1091 	} else {
1092 		/* check type and consistence */
1093 		/* found on all devices */
1094 		for (i = 1; i < found; i++) {
1095 			if (cfg_value[i] != cfg_value[i - 1]) {
1096 				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1097 				    " property %s inconsistent:"
1098 				    " Using default", prop));
1099 				new_value = known_cfg_value;
1100 				break;
1101 			}
1102 			/*
1103 			 * Found on all the ports and consistent. Nothing to
1104 			 * do.
1105 			 */
1106 			update_prop = B_FALSE;
1107 		}
1108 	}
1109 
1110 	if (update_prop == B_TRUE) {
1111 		for (i = 0; i < nxgep->nports; i++) {
1112 			ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE,
1113 			    c_dip[i], prop, new_value);
1114 #ifdef NXGE_DEBUG_ERROR
1115 			if (ddi_status != DDI_SUCCESS)
1116 				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1117 				    " property %s not updating with %d"
1118 				    " Using default",
1119 				    prop, new_value));
1120 #endif
1121 			if (ddi_status != DDI_PROP_SUCCESS)
1122 				status |= NXGE_DDI_FAILED;
1123 		}
1124 	}
1125 	if (status & NXGE_DDI_FAILED)
1126 		status |= NXGE_ERROR;
1127 
1128 	return (status);
1129 }
1130 
1131 static uint64_t
1132 nxge_class_get_known_cfg(p_nxge_t nxgep, int class_prop, int rx_quick_cfg)
1133 {
1134 	int start_prop;
1135 	uint64_t cfg_value;
1136 	p_nxge_param_t param_arr;
1137 
1138 	param_arr = nxgep->param_arr;
1139 	cfg_value = param_arr[class_prop].value;
1140 	start_prop = param_h1_init_value;
1141 
1142 	/* update the properties per quick config */
1143 	switch (rx_quick_cfg) {
1144 	case CFG_L3_WEB:
1145 	case CFG_L3_DISTRIBUTE:
1146 		cfg_value = nxge_classify_get_cfg_value(nxgep,
1147 		    rx_quick_cfg, class_prop - start_prop);
1148 		break;
1149 	default:
1150 		cfg_value = param_arr[class_prop].value;
1151 		break;
1152 	}
1153 	return (cfg_value);
1154 }
1155 
1156 static nxge_status_t
1157 nxge_cfg_verify_set_classify(p_nxge_t nxgep, dev_info_t *c_dip[])
1158 {
1159 	nxge_status_t status = NXGE_OK;
1160 	int rx_quick_cfg, class_prop, start_prop, end_prop;
1161 	char *prop_name;
1162 	int override = B_TRUE;
1163 	uint64_t cfg_value;
1164 	p_nxge_param_t param_arr;
1165 
1166 	param_arr = nxgep->param_arr;
1167 	rx_quick_cfg = param_arr[param_rx_quick_cfg].value;
1168 	start_prop = param_h1_init_value;
1169 	end_prop = param_class_opt_ipv6_sctp;
1170 
1171 	/* update the properties per quick config */
1172 	if (rx_quick_cfg == CFG_NOT_SPECIFIED)
1173 		override = B_FALSE;
1174 
1175 	/*
1176 	 * these parameter affect the classification outcome.
1177 	 * these parameters are used to configure the Flow key and
1178 	 * the TCAM key for each of the IP classes.
1179 	 * Included here are also the H1 and H2 initial values
1180 	 * which affect the distribution as well as final hash value
1181 	 * (hence the offset into RDC table and FCRAM bucket location)
1182 	 *
1183 	 */
1184 	for (class_prop = start_prop; class_prop <= end_prop; class_prop++) {
1185 		prop_name = param_arr[class_prop].fcode_name;
1186 		cfg_value = nxge_class_get_known_cfg(nxgep,
1187 		    class_prop, rx_quick_cfg);
1188 		status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name,
1189 		    cfg_value, override, c_dip);
1190 	}
1191 
1192 	/*
1193 	 * these properties do not affect the actual classification outcome.
1194 	 * used to enable/disable or tune the fflp hardware
1195 	 *
1196 	 * fcram_access_ratio, tcam_access_ratio, tcam_enable, llc_snap_enable
1197 	 *
1198 	 */
1199 	override = B_FALSE;
1200 	for (class_prop = param_fcram_access_ratio;
1201 	    class_prop <= param_llc_snap_enable; class_prop++) {
1202 		prop_name = param_arr[class_prop].fcode_name;
1203 		cfg_value = param_arr[class_prop].value;
1204 		status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name,
1205 		    cfg_value, override, c_dip);
1206 	}
1207 
1208 	return (status);
1209 }
1210 
1211 nxge_status_t
1212 nxge_cfg_verify_set(p_nxge_t nxgep, uint32_t flag)
1213 {
1214 	nxge_status_t status = NXGE_OK;
1215 	int i = 0, found = 0;
1216 	int num_siblings;
1217 	dev_info_t *c_dip[MAX_SIBLINGS + 1];
1218 	char *prop_val[MAX_SIBLINGS];
1219 	config_token_t c_token[MAX_SIBLINGS];
1220 	char *prop;
1221 
1222 	if (nxge_dma_obp_props_only)
1223 		return (NXGE_OK);
1224 
1225 	num_siblings = 0;
1226 	c_dip[num_siblings] = ddi_get_child(nxgep->p_dip);
1227 	while (c_dip[num_siblings]) {
1228 		c_dip[num_siblings + 1] =
1229 		    ddi_get_next_sibling(c_dip[num_siblings]);
1230 		num_siblings++;
1231 	}
1232 
1233 	switch (flag) {
1234 	case COMMON_TXDMA_CFG:
1235 		prop = "txdma-cfg";
1236 		break;
1237 	case COMMON_RXDMA_CFG:
1238 		prop = "rxdma-cfg";
1239 		break;
1240 	case COMMON_RXDMA_GRP_CFG:
1241 		prop = "rxdma-grp-cfg";
1242 		break;
1243 	case COMMON_CLASS_CFG:
1244 		status = nxge_cfg_verify_set_classify(nxgep, c_dip);
1245 		return (status);
1246 	default:
1247 		return (NXGE_ERROR);
1248 	}
1249 
1250 	i = 0;
1251 	while (i < num_siblings) {
1252 		if (ddi_prop_lookup_string(DDI_DEV_T_ANY, c_dip[i], 0, prop,
1253 		    (char **)&prop_val[i]) == DDI_PROP_SUCCESS) {
1254 			c_token[i] = nxge_get_config_token(prop_val[i]);
1255 			ddi_prop_free(prop_val[i]);
1256 			found++;
1257 		} else
1258 			c_token[i] = CONFIG_TOKEN_NONE;
1259 		i++;
1260 	}
1261 
1262 	if (found != i) {
1263 		if (found == 0) {
1264 			/* not specified: Use default */
1265 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1266 			    " property %s not specified on any port:"
1267 			    " Using default", prop));
1268 
1269 			status = nxge_update_cfg_properties(nxgep,
1270 			    flag, FAIR, c_dip);
1271 			return (status);
1272 		} else {
1273 			/*
1274 			 * if  the convention is to use function 0 device then
1275 			 * populate the other devices with this configuration.
1276 			 *
1277 			 * The other alternative is to use the default config.
1278 			 */
1279 			/* not specified: Use default */
1280 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1281 			    " property %s not specified on some ports:"
1282 			    " Using default", prop));
1283 			status = nxge_update_cfg_properties(nxgep,
1284 			    flag, FAIR, c_dip);
1285 			return (status);
1286 		}
1287 	}
1288 
1289 	/* check type and consistence */
1290 	/* found on all devices */
1291 	for (i = 1; i < found; i++) {
1292 		if (c_token[i] != c_token[i - 1]) {
1293 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1294 			    " property %s inconsistent:"
1295 			    " Using default", prop));
1296 			status = nxge_update_cfg_properties(nxgep,
1297 			    flag, FAIR, c_dip);
1298 			return (status);
1299 		}
1300 	}
1301 
1302 	/*
1303 	 * Found on all the ports check if it is custom configuration. if
1304 	 * custom, then verify consistence
1305 	 *
1306 	 * finally create soft properties
1307 	 */
1308 	status = nxge_update_cfg_properties(nxgep, flag, c_token[0], c_dip);
1309 	return (status);
1310 }
1311 
1312 nxge_status_t
1313 nxge_cfg_verify_set_quick_config(p_nxge_t nxgep)
1314 {
1315 	nxge_status_t status = NXGE_OK;
1316 	int ddi_status = DDI_SUCCESS;
1317 	char *prop_val;
1318 	char *rx_prop;
1319 	char *prop;
1320 	uint32_t cfg_value = CFG_NOT_SPECIFIED;
1321 	p_nxge_param_t param_arr;
1322 
1323 	param_arr = nxgep->param_arr;
1324 	rx_prop = param_arr[param_rx_quick_cfg].fcode_name;
1325 
1326 	prop = "rx-quick-cfg";
1327 
1328 	/*
1329 	 * good value are
1330 	 *
1331 	 * "web-server" "generic-server" "l3-classify" "flow-classify"
1332 	 */
1333 	if (ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 0,
1334 	    prop, (char **)&prop_val) != DDI_PROP_SUCCESS) {
1335 		NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1336 		    " property %s not specified: using default ", prop));
1337 		cfg_value = CFG_NOT_SPECIFIED;
1338 	} else {
1339 		cfg_value = CFG_L3_DISTRIBUTE;
1340 		if (strncmp("web-server", (caddr_t)prop_val, 8) == 0) {
1341 			cfg_value = CFG_L3_WEB;
1342 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1343 			    " %s: web server ", prop));
1344 		}
1345 		if (strncmp("generic-server", (caddr_t)prop_val, 8) == 0) {
1346 			cfg_value = CFG_L3_DISTRIBUTE;
1347 			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1348 			    " %s: distribute ", prop));
1349 		}
1350 		/* more */
1351 		ddi_prop_free(prop_val);
1352 	}
1353 
1354 	ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
1355 	    rx_prop, cfg_value);
1356 	if (ddi_status != DDI_PROP_SUCCESS)
1357 		status |= NXGE_DDI_FAILED;
1358 
1359 	/* now handle specified cases: */
1360 	if (status & NXGE_DDI_FAILED)
1361 		status |= NXGE_ERROR;
1362 	return (status);
1363 }
1364 
1365 /*
1366  * Device properties adv-autoneg-cap etc are defined by FWARC
1367  * http://sac.sfbay/FWARC/2002/345/20020610_asif.haswarey
1368  */
1369 static void
1370 nxge_use_cfg_link_cfg(p_nxge_t nxgep)
1371 {
1372 	int *prop_val;
1373 	uint_t prop_len;
1374 	dev_info_t *dip;
1375 	int speed;
1376 	int duplex;
1377 	int adv_autoneg_cap;
1378 	int adv_10gfdx_cap;
1379 	int adv_10ghdx_cap;
1380 	int adv_1000fdx_cap;
1381 	int adv_1000hdx_cap;
1382 	int adv_100fdx_cap;
1383 	int adv_100hdx_cap;
1384 	int adv_10fdx_cap;
1385 	int adv_10hdx_cap;
1386 	int status = DDI_SUCCESS;
1387 
1388 	dip = nxgep->dip;
1389 
1390 	/*
1391 	 * first find out the card type and the supported link speeds and
1392 	 * features
1393 	 */
1394 	/* add code for card type */
1395 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-autoneg-cap",
1396 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1397 		ddi_prop_free(prop_val);
1398 		return;
1399 	}
1400 
1401 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10gfdx-cap",
1402 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1403 		ddi_prop_free(prop_val);
1404 		return;
1405 	}
1406 
1407 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000hdx-cap",
1408 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1409 		ddi_prop_free(prop_val);
1410 		return;
1411 	}
1412 
1413 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000fdx-cap",
1414 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1415 		ddi_prop_free(prop_val);
1416 		return;
1417 	}
1418 
1419 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100fdx-cap",
1420 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1421 		ddi_prop_free(prop_val);
1422 		return;
1423 	}
1424 
1425 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100hdx-cap",
1426 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1427 		ddi_prop_free(prop_val);
1428 		return;
1429 	}
1430 
1431 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10fdx-cap",
1432 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1433 		ddi_prop_free(prop_val);
1434 		return;
1435 	}
1436 
1437 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10hdx-cap",
1438 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1439 		ddi_prop_free(prop_val);
1440 		return;
1441 	}
1442 
1443 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "speed",
1444 	    (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1445 		if (strncmp("10000", (caddr_t)prop_val,
1446 		    (size_t)prop_len) == 0) {
1447 			speed = 10000;
1448 		} else if (strncmp("1000", (caddr_t)prop_val,
1449 		    (size_t)prop_len) == 0) {
1450 			speed = 1000;
1451 		} else if (strncmp("100", (caddr_t)prop_val,
1452 		    (size_t)prop_len) == 0) {
1453 			speed = 100;
1454 		} else if (strncmp("10", (caddr_t)prop_val,
1455 		    (size_t)prop_len) == 0) {
1456 			speed = 10;
1457 		} else if (strncmp("auto", (caddr_t)prop_val,
1458 		    (size_t)prop_len) == 0) {
1459 			speed = 0;
1460 		} else {
1461 			NXGE_ERROR_MSG((nxgep, NXGE_NOTE,
1462 			    "speed property is invalid reverting to auto"));
1463 			speed = 0;
1464 		}
1465 		ddi_prop_free(prop_val);
1466 	} else
1467 		speed = 0;
1468 
1469 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "duplex",
1470 	    (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1471 		if (strncmp("full", (caddr_t)prop_val,
1472 		    (size_t)prop_len) == 0) {
1473 			duplex = 2;
1474 		} else if (strncmp("half", (caddr_t)prop_val,
1475 		    (size_t)prop_len) == 0) {
1476 			duplex = 1;
1477 		} else if (strncmp("auto", (caddr_t)prop_val,
1478 		    (size_t)prop_len) == 0) {
1479 			duplex = 0;
1480 		} else {
1481 			NXGE_ERROR_MSG((nxgep, NXGE_NOTE,
1482 			    "duplex property is invalid"
1483 			    " reverting to auto"));
1484 			duplex = 0;
1485 		}
1486 		ddi_prop_free(prop_val);
1487 	} else
1488 		duplex = 0;
1489 
1490 	/* speed == 0 or duplex == 0 means auto negotiation. */
1491 	adv_autoneg_cap = (speed == 0) || (duplex == 0);
1492 	if (adv_autoneg_cap == 0) {
1493 		adv_10gfdx_cap = ((speed == 10000) && (duplex == 2));
1494 		adv_10ghdx_cap = adv_10gfdx_cap;
1495 		adv_10ghdx_cap |= ((speed == 10000) && (duplex == 1));
1496 		adv_1000fdx_cap = adv_10ghdx_cap;
1497 		adv_1000fdx_cap |= ((speed == 1000) && (duplex == 2));
1498 		adv_1000hdx_cap = adv_1000fdx_cap;
1499 		adv_1000hdx_cap |= ((speed == 1000) && (duplex == 1));
1500 		adv_100fdx_cap = adv_1000hdx_cap;
1501 		adv_100fdx_cap |= ((speed == 100) && (duplex == 2));
1502 		adv_100hdx_cap = adv_100fdx_cap;
1503 		adv_100hdx_cap |= ((speed == 100) && (duplex == 1));
1504 		adv_10fdx_cap = adv_100hdx_cap;
1505 		adv_10fdx_cap |= ((speed == 10) && (duplex == 2));
1506 		adv_10hdx_cap = adv_10fdx_cap;
1507 		adv_10hdx_cap |= ((speed == 10) && (duplex == 1));
1508 	} else if (speed == 0) {
1509 		adv_10gfdx_cap = (duplex == 2);
1510 		adv_10ghdx_cap = (duplex == 1);
1511 		adv_1000fdx_cap = (duplex == 2);
1512 		adv_1000hdx_cap = (duplex == 1);
1513 		adv_100fdx_cap = (duplex == 2);
1514 		adv_100hdx_cap = (duplex == 1);
1515 		adv_10fdx_cap = (duplex == 2);
1516 		adv_10hdx_cap = (duplex == 1);
1517 	}
1518 	if (duplex == 0) {
1519 		adv_10gfdx_cap = (speed == 0);
1520 		adv_10gfdx_cap |= (speed == 10000);
1521 		adv_10ghdx_cap = adv_10gfdx_cap;
1522 		adv_10ghdx_cap |= (speed == 10000);
1523 		adv_1000fdx_cap = adv_10ghdx_cap;
1524 		adv_1000fdx_cap |= (speed == 1000);
1525 		adv_1000hdx_cap = adv_1000fdx_cap;
1526 		adv_1000hdx_cap |= (speed == 1000);
1527 		adv_100fdx_cap = adv_1000hdx_cap;
1528 		adv_100fdx_cap |= (speed == 100);
1529 		adv_100hdx_cap = adv_100fdx_cap;
1530 		adv_100hdx_cap |= (speed == 100);
1531 		adv_10fdx_cap = adv_100hdx_cap;
1532 		adv_10fdx_cap |= (speed == 10);
1533 		adv_10hdx_cap = adv_10fdx_cap;
1534 		adv_10hdx_cap |= (speed == 10);
1535 	}
1536 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1537 	    "adv-autoneg-cap", &adv_autoneg_cap, 1);
1538 	if (status)
1539 		return;
1540 
1541 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1542 	    "adv-10gfdx-cap", &adv_10gfdx_cap, 1);
1543 	if (status)
1544 		goto nxge_map_myargs_to_gmii_fail1;
1545 
1546 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1547 	    "adv-10ghdx-cap", &adv_10ghdx_cap, 1);
1548 	if (status)
1549 		goto nxge_map_myargs_to_gmii_fail2;
1550 
1551 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1552 	    "adv-1000fdx-cap", &adv_1000fdx_cap, 1);
1553 	if (status)
1554 		goto nxge_map_myargs_to_gmii_fail3;
1555 
1556 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1557 	    "adv-1000hdx-cap", &adv_1000hdx_cap, 1);
1558 	if (status)
1559 		goto nxge_map_myargs_to_gmii_fail4;
1560 
1561 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1562 	    "adv-100fdx-cap", &adv_100fdx_cap, 1);
1563 	if (status)
1564 		goto nxge_map_myargs_to_gmii_fail5;
1565 
1566 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1567 	    "adv-100hdx-cap", &adv_100hdx_cap, 1);
1568 	if (status)
1569 		goto nxge_map_myargs_to_gmii_fail6;
1570 
1571 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1572 	    "adv-10fdx-cap", &adv_10fdx_cap, 1);
1573 	if (status)
1574 		goto nxge_map_myargs_to_gmii_fail7;
1575 
1576 	status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1577 	    "adv-10hdx-cap", &adv_10hdx_cap, 1);
1578 	if (status)
1579 		goto nxge_map_myargs_to_gmii_fail8;
1580 
1581 	return;
1582 
1583 nxge_map_myargs_to_gmii_fail9:
1584 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10hdx-cap");
1585 
1586 nxge_map_myargs_to_gmii_fail8:
1587 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10fdx-cap");
1588 
1589 nxge_map_myargs_to_gmii_fail7:
1590 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100hdx-cap");
1591 
1592 nxge_map_myargs_to_gmii_fail6:
1593 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100fdx-cap");
1594 
1595 nxge_map_myargs_to_gmii_fail5:
1596 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000hdx-cap");
1597 
1598 nxge_map_myargs_to_gmii_fail4:
1599 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000fdx-cap");
1600 
1601 nxge_map_myargs_to_gmii_fail3:
1602 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10ghdx-cap");
1603 
1604 nxge_map_myargs_to_gmii_fail2:
1605 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10gfdx-cap");
1606 
1607 nxge_map_myargs_to_gmii_fail1:
1608 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-autoneg-cap");
1609 }
1610 
1611 nxge_status_t
1612 nxge_get_config_properties(p_nxge_t nxgep)
1613 {
1614 	nxge_status_t status = NXGE_OK;
1615 	p_nxge_hw_list_t hw_p;
1616 
1617 	NXGE_DEBUG_MSG((nxgep, VPD_CTL, " ==> nxge_get_config_properties"));
1618 
1619 	if ((hw_p = nxgep->nxge_hw_p) == NULL) {
1620 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1621 		    " nxge_get_config_properties:"
1622 		    " common hardware not set", nxgep->niu_type));
1623 		return (NXGE_ERROR);
1624 	}
1625 
1626 	/*
1627 	 * Get info on how many ports Neptune card has.
1628 	 */
1629 	nxgep->nports = nxge_get_nports(nxgep);
1630 	if (nxgep->nports <= 0) {
1631 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1632 		    "<==nxge_get_config_properties: Invalid Neptune type 0x%x",
1633 		    nxgep->niu_type));
1634 		return (NXGE_ERROR);
1635 	}
1636 	nxgep->classifier.tcam_size = TCAM_NIU_TCAM_MAX_ENTRY;
1637 	if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1638 		nxgep->classifier.tcam_size = TCAM_NXGE_TCAM_MAX_ENTRY;
1639 	}
1640 	if (nxgep->function_num >= nxgep->nports) {
1641 		return (NXGE_ERROR);
1642 	}
1643 
1644 	status = nxge_get_mac_addr_properties(nxgep);
1645 	if (status != NXGE_OK)
1646 		return (NXGE_ERROR);
1647 
1648 	/*
1649 	 * read the configuration type. If none is specified, used default.
1650 	 * Config types: equal: (default) DMA channels, RDC groups, TCAM, FCRAM
1651 	 * are shared equally across all the ports.
1652 	 *
1653 	 * Fair: DMA channels, RDC groups, TCAM, FCRAM are shared proportional
1654 	 * to the port speed.
1655 	 *
1656 	 *
1657 	 * custom: DMA channels, RDC groups, TCAM, FCRAM partition is
1658 	 * specified in nxge.conf. Need to read each parameter and set
1659 	 * up the parameters in nxge structures.
1660 	 *
1661 	 */
1662 	switch (nxgep->niu_type) {
1663 	case N2_NIU:
1664 		NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1665 		    " ==> nxge_get_config_properties: N2"));
1666 		MUTEX_ENTER(&hw_p->nxge_cfg_lock);
1667 		if ((hw_p->flags & COMMON_CFG_VALID) !=
1668 		    COMMON_CFG_VALID) {
1669 			status = nxge_cfg_verify_set(nxgep,
1670 			    COMMON_RXDMA_GRP_CFG);
1671 			status = nxge_cfg_verify_set(nxgep,
1672 			    COMMON_CLASS_CFG);
1673 			hw_p->flags |= COMMON_CFG_VALID;
1674 		}
1675 		MUTEX_EXIT(&hw_p->nxge_cfg_lock);
1676 		status = nxge_use_cfg_n2niu_properties(nxgep);
1677 		break;
1678 	default:
1679 		if (!NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1680 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1681 			    " nxge_get_config_properties:"
1682 			    " unknown NIU type 0x%x", nxgep->niu_type));
1683 			return (NXGE_ERROR);
1684 		}
1685 
1686 		NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1687 		    " ==> nxge_get_config_properties: Neptune"));
1688 		status = nxge_cfg_verify_set_quick_config(nxgep);
1689 		MUTEX_ENTER(&hw_p->nxge_cfg_lock);
1690 		if ((hw_p->flags & COMMON_CFG_VALID) !=
1691 		    COMMON_CFG_VALID) {
1692 			status = nxge_cfg_verify_set(nxgep,
1693 			    COMMON_TXDMA_CFG);
1694 			status = nxge_cfg_verify_set(nxgep,
1695 			    COMMON_RXDMA_CFG);
1696 			status = nxge_cfg_verify_set(nxgep,
1697 			    COMMON_RXDMA_GRP_CFG);
1698 			status = nxge_cfg_verify_set(nxgep,
1699 			    COMMON_CLASS_CFG);
1700 			hw_p->flags |= COMMON_CFG_VALID;
1701 		}
1702 		MUTEX_EXIT(&hw_p->nxge_cfg_lock);
1703 		nxge_use_cfg_neptune_properties(nxgep);
1704 		status = NXGE_OK;
1705 		break;
1706 	}
1707 
1708 	/*
1709 	 * Get the software LSO enable flag property from the
1710 	 * driver configuration file (nxge.conf).
1711 	 * This flag will be set to disable (0) if this property
1712 	 * does not exist.
1713 	 */
1714 	nxgep->soft_lso_enable = ddi_prop_get_int(DDI_DEV_T_ANY, nxgep->dip,
1715 	    DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, "soft-lso-enable", 0);
1716 	NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1717 	    "nxge_get_config_properties: software lso %d\n",
1718 	    nxgep->soft_lso_enable));
1719 
1720 	NXGE_DEBUG_MSG((nxgep, VPD_CTL, " <== nxge_get_config_properties"));
1721 	return (status);
1722 }
1723 
1724 static nxge_status_t
1725 nxge_use_cfg_n2niu_properties(p_nxge_t nxgep)
1726 {
1727 	nxge_status_t status = NXGE_OK;
1728 
1729 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_n2niu_properties"));
1730 
1731 	status = nxge_use_default_dma_config_n2(nxgep);
1732 	if (status != NXGE_OK) {
1733 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1734 		    " ==> nxge_use_cfg_n2niu_properties (err 0x%x)",
1735 		    status));
1736 		return (status | NXGE_ERROR);
1737 	}
1738 
1739 	(void) nxge_use_cfg_vlan_class_config(nxgep);
1740 	(void) nxge_use_cfg_mac_class_config(nxgep);
1741 	(void) nxge_use_cfg_class_config(nxgep);
1742 	(void) nxge_use_cfg_link_cfg(nxgep);
1743 
1744 	/*
1745 	 * Read in the hardware (fcode) properties. Use the ndd array to read
1746 	 * each property.
1747 	 */
1748 	(void) nxge_get_param_soft_properties(nxgep);
1749 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_n2niu_properties"));
1750 
1751 	return (status);
1752 }
1753 
1754 static void
1755 nxge_use_cfg_neptune_properties(p_nxge_t nxgep)
1756 {
1757 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_neptune_properties"));
1758 
1759 	(void) nxge_use_cfg_dma_config(nxgep);
1760 	(void) nxge_use_cfg_vlan_class_config(nxgep);
1761 	(void) nxge_use_cfg_mac_class_config(nxgep);
1762 	(void) nxge_use_cfg_class_config(nxgep);
1763 	(void) nxge_use_cfg_link_cfg(nxgep);
1764 
1765 	/*
1766 	 * Read in the hardware (fcode) properties. Use the ndd array to read
1767 	 * each property.
1768 	 */
1769 	(void) nxge_get_param_soft_properties(nxgep);
1770 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_neptune_properties"));
1771 }
1772 
1773 /*
1774  * FWARC 2006/556 for N2 NIU.  Get the properties
1775  * from the prom.
1776  */
1777 static nxge_status_t
1778 nxge_use_default_dma_config_n2(p_nxge_t nxgep)
1779 {
1780 	int			ndmas;
1781 	uint8_t			func;
1782 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
1783 	p_nxge_hw_pt_cfg_t	p_cfgp;
1784 	int			*prop_val;
1785 	uint_t			prop_len;
1786 	int			i;
1787 	nxge_status_t		status = NXGE_OK;
1788 
1789 	NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2"));
1790 
1791 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1792 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1793 
1794 	func = nxgep->function_num;
1795 	p_cfgp->function_number = func;
1796 	ndmas = NXGE_TDMA_PER_NIU_PORT;
1797 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1798 	    "tx-dma-channels", (int **)&prop_val,
1799 	    &prop_len) == DDI_PROP_SUCCESS) {
1800 		if (prop_len != NXGE_NIU_TDMA_PROP_LEN) {
1801 			ddi_prop_free(prop_val);
1802 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1803 			    "==> nxge_use_default_dma_config_n2: "
1804 			    "invalid tx-dma-channels property for the NIU, "
1805 			    "using defaults"));
1806 			/*
1807 			 * Just failover to defaults
1808 			 */
1809 			p_cfgp->tdc.start = (func * NXGE_TDMA_PER_NIU_PORT);
1810 			ndmas = NXGE_TDMA_PER_NIU_PORT;
1811 		} else {
1812 			p_cfgp->tdc.start = prop_val[0];
1813 			NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1814 			    "==> nxge_use_default_dma_config_n2: tdc starts %d "
1815 			    "(#%d)", p_cfgp->tdc.start, prop_len));
1816 
1817 			ndmas = prop_val[1];
1818 			NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1819 			    "==> nxge_use_default_dma_config_n2: #tdc %d (#%d)",
1820 			    ndmas, prop_len));
1821 			ddi_prop_free(prop_val);
1822 		}
1823 	} else {
1824 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1825 		    "==> nxge_use_default_dma_config_n2: "
1826 		    "get tx-dma-channels failed"));
1827 		return (NXGE_DDI_FAILED);
1828 	}
1829 
1830 	p_cfgp->tdc.count = ndmas;
1831 	p_cfgp->tdc.owned = p_cfgp->tdc.count;
1832 
1833 	NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: "
1834 	    "p_cfgp 0x%llx max_tdcs %d start %d",
1835 	    p_cfgp, p_cfgp->tdc.count, p_cfgp->tdc.start));
1836 
1837 	/* Receive DMA */
1838 	ndmas = NXGE_RDMA_PER_NIU_PORT;
1839 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1840 	    "rx-dma-channels", (int **)&prop_val,
1841 	    &prop_len) == DDI_PROP_SUCCESS) {
1842 		if (prop_len != NXGE_NIU_RDMA_PROP_LEN) {
1843 			ddi_prop_free(prop_val);
1844 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1845 			    "==> nxge_use_default_dma_config_n2: "
1846 			    "invalid rx-dma-channels property for the NIU, "
1847 			    "using defaults"));
1848 			/*
1849 			 * Just failover to defaults
1850 			 */
1851 			p_cfgp->start_rdc = (func * NXGE_RDMA_PER_NIU_PORT);
1852 			ndmas = NXGE_RDMA_PER_NIU_PORT;
1853 		} else {
1854 			p_cfgp->start_rdc = prop_val[0];
1855 			NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1856 			    "==> nxge_use_default_dma_config_n2(obp):"
1857 			    " rdc start %d (#%d)",
1858 			    p_cfgp->start_rdc, prop_len));
1859 			ndmas = prop_val[1];
1860 			NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1861 			    "==> nxge_use_default_dma_config_n2(obp): "
1862 			    "#rdc %d (#%d)", ndmas, prop_len));
1863 			ddi_prop_free(prop_val);
1864 		}
1865 	} else {
1866 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1867 		    "==> nxge_use_default_dma_config_n2: "
1868 		    "get rx-dma-channel failed"));
1869 		return (NXGE_DDI_FAILED);
1870 	}
1871 
1872 	p_cfgp->max_rdcs = ndmas;
1873 	nxgep->rdc_mask = (ndmas - 1);
1874 
1875 	/* Hypervisor: rdc # and group # use the same # !! */
1876 	p_cfgp->max_grpids = p_cfgp->max_rdcs + p_cfgp->tdc.owned;
1877 	p_cfgp->mif_ldvid = p_cfgp->mac_ldvid = p_cfgp->ser_ldvid = 0;
1878 
1879 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1880 	    "interrupts", (int **)&prop_val,
1881 	    &prop_len) == DDI_PROP_SUCCESS) {
1882 		if ((prop_len != NXGE_NIU_0_INTR_PROP_LEN) &&
1883 		    (prop_len != NXGE_NIU_1_INTR_PROP_LEN)) {
1884 			ddi_prop_free(prop_val);
1885 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1886 			    "==> nxge_use_default_dma_config_n2: "
1887 			    "get interrupts failed"));
1888 			return (NXGE_DDI_FAILED);
1889 		}
1890 
1891 		/*
1892 		 * For each device assigned, the content of each interrupts
1893 		 * property is its logical device group.
1894 		 *
1895 		 * Assignment of interrupts property is in the the following
1896 		 * order:
1897 		 *
1898 		 * MAC MIF (if configured) SYSTEM ERROR (if configured) first
1899 		 * receive channel next channel...... last receive channel
1900 		 * first transmit channel next channel...... last transmit
1901 		 * channel
1902 		 *
1903 		 * prop_len should be at least for one mac and total # of rx and
1904 		 * tx channels. Function 0 owns MIF and ERROR
1905 		 */
1906 		NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1907 		    "==> nxge_use_default_dma_config_n2(obp): "
1908 		    "# interrupts %d", prop_len));
1909 
1910 		switch (func) {
1911 		case 0:
1912 			p_cfgp->ldg_chn_start = 3;
1913 			p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT0;
1914 			p_cfgp->mif_ldvid = NXGE_MIF_LD;
1915 			p_cfgp->ser_ldvid = NXGE_SYS_ERROR_LD;
1916 
1917 			break;
1918 		case 1:
1919 			p_cfgp->ldg_chn_start = 1;
1920 			p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT1;
1921 
1922 			break;
1923 		default:
1924 			status = NXGE_DDI_FAILED;
1925 			break;
1926 		}
1927 
1928 		if (status != NXGE_OK)
1929 			return (status);
1930 
1931 		for (i = 0; i < prop_len; i++) {
1932 			p_cfgp->ldg[i] = prop_val[i];
1933 			NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1934 			    "==> nxge_use_default_dma_config_n2(obp): "
1935 			    "F%d: interrupt #%d, ldg %d",
1936 			    nxgep->function_num, i, p_cfgp->ldg[i]));
1937 		}
1938 
1939 		p_cfgp->max_grpids = prop_len;
1940 		NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1941 		    "==> nxge_use_default_dma_config_n2(obp): %d "
1942 		    "(#%d) maxgrpids %d channel starts %d",
1943 		    p_cfgp->mac_ldvid, i, p_cfgp->max_grpids,
1944 		    p_cfgp->ldg_chn_start));
1945 		ddi_prop_free(prop_val);
1946 	} else {
1947 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1948 		    "==> nxge_use_default_dma_config_n2: "
1949 		    "get interrupts failed"));
1950 		return (NXGE_DDI_FAILED);
1951 	}
1952 
1953 	p_cfgp->max_ldgs = p_cfgp->max_grpids;
1954 	NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1955 	    "==> nxge_use_default_dma_config_n2: p_cfgp 0x%llx max_rdcs %d "
1956 	    "max_grpids %d macid %d mifid %d serrid %d",
1957 	    p_cfgp, p_cfgp->max_rdcs, p_cfgp->max_grpids,
1958 	    p_cfgp->mac_ldvid, p_cfgp->mif_ldvid, p_cfgp->ser_ldvid));
1959 
1960 
1961 	NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: "
1962 	    "p_cfgp p%p start_ldg %d nxgep->max_ldgs %d",
1963 	    p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs));
1964 
1965 	/*
1966 	 * RDC groups and the beginning RDC group assigned to this function.
1967 	 */
1968 	p_cfgp->max_rdc_grpids = NXGE_MAX_RDC_GROUPS / nxgep->nports;
1969 	p_cfgp->def_mac_rxdma_grpid =
1970 	    nxgep->function_num * NXGE_MAX_RDC_GROUPS / nxgep->nports;
1971 	p_cfgp->def_mac_txdma_grpid =
1972 	    nxgep->function_num * NXGE_MAX_TDC_GROUPS / nxgep->nports;
1973 
1974 	if ((p_cfgp->def_mac_rxdma_grpid = nxge_fzc_rdc_tbl_bind(nxgep,
1975 	    p_cfgp->def_mac_rxdma_grpid, B_TRUE)) >= NXGE_MAX_RDC_GRPS) {
1976 		NXGE_ERROR_MSG((nxgep, CFG_CTL,
1977 		    "nxge_use_default_dma_config_n2(): "
1978 		    "nxge_fzc_rdc_tbl_bind failed"));
1979 		return (NXGE_DDI_FAILED);
1980 	}
1981 
1982 	status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
1983 	    "rx-rdc-grps", p_cfgp->max_rdc_grpids);
1984 	if (status) {
1985 		return (NXGE_DDI_FAILED);
1986 	}
1987 	status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
1988 	    "rx-rdc-grps-begin", p_cfgp->def_mac_rxdma_grpid);
1989 	if (status) {
1990 		(void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip,
1991 		    "rx-rdc-grps");
1992 		return (NXGE_DDI_FAILED);
1993 	}
1994 	NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: "
1995 	    "p_cfgp $%p # rdc groups %d start rdc group id %d",
1996 	    p_cfgp, p_cfgp->max_rdc_grpids,
1997 	    p_cfgp->def_mac_rxdma_grpid));
1998 
1999 	nxgep->intr_timeout = NXGE_RDC_RCR_TIMEOUT;
2000 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
2001 	    "rxdma-intr-time", (int **)&prop_val, &prop_len) ==
2002 	    DDI_PROP_SUCCESS) {
2003 		if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
2004 			nxgep->intr_timeout = prop_val[0];
2005 			(void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2006 			    nxgep->dip, "rxdma-intr-time", prop_val, prop_len);
2007 		}
2008 		ddi_prop_free(prop_val);
2009 	}
2010 
2011 	nxgep->intr_threshold = NXGE_RDC_RCR_THRESHOLD;
2012 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
2013 	    "rxdma-intr-pkts", (int **)&prop_val, &prop_len) ==
2014 	    DDI_PROP_SUCCESS) {
2015 		if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
2016 			nxgep->intr_threshold = prop_val[0];
2017 			(void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2018 			    nxgep->dip, "rxdma-intr-pkts", prop_val, prop_len);
2019 		}
2020 		ddi_prop_free(prop_val);
2021 	}
2022 
2023 	nxge_set_hw_dma_config(nxgep);
2024 	NXGE_DEBUG_MSG((nxgep, OBP_CTL, "<== nxge_use_default_dma_config_n2"));
2025 	return (status);
2026 }
2027 
2028 static void
2029 nxge_use_cfg_dma_config(p_nxge_t nxgep)
2030 {
2031 	int tx_ndmas, rx_ndmas, nrxgp, st_txdma, st_rxdma;
2032 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2033 	p_nxge_hw_pt_cfg_t p_cfgp;
2034 	dev_info_t *dip;
2035 	p_nxge_param_t param_arr;
2036 	char *prop;
2037 	int *prop_val;
2038 	uint_t prop_len;
2039 	int i;
2040 	uint8_t *ch_arr_p;
2041 
2042 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_dma_config"));
2043 	param_arr = nxgep->param_arr;
2044 
2045 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2046 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2047 	dip = nxgep->dip;
2048 	p_cfgp->function_number = nxgep->function_num;
2049 	prop = param_arr[param_txdma_channels_begin].fcode_name;
2050 
2051 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2052 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2053 		p_cfgp->tdc.start = *prop_val;
2054 		ddi_prop_free(prop_val);
2055 	} else {
2056 		switch (nxgep->niu_type) {
2057 		case NEPTUNE_4_1GC:
2058 			ch_arr_p = &tx_4_1G[0];
2059 			break;
2060 		case NEPTUNE_2_10GF:
2061 			ch_arr_p = &tx_2_10G[0];
2062 			break;
2063 		case NEPTUNE_2_10GF_2_1GC:
2064 		case NEPTUNE_2_10GF_2_1GRF:
2065 			ch_arr_p = &tx_2_10G_2_1G[0];
2066 			break;
2067 		case NEPTUNE_1_10GF_3_1GC:
2068 			ch_arr_p = &tx_1_10G_3_1G[0];
2069 			break;
2070 		case NEPTUNE_1_1GC_1_10GF_2_1GC:
2071 			ch_arr_p = &tx_1_1G_1_10G_2_1G[0];
2072 			break;
2073 		default:
2074 			switch (nxgep->platform_type) {
2075 			case P_NEPTUNE_ALONSO:
2076 				ch_arr_p = &tx_2_10G_2_1G[0];
2077 				break;
2078 			default:
2079 				ch_arr_p = &p4_tx_equal[0];
2080 				break;
2081 			}
2082 			break;
2083 		}
2084 		st_txdma = 0;
2085 		for (i = 0; i < nxgep->function_num; i++, ch_arr_p++)
2086 			st_txdma += *ch_arr_p;
2087 
2088 		(void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2089 		    prop, st_txdma);
2090 		p_cfgp->tdc.start = st_txdma;
2091 	}
2092 
2093 	prop = param_arr[param_txdma_channels].fcode_name;
2094 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2095 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2096 		tx_ndmas = *prop_val;
2097 		ddi_prop_free(prop_val);
2098 	} else {
2099 		switch (nxgep->niu_type) {
2100 		case NEPTUNE_4_1GC:
2101 			tx_ndmas = tx_4_1G[nxgep->function_num];
2102 			break;
2103 		case NEPTUNE_2_10GF:
2104 			tx_ndmas = tx_2_10G[nxgep->function_num];
2105 			break;
2106 		case NEPTUNE_2_10GF_2_1GC:
2107 		case NEPTUNE_2_10GF_2_1GRF:
2108 			tx_ndmas = tx_2_10G_2_1G[nxgep->function_num];
2109 			break;
2110 		case NEPTUNE_1_10GF_3_1GC:
2111 			tx_ndmas = tx_1_10G_3_1G[nxgep->function_num];
2112 			break;
2113 		case NEPTUNE_1_1GC_1_10GF_2_1GC:
2114 			tx_ndmas = tx_1_1G_1_10G_2_1G[nxgep->function_num];
2115 			break;
2116 		default:
2117 			switch (nxgep->platform_type) {
2118 			case P_NEPTUNE_ALONSO:
2119 				tx_ndmas = tx_2_10G_2_1G[nxgep->function_num];
2120 				break;
2121 			default:
2122 				tx_ndmas = p4_tx_equal[nxgep->function_num];
2123 				break;
2124 			}
2125 			break;
2126 		}
2127 		(void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2128 		    prop, tx_ndmas);
2129 	}
2130 
2131 	p_cfgp->tdc.count = tx_ndmas;
2132 	p_cfgp->tdc.owned = p_cfgp->tdc.count;
2133 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: "
2134 	    "p_cfgp 0x%llx max_tdcs %d", p_cfgp, p_cfgp->tdc.count));
2135 
2136 	prop = param_arr[param_rxdma_channels_begin].fcode_name;
2137 
2138 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2139 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2140 		p_cfgp->start_rdc = *prop_val;
2141 		ddi_prop_free(prop_val);
2142 	} else {
2143 		switch (nxgep->niu_type) {
2144 		case NEPTUNE_4_1GC:
2145 			ch_arr_p = &rx_4_1G[0];
2146 			break;
2147 		case NEPTUNE_2_10GF:
2148 			ch_arr_p = &rx_2_10G[0];
2149 			break;
2150 		case NEPTUNE_2_10GF_2_1GC:
2151 		case NEPTUNE_2_10GF_2_1GRF:
2152 			ch_arr_p = &rx_2_10G_2_1G[0];
2153 			break;
2154 		case NEPTUNE_1_10GF_3_1GC:
2155 			ch_arr_p = &rx_1_10G_3_1G[0];
2156 			break;
2157 		case NEPTUNE_1_1GC_1_10GF_2_1GC:
2158 			ch_arr_p = &rx_1_1G_1_10G_2_1G[0];
2159 			break;
2160 		default:
2161 			switch (nxgep->platform_type) {
2162 			case P_NEPTUNE_ALONSO:
2163 				ch_arr_p = &rx_2_10G_2_1G[0];
2164 				break;
2165 			default:
2166 				ch_arr_p = &p4_rx_equal[0];
2167 				break;
2168 			}
2169 			break;
2170 		}
2171 		st_rxdma = 0;
2172 		for (i = 0; i < nxgep->function_num; i++, ch_arr_p++)
2173 			st_rxdma += *ch_arr_p;
2174 
2175 		(void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2176 		    prop, st_rxdma);
2177 		p_cfgp->start_rdc = st_rxdma;
2178 	}
2179 
2180 	prop = param_arr[param_rxdma_channels].fcode_name;
2181 
2182 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2183 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2184 		rx_ndmas = *prop_val;
2185 		ddi_prop_free(prop_val);
2186 	} else {
2187 		switch (nxgep->niu_type) {
2188 		case NEPTUNE_4_1GC:
2189 			rx_ndmas = rx_4_1G[nxgep->function_num];
2190 			break;
2191 		case NEPTUNE_2_10GF:
2192 			rx_ndmas = rx_2_10G[nxgep->function_num];
2193 			break;
2194 		case NEPTUNE_2_10GF_2_1GC:
2195 		case NEPTUNE_2_10GF_2_1GRF:
2196 			rx_ndmas = rx_2_10G_2_1G[nxgep->function_num];
2197 			break;
2198 		case NEPTUNE_1_10GF_3_1GC:
2199 			rx_ndmas = rx_1_10G_3_1G[nxgep->function_num];
2200 			break;
2201 		case NEPTUNE_1_1GC_1_10GF_2_1GC:
2202 			rx_ndmas = rx_1_1G_1_10G_2_1G[nxgep->function_num];
2203 			break;
2204 		default:
2205 			switch (nxgep->platform_type) {
2206 			case P_NEPTUNE_ALONSO:
2207 				rx_ndmas = rx_2_10G_2_1G[nxgep->function_num];
2208 				break;
2209 			default:
2210 				rx_ndmas = p4_rx_equal[nxgep->function_num];
2211 				break;
2212 			}
2213 			break;
2214 		}
2215 		(void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2216 		    prop, rx_ndmas);
2217 	}
2218 
2219 	p_cfgp->max_rdcs = rx_ndmas;
2220 
2221 	/*
2222 	 * RDC groups and the beginning RDC group assigned to this function.
2223 	 * XXX: this may be wrong if prop value is used.
2224 	 */
2225 	p_cfgp->def_mac_rxdma_grpid =
2226 	    nxgep->function_num * NXGE_MAX_RDC_GROUPS / nxgep->nports;
2227 	p_cfgp->def_mac_txdma_grpid =
2228 	    nxgep->function_num * NXGE_MAX_TDC_GROUPS / nxgep->nports;
2229 
2230 	if ((p_cfgp->def_mac_rxdma_grpid = nxge_fzc_rdc_tbl_bind(nxgep,
2231 	    p_cfgp->def_mac_rxdma_grpid, B_TRUE)) >= NXGE_MAX_RDC_GRPS) {
2232 		NXGE_ERROR_MSG((nxgep, CFG_CTL,
2233 		    "nxge_use_default_dma_config2(): "
2234 		    "nxge_fzc_rdc_tbl_bind failed"));
2235 		goto nxge_use_cfg_dma_config_exit;
2236 	}
2237 
2238 	prop = param_arr[param_rx_rdc_grps].fcode_name;
2239 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2240 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2241 		nrxgp = *prop_val;
2242 		ddi_prop_free(prop_val);
2243 	} else {
2244 		nrxgp = NXGE_MAX_RDC_GRPS / nxgep->nports;
2245 		(void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2246 		    prop, nrxgp);
2247 		NXGE_DEBUG_MSG((nxgep, CFG_CTL,
2248 		    "==> nxge_use_default_dma_config: "
2249 		    "num_rdc_grpid not found: use def:# of "
2250 		    "rdc groups %d\n", nrxgp));
2251 	}
2252 	p_cfgp->max_rdc_grpids = nrxgp;
2253 
2254 	/*
2255 	 * 2/4 ports have the same hard-wired logical groups assigned.
2256 	 */
2257 	p_cfgp->start_ldg = nxgep->function_num * NXGE_LDGRP_PER_4PORTS;
2258 	p_cfgp->max_ldgs = NXGE_LDGRP_PER_4PORTS;
2259 
2260 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_default_dma_config: "
2261 	    "p_cfgp 0x%llx max_rdcs %d max_grpids %d default_grpid %d",
2262 	    p_cfgp, p_cfgp->max_rdcs, p_cfgp->max_grpids,
2263 	    p_cfgp->def_mac_rxdma_grpid));
2264 
2265 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: "
2266 	    "p_cfgp 0x%016llx start_ldg %d nxgep->max_ldgs %d "
2267 	    "def_mac_rxdma_grpid %d",
2268 	    p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs,
2269 	    p_cfgp->def_mac_rxdma_grpid));
2270 
2271 	nxgep->intr_timeout = NXGE_RDC_RCR_TIMEOUT;
2272 	prop = param_arr[param_rxdma_intr_time].fcode_name;
2273 
2274 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2275 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2276 		if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
2277 			nxgep->intr_timeout = prop_val[0];
2278 			(void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2279 			    nxgep->dip, prop, prop_val, prop_len);
2280 		}
2281 		ddi_prop_free(prop_val);
2282 	}
2283 
2284 	nxgep->intr_threshold = NXGE_RDC_RCR_THRESHOLD;
2285 	prop = param_arr[param_rxdma_intr_pkts].fcode_name;
2286 
2287 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2288 	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2289 		if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
2290 			nxgep->intr_threshold = prop_val[0];
2291 			(void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2292 			    nxgep->dip, prop, prop_val, prop_len);
2293 		}
2294 		ddi_prop_free(prop_val);
2295 	}
2296 	nxge_set_hw_dma_config(nxgep);
2297 
2298 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config: "
2299 	    "sTDC[%d] nTDC[%d] sRDC[%d] nRDC[%d]",
2300 	    p_cfgp->tdc.start, p_cfgp->tdc.count,
2301 	    p_cfgp->start_rdc, p_cfgp->max_rdcs));
2302 
2303 nxge_use_cfg_dma_config_exit:
2304 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config"));
2305 }
2306 
2307 void
2308 nxge_get_logical_props(p_nxge_t nxgep)
2309 {
2310 	nxge_dma_pt_cfg_t *port = &nxgep->pt_config;
2311 	nxge_hw_pt_cfg_t *hardware;
2312 	nxge_rdc_grp_t *group;
2313 
2314 	(void) memset(port, 0, sizeof (*port));
2315 
2316 	port->mac_port = nxgep->function_num;	/* := function number */
2317 
2318 	/*
2319 	 * alloc_buf_size:
2320 	 * dead variables.
2321 	 */
2322 	port->rbr_size = nxge_rbr_size;
2323 	port->rcr_size = nxge_rcr_size;
2324 
2325 	port->tx_dma_map = 0;	/* Transmit DMA channel bit map */
2326 
2327 	nxge_set_rdc_intr_property(nxgep);
2328 
2329 	port->rcr_full_header = NXGE_RCR_FULL_HEADER;
2330 	port->rx_drr_weight = PT_DRR_WT_DEFAULT_10G;
2331 
2332 	/* ----------------------------------------------------- */
2333 	hardware = &port->hw_config;
2334 
2335 	(void) memset(hardware, 0, sizeof (*hardware));
2336 
2337 	/*
2338 	 * partition_id, read_write_mode:
2339 	 * dead variables.
2340 	 */
2341 
2342 	/*
2343 	 * drr_wt, rx_full_header, *_ldg?, start_mac_entry,
2344 	 * mac_pref, def_mac_rxdma_grpid, start_vlan, max_vlans,
2345 	 * start_ldgs, max_ldgs, max_ldvs,
2346 	 * vlan_pref, def_vlan_rxdma_grpid are meaningful only
2347 	 * in the service domain.
2348 	 */
2349 
2350 	group = &port->rdc_grps[0];
2351 
2352 	group->flag = B_TRUE;	/* configured */
2353 	group->config_method = RDC_TABLE_ENTRY_METHOD_REP;
2354 	group->port = NXGE_GET_PORT_NUM(nxgep->function_num);
2355 
2356 	/* HIO futures: this is still an open question. */
2357 	hardware->max_macs = 1;
2358 }
2359 
2360 static void
2361 nxge_use_cfg_vlan_class_config(p_nxge_t nxgep)
2362 {
2363 	uint_t vlan_cnt;
2364 	int *vlan_cfg_val;
2365 	int status;
2366 	p_nxge_param_t param_arr;
2367 	char *prop;
2368 
2369 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_vlan_config"));
2370 	param_arr = nxgep->param_arr;
2371 	prop = param_arr[param_vlan_2rdc_grp].fcode_name;
2372 
2373 	status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2374 	    &vlan_cfg_val, &vlan_cnt);
2375 	if (status == DDI_PROP_SUCCESS) {
2376 		status = ddi_prop_update_int_array(DDI_DEV_T_NONE,
2377 		    nxgep->dip, prop, vlan_cfg_val, vlan_cnt);
2378 		ddi_prop_free(vlan_cfg_val);
2379 	}
2380 	nxge_set_hw_vlan_class_config(nxgep);
2381 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_vlan_config"));
2382 }
2383 
2384 static void
2385 nxge_use_cfg_mac_class_config(p_nxge_t nxgep)
2386 {
2387 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2388 	p_nxge_hw_pt_cfg_t p_cfgp;
2389 	uint_t mac_cnt;
2390 	int *mac_cfg_val;
2391 	int status;
2392 	p_nxge_param_t param_arr;
2393 	char *prop;
2394 
2395 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_mac_class_config"));
2396 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2397 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2398 	p_cfgp->start_mac_entry = 0;
2399 	param_arr = nxgep->param_arr;
2400 	prop = param_arr[param_mac_2rdc_grp].fcode_name;
2401 
2402 	switch (nxgep->function_num) {
2403 	case 0:
2404 	case 1:
2405 		/* 10G ports */
2406 		p_cfgp->max_macs = NXGE_MAX_MACS_XMACS;
2407 		break;
2408 	case 2:
2409 	case 3:
2410 		/* 1G ports */
2411 	default:
2412 		p_cfgp->max_macs = NXGE_MAX_MACS_BMACS;
2413 		break;
2414 	}
2415 
2416 	p_cfgp->mac_pref = 1;
2417 	NXGE_DEBUG_MSG((nxgep, OBP_CTL,
2418 	    "== nxge_use_cfg_mac_class_config: "
2419 	    " mac_pref bit set def_mac_rxdma_grpid %d",
2420 	    p_cfgp->def_mac_rxdma_grpid));
2421 
2422 	status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2423 	    &mac_cfg_val, &mac_cnt);
2424 	if (status == DDI_PROP_SUCCESS) {
2425 		if (mac_cnt <= p_cfgp->max_macs)
2426 			status = ddi_prop_update_int_array(DDI_DEV_T_NONE,
2427 			    nxgep->dip, prop, mac_cfg_val, mac_cnt);
2428 		ddi_prop_free(mac_cfg_val);
2429 	}
2430 	nxge_set_hw_mac_class_config(nxgep);
2431 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_mac_class_config"));
2432 }
2433 
2434 static void
2435 nxge_use_cfg_class_config(p_nxge_t nxgep)
2436 {
2437 	nxge_set_hw_class_config(nxgep);
2438 }
2439 
2440 static void
2441 nxge_set_rdc_intr_property(p_nxge_t nxgep)
2442 {
2443 	int i;
2444 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2445 
2446 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_rdc_intr_property"));
2447 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2448 
2449 	for (i = 0; i < NXGE_MAX_RDCS; i++) {
2450 		p_dma_cfgp->rcr_timeout[i] = nxgep->intr_timeout;
2451 		p_dma_cfgp->rcr_threshold[i] = nxgep->intr_threshold;
2452 	}
2453 
2454 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_rdc_intr_property"));
2455 }
2456 
2457 static void
2458 nxge_set_hw_dma_config(p_nxge_t nxgep)
2459 {
2460 	int			i, j, ngrps, bitmap, end, st_rdc;
2461 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
2462 	p_nxge_hw_pt_cfg_t	p_cfgp;
2463 	p_nxge_rdc_grp_t	rdc_grp_p;
2464 	p_nxge_tdc_grp_t	tdc_grp_p;
2465 	nxge_grp_t		*group;
2466 	uint8_t			nrdcs;
2467 	dc_map_t		map = 0;
2468 
2469 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_dma_config"));
2470 
2471 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2472 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2473 
2474 	switch (nxgep->niu_type) {
2475 	case NEPTUNE_4_1GC:
2476 	case NEPTUNE_2_10GF_2_1GC:
2477 	case NEPTUNE_1_10GF_3_1GC:
2478 	case NEPTUNE_1_1GC_1_10GF_2_1GC:
2479 	case NEPTUNE_2_10GF_2_1GRF:
2480 	default:
2481 		ngrps = 2;
2482 		break;
2483 	case NEPTUNE_2_10GF:
2484 	case NEPTUNE_2_1GRF:
2485 	case N2_NIU:
2486 		ngrps = 4;
2487 		break;
2488 	}
2489 
2490 	/*
2491 	 * Setup TDC groups
2492 	 */
2493 	bitmap = 0;
2494 	end = p_cfgp->tdc.start + p_cfgp->tdc.owned;
2495 	for (i = p_cfgp->tdc.start; i < end; i++) {
2496 		bitmap |= (1 << i);
2497 	}
2498 
2499 	nxgep->tx_set.owned.map |= bitmap; /* Owned, & not shared. */
2500 	nxgep->tx_set.owned.count = p_cfgp->tdc.owned;
2501 	p_dma_cfgp->tx_dma_map = bitmap;
2502 
2503 	for (i = 0; i < ngrps; i++) {
2504 		group = (nxge_grp_t *)nxge_grp_add(nxgep,
2505 		    NXGE_TRANSMIT_GROUP);
2506 		tdc_grp_p = &p_dma_cfgp->tdc_grps[
2507 		    p_cfgp->def_mac_txdma_grpid + i];
2508 		if (i == 0)
2509 			tdc_grp_p->map = bitmap;
2510 		else
2511 			tdc_grp_p->map = 0;
2512 		/* no ring is associated with a group initially */
2513 		tdc_grp_p->start_tdc = 0;
2514 		tdc_grp_p->max_tdcs = 0;
2515 		tdc_grp_p->grp_index = group->index;
2516 	}
2517 
2518 	for (i = 0; i < NXGE_MAX_RDCS; i++) {
2519 		nxgep->rx_channel_started[i] = B_FALSE;
2520 	}
2521 
2522 	/*
2523 	 * Setup RDC groups
2524 	 */
2525 	st_rdc = p_cfgp->start_rdc;
2526 	for (i = 0; i < ngrps; i++) {
2527 		/*
2528 		 * All rings are associated with the default group initially
2529 		 */
2530 		if (i == 0) {
2531 			/* default group */
2532 			switch (nxgep->niu_type) {
2533 			case NEPTUNE_4_1GC:
2534 				nrdcs = rx_4_1G[nxgep->function_num];
2535 				break;
2536 			case N2_NIU:
2537 			case NEPTUNE_2_10GF:
2538 				nrdcs = rx_2_10G[nxgep->function_num];
2539 				break;
2540 			case NEPTUNE_2_10GF_2_1GC:
2541 				nrdcs = rx_2_10G_2_1G[nxgep->function_num];
2542 				break;
2543 			case NEPTUNE_1_10GF_3_1GC:
2544 				nrdcs = rx_1_10G_3_1G[nxgep->function_num];
2545 				break;
2546 			case NEPTUNE_1_1GC_1_10GF_2_1GC:
2547 				nrdcs = rx_1_1G_1_10G_2_1G[nxgep->function_num];
2548 				break;
2549 			default:
2550 				switch (nxgep->platform_type) {
2551 				case P_NEPTUNE_ALONSO:
2552 					nrdcs =
2553 					    rx_2_10G_2_1G[nxgep->function_num];
2554 					break;
2555 				default:
2556 					nrdcs = rx_4_1G[nxgep->function_num];
2557 					break;
2558 				}
2559 				break;
2560 			}
2561 
2562 			if (p_cfgp->max_rdcs < nrdcs)
2563 				nrdcs = p_cfgp->max_rdcs;
2564 		} else {
2565 			nrdcs = 0;
2566 		}
2567 
2568 		rdc_grp_p = &p_dma_cfgp->rdc_grps[
2569 		    p_cfgp->def_mac_rxdma_grpid + i];
2570 		rdc_grp_p->start_rdc = st_rdc;
2571 		rdc_grp_p->max_rdcs = nrdcs;
2572 		rdc_grp_p->def_rdc = rdc_grp_p->start_rdc;
2573 
2574 		/* default to: 0, 1, 2, 3, ...., 0, 1, 2, 3.... */
2575 		if (nrdcs != 0) {
2576 			for (j = 0; j < nrdcs; j++) {
2577 				map |= (1 << j);
2578 			}
2579 			map <<= rdc_grp_p->start_rdc;
2580 		} else
2581 			map = 0;
2582 		rdc_grp_p->map = map;
2583 
2584 		nxgep->rx_set.owned.map |= map; /* Owned, & not shared. */
2585 		nxgep->rx_set.owned.count = nrdcs;
2586 
2587 		group = (nxge_grp_t *)nxge_grp_add(nxgep, NXGE_RECEIVE_GROUP);
2588 
2589 		rdc_grp_p->config_method = RDC_TABLE_ENTRY_METHOD_SEQ;
2590 		rdc_grp_p->flag = B_TRUE; /* This group has been configured. */
2591 		rdc_grp_p->grp_index = group->index;
2592 		rdc_grp_p->port = NXGE_GET_PORT_NUM(nxgep->function_num);
2593 
2594 		map = 0;
2595 	}
2596 
2597 
2598 	/* default RDC */
2599 	p_cfgp->def_rdc = p_cfgp->start_rdc;
2600 	nxgep->def_rdc = p_cfgp->start_rdc;
2601 
2602 	/* full 18 byte header ? */
2603 	p_dma_cfgp->rcr_full_header = NXGE_RCR_FULL_HEADER;
2604 	p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_10G;
2605 	if (nxgep->function_num > 1)
2606 		p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_1G;
2607 	p_dma_cfgp->rbr_size = nxge_rbr_size;
2608 	p_dma_cfgp->rcr_size = nxge_rcr_size;
2609 
2610 	nxge_set_rdc_intr_property(nxgep);
2611 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_dma_config"));
2612 }
2613 
2614 boolean_t
2615 nxge_check_rxdma_port_member(p_nxge_t nxgep, uint8_t rdc)
2616 {
2617 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2618 	p_nxge_hw_pt_cfg_t p_cfgp;
2619 	int status = B_TRUE;
2620 
2621 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rxdma_port_member"));
2622 
2623 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2624 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2625 
2626 	/* Receive DMA Channels */
2627 	if (rdc < p_cfgp->max_rdcs)
2628 		status = B_TRUE;
2629 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rxdma_port_member"));
2630 	return (status);
2631 }
2632 
2633 boolean_t
2634 nxge_check_txdma_port_member(p_nxge_t nxgep, uint8_t tdc)
2635 {
2636 	int status = B_FALSE;
2637 
2638 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_txdma_port_member"));
2639 
2640 	if (tdc >= nxgep->pt_config.hw_config.tdc.start &&
2641 	    tdc < nxgep->pt_config.hw_config.tdc.count)
2642 		status = B_TRUE;
2643 
2644 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_txdma_port_member"));
2645 	return (status);
2646 }
2647 
2648 boolean_t
2649 nxge_check_rxdma_rdcgrp_member(p_nxge_t nxgep, uint8_t rdc_grp, uint8_t rdc)
2650 {
2651 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2652 	int status = B_TRUE;
2653 	p_nxge_rdc_grp_t rdc_grp_p;
2654 
2655 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2656 	    " ==> nxge_check_rxdma_rdcgrp_member"));
2657 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "  nxge_check_rxdma_rdcgrp_member"
2658 	    " rdc  %d group %d", rdc, rdc_grp));
2659 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2660 
2661 	rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp];
2662 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "  max  %d ", rdc_grp_p->max_rdcs));
2663 	if (rdc >= rdc_grp_p->max_rdcs) {
2664 		status = B_FALSE;
2665 	}
2666 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2667 	    " <== nxge_check_rxdma_rdcgrp_member"));
2668 	return (status);
2669 }
2670 
2671 boolean_t
2672 nxge_check_rdcgrp_port_member(p_nxge_t nxgep, uint8_t rdc_grp)
2673 {
2674 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2675 	p_nxge_hw_pt_cfg_t p_cfgp;
2676 	int status = B_TRUE;
2677 
2678 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rdcgrp_port_member"));
2679 
2680 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2681 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2682 
2683 	if (rdc_grp >= p_cfgp->max_rdc_grpids)
2684 		status = B_FALSE;
2685 	NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rdcgrp_port_member"));
2686 	return (status);
2687 }
2688 
2689 static void
2690 nxge_set_hw_vlan_class_config(p_nxge_t nxgep)
2691 {
2692 	int i;
2693 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2694 	p_nxge_hw_pt_cfg_t p_cfgp;
2695 	p_nxge_param_t param_arr;
2696 	uint_t vlan_cnt;
2697 	int *vlan_cfg_val;
2698 	nxge_param_map_t *vmap;
2699 	char *prop;
2700 	p_nxge_class_pt_cfg_t p_class_cfgp;
2701 	uint32_t good_cfg[32];
2702 	int good_count = 0;
2703 	nxge_mv_cfg_t *vlan_tbl;
2704 
2705 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_vlan_config"));
2706 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2707 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2708 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
2709 
2710 	param_arr = nxgep->param_arr;
2711 	prop = param_arr[param_vlan_2rdc_grp].fcode_name;
2712 
2713 	/*
2714 	 * By default, VLAN to RDC group mapping is disabled Need to read HW or
2715 	 * .conf properties to find out if mapping is required
2716 	 *
2717 	 * Format
2718 	 *
2719 	 * uint32_t array, each array entry specifying the VLAN id and the
2720 	 * mapping
2721 	 *
2722 	 * bit[30] = add bit[29] = remove bit[28]  = preference bits[23-16] =
2723 	 * rdcgrp bits[15-0] = VLAN ID ( )
2724 	 */
2725 
2726 	for (i = 0; i < NXGE_MAX_VLANS; i++) {
2727 		p_class_cfgp->vlan_tbl[i].flag = 0;
2728 	}
2729 
2730 	vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0];
2731 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2732 	    &vlan_cfg_val, &vlan_cnt) == DDI_PROP_SUCCESS) {
2733 		for (i = 0; i < vlan_cnt; i++) {
2734 			vmap = (nxge_param_map_t *)&vlan_cfg_val[i];
2735 			if ((vmap->param_id) &&
2736 			    (vmap->param_id < NXGE_MAX_VLANS) &&
2737 			    (vmap->map_to <
2738 			    p_cfgp->max_rdc_grpids) &&
2739 			    (vmap->map_to >= (uint8_t)0)) {
2740 				NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2741 				    " nxge_vlan_config mapping"
2742 				    " id %d grp %d",
2743 				    vmap->param_id, vmap->map_to));
2744 				good_cfg[good_count] = vlan_cfg_val[i];
2745 				if (vlan_tbl[vmap->param_id].flag == 0)
2746 					good_count++;
2747 				vlan_tbl[vmap->param_id].flag = 1;
2748 				vlan_tbl[vmap->param_id].rdctbl =
2749 				    vmap->map_to + p_cfgp->def_mac_rxdma_grpid;
2750 				vlan_tbl[vmap->param_id].mpr_npr = vmap->pref;
2751 			}
2752 		}
2753 		ddi_prop_free(vlan_cfg_val);
2754 		if (good_count != vlan_cnt) {
2755 			(void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2756 			    nxgep->dip, prop, (int *)good_cfg, good_count);
2757 		}
2758 	}
2759 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_vlan_config"));
2760 }
2761 
2762 static void
2763 nxge_set_hw_mac_class_config(p_nxge_t nxgep)
2764 {
2765 	int i;
2766 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2767 	p_nxge_hw_pt_cfg_t p_cfgp;
2768 	p_nxge_param_t param_arr;
2769 	uint_t mac_cnt;
2770 	int *mac_cfg_val;
2771 	nxge_param_map_t *mac_map;
2772 	char *prop;
2773 	p_nxge_class_pt_cfg_t p_class_cfgp;
2774 	int good_count = 0;
2775 	int good_cfg[NXGE_MAX_MACS];
2776 	nxge_mv_cfg_t *mac_host_info;
2777 
2778 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_mac_config"));
2779 
2780 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2781 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2782 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
2783 	mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0];
2784 
2785 	param_arr = nxgep->param_arr;
2786 	prop = param_arr[param_mac_2rdc_grp].fcode_name;
2787 
2788 	for (i = 0; i < NXGE_MAX_MACS; i++) {
2789 		p_class_cfgp->mac_host_info[i].flag = 0;
2790 		p_class_cfgp->mac_host_info[i].rdctbl =
2791 		    p_cfgp->def_mac_rxdma_grpid;
2792 	}
2793 
2794 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2795 	    &mac_cfg_val, &mac_cnt) == DDI_PROP_SUCCESS) {
2796 		for (i = 0; i < mac_cnt; i++) {
2797 			mac_map = (nxge_param_map_t *)&mac_cfg_val[i];
2798 			if ((mac_map->param_id < p_cfgp->max_macs) &&
2799 			    (mac_map->map_to <
2800 			    p_cfgp->max_rdc_grpids) &&
2801 			    (mac_map->map_to >= (uint8_t)0)) {
2802 				NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2803 				    " nxge_mac_config mapping"
2804 				    " id %d grp %d",
2805 				    mac_map->param_id, mac_map->map_to));
2806 				mac_host_info[mac_map->param_id].mpr_npr =
2807 				    p_cfgp->mac_pref;
2808 				mac_host_info[mac_map->param_id].rdctbl =
2809 				    mac_map->map_to +
2810 				    p_cfgp->def_mac_rxdma_grpid;
2811 				good_cfg[good_count] = mac_cfg_val[i];
2812 				if (mac_host_info[mac_map->param_id].flag == 0)
2813 					good_count++;
2814 				mac_host_info[mac_map->param_id].flag = 1;
2815 			}
2816 		}
2817 		ddi_prop_free(mac_cfg_val);
2818 		if (good_count != mac_cnt) {
2819 			(void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2820 			    nxgep->dip, prop, good_cfg, good_count);
2821 		}
2822 	}
2823 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_mac_config"));
2824 }
2825 
2826 static void
2827 nxge_set_hw_class_config(p_nxge_t nxgep)
2828 {
2829 	int i;
2830 	p_nxge_param_t param_arr;
2831 	int *int_prop_val;
2832 	uint32_t cfg_value;
2833 	char *prop;
2834 	p_nxge_class_pt_cfg_t p_class_cfgp;
2835 	int start_prop, end_prop;
2836 	uint_t prop_cnt;
2837 	int start_class, j = 0;
2838 
2839 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_class_config"));
2840 
2841 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
2842 	param_arr = nxgep->param_arr;
2843 	start_prop = param_class_opt_ipv4_tcp;
2844 	end_prop = param_class_opt_ipv6_sctp;
2845 	start_class = TCAM_CLASS_TCP_IPV4;
2846 
2847 	for (i = start_prop, j = 0; i <= end_prop; i++, j++) {
2848 		prop = param_arr[i].fcode_name;
2849 		if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip,
2850 		    0, prop, &int_prop_val,
2851 		    &prop_cnt) == DDI_PROP_SUCCESS) {
2852 			cfg_value = (uint32_t)*int_prop_val;
2853 			ddi_prop_free(int_prop_val);
2854 		} else {
2855 			cfg_value = (uint32_t)param_arr[i].value;
2856 		}
2857 		p_class_cfgp->class_cfg[start_class + j] = cfg_value;
2858 	}
2859 
2860 	prop = param_arr[param_h1_init_value].fcode_name;
2861 
2862 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2863 	    &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) {
2864 		cfg_value = (uint32_t)*int_prop_val;
2865 		ddi_prop_free(int_prop_val);
2866 	} else {
2867 		cfg_value = (uint32_t)param_arr[param_h1_init_value].value;
2868 	}
2869 
2870 	p_class_cfgp->init_h1 = (uint32_t)cfg_value;
2871 	prop = param_arr[param_h2_init_value].fcode_name;
2872 
2873 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2874 	    &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) {
2875 		cfg_value = (uint32_t)*int_prop_val;
2876 		ddi_prop_free(int_prop_val);
2877 	} else {
2878 		cfg_value = (uint32_t)param_arr[param_h2_init_value].value;
2879 	}
2880 
2881 	p_class_cfgp->init_h2 = (uint16_t)cfg_value;
2882 	NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_class_config"));
2883 }
2884 
2885 nxge_status_t
2886 nxge_ldgv_init_n2(p_nxge_t nxgep, int *navail_p, int *nrequired_p)
2887 {
2888 	int i, maxldvs, maxldgs, nldvs;
2889 	int ldv, endldg;
2890 	uint8_t func;
2891 	uint8_t channel;
2892 	uint8_t chn_start;
2893 	boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE;
2894 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
2895 	p_nxge_hw_pt_cfg_t p_cfgp;
2896 	p_nxge_ldgv_t ldgvp;
2897 	p_nxge_ldg_t ldgp, ptr;
2898 	p_nxge_ldv_t ldvp, sysldvp;
2899 	nxge_status_t status = NXGE_OK;
2900 	nxge_grp_set_t *set;
2901 
2902 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2"));
2903 	if (!*navail_p) {
2904 		*nrequired_p = 0;
2905 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2906 		    "<== nxge_ldgv_init:no avail"));
2907 		return (NXGE_ERROR);
2908 	}
2909 	/*
2910 	 * N2/NIU: one logical device owns one logical group. and each
2911 	 * device/group will be assigned one vector by Hypervisor.
2912 	 */
2913 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2914 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2915 	maxldgs = p_cfgp->max_ldgs;
2916 	if (!maxldgs) {
2917 		/* No devices configured. */
2918 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init_n2: "
2919 		    "no logical groups configured."));
2920 		return (NXGE_ERROR);
2921 	} else {
2922 		maxldvs = maxldgs + 1;
2923 	}
2924 
2925 	/*
2926 	 * If function zero instance, it needs to handle the system and MIF
2927 	 * error interrupts. MIF interrupt may not be needed for N2/NIU.
2928 	 */
2929 	func = nxgep->function_num;
2930 	if (func == 0) {
2931 		own_sys_err = B_TRUE;
2932 		if (!p_cfgp->ser_ldvid) {
2933 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2934 			    "nxge_ldgv_init_n2: func 0, ERR ID not set!"));
2935 		}
2936 		/* MIF interrupt */
2937 		if (!p_cfgp->mif_ldvid) {
2938 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2939 			    "nxge_ldgv_init_n2: func 0, MIF ID not set!"));
2940 		}
2941 	}
2942 
2943 	/*
2944 	 * Assume single partition, each function owns mac.
2945 	 */
2946 	if (!nxge_use_partition)
2947 		own_fzc = B_TRUE;
2948 
2949 	ldgvp = nxgep->ldgvp;
2950 	if (ldgvp == NULL) {
2951 		ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP);
2952 		nxgep->ldgvp = ldgvp;
2953 		ldgvp->maxldgs = (uint8_t)maxldgs;
2954 		ldgvp->maxldvs = (uint8_t)maxldvs;
2955 		ldgp = ldgvp->ldgp = KMEM_ZALLOC(
2956 		    sizeof (nxge_ldg_t) * maxldgs, KM_SLEEP);
2957 		ldvp = ldgvp->ldvp = KMEM_ZALLOC(
2958 		    sizeof (nxge_ldv_t) * maxldvs, KM_SLEEP);
2959 	} else {
2960 		ldgp = ldgvp->ldgp;
2961 		ldvp = ldgvp->ldvp;
2962 	}
2963 
2964 	ldgvp->ndma_ldvs = p_cfgp->tdc.owned + p_cfgp->max_rdcs;
2965 	ldgvp->tmres = NXGE_TIMER_RESO;
2966 
2967 	NXGE_DEBUG_MSG((nxgep, INT_CTL,
2968 	    "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d",
2969 	    maxldvs, maxldgs));
2970 
2971 	/* logical start_ldg is ldv */
2972 	ptr = ldgp;
2973 	for (i = 0; i < maxldgs; i++) {
2974 		ptr->func = func;
2975 		ptr->arm = B_TRUE;
2976 		ptr->vldg_index = (uint8_t)i;
2977 		ptr->ldg_timer = NXGE_TIMER_LDG;
2978 		ptr->ldg = p_cfgp->ldg[i];
2979 		ptr->sys_intr_handler = nxge_intr;
2980 		ptr->nldvs = 0;
2981 		ptr->ldvp = NULL;
2982 		ptr->nxgep = nxgep;
2983 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
2984 		    "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d "
2985 		    "ldg %d ldgptr $%p",
2986 		    maxldvs, maxldgs, ptr->ldg, ptr));
2987 		ptr++;
2988 	}
2989 
2990 	endldg = NXGE_INT_MAX_LDG;
2991 	nldvs = 0;
2992 	ldgvp->nldvs = 0;
2993 	ldgp->ldvp = NULL;
2994 	*nrequired_p = 0;
2995 
2996 	/*
2997 	 * logical device group table is organized in the following order (same
2998 	 * as what interrupt property has). function 0: owns MAC, MIF, error,
2999 	 * rx, tx. function 1: owns MAC, rx, tx.
3000 	 */
3001 
3002 	if (own_fzc && p_cfgp->mac_ldvid) {
3003 		/* Each function should own MAC interrupt */
3004 		ldv = p_cfgp->mac_ldvid;
3005 		ldvp->ldv = (uint8_t)ldv;
3006 		ldvp->is_mac = B_TRUE;
3007 		ldvp->ldv_intr_handler = nxge_mac_intr;
3008 		ldvp->ldv_ldf_masks = 0;
3009 		ldvp->nxgep = nxgep;
3010 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
3011 		    "==> nxge_ldgv_init_n2(mac): maxldvs %d ldv %d "
3012 		    "ldg %d ldgptr $%p ldvptr $%p",
3013 		    maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
3014 		nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3015 		nldvs++;
3016 	}
3017 
3018 	if (own_fzc && p_cfgp->mif_ldvid) {
3019 		ldv = p_cfgp->mif_ldvid;
3020 		ldvp->ldv = (uint8_t)ldv;
3021 		ldvp->is_mif = B_TRUE;
3022 		ldvp->ldv_intr_handler = nxge_mif_intr;
3023 		ldvp->ldv_ldf_masks = 0;
3024 		ldvp->nxgep = nxgep;
3025 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
3026 		    "==> nxge_ldgv_init_n2(mif): maxldvs %d ldv %d "
3027 		    "ldg %d ldgptr $%p ldvptr $%p",
3028 		    maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
3029 		nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3030 		nldvs++;
3031 	}
3032 
3033 	/*
3034 	 * HW based syserr interrupt for port0, and SW based syserr interrupt
3035 	 * for port1
3036 	 */
3037 	if (own_sys_err && p_cfgp->ser_ldvid) {
3038 		ldv = p_cfgp->ser_ldvid;
3039 		/*
3040 		 * Unmask the system interrupt states.
3041 		 */
3042 		(void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK |
3043 		    SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK |
3044 		    SYS_ERR_ZCP_MASK);
3045 
3046 		ldvp->use_timer = B_TRUE;
3047 		ldvp->ldv = (uint8_t)ldv;
3048 		ldvp->is_syserr = B_TRUE;
3049 		ldvp->ldv_intr_handler = nxge_syserr_intr;
3050 		ldvp->ldv_ldf_masks = 0;
3051 		ldvp->nxgep = nxgep;
3052 		ldgvp->ldvp_syserr = ldvp;
3053 
3054 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
3055 		    "==> nxge_ldgv_init_n2(syserr): maxldvs %d ldv %d "
3056 		    "ldg %d ldgptr $%p ldvptr p%p",
3057 		    maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
3058 		nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3059 		nldvs++;
3060 	} else {
3061 		/*
3062 		 * SW based: allocate the ldv for the syserr since the vector
3063 		 * should not be consumed for port1
3064 		 */
3065 		sysldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t), KM_SLEEP);
3066 		sysldvp->use_timer = B_TRUE;
3067 		sysldvp->ldv = NXGE_SYS_ERROR_LD;
3068 		sysldvp->is_syserr = B_TRUE;
3069 		sysldvp->ldv_intr_handler = nxge_syserr_intr;
3070 		sysldvp->ldv_ldf_masks = 0;
3071 		sysldvp->nxgep = nxgep;
3072 		ldgvp->ldvp_syserr = sysldvp;
3073 		ldgvp->ldvp_syserr_alloced = B_TRUE;
3074 	}
3075 
3076 
3077 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
3078 	    "(before rx) func %d nldvs %d navail %d nrequired %d",
3079 	    func, nldvs, *navail_p, *nrequired_p));
3080 
3081 	/*
3082 	 * Start with RDC to configure logical devices for each group.
3083 	 */
3084 	chn_start = p_cfgp->ldg_chn_start;
3085 	set = &nxgep->rx_set;
3086 	for (channel = 0; channel < NXGE_MAX_RDCS; channel++) {
3087 		if ((1 << channel) & set->owned.map) {
3088 			ldvp->is_rxdma = B_TRUE;
3089 			ldvp->ldv = (uint8_t)channel + NXGE_RDMA_LD_START;
3090 			ldvp->channel = channel;
3091 			ldvp->vdma_index = (uint8_t)channel;
3092 			ldvp->ldv_intr_handler = nxge_rx_intr;
3093 			ldvp->ldv_ldf_masks = 0;
3094 			ldvp->nxgep = nxgep;
3095 			ldgp->ldg = p_cfgp->ldg[chn_start];
3096 
3097 			NXGE_DEBUG_MSG((nxgep, INT_CTL,
3098 			    "==> nxge_ldgv_init_n2(rx%d): maxldvs %d ldv %d "
3099 			    "ldg %d ldgptr 0x%016llx ldvptr 0x%016llx",
3100 			    i, maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
3101 			nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv,
3102 			    endldg, nrequired_p);
3103 			nldvs++;
3104 			chn_start++;
3105 		}
3106 	}
3107 
3108 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
3109 	    "func %d nldvs %d navail %d nrequired %d",
3110 	    func, nldvs, *navail_p, *nrequired_p));
3111 
3112 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
3113 	    "func %d nldvs %d navail %d nrequired %d ldgp 0x%llx "
3114 	    "ldvp 0x%llx",
3115 	    func, nldvs, *navail_p, *nrequired_p, ldgp, ldvp));
3116 	/*
3117 	 * Transmit DMA channels.
3118 	 */
3119 	chn_start = p_cfgp->ldg_chn_start + 8;
3120 	set = &nxgep->tx_set;
3121 	for (channel = 0; channel < NXGE_MAX_TDCS; channel++) {
3122 		if ((1 << channel) & set->owned.map) {
3123 			ldvp->is_txdma = B_TRUE;
3124 			ldvp->ldv = (uint8_t)channel + NXGE_TDMA_LD_START;
3125 			ldvp->channel = channel;
3126 			ldvp->vdma_index = (uint8_t)channel;
3127 			ldvp->ldv_intr_handler = nxge_tx_intr;
3128 			ldvp->ldv_ldf_masks = 0;
3129 			ldgp->ldg = p_cfgp->ldg[chn_start];
3130 			ldvp->nxgep = nxgep;
3131 			NXGE_DEBUG_MSG((nxgep, INT_CTL,
3132 			    "==> nxge_ldgv_init_n2(tx%d): maxldvs %d ldv %d "
3133 			    "ldg %d ldgptr %p ldvptr %p",
3134 			    channel, maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
3135 			nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv,
3136 			    endldg, nrequired_p);
3137 			nldvs++;
3138 			chn_start++;
3139 		}
3140 	}
3141 
3142 	ldgvp->ldg_intrs = *nrequired_p;
3143 	ldgvp->nldvs = (uint8_t)nldvs;
3144 
3145 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
3146 	    "func %d nldvs %d maxgrps %d navail %d nrequired %d",
3147 	    func, nldvs, maxldgs, *navail_p, *nrequired_p));
3148 
3149 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init_n2"));
3150 	return (status);
3151 }
3152 
3153 /*
3154  * Interrupts related interface functions.
3155  */
3156 
3157 nxge_status_t
3158 nxge_ldgv_init(p_nxge_t nxgep, int *navail_p, int *nrequired_p)
3159 {
3160 	int i, maxldvs, maxldgs, nldvs;
3161 	int ldv, ldg, endldg, ngrps;
3162 	uint8_t func;
3163 	uint8_t channel;
3164 	boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE;
3165 	p_nxge_dma_pt_cfg_t p_dma_cfgp;
3166 	p_nxge_hw_pt_cfg_t p_cfgp;
3167 	p_nxge_ldgv_t ldgvp;
3168 	p_nxge_ldg_t ldgp, ptr;
3169 	p_nxge_ldv_t ldvp;
3170 	nxge_grp_set_t *set;
3171 
3172 	nxge_status_t status = NXGE_OK;
3173 
3174 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init"));
3175 	if (!*navail_p) {
3176 		*nrequired_p = 0;
3177 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3178 		    "<== nxge_ldgv_init:no avail"));
3179 		return (NXGE_ERROR);
3180 	}
3181 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
3182 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
3183 
3184 	nldvs = p_cfgp->tdc.owned + p_cfgp->max_rdcs;
3185 
3186 	/*
3187 	 * If function zero instance, it needs to handle the system error
3188 	 * interrupts.
3189 	 */
3190 	func = nxgep->function_num;
3191 	if (func == 0) {
3192 		nldvs++;
3193 		own_sys_err = B_TRUE;
3194 	} else {
3195 		/* use timer */
3196 		nldvs++;
3197 	}
3198 
3199 	/*
3200 	 * Assume single partition, each function owns mac.
3201 	 */
3202 	if (!nxge_use_partition) {
3203 		/* mac */
3204 		nldvs++;
3205 		/* MIF */
3206 		nldvs++;
3207 		own_fzc = B_TRUE;
3208 	}
3209 	maxldvs = nldvs;
3210 	maxldgs = p_cfgp->max_ldgs;
3211 	if (!maxldvs || !maxldgs) {
3212 		/* No devices configured. */
3213 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init: "
3214 		    "no logical devices or groups configured."));
3215 		return (NXGE_ERROR);
3216 	}
3217 	ldgvp = nxgep->ldgvp;
3218 	if (ldgvp == NULL) {
3219 		ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP);
3220 		nxgep->ldgvp = ldgvp;
3221 		ldgvp->maxldgs = (uint8_t)maxldgs;
3222 		ldgvp->maxldvs = (uint8_t)maxldvs;
3223 		ldgp = ldgvp->ldgp = KMEM_ZALLOC(sizeof (nxge_ldg_t) * maxldgs,
3224 		    KM_SLEEP);
3225 		ldvp = ldgvp->ldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t) * maxldvs,
3226 		    KM_SLEEP);
3227 	}
3228 	ldgvp->ndma_ldvs = p_cfgp->tdc.owned + p_cfgp->max_rdcs;
3229 	ldgvp->tmres = NXGE_TIMER_RESO;
3230 
3231 	NXGE_DEBUG_MSG((nxgep, INT_CTL,
3232 	    "==> nxge_ldgv_init: maxldvs %d maxldgs %d nldvs %d",
3233 	    maxldvs, maxldgs, nldvs));
3234 	ldg = p_cfgp->start_ldg;
3235 	ptr = ldgp;
3236 	for (i = 0; i < maxldgs; i++) {
3237 		ptr->func = func;
3238 		ptr->arm = B_TRUE;
3239 		ptr->vldg_index = (uint8_t)i;
3240 		ptr->ldg_timer = NXGE_TIMER_LDG;
3241 		ptr->ldg = ldg++;
3242 		ptr->sys_intr_handler = nxge_intr;
3243 		ptr->nldvs = 0;
3244 		ptr->nxgep = nxgep;
3245 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
3246 		    "==> nxge_ldgv_init: maxldvs %d maxldgs %d ldg %d",
3247 		    maxldvs, maxldgs, ptr->ldg));
3248 		ptr++;
3249 	}
3250 
3251 	ldg = p_cfgp->start_ldg;
3252 	if (maxldgs > *navail_p) {
3253 		ngrps = *navail_p;
3254 	} else {
3255 		ngrps = maxldgs;
3256 	}
3257 	endldg = ldg + ngrps;
3258 
3259 	/*
3260 	 * Receive DMA channels.
3261 	 */
3262 	nldvs = 0;
3263 	ldgvp->nldvs = 0;
3264 	ldgp->ldvp = NULL;
3265 	*nrequired_p = 0;
3266 
3267 	/*
3268 	 * Start with RDC to configure logical devices for each group.
3269 	 */
3270 	set = &nxgep->rx_set;
3271 	for (channel = 0; channel < NXGE_MAX_RDCS; channel++) {
3272 		if ((1 << channel) & set->owned.map) {
3273 			/* For now, <channel & <vdma_index> are the same. */
3274 			ldvp->is_rxdma = B_TRUE;
3275 			ldvp->ldv = (uint8_t)channel + NXGE_RDMA_LD_START;
3276 			ldvp->channel = channel;
3277 			ldvp->vdma_index = (uint8_t)channel;
3278 			ldvp->ldv_intr_handler = nxge_rx_intr;
3279 			ldvp->ldv_ldf_masks = 0;
3280 			ldvp->use_timer = B_FALSE;
3281 			ldvp->nxgep = nxgep;
3282 			nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv,
3283 			    endldg, nrequired_p);
3284 			nldvs++;
3285 		}
3286 	}
3287 
3288 	/*
3289 	 * Transmit DMA channels.
3290 	 */
3291 	set = &nxgep->tx_set;
3292 	for (channel = 0; channel < NXGE_MAX_TDCS; channel++) {
3293 		if ((1 << channel) & set->owned.map) {
3294 			/* For now, <channel & <vdma_index> are the same. */
3295 			ldvp->is_txdma = B_TRUE;
3296 			ldvp->ldv = (uint8_t)channel + NXGE_TDMA_LD_START;
3297 			ldvp->channel = channel;
3298 			ldvp->vdma_index = (uint8_t)channel;
3299 			ldvp->ldv_intr_handler = nxge_tx_intr;
3300 			ldvp->ldv_ldf_masks = 0;
3301 			ldvp->use_timer = B_FALSE;
3302 			ldvp->nxgep = nxgep;
3303 			nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv,
3304 			    endldg, nrequired_p);
3305 			nldvs++;
3306 		}
3307 	}
3308 
3309 	if (own_fzc) {
3310 		ldv = NXGE_MIF_LD;
3311 		ldvp->ldv = (uint8_t)ldv;
3312 		ldvp->is_mif = B_TRUE;
3313 		ldvp->ldv_intr_handler = nxge_mif_intr;
3314 		ldvp->ldv_ldf_masks = 0;
3315 		ldvp->use_timer = B_FALSE;
3316 		ldvp->nxgep = nxgep;
3317 		nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3318 		nldvs++;
3319 	}
3320 	/*
3321 	 * MAC port (function zero control)
3322 	 */
3323 	if (own_fzc) {
3324 		ldvp->is_mac = B_TRUE;
3325 		ldvp->ldv_intr_handler = nxge_mac_intr;
3326 		ldvp->ldv_ldf_masks = 0;
3327 		ldv = func + NXGE_MAC_LD_START;
3328 		ldvp->ldv = (uint8_t)ldv;
3329 		ldvp->use_timer = B_FALSE;
3330 		ldvp->nxgep = nxgep;
3331 		nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3332 		nldvs++;
3333 	}
3334 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: "
3335 	    "func %d nldvs %d navail %d nrequired %d",
3336 	    func, nldvs, *navail_p, *nrequired_p));
3337 	/*
3338 	 * Function 0 owns system error interrupts.
3339 	 */
3340 	ldvp->use_timer = B_TRUE;
3341 	if (own_sys_err) {
3342 		ldv = NXGE_SYS_ERROR_LD;
3343 		ldvp->ldv = (uint8_t)ldv;
3344 		ldvp->is_syserr = B_TRUE;
3345 		ldvp->ldv_intr_handler = nxge_syserr_intr;
3346 		ldvp->ldv_ldf_masks = 0;
3347 		ldvp->nxgep = nxgep;
3348 		ldgvp->ldvp_syserr = ldvp;
3349 		/*
3350 		 * Unmask the system interrupt states.
3351 		 */
3352 		(void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK |
3353 		    SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK |
3354 		    SYS_ERR_ZCP_MASK);
3355 
3356 		(void) nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3357 		nldvs++;
3358 	} else {
3359 		ldv = NXGE_SYS_ERROR_LD;
3360 		ldvp->ldv = (uint8_t)ldv;
3361 		ldvp->is_syserr = B_TRUE;
3362 		ldvp->ldv_intr_handler = nxge_syserr_intr;
3363 		ldvp->nxgep = nxgep;
3364 		ldvp->ldv_ldf_masks = 0;
3365 		ldgvp->ldvp_syserr = ldvp;
3366 	}
3367 
3368 	ldgvp->ldg_intrs = *nrequired_p;
3369 
3370 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: "
3371 	    "func %d nldvs %d navail %d nrequired %d",
3372 	    func, nldvs, *navail_p, *nrequired_p));
3373 
3374 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init"));
3375 	return (status);
3376 }
3377 
3378 nxge_status_t
3379 nxge_ldgv_uninit(p_nxge_t nxgep)
3380 {
3381 	p_nxge_ldgv_t ldgvp;
3382 
3383 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_uninit"));
3384 	ldgvp = nxgep->ldgvp;
3385 	if (ldgvp == NULL) {
3386 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_uninit: "
3387 		    "no logical group configured."));
3388 		return (NXGE_OK);
3389 	}
3390 	if (ldgvp->ldvp_syserr_alloced == B_TRUE) {
3391 		KMEM_FREE(ldgvp->ldvp_syserr, sizeof (nxge_ldv_t));
3392 	}
3393 	if (ldgvp->ldgp) {
3394 		KMEM_FREE(ldgvp->ldgp, sizeof (nxge_ldg_t) * ldgvp->maxldgs);
3395 	}
3396 	if (ldgvp->ldvp) {
3397 		KMEM_FREE(ldgvp->ldvp, sizeof (nxge_ldv_t) * ldgvp->maxldvs);
3398 	}
3399 	KMEM_FREE(ldgvp, sizeof (nxge_ldgv_t));
3400 	nxgep->ldgvp = NULL;
3401 
3402 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_uninit"));
3403 	return (NXGE_OK);
3404 }
3405 
3406 nxge_status_t
3407 nxge_intr_ldgv_init(p_nxge_t nxgep)
3408 {
3409 	nxge_status_t status = NXGE_OK;
3410 
3411 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_ldgv_init"));
3412 	/*
3413 	 * Configure the logical device group numbers, state vectors and
3414 	 * interrupt masks for each logical device.
3415 	 */
3416 	status = nxge_fzc_intr_init(nxgep);
3417 
3418 	/*
3419 	 * Configure logical device masks and timers.
3420 	 */
3421 	status = nxge_intr_mask_mgmt(nxgep);
3422 
3423 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_ldgv_init"));
3424 	return (status);
3425 }
3426 
3427 nxge_status_t
3428 nxge_intr_mask_mgmt(p_nxge_t nxgep)
3429 {
3430 	p_nxge_ldgv_t ldgvp;
3431 	p_nxge_ldg_t ldgp;
3432 	p_nxge_ldv_t ldvp;
3433 	npi_handle_t handle;
3434 	int i, j;
3435 	npi_status_t rs = NPI_SUCCESS;
3436 
3437 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_mask_mgmt"));
3438 
3439 	if ((ldgvp = nxgep->ldgvp) == NULL) {
3440 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3441 		    "<== nxge_intr_mask_mgmt: Null ldgvp"));
3442 		return (NXGE_ERROR);
3443 	}
3444 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
3445 	ldgp = ldgvp->ldgp;
3446 	ldvp = ldgvp->ldvp;
3447 	if (ldgp == NULL || ldvp == NULL) {
3448 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3449 		    "<== nxge_intr_mask_mgmt: Null ldgp or ldvp"));
3450 		return (NXGE_ERROR);
3451 	}
3452 	NXGE_DEBUG_MSG((nxgep, INT_CTL,
3453 	    "==> nxge_intr_mask_mgmt: # of intrs %d ", ldgvp->ldg_intrs));
3454 	/* Initialize masks. */
3455 	if (nxgep->niu_type != N2_NIU) {
3456 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
3457 		    "==> nxge_intr_mask_mgmt(Neptune): # intrs %d ",
3458 		    ldgvp->ldg_intrs));
3459 		for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) {
3460 			NXGE_DEBUG_MSG((nxgep, INT_CTL,
3461 			    "==> nxge_intr_mask_mgmt(Neptune): # ldv %d "
3462 			    "in group %d", ldgp->nldvs, ldgp->ldg));
3463 			for (j = 0; j < ldgp->nldvs; j++, ldvp++) {
3464 				NXGE_DEBUG_MSG((nxgep, INT_CTL,
3465 				    "==> nxge_intr_mask_mgmt: set ldv # %d "
3466 				    "for ldg %d", ldvp->ldv, ldgp->ldg));
3467 				rs = npi_intr_mask_set(handle, ldvp->ldv,
3468 				    ldvp->ldv_ldf_masks);
3469 				if (rs != NPI_SUCCESS) {
3470 					NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3471 					    "<== nxge_intr_mask_mgmt: "
3472 					    "set mask failed "
3473 					    " rs 0x%x ldv %d mask 0x%x",
3474 					    rs, ldvp->ldv,
3475 					    ldvp->ldv_ldf_masks));
3476 					return (NXGE_ERROR | rs);
3477 				}
3478 				NXGE_DEBUG_MSG((nxgep, INT_CTL,
3479 				    "==> nxge_intr_mask_mgmt: "
3480 				    "set mask OK "
3481 				    " rs 0x%x ldv %d mask 0x%x",
3482 				    rs, ldvp->ldv,
3483 				    ldvp->ldv_ldf_masks));
3484 			}
3485 		}
3486 	}
3487 	ldgp = ldgvp->ldgp;
3488 	/* Configure timer and arm bit */
3489 	for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) {
3490 		rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg,
3491 		    ldgp->arm, ldgp->ldg_timer);
3492 		if (rs != NPI_SUCCESS) {
3493 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3494 			    "<== nxge_intr_mask_mgmt: "
3495 			    "set timer failed "
3496 			    " rs 0x%x dg %d timer 0x%x",
3497 			    rs, ldgp->ldg, ldgp->ldg_timer));
3498 			return (NXGE_ERROR | rs);
3499 		}
3500 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
3501 		    "==> nxge_intr_mask_mgmt: "
3502 		    "set timer OK "
3503 		    " rs 0x%x ldg %d timer 0x%x",
3504 		    rs, ldgp->ldg, ldgp->ldg_timer));
3505 	}
3506 
3507 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_mask_mgmt"));
3508 	return (NXGE_OK);
3509 }
3510 
3511 nxge_status_t
3512 nxge_intr_mask_mgmt_set(p_nxge_t nxgep, boolean_t on)
3513 {
3514 	p_nxge_ldgv_t ldgvp;
3515 	p_nxge_ldg_t ldgp;
3516 	p_nxge_ldv_t ldvp;
3517 	npi_handle_t handle;
3518 	int i, j;
3519 	npi_status_t rs = NPI_SUCCESS;
3520 
3521 	NXGE_DEBUG_MSG((nxgep, INT_CTL,
3522 	    "==> nxge_intr_mask_mgmt_set (%d)", on));
3523 
3524 	if (nxgep->niu_type == N2_NIU) {
3525 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
3526 		    "<== nxge_intr_mask_mgmt_set (%d) not set (N2/NIU)",
3527 		    on));
3528 		return (NXGE_ERROR);
3529 	}
3530 
3531 	if ((ldgvp = nxgep->ldgvp) == NULL) {
3532 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3533 		    "==> nxge_intr_mask_mgmt_set: Null ldgvp"));
3534 		return (NXGE_ERROR);
3535 	}
3536 
3537 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
3538 	ldgp = ldgvp->ldgp;
3539 	ldvp = ldgvp->ldvp;
3540 	if (ldgp == NULL || ldvp == NULL) {
3541 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3542 		    "<== nxge_intr_mask_mgmt_set: Null ldgp or ldvp"));
3543 		return (NXGE_ERROR);
3544 	}
3545 	/* set masks. */
3546 	for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) {
3547 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
3548 		    "==> nxge_intr_mask_mgmt_set: flag %d ldg %d"
3549 		    "set mask nldvs %d", on, ldgp->ldg, ldgp->nldvs));
3550 		for (j = 0; j < ldgp->nldvs; j++, ldvp++) {
3551 			NXGE_DEBUG_MSG((nxgep, INT_CTL,
3552 			    "==> nxge_intr_mask_mgmt_set: "
3553 			    "for %d %d flag %d", i, j, on));
3554 			if (on) {
3555 				ldvp->ldv_ldf_masks = 0;
3556 				NXGE_DEBUG_MSG((nxgep, INT_CTL,
3557 				    "==> nxge_intr_mask_mgmt_set: "
3558 				    "ON mask off"));
3559 			} else if (!on) {
3560 				ldvp->ldv_ldf_masks = (uint8_t)LD_IM1_MASK;
3561 				NXGE_DEBUG_MSG((nxgep, INT_CTL,
3562 				    "==> nxge_intr_mask_mgmt_set:mask on"));
3563 			}
3564 			rs = npi_intr_mask_set(handle, ldvp->ldv,
3565 			    ldvp->ldv_ldf_masks);
3566 			if (rs != NPI_SUCCESS) {
3567 				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3568 				    "==> nxge_intr_mask_mgmt_set: "
3569 				    "set mask failed "
3570 				    " rs 0x%x ldv %d mask 0x%x",
3571 				    rs, ldvp->ldv, ldvp->ldv_ldf_masks));
3572 				return (NXGE_ERROR | rs);
3573 			}
3574 			NXGE_DEBUG_MSG((nxgep, INT_CTL,
3575 			    "==> nxge_intr_mask_mgmt_set: flag %d"
3576 			    "set mask OK "
3577 			    " ldv %d mask 0x%x",
3578 			    on, ldvp->ldv, ldvp->ldv_ldf_masks));
3579 		}
3580 	}
3581 
3582 	ldgp = ldgvp->ldgp;
3583 	/* set the arm bit */
3584 	for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) {
3585 		if (on && !ldgp->arm) {
3586 			ldgp->arm = B_TRUE;
3587 		} else if (!on && ldgp->arm) {
3588 			ldgp->arm = B_FALSE;
3589 		}
3590 		rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg,
3591 		    ldgp->arm, ldgp->ldg_timer);
3592 		if (rs != NPI_SUCCESS) {
3593 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3594 			    "<== nxge_intr_mask_mgmt_set: "
3595 			    "set timer failed "
3596 			    " rs 0x%x ldg %d timer 0x%x",
3597 			    rs, ldgp->ldg, ldgp->ldg_timer));
3598 			return (NXGE_ERROR | rs);
3599 		}
3600 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
3601 		    "==> nxge_intr_mask_mgmt_set: OK (flag %d) "
3602 		    "set timer "
3603 		    " ldg %d timer 0x%x",
3604 		    on, ldgp->ldg, ldgp->ldg_timer));
3605 	}
3606 
3607 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_mask_mgmt_set"));
3608 	return (NXGE_OK);
3609 }
3610 
3611 static nxge_status_t
3612 nxge_get_mac_addr_properties(p_nxge_t nxgep)
3613 {
3614 #if defined(_BIG_ENDIAN)
3615 	uchar_t *prop_val;
3616 	uint_t prop_len;
3617 	uint_t j;
3618 #endif
3619 	uint_t i;
3620 	uint8_t func_num;
3621 	boolean_t compute_macs = B_TRUE;
3622 
3623 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_mac_addr_properties "));
3624 
3625 #if defined(_BIG_ENDIAN)
3626 	/*
3627 	 * Get the ethernet address.
3628 	 */
3629 	(void) localetheraddr((struct ether_addr *)NULL, &nxgep->ouraddr);
3630 
3631 	/*
3632 	 * Check if it is an adapter with its own local mac address If it is
3633 	 * present, override the system mac address.
3634 	 */
3635 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3636 	    "local-mac-address", &prop_val,
3637 	    &prop_len) == DDI_PROP_SUCCESS) {
3638 		if (prop_len == ETHERADDRL) {
3639 			nxgep->factaddr = *(p_ether_addr_t)prop_val;
3640 			NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Local mac address = "
3641 			    "%02x:%02x:%02x:%02x:%02x:%02x",
3642 			    prop_val[0], prop_val[1], prop_val[2],
3643 			    prop_val[3], prop_val[4], prop_val[5]));
3644 		}
3645 		ddi_prop_free(prop_val);
3646 	}
3647 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3648 	    "local-mac-address?", &prop_val,
3649 	    &prop_len) == DDI_PROP_SUCCESS) {
3650 		if (strncmp("true", (caddr_t)prop_val, (size_t)prop_len) == 0) {
3651 			nxgep->ouraddr = nxgep->factaddr;
3652 			NXGE_DEBUG_MSG((nxgep, DDI_CTL,
3653 			    "Using local MAC address"));
3654 		}
3655 		ddi_prop_free(prop_val);
3656 	} else {
3657 		nxgep->ouraddr = nxgep->factaddr;
3658 	}
3659 
3660 	if ((!nxgep->vpd_info.present) ||
3661 	    (nxge_is_valid_local_mac(nxgep->factaddr)))
3662 		goto got_mac_addr;
3663 
3664 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_get_mac_addr_properties: "
3665 	    "MAC address from properties is not valid...reading from PROM"));
3666 
3667 #endif
3668 	if (!nxgep->vpd_info.ver_valid) {
3669 		(void) nxge_espc_mac_addrs_get(nxgep);
3670 		if (!nxge_is_valid_local_mac(nxgep->factaddr)) {
3671 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get "
3672 			    "MAC address"));
3673 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version "
3674 			    "[%s] invalid...please update",
3675 			    nxgep->vpd_info.ver));
3676 			return (NXGE_ERROR);
3677 		}
3678 		nxgep->ouraddr = nxgep->factaddr;
3679 		goto got_mac_addr;
3680 	}
3681 	/*
3682 	 * First get the MAC address from the info in the VPD data read
3683 	 * from the EEPROM.
3684 	 */
3685 	nxge_espc_get_next_mac_addr(nxgep->vpd_info.mac_addr,
3686 	    nxgep->function_num, &nxgep->factaddr);
3687 
3688 	if (!nxge_is_valid_local_mac(nxgep->factaddr)) {
3689 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
3690 		    "nxge_get_mac_addr_properties: "
3691 		    "MAC address in EEPROM VPD data not valid"
3692 		    "...reading from NCR registers"));
3693 		(void) nxge_espc_mac_addrs_get(nxgep);
3694 		if (!nxge_is_valid_local_mac(nxgep->factaddr)) {
3695 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get "
3696 			    "MAC address"));
3697 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version "
3698 			    "[%s] invalid...please update",
3699 			    nxgep->vpd_info.ver));
3700 			return (NXGE_ERROR);
3701 		}
3702 	}
3703 
3704 	nxgep->ouraddr = nxgep->factaddr;
3705 
3706 got_mac_addr:
3707 	func_num = nxgep->function_num;
3708 
3709 	/*
3710 	 * Note: mac-addresses property is the list of mac addresses for a
3711 	 * port. NXGE_MAX_MMAC_ADDRS is the total number of MAC addresses
3712 	 * allocated for a board.
3713 	 */
3714 	nxgep->nxge_mmac_info.total_factory_macs = NXGE_MAX_MMAC_ADDRS;
3715 
3716 #if defined(_BIG_ENDIAN)
3717 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3718 	    "mac-addresses", &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
3719 		/*
3720 		 * XAUI may have up to 18 MACs, more than the XMAC can
3721 		 * use (1 unique MAC plus 16 alternate MACs)
3722 		 */
3723 		nxgep->nxge_mmac_info.num_factory_mmac =
3724 		    prop_len / ETHERADDRL - 1;
3725 		if (nxgep->nxge_mmac_info.num_factory_mmac >
3726 		    XMAC_MAX_ALT_ADDR_ENTRY) {
3727 			nxgep->nxge_mmac_info.num_factory_mmac =
3728 			    XMAC_MAX_ALT_ADDR_ENTRY;
3729 		}
3730 
3731 		for (i = 1; i <= nxgep->nxge_mmac_info.num_factory_mmac; i++) {
3732 			for (j = 0; j < ETHERADDRL; j++) {
3733 				nxgep->nxge_mmac_info.factory_mac_pool[i][j] =
3734 				    *(prop_val + (i * ETHERADDRL) + j);
3735 			}
3736 			NXGE_DEBUG_MSG((nxgep, DDI_CTL,
3737 			    "nxge_get_mac_addr_properties: Alt mac[%d] from "
3738 			    "mac-addresses property[%2x:%2x:%2x:%2x:%2x:%2x]",
3739 			    i, nxgep->nxge_mmac_info.factory_mac_pool[i][0],
3740 			    nxgep->nxge_mmac_info.factory_mac_pool[i][1],
3741 			    nxgep->nxge_mmac_info.factory_mac_pool[i][2],
3742 			    nxgep->nxge_mmac_info.factory_mac_pool[i][3],
3743 			    nxgep->nxge_mmac_info.factory_mac_pool[i][4],
3744 			    nxgep->nxge_mmac_info.factory_mac_pool[i][5]));
3745 		}
3746 
3747 		compute_macs = B_FALSE;
3748 		ddi_prop_free(prop_val);
3749 		goto got_mmac_info;
3750 	}
3751 #endif
3752 	/*
3753 	 * total_factory_macs = 32
3754 	 * num_factory_mmac = (32 >> (nports/2)) - 1
3755 	 * So if nports = 4, then num_factory_mmac =  7
3756 	 *    if nports = 2, then num_factory_mmac = 15
3757 	 */
3758 	nxgep->nxge_mmac_info.num_factory_mmac =
3759 	    ((nxgep->nxge_mmac_info.total_factory_macs >>
3760 	    (nxgep->nports >> 1))) - 1;
3761 
3762 got_mmac_info:
3763 
3764 	if ((nxgep->function_num < 2) &&
3765 	    (nxgep->nxge_mmac_info.num_factory_mmac >
3766 	    XMAC_MAX_ALT_ADDR_ENTRY)) {
3767 		nxgep->nxge_mmac_info.num_factory_mmac =
3768 		    XMAC_MAX_ALT_ADDR_ENTRY;
3769 	} else if ((nxgep->function_num > 1) &&
3770 	    (nxgep->nxge_mmac_info.num_factory_mmac >
3771 	    BMAC_MAX_ALT_ADDR_ENTRY)) {
3772 		nxgep->nxge_mmac_info.num_factory_mmac =
3773 		    BMAC_MAX_ALT_ADDR_ENTRY;
3774 	}
3775 
3776 	for (i = 0; i <= nxgep->nxge_mmac_info.num_mmac; i++) {
3777 		(void) npi_mac_altaddr_disable(nxgep->npi_handle,
3778 		    NXGE_GET_PORT_NUM(func_num), i);
3779 	}
3780 
3781 	(void) nxge_init_mmac(nxgep, compute_macs);
3782 	return (NXGE_OK);
3783 }
3784 
3785 void
3786 nxge_get_xcvr_properties(p_nxge_t nxgep)
3787 {
3788 	uchar_t *prop_val;
3789 	uint_t prop_len;
3790 
3791 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_xcvr_properties"));
3792 
3793 	/*
3794 	 * Read the type of physical layer interface being used.
3795 	 */
3796 	nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
3797 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3798 	    "phy-type", &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
3799 		if (strncmp("pcs", (caddr_t)prop_val,
3800 		    (size_t)prop_len) == 0) {
3801 			nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
3802 		} else {
3803 			nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
3804 		}
3805 		ddi_prop_free(prop_val);
3806 	} else if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3807 	    "phy-interface", &prop_val,
3808 	    &prop_len) == DDI_PROP_SUCCESS) {
3809 		if (strncmp("pcs", (caddr_t)prop_val, (size_t)prop_len) == 0) {
3810 			nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
3811 		} else {
3812 			nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
3813 		}
3814 		ddi_prop_free(prop_val);
3815 	}
3816 }
3817 
3818 /*
3819  * Static functions start here.
3820  */
3821 
3822 static void
3823 nxge_ldgv_setup(p_nxge_ldg_t *ldgp, p_nxge_ldv_t *ldvp, uint8_t ldv,
3824 	uint8_t endldg, int *ngrps)
3825 {
3826 	NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup"));
3827 	/* Assign the group number for each device. */
3828 	(*ldvp)->ldg_assigned = (*ldgp)->ldg;
3829 	(*ldvp)->ldgp = *ldgp;
3830 	(*ldvp)->ldv = ldv;
3831 
3832 	NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: "
3833 	    "ldv %d endldg %d ldg %d, ldvp $%p",
3834 	    ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp));
3835 
3836 	(*ldgp)->nldvs++;
3837 	if ((*ldgp)->ldg == (endldg - 1)) {
3838 		if ((*ldgp)->ldvp == NULL) {
3839 			(*ldgp)->ldvp = *ldvp;
3840 			*ngrps += 1;
3841 			NXGE_DEBUG_MSG((NULL, INT_CTL,
3842 			    "==> nxge_ldgv_setup: ngrps %d", *ngrps));
3843 		}
3844 		NXGE_DEBUG_MSG((NULL, INT_CTL,
3845 		    "==> nxge_ldgv_setup: ldvp $%p ngrps %d",
3846 		    *ldvp, *ngrps));
3847 		++*ldvp;
3848 	} else {
3849 		(*ldgp)->ldvp = *ldvp;
3850 		*ngrps += 1;
3851 		NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup(done): "
3852 		    "ldv %d endldg %d ldg %d, ldvp $%p",
3853 		    ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp));
3854 		(*ldvp) = ++*ldvp;
3855 		(*ldgp) = ++*ldgp;
3856 		NXGE_DEBUG_MSG((NULL, INT_CTL,
3857 		    "==> nxge_ldgv_setup: new ngrps %d", *ngrps));
3858 	}
3859 
3860 	NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: "
3861 	    "ldv %d ldvp $%p endldg %d ngrps %d",
3862 	    ldv, ldvp, endldg, *ngrps));
3863 
3864 	NXGE_DEBUG_MSG((NULL, INT_CTL, "<== nxge_ldgv_setup"));
3865 }
3866 
3867 /*
3868  * Note: This function assumes the following distribution of mac
3869  * addresses among 4 ports in neptune:
3870  *
3871  *      -------------
3872  *    0|            |0 - local-mac-address for fn 0
3873  *      -------------
3874  *    1|            |1 - local-mac-address for fn 1
3875  *      -------------
3876  *    2|            |2 - local-mac-address for fn 2
3877  *      -------------
3878  *    3|            |3 - local-mac-address for fn 3
3879  *      -------------
3880  *     |            |4 - Start of alt. mac addr. for fn 0
3881  *     |            |
3882  *     |            |
3883  *     |            |10
3884  *     --------------
3885  *     |            |11 - Start of alt. mac addr. for fn 1
3886  *     |            |
3887  *     |            |
3888  *     |            |17
3889  *     --------------
3890  *     |            |18 - Start of alt. mac addr. for fn 2
3891  *     |            |
3892  *     |            |
3893  *     |            |24
3894  *     --------------
3895  *     |            |25 - Start of alt. mac addr. for fn 3
3896  *     |            |
3897  *     |            |
3898  *     |            |31
3899  *     --------------
3900  *
3901  * For N2/NIU the mac addresses is from XAUI card.
3902  *
3903  * When 'compute_addrs' is true, the alternate mac addresses are computed
3904  * using the unique mac address as base. Otherwise the alternate addresses
3905  * are assigned from the list read off the 'mac-addresses' property.
3906  */
3907 
3908 static void
3909 nxge_init_mmac(p_nxge_t nxgep, boolean_t compute_addrs)
3910 {
3911 	int slot;
3912 	uint8_t func_num;
3913 	uint16_t *base_mmac_addr;
3914 	uint32_t alt_mac_ls4b;
3915 	uint16_t *mmac_addr;
3916 	uint32_t base_mac_ls4b; /* least significant 4 bytes */
3917 	nxge_mmac_t *mmac_info;
3918 	npi_mac_addr_t mac_addr;
3919 
3920 	func_num = nxgep->function_num;
3921 	base_mmac_addr = (uint16_t *)&nxgep->factaddr;
3922 	mmac_info = (nxge_mmac_t *)&nxgep->nxge_mmac_info;
3923 
3924 	if (compute_addrs) {
3925 		base_mac_ls4b = ((uint32_t)base_mmac_addr[1]) << 16 |
3926 		    base_mmac_addr[2];
3927 
3928 		if (nxgep->niu_type == N2_NIU) {
3929 			/* ls4b of 1st altmac */
3930 			alt_mac_ls4b = base_mac_ls4b + 1;
3931 		} else {			/* Neptune */
3932 			alt_mac_ls4b = base_mac_ls4b +
3933 			    (nxgep->nports - func_num) +
3934 			    (func_num * (mmac_info->num_factory_mmac));
3935 		}
3936 	}
3937 
3938 	/* Set flags for unique MAC */
3939 	mmac_info->mac_pool[0].flags |= MMAC_SLOT_USED | MMAC_VENDOR_ADDR;
3940 
3941 	/* Clear flags of all alternate MAC slots */
3942 	for (slot = 1; slot <= mmac_info->num_mmac; slot++) {
3943 		if (slot <= mmac_info->num_factory_mmac)
3944 			mmac_info->mac_pool[slot].flags = MMAC_VENDOR_ADDR;
3945 		else
3946 			mmac_info->mac_pool[slot].flags = 0;
3947 	}
3948 
3949 	/* Generate and store factory alternate MACs */
3950 	for (slot = 1; slot <= mmac_info->num_factory_mmac; slot++) {
3951 		mmac_addr = (uint16_t *)&mmac_info->factory_mac_pool[slot];
3952 		if (compute_addrs) {
3953 			mmac_addr[0] = base_mmac_addr[0];
3954 			mac_addr.w2 = mmac_addr[0];
3955 
3956 			mmac_addr[1] = (alt_mac_ls4b >> 16) & 0x0FFFF;
3957 			mac_addr.w1 = mmac_addr[1];
3958 
3959 			mmac_addr[2] = alt_mac_ls4b & 0x0FFFF;
3960 			mac_addr.w0 = mmac_addr[2];
3961 
3962 			alt_mac_ls4b++;
3963 		} else {
3964 			mac_addr.w2 = mmac_addr[0];
3965 			mac_addr.w1 = mmac_addr[1];
3966 			mac_addr.w0 = mmac_addr[2];
3967 		}
3968 
3969 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
3970 		    "mac_pool_addr[%2x:%2x:%2x:%2x:%2x:%2x] npi_addr[%x%x%x]",
3971 		    mmac_info->factory_mac_pool[slot][0],
3972 		    mmac_info->factory_mac_pool[slot][1],
3973 		    mmac_info->factory_mac_pool[slot][2],
3974 		    mmac_info->factory_mac_pool[slot][3],
3975 		    mmac_info->factory_mac_pool[slot][4],
3976 		    mmac_info->factory_mac_pool[slot][5],
3977 		    mac_addr.w0, mac_addr.w1, mac_addr.w2));
3978 		/*
3979 		 * slot minus 1 because npi_mac_altaddr_entry expects 0
3980 		 * for the first alternate mac address.
3981 		 */
3982 		(void) npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET,
3983 		    NXGE_GET_PORT_NUM(func_num), slot - 1, &mac_addr);
3984 	}
3985 	/* Initialize the first two parameters for mmac kstat */
3986 	nxgep->statsp->mmac_stats.mmac_max_cnt = mmac_info->num_mmac;
3987 	nxgep->statsp->mmac_stats.mmac_avail_cnt = mmac_info->num_mmac;
3988 }
3989 
3990 /*
3991  * Convert an RDC group index into a port ring index.  That is, map
3992  * <groupid> to an index into nxgep->rx_ring_handles.
3993  * (group ring index -> port ring index)
3994  */
3995 int
3996 nxge_get_rxring_index(p_nxge_t nxgep, int groupid, int ringidx)
3997 {
3998 	int			i;
3999 	int			index = 0;
4000 	p_nxge_rdc_grp_t	rdc_grp_p;
4001 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
4002 	p_nxge_hw_pt_cfg_t	p_cfgp;
4003 
4004 	p_dma_cfgp = &nxgep->pt_config;
4005 	p_cfgp = &p_dma_cfgp->hw_config;
4006 
4007 	if (isLDOMguest(nxgep))
4008 		return (ringidx);
4009 
4010 	for (i = 0; i < groupid; i++) {
4011 		rdc_grp_p =
4012 		    &p_dma_cfgp->rdc_grps[p_cfgp->def_mac_rxdma_grpid + i];
4013 		index += rdc_grp_p->max_rdcs;
4014 	}
4015 
4016 	return (index + ringidx);
4017 }
4018