1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/nxge/nxge_impl.h> 27 #include <sys/nxge/nxge_rxdma.h> 28 #include <sys/nxge/nxge_hio.h> 29 30 #if !defined(_BIG_ENDIAN) 31 #include <npi_rx_rd32.h> 32 #endif 33 #include <npi_rx_rd64.h> 34 #include <npi_rx_wr64.h> 35 36 #define NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp) \ 37 (rdcgrp + nxgep->pt_config.hw_config.def_mac_rxdma_grpid) 38 #define NXGE_ACTUAL_RDC(nxgep, rdc) \ 39 (rdc + nxgep->pt_config.hw_config.start_rdc) 40 41 /* 42 * XXX: This is a tunable to limit the number of packets each interrupt 43 * handles. 0 (default) means that each interrupt takes as much packets 44 * as it finds. 45 */ 46 extern int nxge_max_intr_pkts; 47 48 /* 49 * Globals: tunable parameters (/etc/system or adb) 50 * 51 */ 52 extern uint32_t nxge_rbr_size; 53 extern uint32_t nxge_rcr_size; 54 extern uint32_t nxge_rbr_spare_size; 55 56 extern uint32_t nxge_mblks_pending; 57 58 /* 59 * Tunable to reduce the amount of time spent in the 60 * ISR doing Rx Processing. 61 */ 62 extern uint32_t nxge_max_rx_pkts; 63 boolean_t nxge_jumbo_enable; 64 65 /* 66 * Tunables to manage the receive buffer blocks. 67 * 68 * nxge_rx_threshold_hi: copy all buffers. 69 * nxge_rx_bcopy_size_type: receive buffer block size type. 70 * nxge_rx_threshold_lo: copy only up to tunable block size type. 71 */ 72 extern nxge_rxbuf_threshold_t nxge_rx_threshold_hi; 73 extern nxge_rxbuf_type_t nxge_rx_buf_size_type; 74 extern nxge_rxbuf_threshold_t nxge_rx_threshold_lo; 75 76 extern uint32_t nxge_cksum_offload; 77 78 static nxge_status_t nxge_map_rxdma(p_nxge_t, int); 79 static void nxge_unmap_rxdma(p_nxge_t, int); 80 81 static nxge_status_t nxge_rxdma_hw_start_common(p_nxge_t); 82 83 static nxge_status_t nxge_rxdma_hw_start(p_nxge_t, int); 84 static void nxge_rxdma_hw_stop(p_nxge_t, int); 85 86 static nxge_status_t nxge_map_rxdma_channel(p_nxge_t, uint16_t, 87 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 88 uint32_t, 89 p_nxge_dma_common_t *, p_rx_rcr_ring_t *, 90 p_rx_mbox_t *); 91 static void nxge_unmap_rxdma_channel(p_nxge_t, uint16_t, 92 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 93 94 static nxge_status_t nxge_map_rxdma_channel_cfg_ring(p_nxge_t, 95 uint16_t, 96 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 97 p_rx_rcr_ring_t *, p_rx_mbox_t *); 98 static void nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t, 99 p_rx_rcr_ring_t, p_rx_mbox_t); 100 101 static nxge_status_t nxge_map_rxdma_channel_buf_ring(p_nxge_t, 102 uint16_t, 103 p_nxge_dma_common_t *, 104 p_rx_rbr_ring_t *, uint32_t); 105 static void nxge_unmap_rxdma_channel_buf_ring(p_nxge_t, 106 p_rx_rbr_ring_t); 107 108 static nxge_status_t nxge_rxdma_start_channel(p_nxge_t, uint16_t, 109 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 110 static nxge_status_t nxge_rxdma_stop_channel(p_nxge_t, uint16_t); 111 112 static mblk_t * 113 nxge_rx_pkts(p_nxge_t, p_rx_rcr_ring_t, rx_dma_ctl_stat_t, int); 114 115 static void nxge_receive_packet(p_nxge_t, 116 p_rx_rcr_ring_t, 117 p_rcr_entry_t, 118 boolean_t *, 119 mblk_t **, mblk_t **); 120 121 nxge_status_t nxge_disable_rxdma_channel(p_nxge_t, uint16_t); 122 123 static p_rx_msg_t nxge_allocb(size_t, uint32_t, p_nxge_dma_common_t); 124 static void nxge_freeb(p_rx_msg_t); 125 static mblk_t *nxge_rx_pkts_vring(p_nxge_t, uint_t, rx_dma_ctl_stat_t); 126 static nxge_status_t nxge_rx_err_evnts(p_nxge_t, int, rx_dma_ctl_stat_t); 127 128 static nxge_status_t nxge_rxdma_handle_port_errors(p_nxge_t, 129 uint32_t, uint32_t); 130 131 static nxge_status_t nxge_rxbuf_index_info_init(p_nxge_t, 132 p_rx_rbr_ring_t); 133 134 135 static nxge_status_t 136 nxge_rxdma_fatal_err_recover(p_nxge_t, uint16_t); 137 138 nxge_status_t 139 nxge_rx_port_fatal_err_recover(p_nxge_t); 140 141 static void nxge_rxdma_databuf_free(p_rx_rbr_ring_t); 142 143 nxge_status_t 144 nxge_init_rxdma_channels(p_nxge_t nxgep) 145 { 146 nxge_grp_set_t *set = &nxgep->rx_set; 147 int i, count, channel; 148 nxge_grp_t *group; 149 dc_map_t map; 150 int dev_gindex; 151 152 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_init_rxdma_channels")); 153 154 if (!isLDOMguest(nxgep)) { 155 if (nxge_rxdma_hw_start_common(nxgep) != NXGE_OK) { 156 cmn_err(CE_NOTE, "hw_start_common"); 157 return (NXGE_ERROR); 158 } 159 } 160 161 /* 162 * NXGE_LOGICAL_GROUP_MAX > NXGE_MAX_RDC_GROUPS (8) 163 * We only have 8 hardware RDC tables, but we may have 164 * up to 16 logical (software-defined) groups of RDCS, 165 * if we make use of layer 3 & 4 hardware classification. 166 */ 167 for (i = 0, count = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) { 168 if ((1 << i) & set->lg.map) { 169 group = set->group[i]; 170 dev_gindex = 171 nxgep->pt_config.hw_config.def_mac_rxdma_grpid + i; 172 map = nxgep->pt_config.rdc_grps[dev_gindex].map; 173 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { 174 if ((1 << channel) & map) { 175 if ((nxge_grp_dc_add(nxgep, 176 group, VP_BOUND_RX, channel))) 177 goto init_rxdma_channels_exit; 178 } 179 } 180 } 181 if (++count == set->lg.count) 182 break; 183 } 184 185 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels")); 186 return (NXGE_OK); 187 188 init_rxdma_channels_exit: 189 for (i = 0, count = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) { 190 if ((1 << i) & set->lg.map) { 191 group = set->group[i]; 192 dev_gindex = 193 nxgep->pt_config.hw_config.def_mac_rxdma_grpid + i; 194 map = nxgep->pt_config.rdc_grps[dev_gindex].map; 195 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { 196 if ((1 << channel) & map) { 197 nxge_grp_dc_remove(nxgep, 198 VP_BOUND_RX, channel); 199 } 200 } 201 } 202 if (++count == set->lg.count) 203 break; 204 } 205 206 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels")); 207 return (NXGE_ERROR); 208 } 209 210 nxge_status_t 211 nxge_init_rxdma_channel(p_nxge_t nxge, int channel) 212 { 213 nxge_status_t status; 214 215 NXGE_DEBUG_MSG((nxge, MEM2_CTL, "==> nxge_init_rxdma_channel")); 216 217 status = nxge_map_rxdma(nxge, channel); 218 if (status != NXGE_OK) { 219 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 220 "<== nxge_init_rxdma: status 0x%x", status)); 221 return (status); 222 } 223 224 #if defined(sun4v) 225 if (isLDOMguest(nxge)) { 226 /* set rcr_ring */ 227 p_rx_rcr_ring_t ring = nxge->rx_rcr_rings->rcr_rings[channel]; 228 229 status = nxge_hio_rxdma_bind_intr(nxge, ring, channel); 230 if (status != NXGE_OK) { 231 nxge_unmap_rxdma(nxge, channel); 232 return (status); 233 } 234 } 235 #endif 236 237 status = nxge_rxdma_hw_start(nxge, channel); 238 if (status != NXGE_OK) { 239 nxge_unmap_rxdma(nxge, channel); 240 } 241 242 if (!nxge->statsp->rdc_ksp[channel]) 243 nxge_setup_rdc_kstats(nxge, channel); 244 245 NXGE_DEBUG_MSG((nxge, MEM2_CTL, 246 "<== nxge_init_rxdma_channel: status 0x%x", status)); 247 248 return (status); 249 } 250 251 void 252 nxge_uninit_rxdma_channels(p_nxge_t nxgep) 253 { 254 nxge_grp_set_t *set = &nxgep->rx_set; 255 int rdc; 256 257 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channels")); 258 259 if (set->owned.map == 0) { 260 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 261 "nxge_uninit_rxdma_channels: no channels")); 262 return; 263 } 264 265 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 266 if ((1 << rdc) & set->owned.map) { 267 nxge_grp_dc_remove(nxgep, VP_BOUND_RX, rdc); 268 } 269 } 270 271 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uninit_rxdma_channels")); 272 } 273 274 void 275 nxge_uninit_rxdma_channel(p_nxge_t nxgep, int channel) 276 { 277 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channel")); 278 279 if (nxgep->statsp->rdc_ksp[channel]) { 280 kstat_delete(nxgep->statsp->rdc_ksp[channel]); 281 nxgep->statsp->rdc_ksp[channel] = 0; 282 } 283 284 nxge_rxdma_hw_stop(nxgep, channel); 285 nxge_unmap_rxdma(nxgep, channel); 286 287 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uinit_rxdma_channel")); 288 } 289 290 nxge_status_t 291 nxge_reset_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 292 { 293 npi_handle_t handle; 294 npi_status_t rs = NPI_SUCCESS; 295 nxge_status_t status = NXGE_OK; 296 297 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_reset_rxdma_channel")); 298 299 handle = NXGE_DEV_NPI_HANDLE(nxgep); 300 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 301 302 if (rs != NPI_SUCCESS) { 303 status = NXGE_ERROR | rs; 304 } 305 306 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_reset_rxdma_channel")); 307 308 return (status); 309 } 310 311 void 312 nxge_rxdma_regs_dump_channels(p_nxge_t nxgep) 313 { 314 nxge_grp_set_t *set = &nxgep->rx_set; 315 int rdc; 316 317 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_regs_dump_channels")); 318 319 if (!isLDOMguest(nxgep)) { 320 npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 321 (void) npi_rxdma_dump_fzc_regs(handle); 322 } 323 324 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 325 NXGE_DEBUG_MSG((nxgep, TX_CTL, 326 "nxge_rxdma_regs_dump_channels: " 327 "NULL ring pointer(s)")); 328 return; 329 } 330 331 if (set->owned.map == 0) { 332 NXGE_DEBUG_MSG((nxgep, RX_CTL, 333 "nxge_rxdma_regs_dump_channels: no channels")); 334 return; 335 } 336 337 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 338 if ((1 << rdc) & set->owned.map) { 339 rx_rbr_ring_t *ring = 340 nxgep->rx_rbr_rings->rbr_rings[rdc]; 341 if (ring) { 342 (void) nxge_dump_rxdma_channel(nxgep, rdc); 343 } 344 } 345 } 346 347 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_regs_dump")); 348 } 349 350 nxge_status_t 351 nxge_dump_rxdma_channel(p_nxge_t nxgep, uint8_t channel) 352 { 353 npi_handle_t handle; 354 npi_status_t rs = NPI_SUCCESS; 355 nxge_status_t status = NXGE_OK; 356 357 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_dump_rxdma_channel")); 358 359 handle = NXGE_DEV_NPI_HANDLE(nxgep); 360 rs = npi_rxdma_dump_rdc_regs(handle, channel); 361 362 if (rs != NPI_SUCCESS) { 363 status = NXGE_ERROR | rs; 364 } 365 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dump_rxdma_channel")); 366 return (status); 367 } 368 369 nxge_status_t 370 nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep, uint16_t channel, 371 p_rx_dma_ent_msk_t mask_p) 372 { 373 npi_handle_t handle; 374 npi_status_t rs = NPI_SUCCESS; 375 nxge_status_t status = NXGE_OK; 376 377 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 378 "<== nxge_init_rxdma_channel_event_mask")); 379 380 handle = NXGE_DEV_NPI_HANDLE(nxgep); 381 rs = npi_rxdma_event_mask(handle, OP_SET, channel, mask_p); 382 if (rs != NPI_SUCCESS) { 383 status = NXGE_ERROR | rs; 384 } 385 386 return (status); 387 } 388 389 nxge_status_t 390 nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep, uint16_t channel, 391 p_rx_dma_ctl_stat_t cs_p) 392 { 393 npi_handle_t handle; 394 npi_status_t rs = NPI_SUCCESS; 395 nxge_status_t status = NXGE_OK; 396 397 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 398 "<== nxge_init_rxdma_channel_cntl_stat")); 399 400 handle = NXGE_DEV_NPI_HANDLE(nxgep); 401 rs = npi_rxdma_control_status(handle, OP_SET, channel, cs_p); 402 403 if (rs != NPI_SUCCESS) { 404 status = NXGE_ERROR | rs; 405 } 406 407 return (status); 408 } 409 410 /* 411 * nxge_rxdma_cfg_rdcgrp_default_rdc 412 * 413 * Set the default RDC for an RDC Group (Table) 414 * 415 * Arguments: 416 * nxgep 417 * rdcgrp The group to modify 418 * rdc The new default RDC. 419 * 420 * Notes: 421 * 422 * NPI/NXGE function calls: 423 * npi_rxdma_cfg_rdc_table_default_rdc() 424 * 425 * Registers accessed: 426 * RDC_TBL_REG: FZC_ZCP + 0x10000 427 * 428 * Context: 429 * Service domain 430 */ 431 nxge_status_t 432 nxge_rxdma_cfg_rdcgrp_default_rdc( 433 p_nxge_t nxgep, 434 uint8_t rdcgrp, 435 uint8_t rdc) 436 { 437 npi_handle_t handle; 438 npi_status_t rs = NPI_SUCCESS; 439 p_nxge_dma_pt_cfg_t p_dma_cfgp; 440 p_nxge_rdc_grp_t rdc_grp_p; 441 uint8_t actual_rdcgrp, actual_rdc; 442 443 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 444 " ==> nxge_rxdma_cfg_rdcgrp_default_rdc")); 445 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 446 447 handle = NXGE_DEV_NPI_HANDLE(nxgep); 448 449 /* 450 * This has to be rewritten. Do we even allow this anymore? 451 */ 452 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdcgrp]; 453 RDC_MAP_IN(rdc_grp_p->map, rdc); 454 rdc_grp_p->def_rdc = rdc; 455 456 actual_rdcgrp = NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp); 457 actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc); 458 459 rs = npi_rxdma_cfg_rdc_table_default_rdc( 460 handle, actual_rdcgrp, actual_rdc); 461 462 if (rs != NPI_SUCCESS) { 463 return (NXGE_ERROR | rs); 464 } 465 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 466 " <== nxge_rxdma_cfg_rdcgrp_default_rdc")); 467 return (NXGE_OK); 468 } 469 470 nxge_status_t 471 nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep, uint8_t port, uint8_t rdc) 472 { 473 npi_handle_t handle; 474 475 uint8_t actual_rdc; 476 npi_status_t rs = NPI_SUCCESS; 477 478 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 479 " ==> nxge_rxdma_cfg_port_default_rdc")); 480 481 handle = NXGE_DEV_NPI_HANDLE(nxgep); 482 actual_rdc = rdc; /* XXX Hack! */ 483 rs = npi_rxdma_cfg_default_port_rdc(handle, port, actual_rdc); 484 485 486 if (rs != NPI_SUCCESS) { 487 return (NXGE_ERROR | rs); 488 } 489 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 490 " <== nxge_rxdma_cfg_port_default_rdc")); 491 492 return (NXGE_OK); 493 } 494 495 nxge_status_t 496 nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep, uint8_t channel, 497 uint16_t pkts) 498 { 499 npi_status_t rs = NPI_SUCCESS; 500 npi_handle_t handle; 501 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 502 " ==> nxge_rxdma_cfg_rcr_threshold")); 503 handle = NXGE_DEV_NPI_HANDLE(nxgep); 504 505 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, pkts); 506 507 if (rs != NPI_SUCCESS) { 508 return (NXGE_ERROR | rs); 509 } 510 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_threshold")); 511 return (NXGE_OK); 512 } 513 514 nxge_status_t 515 nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep, uint8_t channel, 516 uint16_t tout, uint8_t enable) 517 { 518 npi_status_t rs = NPI_SUCCESS; 519 npi_handle_t handle; 520 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " ==> nxge_rxdma_cfg_rcr_timeout")); 521 handle = NXGE_DEV_NPI_HANDLE(nxgep); 522 if (enable == 0) { 523 rs = npi_rxdma_cfg_rdc_rcr_timeout_disable(handle, channel); 524 } else { 525 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 526 tout); 527 } 528 529 if (rs != NPI_SUCCESS) { 530 return (NXGE_ERROR | rs); 531 } 532 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_timeout")); 533 return (NXGE_OK); 534 } 535 536 nxge_status_t 537 nxge_enable_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 538 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 539 { 540 npi_handle_t handle; 541 rdc_desc_cfg_t rdc_desc; 542 p_rcrcfig_b_t cfgb_p; 543 npi_status_t rs = NPI_SUCCESS; 544 545 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel")); 546 handle = NXGE_DEV_NPI_HANDLE(nxgep); 547 /* 548 * Use configuration data composed at init time. 549 * Write to hardware the receive ring configurations. 550 */ 551 rdc_desc.mbox_enable = 1; 552 rdc_desc.mbox_addr = mbox_p->mbox_addr; 553 NXGE_DEBUG_MSG((nxgep, RX_CTL, 554 "==> nxge_enable_rxdma_channel: mboxp $%p($%p)", 555 mbox_p->mbox_addr, rdc_desc.mbox_addr)); 556 557 rdc_desc.rbr_len = rbr_p->rbb_max; 558 rdc_desc.rbr_addr = rbr_p->rbr_addr; 559 560 switch (nxgep->rx_bksize_code) { 561 case RBR_BKSIZE_4K: 562 rdc_desc.page_size = SIZE_4KB; 563 break; 564 case RBR_BKSIZE_8K: 565 rdc_desc.page_size = SIZE_8KB; 566 break; 567 case RBR_BKSIZE_16K: 568 rdc_desc.page_size = SIZE_16KB; 569 break; 570 case RBR_BKSIZE_32K: 571 rdc_desc.page_size = SIZE_32KB; 572 break; 573 } 574 575 rdc_desc.size0 = rbr_p->npi_pkt_buf_size0; 576 rdc_desc.valid0 = 1; 577 578 rdc_desc.size1 = rbr_p->npi_pkt_buf_size1; 579 rdc_desc.valid1 = 1; 580 581 rdc_desc.size2 = rbr_p->npi_pkt_buf_size2; 582 rdc_desc.valid2 = 1; 583 584 rdc_desc.full_hdr = rcr_p->full_hdr_flag; 585 rdc_desc.offset = rcr_p->sw_priv_hdr_len; 586 587 rdc_desc.rcr_len = rcr_p->comp_size; 588 rdc_desc.rcr_addr = rcr_p->rcr_addr; 589 590 cfgb_p = &(rcr_p->rcr_cfgb); 591 rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres; 592 /* For now, disable this timeout in a guest domain. */ 593 if (isLDOMguest(nxgep)) { 594 rdc_desc.rcr_timeout = 0; 595 rdc_desc.rcr_timeout_enable = 0; 596 } else { 597 rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout; 598 rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout; 599 } 600 601 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 602 "rbr_len qlen %d pagesize code %d rcr_len %d", 603 rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 604 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 605 "size 0 %d size 1 %d size 2 %d", 606 rbr_p->npi_pkt_buf_size0, rbr_p->npi_pkt_buf_size1, 607 rbr_p->npi_pkt_buf_size2)); 608 609 rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, &rdc_desc); 610 if (rs != NPI_SUCCESS) { 611 return (NXGE_ERROR | rs); 612 } 613 614 /* 615 * Enable the timeout and threshold. 616 */ 617 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 618 rdc_desc.rcr_threshold); 619 if (rs != NPI_SUCCESS) { 620 return (NXGE_ERROR | rs); 621 } 622 623 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 624 rdc_desc.rcr_timeout); 625 if (rs != NPI_SUCCESS) { 626 return (NXGE_ERROR | rs); 627 } 628 629 /* Enable the DMA */ 630 rs = npi_rxdma_cfg_rdc_enable(handle, channel); 631 if (rs != NPI_SUCCESS) { 632 return (NXGE_ERROR | rs); 633 } 634 635 /* Kick the DMA engine. */ 636 npi_rxdma_rdc_rbr_kick(handle, channel, rbr_p->rbb_max); 637 /* Clear the rbr empty bit */ 638 (void) npi_rxdma_channel_rbr_empty_clear(handle, channel); 639 640 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_enable_rxdma_channel")); 641 642 return (NXGE_OK); 643 } 644 645 nxge_status_t 646 nxge_disable_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 647 { 648 npi_handle_t handle; 649 npi_status_t rs = NPI_SUCCESS; 650 651 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_disable_rxdma_channel")); 652 handle = NXGE_DEV_NPI_HANDLE(nxgep); 653 654 /* disable the DMA */ 655 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 656 if (rs != NPI_SUCCESS) { 657 NXGE_DEBUG_MSG((nxgep, RX_CTL, 658 "<== nxge_disable_rxdma_channel:failed (0x%x)", 659 rs)); 660 return (NXGE_ERROR | rs); 661 } 662 663 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_disable_rxdma_channel")); 664 return (NXGE_OK); 665 } 666 667 nxge_status_t 668 nxge_rxdma_channel_rcrflush(p_nxge_t nxgep, uint8_t channel) 669 { 670 npi_handle_t handle; 671 nxge_status_t status = NXGE_OK; 672 673 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 674 "<== nxge_init_rxdma_channel_rcrflush")); 675 676 handle = NXGE_DEV_NPI_HANDLE(nxgep); 677 npi_rxdma_rdc_rcr_flush(handle, channel); 678 679 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 680 "<== nxge_init_rxdma_channel_rcrflsh")); 681 return (status); 682 683 } 684 685 #define MID_INDEX(l, r) ((r + l + 1) >> 1) 686 687 #define TO_LEFT -1 688 #define TO_RIGHT 1 689 #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 690 #define BOTH_LEFT (TO_LEFT + TO_LEFT) 691 #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 692 #define NO_HINT 0xffffffff 693 694 /*ARGSUSED*/ 695 nxge_status_t 696 nxge_rxbuf_pp_to_vp(p_nxge_t nxgep, p_rx_rbr_ring_t rbr_p, 697 uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 698 uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 699 { 700 int bufsize; 701 uint64_t pktbuf_pp; 702 uint64_t dvma_addr; 703 rxring_info_t *ring_info; 704 int base_side, end_side; 705 int r_index, l_index, anchor_index; 706 int found, search_done; 707 uint32_t offset, chunk_size, block_size, page_size_mask; 708 uint32_t chunk_index, block_index, total_index; 709 int max_iterations, iteration; 710 rxbuf_index_info_t *bufinfo; 711 712 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_rxbuf_pp_to_vp")); 713 714 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 715 "==> nxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 716 pkt_buf_addr_pp, 717 pktbufsz_type)); 718 #if defined(__i386) 719 pktbuf_pp = (uint64_t)(uint32_t)pkt_buf_addr_pp; 720 #else 721 pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 722 #endif 723 724 switch (pktbufsz_type) { 725 case 0: 726 bufsize = rbr_p->pkt_buf_size0; 727 break; 728 case 1: 729 bufsize = rbr_p->pkt_buf_size1; 730 break; 731 case 2: 732 bufsize = rbr_p->pkt_buf_size2; 733 break; 734 case RCR_SINGLE_BLOCK: 735 bufsize = 0; 736 anchor_index = 0; 737 break; 738 default: 739 return (NXGE_ERROR); 740 } 741 742 if (rbr_p->num_blocks == 1) { 743 anchor_index = 0; 744 ring_info = rbr_p->ring_info; 745 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 746 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 747 "==> nxge_rxbuf_pp_to_vp: (found, 1 block) " 748 "buf_pp $%p btype %d anchor_index %d " 749 "bufinfo $%p", 750 pkt_buf_addr_pp, 751 pktbufsz_type, 752 anchor_index, 753 bufinfo)); 754 755 goto found_index; 756 } 757 758 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 759 "==> nxge_rxbuf_pp_to_vp: " 760 "buf_pp $%p btype %d anchor_index %d", 761 pkt_buf_addr_pp, 762 pktbufsz_type, 763 anchor_index)); 764 765 ring_info = rbr_p->ring_info; 766 found = B_FALSE; 767 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 768 iteration = 0; 769 max_iterations = ring_info->max_iterations; 770 /* 771 * First check if this block has been seen 772 * recently. This is indicated by a hint which 773 * is initialized when the first buffer of the block 774 * is seen. The hint is reset when the last buffer of 775 * the block has been processed. 776 * As three block sizes are supported, three hints 777 * are kept. The idea behind the hints is that once 778 * the hardware uses a block for a buffer of that 779 * size, it will use it exclusively for that size 780 * and will use it until it is exhausted. It is assumed 781 * that there would a single block being used for the same 782 * buffer sizes at any given time. 783 */ 784 if (ring_info->hint[pktbufsz_type] != NO_HINT) { 785 anchor_index = ring_info->hint[pktbufsz_type]; 786 dvma_addr = bufinfo[anchor_index].dvma_addr; 787 chunk_size = bufinfo[anchor_index].buf_size; 788 if ((pktbuf_pp >= dvma_addr) && 789 (pktbuf_pp < (dvma_addr + chunk_size))) { 790 found = B_TRUE; 791 /* 792 * check if this is the last buffer in the block 793 * If so, then reset the hint for the size; 794 */ 795 796 if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 797 ring_info->hint[pktbufsz_type] = NO_HINT; 798 } 799 } 800 801 if (found == B_FALSE) { 802 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 803 "==> nxge_rxbuf_pp_to_vp: (!found)" 804 "buf_pp $%p btype %d anchor_index %d", 805 pkt_buf_addr_pp, 806 pktbufsz_type, 807 anchor_index)); 808 809 /* 810 * This is the first buffer of the block of this 811 * size. Need to search the whole information 812 * array. 813 * the search algorithm uses a binary tree search 814 * algorithm. It assumes that the information is 815 * already sorted with increasing order 816 * info[0] < info[1] < info[2] .... < info[n-1] 817 * where n is the size of the information array 818 */ 819 r_index = rbr_p->num_blocks - 1; 820 l_index = 0; 821 search_done = B_FALSE; 822 anchor_index = MID_INDEX(r_index, l_index); 823 while (search_done == B_FALSE) { 824 if ((r_index == l_index) || 825 (iteration >= max_iterations)) 826 search_done = B_TRUE; 827 end_side = TO_RIGHT; /* to the right */ 828 base_side = TO_LEFT; /* to the left */ 829 /* read the DVMA address information and sort it */ 830 dvma_addr = bufinfo[anchor_index].dvma_addr; 831 chunk_size = bufinfo[anchor_index].buf_size; 832 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 833 "==> nxge_rxbuf_pp_to_vp: (searching)" 834 "buf_pp $%p btype %d " 835 "anchor_index %d chunk_size %d dvmaaddr $%p", 836 pkt_buf_addr_pp, 837 pktbufsz_type, 838 anchor_index, 839 chunk_size, 840 dvma_addr)); 841 842 if (pktbuf_pp >= dvma_addr) 843 base_side = TO_RIGHT; /* to the right */ 844 if (pktbuf_pp < (dvma_addr + chunk_size)) 845 end_side = TO_LEFT; /* to the left */ 846 847 switch (base_side + end_side) { 848 case IN_MIDDLE: 849 /* found */ 850 found = B_TRUE; 851 search_done = B_TRUE; 852 if ((pktbuf_pp + bufsize) < 853 (dvma_addr + chunk_size)) 854 ring_info->hint[pktbufsz_type] = 855 bufinfo[anchor_index].buf_index; 856 break; 857 case BOTH_RIGHT: 858 /* not found: go to the right */ 859 l_index = anchor_index + 1; 860 anchor_index = MID_INDEX(r_index, l_index); 861 break; 862 863 case BOTH_LEFT: 864 /* not found: go to the left */ 865 r_index = anchor_index - 1; 866 anchor_index = MID_INDEX(r_index, l_index); 867 break; 868 default: /* should not come here */ 869 return (NXGE_ERROR); 870 } 871 iteration++; 872 } 873 874 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 875 "==> nxge_rxbuf_pp_to_vp: (search done)" 876 "buf_pp $%p btype %d anchor_index %d", 877 pkt_buf_addr_pp, 878 pktbufsz_type, 879 anchor_index)); 880 } 881 882 if (found == B_FALSE) { 883 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 884 "==> nxge_rxbuf_pp_to_vp: (search failed)" 885 "buf_pp $%p btype %d anchor_index %d", 886 pkt_buf_addr_pp, 887 pktbufsz_type, 888 anchor_index)); 889 return (NXGE_ERROR); 890 } 891 892 found_index: 893 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 894 "==> nxge_rxbuf_pp_to_vp: (FOUND1)" 895 "buf_pp $%p btype %d bufsize %d anchor_index %d", 896 pkt_buf_addr_pp, 897 pktbufsz_type, 898 bufsize, 899 anchor_index)); 900 901 /* index of the first block in this chunk */ 902 chunk_index = bufinfo[anchor_index].start_index; 903 dvma_addr = bufinfo[anchor_index].dvma_addr; 904 page_size_mask = ring_info->block_size_mask; 905 906 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 907 "==> nxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 908 "buf_pp $%p btype %d bufsize %d " 909 "anchor_index %d chunk_index %d dvma $%p", 910 pkt_buf_addr_pp, 911 pktbufsz_type, 912 bufsize, 913 anchor_index, 914 chunk_index, 915 dvma_addr)); 916 917 offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 918 block_size = rbr_p->block_size; /* System block(page) size */ 919 920 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 921 "==> nxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 922 "buf_pp $%p btype %d bufsize %d " 923 "anchor_index %d chunk_index %d dvma $%p " 924 "offset %d block_size %d", 925 pkt_buf_addr_pp, 926 pktbufsz_type, 927 bufsize, 928 anchor_index, 929 chunk_index, 930 dvma_addr, 931 offset, 932 block_size)); 933 934 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> getting total index")); 935 936 block_index = (offset / block_size); /* index within chunk */ 937 total_index = chunk_index + block_index; 938 939 940 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 941 "==> nxge_rxbuf_pp_to_vp: " 942 "total_index %d dvma_addr $%p " 943 "offset %d block_size %d " 944 "block_index %d ", 945 total_index, dvma_addr, 946 offset, block_size, 947 block_index)); 948 #if defined(__i386) 949 *pkt_buf_addr_p = (uint64_t *)((uint32_t)bufinfo[anchor_index].kaddr + 950 (uint32_t)offset); 951 #else 952 *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr + 953 (uint64_t)offset); 954 #endif 955 956 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 957 "==> nxge_rxbuf_pp_to_vp: " 958 "total_index %d dvma_addr $%p " 959 "offset %d block_size %d " 960 "block_index %d " 961 "*pkt_buf_addr_p $%p", 962 total_index, dvma_addr, 963 offset, block_size, 964 block_index, 965 *pkt_buf_addr_p)); 966 967 968 *msg_index = total_index; 969 *bufoffset = (offset & page_size_mask); 970 971 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 972 "==> nxge_rxbuf_pp_to_vp: get msg index: " 973 "msg_index %d bufoffset_index %d", 974 *msg_index, 975 *bufoffset)); 976 977 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rxbuf_pp_to_vp")); 978 979 return (NXGE_OK); 980 } 981 982 /* 983 * used by quick sort (qsort) function 984 * to perform comparison 985 */ 986 static int 987 nxge_sort_compare(const void *p1, const void *p2) 988 { 989 990 rxbuf_index_info_t *a, *b; 991 992 a = (rxbuf_index_info_t *)p1; 993 b = (rxbuf_index_info_t *)p2; 994 995 if (a->dvma_addr > b->dvma_addr) 996 return (1); 997 if (a->dvma_addr < b->dvma_addr) 998 return (-1); 999 return (0); 1000 } 1001 1002 1003 1004 /* 1005 * grabbed this sort implementation from common/syscall/avl.c 1006 * 1007 */ 1008 /* 1009 * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 1010 * v = Ptr to array/vector of objs 1011 * n = # objs in the array 1012 * s = size of each obj (must be multiples of a word size) 1013 * f = ptr to function to compare two objs 1014 * returns (-1 = less than, 0 = equal, 1 = greater than 1015 */ 1016 void 1017 nxge_ksort(caddr_t v, int n, int s, int (*f)()) 1018 { 1019 int g, i, j, ii; 1020 unsigned int *p1, *p2; 1021 unsigned int tmp; 1022 1023 /* No work to do */ 1024 if (v == NULL || n <= 1) 1025 return; 1026 /* Sanity check on arguments */ 1027 ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 1028 ASSERT(s > 0); 1029 1030 for (g = n / 2; g > 0; g /= 2) { 1031 for (i = g; i < n; i++) { 1032 for (j = i - g; j >= 0 && 1033 (*f)(v + j * s, v + (j + g) * s) == 1; 1034 j -= g) { 1035 p1 = (unsigned *)(v + j * s); 1036 p2 = (unsigned *)(v + (j + g) * s); 1037 for (ii = 0; ii < s / 4; ii++) { 1038 tmp = *p1; 1039 *p1++ = *p2; 1040 *p2++ = tmp; 1041 } 1042 } 1043 } 1044 } 1045 } 1046 1047 /* 1048 * Initialize data structures required for rxdma 1049 * buffer dvma->vmem address lookup 1050 */ 1051 /*ARGSUSED*/ 1052 static nxge_status_t 1053 nxge_rxbuf_index_info_init(p_nxge_t nxgep, p_rx_rbr_ring_t rbrp) 1054 { 1055 1056 int index; 1057 rxring_info_t *ring_info; 1058 int max_iteration = 0, max_index = 0; 1059 1060 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_rxbuf_index_info_init")); 1061 1062 ring_info = rbrp->ring_info; 1063 ring_info->hint[0] = NO_HINT; 1064 ring_info->hint[1] = NO_HINT; 1065 ring_info->hint[2] = NO_HINT; 1066 max_index = rbrp->num_blocks; 1067 1068 /* read the DVMA address information and sort it */ 1069 /* do init of the information array */ 1070 1071 1072 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 1073 " nxge_rxbuf_index_info_init Sort ptrs")); 1074 1075 /* sort the array */ 1076 nxge_ksort((void *)ring_info->buffer, max_index, 1077 sizeof (rxbuf_index_info_t), nxge_sort_compare); 1078 1079 1080 1081 for (index = 0; index < max_index; index++) { 1082 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 1083 " nxge_rxbuf_index_info_init: sorted chunk %d " 1084 " ioaddr $%p kaddr $%p size %x", 1085 index, ring_info->buffer[index].dvma_addr, 1086 ring_info->buffer[index].kaddr, 1087 ring_info->buffer[index].buf_size)); 1088 } 1089 1090 max_iteration = 0; 1091 while (max_index >= (1ULL << max_iteration)) 1092 max_iteration++; 1093 ring_info->max_iterations = max_iteration + 1; 1094 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 1095 " nxge_rxbuf_index_info_init Find max iter %d", 1096 ring_info->max_iterations)); 1097 1098 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxbuf_index_info_init")); 1099 return (NXGE_OK); 1100 } 1101 1102 /* ARGSUSED */ 1103 void 1104 nxge_dump_rcr_entry(p_nxge_t nxgep, p_rcr_entry_t entry_p) 1105 { 1106 #ifdef NXGE_DEBUG 1107 1108 uint32_t bptr; 1109 uint64_t pp; 1110 1111 bptr = entry_p->bits.hdw.pkt_buf_addr; 1112 1113 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1114 "\trcr entry $%p " 1115 "\trcr entry 0x%0llx " 1116 "\trcr entry 0x%08x " 1117 "\trcr entry 0x%08x " 1118 "\tvalue 0x%0llx\n" 1119 "\tmulti = %d\n" 1120 "\tpkt_type = 0x%x\n" 1121 "\tzero_copy = %d\n" 1122 "\tnoport = %d\n" 1123 "\tpromis = %d\n" 1124 "\terror = 0x%04x\n" 1125 "\tdcf_err = 0x%01x\n" 1126 "\tl2_len = %d\n" 1127 "\tpktbufsize = %d\n" 1128 "\tpkt_buf_addr = $%p\n" 1129 "\tpkt_buf_addr (<< 6) = $%p\n", 1130 entry_p, 1131 *(int64_t *)entry_p, 1132 *(int32_t *)entry_p, 1133 *(int32_t *)((char *)entry_p + 32), 1134 entry_p->value, 1135 entry_p->bits.hdw.multi, 1136 entry_p->bits.hdw.pkt_type, 1137 entry_p->bits.hdw.zero_copy, 1138 entry_p->bits.hdw.noport, 1139 entry_p->bits.hdw.promis, 1140 entry_p->bits.hdw.error, 1141 entry_p->bits.hdw.dcf_err, 1142 entry_p->bits.hdw.l2_len, 1143 entry_p->bits.hdw.pktbufsz, 1144 bptr, 1145 entry_p->bits.ldw.pkt_buf_addr)); 1146 1147 pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 1148 RCR_PKT_BUF_ADDR_SHIFT; 1149 1150 NXGE_DEBUG_MSG((nxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 1151 pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 1152 #endif 1153 } 1154 1155 void 1156 nxge_rxdma_regs_dump(p_nxge_t nxgep, int rdc) 1157 { 1158 npi_handle_t handle; 1159 rbr_stat_t rbr_stat; 1160 addr44_t hd_addr; 1161 addr44_t tail_addr; 1162 uint16_t qlen; 1163 1164 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1165 "==> nxge_rxdma_regs_dump: rdc channel %d", rdc)); 1166 1167 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1168 1169 /* RBR head */ 1170 hd_addr.addr = 0; 1171 (void) npi_rxdma_rdc_rbr_head_get(handle, rdc, &hd_addr); 1172 #if defined(__i386) 1173 printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 1174 (void *)(uint32_t)hd_addr.addr); 1175 #else 1176 printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 1177 (void *)hd_addr.addr); 1178 #endif 1179 1180 /* RBR stats */ 1181 (void) npi_rxdma_rdc_rbr_stat_get(handle, rdc, &rbr_stat); 1182 printf("nxge_rxdma_regs_dump: rbr len %d \n", rbr_stat.bits.ldw.qlen); 1183 1184 /* RCR tail */ 1185 tail_addr.addr = 0; 1186 (void) npi_rxdma_rdc_rcr_tail_get(handle, rdc, &tail_addr); 1187 #if defined(__i386) 1188 printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 1189 (void *)(uint32_t)tail_addr.addr); 1190 #else 1191 printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 1192 (void *)tail_addr.addr); 1193 #endif 1194 1195 /* RCR qlen */ 1196 (void) npi_rxdma_rdc_rcr_qlen_get(handle, rdc, &qlen); 1197 printf("nxge_rxdma_regs_dump: rcr len %x \n", qlen); 1198 1199 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1200 "<== nxge_rxdma_regs_dump: rdc rdc %d", rdc)); 1201 } 1202 1203 nxge_status_t 1204 nxge_rxdma_hw_mode(p_nxge_t nxgep, boolean_t enable) 1205 { 1206 nxge_grp_set_t *set = &nxgep->rx_set; 1207 nxge_status_t status; 1208 npi_status_t rs; 1209 int rdc; 1210 1211 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1212 "==> nxge_rxdma_hw_mode: mode %d", enable)); 1213 1214 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1215 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1216 "<== nxge_rxdma_mode: not initialized")); 1217 return (NXGE_ERROR); 1218 } 1219 1220 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 1221 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1222 "<== nxge_tx_port_fatal_err_recover: " 1223 "NULL ring pointer(s)")); 1224 return (NXGE_ERROR); 1225 } 1226 1227 if (set->owned.map == 0) { 1228 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1229 "nxge_rxdma_regs_dump_channels: no channels")); 1230 return (NULL); 1231 } 1232 1233 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1234 if ((1 << rdc) & set->owned.map) { 1235 rx_rbr_ring_t *ring = 1236 nxgep->rx_rbr_rings->rbr_rings[rdc]; 1237 npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 1238 if (ring) { 1239 if (enable) { 1240 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1241 "==> nxge_rxdma_hw_mode: " 1242 "channel %d (enable)", rdc)); 1243 rs = npi_rxdma_cfg_rdc_enable 1244 (handle, rdc); 1245 } else { 1246 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1247 "==> nxge_rxdma_hw_mode: " 1248 "channel %d disable)", rdc)); 1249 rs = npi_rxdma_cfg_rdc_disable 1250 (handle, rdc); 1251 } 1252 } 1253 } 1254 } 1255 1256 status = ((rs == NPI_SUCCESS) ? NXGE_OK : NXGE_ERROR | rs); 1257 1258 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1259 "<== nxge_rxdma_hw_mode: status 0x%x", status)); 1260 1261 return (status); 1262 } 1263 1264 void 1265 nxge_rxdma_enable_channel(p_nxge_t nxgep, uint16_t channel) 1266 { 1267 npi_handle_t handle; 1268 1269 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1270 "==> nxge_rxdma_enable_channel: channel %d", channel)); 1271 1272 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1273 (void) npi_rxdma_cfg_rdc_enable(handle, channel); 1274 1275 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_enable_channel")); 1276 } 1277 1278 void 1279 nxge_rxdma_disable_channel(p_nxge_t nxgep, uint16_t channel) 1280 { 1281 npi_handle_t handle; 1282 1283 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1284 "==> nxge_rxdma_disable_channel: channel %d", channel)); 1285 1286 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1287 (void) npi_rxdma_cfg_rdc_disable(handle, channel); 1288 1289 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_disable_channel")); 1290 } 1291 1292 void 1293 nxge_hw_start_rx(p_nxge_t nxgep) 1294 { 1295 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_start_rx")); 1296 1297 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 1298 (void) nxge_rx_mac_enable(nxgep); 1299 1300 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_start_rx")); 1301 } 1302 1303 /*ARGSUSED*/ 1304 void 1305 nxge_fixup_rxdma_rings(p_nxge_t nxgep) 1306 { 1307 nxge_grp_set_t *set = &nxgep->rx_set; 1308 int rdc; 1309 1310 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_fixup_rxdma_rings")); 1311 1312 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 1313 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1314 "<== nxge_tx_port_fatal_err_recover: " 1315 "NULL ring pointer(s)")); 1316 return; 1317 } 1318 1319 if (set->owned.map == 0) { 1320 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1321 "nxge_rxdma_regs_dump_channels: no channels")); 1322 return; 1323 } 1324 1325 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1326 if ((1 << rdc) & set->owned.map) { 1327 rx_rbr_ring_t *ring = 1328 nxgep->rx_rbr_rings->rbr_rings[rdc]; 1329 if (ring) { 1330 nxge_rxdma_hw_stop(nxgep, rdc); 1331 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1332 "==> nxge_fixup_rxdma_rings: " 1333 "channel %d ring $%px", 1334 rdc, ring)); 1335 (void) nxge_rxdma_fixup_channel 1336 (nxgep, rdc, rdc); 1337 } 1338 } 1339 } 1340 1341 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_fixup_rxdma_rings")); 1342 } 1343 1344 void 1345 nxge_rxdma_fix_channel(p_nxge_t nxgep, uint16_t channel) 1346 { 1347 int i; 1348 1349 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fix_channel")); 1350 i = nxge_rxdma_get_ring_index(nxgep, channel); 1351 if (i < 0) { 1352 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1353 "<== nxge_rxdma_fix_channel: no entry found")); 1354 return; 1355 } 1356 1357 nxge_rxdma_fixup_channel(nxgep, channel, i); 1358 1359 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fix_channel")); 1360 } 1361 1362 void 1363 nxge_rxdma_fixup_channel(p_nxge_t nxgep, uint16_t channel, int entry) 1364 { 1365 int ndmas; 1366 p_rx_rbr_rings_t rx_rbr_rings; 1367 p_rx_rbr_ring_t *rbr_rings; 1368 p_rx_rcr_rings_t rx_rcr_rings; 1369 p_rx_rcr_ring_t *rcr_rings; 1370 p_rx_mbox_areas_t rx_mbox_areas_p; 1371 p_rx_mbox_t *rx_mbox_p; 1372 p_nxge_dma_pool_t dma_buf_poolp; 1373 p_nxge_dma_pool_t dma_cntl_poolp; 1374 p_rx_rbr_ring_t rbrp; 1375 p_rx_rcr_ring_t rcrp; 1376 p_rx_mbox_t mboxp; 1377 p_nxge_dma_common_t dmap; 1378 nxge_status_t status = NXGE_OK; 1379 1380 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fixup_channel")); 1381 1382 (void) nxge_rxdma_stop_channel(nxgep, channel); 1383 1384 dma_buf_poolp = nxgep->rx_buf_pool_p; 1385 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 1386 1387 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 1388 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1389 "<== nxge_rxdma_fixup_channel: buf not allocated")); 1390 return; 1391 } 1392 1393 ndmas = dma_buf_poolp->ndmas; 1394 if (!ndmas) { 1395 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1396 "<== nxge_rxdma_fixup_channel: no dma allocated")); 1397 return; 1398 } 1399 1400 rx_rbr_rings = nxgep->rx_rbr_rings; 1401 rx_rcr_rings = nxgep->rx_rcr_rings; 1402 rbr_rings = rx_rbr_rings->rbr_rings; 1403 rcr_rings = rx_rcr_rings->rcr_rings; 1404 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 1405 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 1406 1407 /* Reinitialize the receive block and completion rings */ 1408 rbrp = (p_rx_rbr_ring_t)rbr_rings[entry], 1409 rcrp = (p_rx_rcr_ring_t)rcr_rings[entry], 1410 mboxp = (p_rx_mbox_t)rx_mbox_p[entry]; 1411 1412 1413 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 1414 rbrp->rbr_rd_index = 0; 1415 rcrp->comp_rd_index = 0; 1416 rcrp->comp_wt_index = 0; 1417 1418 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 1419 bzero((caddr_t)dmap->kaddrp, dmap->alength); 1420 1421 status = nxge_rxdma_start_channel(nxgep, channel, 1422 rbrp, rcrp, mboxp); 1423 if (status != NXGE_OK) { 1424 goto nxge_rxdma_fixup_channel_fail; 1425 } 1426 if (status != NXGE_OK) { 1427 goto nxge_rxdma_fixup_channel_fail; 1428 } 1429 1430 nxge_rxdma_fixup_channel_fail: 1431 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1432 "==> nxge_rxdma_fixup_channel: failed (0x%08x)", status)); 1433 1434 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fixup_channel")); 1435 } 1436 1437 /* 1438 * Convert an absolute RDC number to a Receive Buffer Ring index. That is, 1439 * map <channel> to an index into nxgep->rx_rbr_rings. 1440 * (device ring index -> port ring index) 1441 */ 1442 int 1443 nxge_rxdma_get_ring_index(p_nxge_t nxgep, uint16_t channel) 1444 { 1445 int i, ndmas; 1446 uint16_t rdc; 1447 p_rx_rbr_rings_t rx_rbr_rings; 1448 p_rx_rbr_ring_t *rbr_rings; 1449 1450 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1451 "==> nxge_rxdma_get_ring_index: channel %d", channel)); 1452 1453 rx_rbr_rings = nxgep->rx_rbr_rings; 1454 if (rx_rbr_rings == NULL) { 1455 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1456 "<== nxge_rxdma_get_ring_index: NULL ring pointer")); 1457 return (-1); 1458 } 1459 ndmas = rx_rbr_rings->ndmas; 1460 if (!ndmas) { 1461 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1462 "<== nxge_rxdma_get_ring_index: no channel")); 1463 return (-1); 1464 } 1465 1466 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1467 "==> nxge_rxdma_get_ring_index (ndmas %d)", ndmas)); 1468 1469 rbr_rings = rx_rbr_rings->rbr_rings; 1470 for (i = 0; i < ndmas; i++) { 1471 rdc = rbr_rings[i]->rdc; 1472 if (channel == rdc) { 1473 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1474 "==> nxge_rxdma_get_rbr_ring: channel %d " 1475 "(index %d) ring %d", channel, i, rbr_rings[i])); 1476 return (i); 1477 } 1478 } 1479 1480 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1481 "<== nxge_rxdma_get_rbr_ring_index: not found")); 1482 1483 return (-1); 1484 } 1485 1486 p_rx_rbr_ring_t 1487 nxge_rxdma_get_rbr_ring(p_nxge_t nxgep, uint16_t channel) 1488 { 1489 nxge_grp_set_t *set = &nxgep->rx_set; 1490 nxge_channel_t rdc; 1491 1492 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1493 "==> nxge_rxdma_get_rbr_ring: channel %d", channel)); 1494 1495 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) { 1496 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1497 "<== nxge_rxdma_get_rbr_ring: " 1498 "NULL ring pointer(s)")); 1499 return (NULL); 1500 } 1501 1502 if (set->owned.map == 0) { 1503 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1504 "<== nxge_rxdma_get_rbr_ring: no channels")); 1505 return (NULL); 1506 } 1507 1508 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1509 if ((1 << rdc) & set->owned.map) { 1510 rx_rbr_ring_t *ring = 1511 nxgep->rx_rbr_rings->rbr_rings[rdc]; 1512 if (ring) { 1513 if (channel == ring->rdc) { 1514 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1515 "==> nxge_rxdma_get_rbr_ring: " 1516 "channel %d ring $%p", rdc, ring)); 1517 return (ring); 1518 } 1519 } 1520 } 1521 } 1522 1523 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1524 "<== nxge_rxdma_get_rbr_ring: not found")); 1525 1526 return (NULL); 1527 } 1528 1529 p_rx_rcr_ring_t 1530 nxge_rxdma_get_rcr_ring(p_nxge_t nxgep, uint16_t channel) 1531 { 1532 nxge_grp_set_t *set = &nxgep->rx_set; 1533 nxge_channel_t rdc; 1534 1535 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1536 "==> nxge_rxdma_get_rcr_ring: channel %d", channel)); 1537 1538 if (nxgep->rx_rcr_rings == 0 || nxgep->rx_rcr_rings->rcr_rings == 0) { 1539 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1540 "<== nxge_rxdma_get_rcr_ring: " 1541 "NULL ring pointer(s)")); 1542 return (NULL); 1543 } 1544 1545 if (set->owned.map == 0) { 1546 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1547 "<== nxge_rxdma_get_rbr_ring: no channels")); 1548 return (NULL); 1549 } 1550 1551 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1552 if ((1 << rdc) & set->owned.map) { 1553 rx_rcr_ring_t *ring = 1554 nxgep->rx_rcr_rings->rcr_rings[rdc]; 1555 if (ring) { 1556 if (channel == ring->rdc) { 1557 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1558 "==> nxge_rxdma_get_rcr_ring: " 1559 "channel %d ring $%p", rdc, ring)); 1560 return (ring); 1561 } 1562 } 1563 } 1564 } 1565 1566 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1567 "<== nxge_rxdma_get_rcr_ring: not found")); 1568 1569 return (NULL); 1570 } 1571 1572 /* 1573 * Static functions start here. 1574 */ 1575 static p_rx_msg_t 1576 nxge_allocb(size_t size, uint32_t pri, p_nxge_dma_common_t dmabuf_p) 1577 { 1578 p_rx_msg_t nxge_mp = NULL; 1579 p_nxge_dma_common_t dmamsg_p; 1580 uchar_t *buffer; 1581 1582 nxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 1583 if (nxge_mp == NULL) { 1584 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1585 "Allocation of a rx msg failed.")); 1586 goto nxge_allocb_exit; 1587 } 1588 1589 nxge_mp->use_buf_pool = B_FALSE; 1590 if (dmabuf_p) { 1591 nxge_mp->use_buf_pool = B_TRUE; 1592 dmamsg_p = (p_nxge_dma_common_t)&nxge_mp->buf_dma; 1593 *dmamsg_p = *dmabuf_p; 1594 dmamsg_p->nblocks = 1; 1595 dmamsg_p->block_size = size; 1596 dmamsg_p->alength = size; 1597 buffer = (uchar_t *)dmabuf_p->kaddrp; 1598 1599 dmabuf_p->kaddrp = (void *) 1600 ((char *)dmabuf_p->kaddrp + size); 1601 dmabuf_p->ioaddr_pp = (void *) 1602 ((char *)dmabuf_p->ioaddr_pp + size); 1603 dmabuf_p->alength -= size; 1604 dmabuf_p->offset += size; 1605 dmabuf_p->dma_cookie.dmac_laddress += size; 1606 dmabuf_p->dma_cookie.dmac_size -= size; 1607 1608 } else { 1609 buffer = KMEM_ALLOC(size, KM_NOSLEEP); 1610 if (buffer == NULL) { 1611 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1612 "Allocation of a receive page failed.")); 1613 goto nxge_allocb_fail1; 1614 } 1615 } 1616 1617 nxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &nxge_mp->freeb); 1618 if (nxge_mp->rx_mblk_p == NULL) { 1619 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "desballoc failed.")); 1620 goto nxge_allocb_fail2; 1621 } 1622 1623 nxge_mp->buffer = buffer; 1624 nxge_mp->block_size = size; 1625 nxge_mp->freeb.free_func = (void (*)())nxge_freeb; 1626 nxge_mp->freeb.free_arg = (caddr_t)nxge_mp; 1627 nxge_mp->ref_cnt = 1; 1628 nxge_mp->free = B_TRUE; 1629 nxge_mp->rx_use_bcopy = B_FALSE; 1630 1631 atomic_inc_32(&nxge_mblks_pending); 1632 1633 goto nxge_allocb_exit; 1634 1635 nxge_allocb_fail2: 1636 if (!nxge_mp->use_buf_pool) { 1637 KMEM_FREE(buffer, size); 1638 } 1639 1640 nxge_allocb_fail1: 1641 KMEM_FREE(nxge_mp, sizeof (rx_msg_t)); 1642 nxge_mp = NULL; 1643 1644 nxge_allocb_exit: 1645 return (nxge_mp); 1646 } 1647 1648 p_mblk_t 1649 nxge_dupb(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1650 { 1651 p_mblk_t mp; 1652 1653 NXGE_DEBUG_MSG((NULL, MEM_CTL, "==> nxge_dupb")); 1654 NXGE_DEBUG_MSG((NULL, MEM_CTL, "nxge_mp = $%p " 1655 "offset = 0x%08X " 1656 "size = 0x%08X", 1657 nxge_mp, offset, size)); 1658 1659 mp = desballoc(&nxge_mp->buffer[offset], size, 1660 0, &nxge_mp->freeb); 1661 if (mp == NULL) { 1662 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1663 goto nxge_dupb_exit; 1664 } 1665 atomic_inc_32(&nxge_mp->ref_cnt); 1666 1667 1668 nxge_dupb_exit: 1669 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1670 nxge_mp)); 1671 return (mp); 1672 } 1673 1674 p_mblk_t 1675 nxge_dupb_bcopy(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1676 { 1677 p_mblk_t mp; 1678 uchar_t *dp; 1679 1680 mp = allocb(size + NXGE_RXBUF_EXTRA, 0); 1681 if (mp == NULL) { 1682 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1683 goto nxge_dupb_bcopy_exit; 1684 } 1685 dp = mp->b_rptr = mp->b_rptr + NXGE_RXBUF_EXTRA; 1686 bcopy((void *)&nxge_mp->buffer[offset], dp, size); 1687 mp->b_wptr = dp + size; 1688 1689 nxge_dupb_bcopy_exit: 1690 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1691 nxge_mp)); 1692 return (mp); 1693 } 1694 1695 void nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, 1696 p_rx_msg_t rx_msg_p); 1697 1698 void 1699 nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 1700 { 1701 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_post_page")); 1702 1703 /* Reuse this buffer */ 1704 rx_msg_p->free = B_FALSE; 1705 rx_msg_p->cur_usage_cnt = 0; 1706 rx_msg_p->max_usage_cnt = 0; 1707 rx_msg_p->pkt_buf_size = 0; 1708 1709 if (rx_rbr_p->rbr_use_bcopy) { 1710 rx_msg_p->rx_use_bcopy = B_FALSE; 1711 atomic_dec_32(&rx_rbr_p->rbr_consumed); 1712 } 1713 1714 /* 1715 * Get the rbr header pointer and its offset index. 1716 */ 1717 MUTEX_ENTER(&rx_rbr_p->post_lock); 1718 rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 1719 rx_rbr_p->rbr_wrap_mask); 1720 rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 1721 MUTEX_EXIT(&rx_rbr_p->post_lock); 1722 npi_rxdma_rdc_rbr_kick(NXGE_DEV_NPI_HANDLE(nxgep), 1723 rx_rbr_p->rdc, 1); 1724 1725 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1726 "<== nxge_post_page (channel %d post_next_index %d)", 1727 rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 1728 1729 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_post_page")); 1730 } 1731 1732 void 1733 nxge_freeb(p_rx_msg_t rx_msg_p) 1734 { 1735 size_t size; 1736 uchar_t *buffer = NULL; 1737 int ref_cnt; 1738 boolean_t free_state = B_FALSE; 1739 1740 rx_rbr_ring_t *ring = rx_msg_p->rx_rbr_p; 1741 1742 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> nxge_freeb")); 1743 NXGE_DEBUG_MSG((NULL, MEM2_CTL, 1744 "nxge_freeb:rx_msg_p = $%p (block pending %d)", 1745 rx_msg_p, nxge_mblks_pending)); 1746 1747 /* 1748 * First we need to get the free state, then 1749 * atomic decrement the reference count to prevent 1750 * the race condition with the interrupt thread that 1751 * is processing a loaned up buffer block. 1752 */ 1753 free_state = rx_msg_p->free; 1754 ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 1755 if (!ref_cnt) { 1756 atomic_dec_32(&nxge_mblks_pending); 1757 buffer = rx_msg_p->buffer; 1758 size = rx_msg_p->block_size; 1759 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "nxge_freeb: " 1760 "will free: rx_msg_p = $%p (block pending %d)", 1761 rx_msg_p, nxge_mblks_pending)); 1762 1763 if (!rx_msg_p->use_buf_pool) { 1764 KMEM_FREE(buffer, size); 1765 } 1766 1767 KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1768 1769 if (ring) { 1770 /* 1771 * Decrement the receive buffer ring's reference 1772 * count, too. 1773 */ 1774 atomic_dec_32(&ring->rbr_ref_cnt); 1775 1776 /* 1777 * Free the receive buffer ring, if 1778 * 1. all the receive buffers have been freed 1779 * 2. and we are in the proper state (that is, 1780 * we are not UNMAPPING). 1781 */ 1782 if (ring->rbr_ref_cnt == 0 && 1783 ring->rbr_state == RBR_UNMAPPED) { 1784 /* 1785 * Free receive data buffers, 1786 * buffer index information 1787 * (rxring_info) and 1788 * the message block ring. 1789 */ 1790 NXGE_DEBUG_MSG((NULL, RX_CTL, 1791 "nxge_freeb:rx_msg_p = $%p " 1792 "(block pending %d) free buffers", 1793 rx_msg_p, nxge_mblks_pending)); 1794 nxge_rxdma_databuf_free(ring); 1795 if (ring->ring_info) { 1796 KMEM_FREE(ring->ring_info, 1797 sizeof (rxring_info_t)); 1798 } 1799 1800 if (ring->rx_msg_ring) { 1801 KMEM_FREE(ring->rx_msg_ring, 1802 ring->tnblocks * 1803 sizeof (p_rx_msg_t)); 1804 } 1805 KMEM_FREE(ring, sizeof (*ring)); 1806 } 1807 } 1808 return; 1809 } 1810 1811 /* 1812 * Repost buffer. 1813 */ 1814 if (free_state && (ref_cnt == 1) && ring) { 1815 NXGE_DEBUG_MSG((NULL, RX_CTL, 1816 "nxge_freeb: post page $%p:", rx_msg_p)); 1817 if (ring->rbr_state == RBR_POSTING) 1818 nxge_post_page(rx_msg_p->nxgep, ring, rx_msg_p); 1819 } 1820 1821 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== nxge_freeb")); 1822 } 1823 1824 uint_t 1825 nxge_rx_intr(void *arg1, void *arg2) 1826 { 1827 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 1828 p_nxge_t nxgep = (p_nxge_t)arg2; 1829 p_nxge_ldg_t ldgp; 1830 uint8_t channel; 1831 npi_handle_t handle; 1832 rx_dma_ctl_stat_t cs; 1833 p_rx_rcr_ring_t rcr_ring; 1834 mblk_t *mp; 1835 1836 #ifdef NXGE_DEBUG 1837 rxdma_cfig1_t cfg; 1838 #endif 1839 1840 if (ldvp == NULL) { 1841 NXGE_DEBUG_MSG((NULL, INT_CTL, 1842 "<== nxge_rx_intr: arg2 $%p arg1 $%p", 1843 nxgep, ldvp)); 1844 1845 return (DDI_INTR_CLAIMED); 1846 } 1847 1848 if (arg2 == NULL || (void *)ldvp->nxgep != arg2) { 1849 nxgep = ldvp->nxgep; 1850 } 1851 1852 if ((!(nxgep->drv_state & STATE_HW_INITIALIZED)) || 1853 (nxgep->nxge_mac_state != NXGE_MAC_STARTED)) { 1854 NXGE_DEBUG_MSG((nxgep, INT_CTL, 1855 "<== nxge_rx_intr: interface not started or intialized")); 1856 return (DDI_INTR_CLAIMED); 1857 } 1858 1859 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1860 "==> nxge_rx_intr: arg2 $%p arg1 $%p", 1861 nxgep, ldvp)); 1862 1863 /* 1864 * This interrupt handler is for a specific 1865 * receive dma channel. 1866 */ 1867 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1868 1869 rcr_ring = nxgep->rx_rcr_rings->rcr_rings[ldvp->vdma_index]; 1870 1871 /* 1872 * The RCR ring lock must be held when packets 1873 * are being processed and the hardware registers are 1874 * being read or written to prevent race condition 1875 * among the interrupt thread, the polling thread 1876 * (will cause fatal errors such as rcrincon bit set) 1877 * and the setting of the poll_flag. 1878 */ 1879 MUTEX_ENTER(&rcr_ring->lock); 1880 1881 /* 1882 * Get the control and status for this channel. 1883 */ 1884 channel = ldvp->channel; 1885 ldgp = ldvp->ldgp; 1886 1887 if (!isLDOMguest(nxgep)) { 1888 if (!nxgep->rx_channel_started[channel]) { 1889 NXGE_DEBUG_MSG((nxgep, INT_CTL, 1890 "<== nxge_rx_intr: channel is not started")); 1891 MUTEX_EXIT(&rcr_ring->lock); 1892 return (DDI_INTR_CLAIMED); 1893 } 1894 } 1895 1896 ASSERT(rcr_ring->ldgp == ldgp); 1897 ASSERT(rcr_ring->ldvp == ldvp); 1898 1899 RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, &cs.value); 1900 1901 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_intr:channel %d " 1902 "cs 0x%016llx rcrto 0x%x rcrthres %x", 1903 channel, 1904 cs.value, 1905 cs.bits.hdw.rcrto, 1906 cs.bits.hdw.rcrthres)); 1907 1908 mp = nxge_rx_pkts_vring(nxgep, ldvp->vdma_index, cs); 1909 1910 /* error events. */ 1911 if (cs.value & RX_DMA_CTL_STAT_ERROR) { 1912 (void) nxge_rx_err_evnts(nxgep, channel, cs); 1913 } 1914 1915 /* 1916 * Enable the mailbox update interrupt if we want 1917 * to use mailbox. We probably don't need to use 1918 * mailbox as it only saves us one pio read. 1919 * Also write 1 to rcrthres and rcrto to clear 1920 * these two edge triggered bits. 1921 */ 1922 cs.value &= RX_DMA_CTL_STAT_WR1C; 1923 cs.bits.hdw.mex = rcr_ring->poll_flag ? 0 : 1; 1924 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, 1925 cs.value); 1926 1927 /* 1928 * If the polling mode is enabled, disable the interrupt. 1929 */ 1930 if (rcr_ring->poll_flag) { 1931 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 1932 "==> nxge_rx_intr: rdc %d ldgp $%p ldvp $%p " 1933 "(disabling interrupts)", channel, ldgp, ldvp)); 1934 /* 1935 * Disarm this logical group if this is a single device 1936 * group. 1937 */ 1938 if (ldgp->nldvs == 1) { 1939 ldgimgm_t mgm; 1940 mgm.value = 0; 1941 mgm.bits.ldw.arm = 0; 1942 NXGE_REG_WR64(handle, 1943 LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), mgm.value); 1944 } 1945 } else { 1946 /* 1947 * Rearm this logical group if this is a single device 1948 * group. 1949 */ 1950 if (ldgp->nldvs == 1) { 1951 if (isLDOMguest(nxgep)) { 1952 nxge_hio_ldgimgn(nxgep, ldgp); 1953 } else { 1954 ldgimgm_t mgm; 1955 1956 mgm.value = 0; 1957 mgm.bits.ldw.arm = 1; 1958 mgm.bits.ldw.timer = ldgp->ldg_timer; 1959 1960 NXGE_REG_WR64(handle, 1961 LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 1962 mgm.value); 1963 } 1964 } 1965 1966 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 1967 "==> nxge_rx_intr: rdc %d ldgp $%p " 1968 "exiting ISR (and call mac_rx_ring)", channel, ldgp)); 1969 } 1970 MUTEX_EXIT(&rcr_ring->lock); 1971 1972 if (mp) { 1973 if (!isLDOMguest(nxgep)) 1974 mac_rx_ring(nxgep->mach, rcr_ring->rcr_mac_handle, mp, 1975 rcr_ring->rcr_gen_num); 1976 #if defined(sun4v) 1977 else { /* isLDOMguest(nxgep) */ 1978 nxge_hio_data_t *nhd = (nxge_hio_data_t *) 1979 nxgep->nxge_hw_p->hio; 1980 nx_vio_fp_t *vio = &nhd->hio.vio; 1981 1982 if (vio->cb.vio_net_rx_cb) { 1983 (*vio->cb.vio_net_rx_cb) 1984 (nxgep->hio_vr->vhp, mp); 1985 } 1986 } 1987 #endif 1988 } 1989 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_intr: DDI_INTR_CLAIMED")); 1990 return (DDI_INTR_CLAIMED); 1991 } 1992 1993 /* 1994 * Process the packets received in the specified logical device 1995 * and pass up a chain of message blocks to the upper layer. 1996 * The RCR ring lock must be held before calling this function. 1997 */ 1998 static mblk_t * 1999 nxge_rx_pkts_vring(p_nxge_t nxgep, uint_t vindex, rx_dma_ctl_stat_t cs) 2000 { 2001 p_mblk_t mp; 2002 p_rx_rcr_ring_t rcrp; 2003 2004 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring")); 2005 rcrp = nxgep->rx_rcr_rings->rcr_rings[vindex]; 2006 2007 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2008 "==> nxge_rx_pkts_vring: (calling nxge_rx_pkts)rdc %d " 2009 "rcr_mac_handle $%p ", rcrp->rdc, rcrp->rcr_mac_handle)); 2010 if ((mp = nxge_rx_pkts(nxgep, rcrp, cs, -1)) == NULL) { 2011 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2012 "<== nxge_rx_pkts_vring: no mp")); 2013 return (NULL); 2014 } 2015 2016 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring: $%p", 2017 mp)); 2018 2019 #ifdef NXGE_DEBUG 2020 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2021 "==> nxge_rx_pkts_vring:calling mac_rx " 2022 "LEN %d mp $%p mp->b_cont $%p mp->b_next $%p rcrp $%p " 2023 "mac_handle $%p", 2024 mp->b_wptr - mp->b_rptr, 2025 mp, mp->b_cont, mp->b_next, 2026 rcrp, rcrp->rcr_mac_handle)); 2027 2028 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2029 "==> nxge_rx_pkts_vring: dump packets " 2030 "(mp $%p b_rptr $%p b_wptr $%p):\n %s", 2031 mp, 2032 mp->b_rptr, 2033 mp->b_wptr, 2034 nxge_dump_packet((char *)mp->b_rptr, 2035 mp->b_wptr - mp->b_rptr))); 2036 if (mp->b_cont) { 2037 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2038 "==> nxge_rx_pkts_vring: dump b_cont packets " 2039 "(mp->b_cont $%p b_rptr $%p b_wptr $%p):\n %s", 2040 mp->b_cont, 2041 mp->b_cont->b_rptr, 2042 mp->b_cont->b_wptr, 2043 nxge_dump_packet((char *)mp->b_cont->b_rptr, 2044 mp->b_cont->b_wptr - mp->b_cont->b_rptr))); 2045 } 2046 if (mp->b_next) { 2047 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2048 "==> nxge_rx_pkts_vring: dump next packets " 2049 "(b_rptr $%p): %s", 2050 mp->b_next->b_rptr, 2051 nxge_dump_packet((char *)mp->b_next->b_rptr, 2052 mp->b_next->b_wptr - mp->b_next->b_rptr))); 2053 } 2054 #endif 2055 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2056 "<== nxge_rx_pkts_vring: returning rdc %d rcr_mac_handle $%p ", 2057 rcrp->rdc, rcrp->rcr_mac_handle)); 2058 2059 return (mp); 2060 } 2061 2062 2063 /* 2064 * This routine is the main packet receive processing function. 2065 * It gets the packet type, error code, and buffer related 2066 * information from the receive completion entry. 2067 * How many completion entries to process is based on the number of packets 2068 * queued by the hardware, a hardware maintained tail pointer 2069 * and a configurable receive packet count. 2070 * 2071 * A chain of message blocks will be created as result of processing 2072 * the completion entries. This chain of message blocks will be returned and 2073 * a hardware control status register will be updated with the number of 2074 * packets were removed from the hardware queue. 2075 * 2076 * The RCR ring lock is held when entering this function. 2077 */ 2078 static mblk_t * 2079 nxge_rx_pkts(p_nxge_t nxgep, p_rx_rcr_ring_t rcr_p, rx_dma_ctl_stat_t cs, 2080 int bytes_to_pickup) 2081 { 2082 npi_handle_t handle; 2083 uint8_t channel; 2084 uint32_t comp_rd_index; 2085 p_rcr_entry_t rcr_desc_rd_head_p; 2086 p_rcr_entry_t rcr_desc_rd_head_pp; 2087 p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 2088 uint16_t qlen, nrcr_read, npkt_read; 2089 uint32_t qlen_hw; 2090 boolean_t multi; 2091 rcrcfig_b_t rcr_cfg_b; 2092 int totallen = 0; 2093 #if defined(_BIG_ENDIAN) 2094 npi_status_t rs = NPI_SUCCESS; 2095 #endif 2096 2097 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_rx_pkts: " 2098 "channel %d", rcr_p->rdc)); 2099 2100 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 2101 return (NULL); 2102 } 2103 handle = NXGE_DEV_NPI_HANDLE(nxgep); 2104 channel = rcr_p->rdc; 2105 2106 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2107 "==> nxge_rx_pkts: START: rcr channel %d " 2108 "head_p $%p head_pp $%p index %d ", 2109 channel, rcr_p->rcr_desc_rd_head_p, 2110 rcr_p->rcr_desc_rd_head_pp, 2111 rcr_p->comp_rd_index)); 2112 2113 2114 #if !defined(_BIG_ENDIAN) 2115 qlen = RXDMA_REG_READ32(handle, RCRSTAT_A_REG, channel) & 0xffff; 2116 #else 2117 rs = npi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 2118 if (rs != NPI_SUCCESS) { 2119 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts: " 2120 "channel %d, get qlen failed 0x%08x", 2121 channel, rs)); 2122 return (NULL); 2123 } 2124 #endif 2125 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:rcr channel %d " 2126 "qlen %d", channel, qlen)); 2127 2128 2129 2130 if (!qlen) { 2131 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2132 "==> nxge_rx_pkts:rcr channel %d " 2133 "qlen %d (no pkts)", channel, qlen)); 2134 2135 return (NULL); 2136 } 2137 2138 comp_rd_index = rcr_p->comp_rd_index; 2139 2140 rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p; 2141 rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp; 2142 nrcr_read = npkt_read = 0; 2143 2144 /* 2145 * Number of packets queued 2146 * (The jumbo or multi packet will be counted as only one 2147 * packets and it may take up more than one completion entry). 2148 */ 2149 qlen_hw = (qlen < nxge_max_rx_pkts) ? 2150 qlen : nxge_max_rx_pkts; 2151 head_mp = NULL; 2152 tail_mp = &head_mp; 2153 nmp = mp_cont = NULL; 2154 multi = B_FALSE; 2155 2156 while (qlen_hw) { 2157 2158 #ifdef NXGE_DEBUG 2159 nxge_dump_rcr_entry(nxgep, rcr_desc_rd_head_p); 2160 #endif 2161 /* 2162 * Process one completion ring entry. 2163 */ 2164 nxge_receive_packet(nxgep, 2165 rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont); 2166 2167 /* 2168 * message chaining modes 2169 */ 2170 if (nmp) { 2171 nmp->b_next = NULL; 2172 if (!multi && !mp_cont) { /* frame fits a partition */ 2173 *tail_mp = nmp; 2174 tail_mp = &nmp->b_next; 2175 totallen += MBLKL(nmp); 2176 nmp = NULL; 2177 } else if (multi && !mp_cont) { /* first segment */ 2178 *tail_mp = nmp; 2179 tail_mp = &nmp->b_cont; 2180 totallen += MBLKL(nmp); 2181 } else if (multi && mp_cont) { /* mid of multi segs */ 2182 *tail_mp = mp_cont; 2183 tail_mp = &mp_cont->b_cont; 2184 totallen += MBLKL(mp_cont); 2185 } else if (!multi && mp_cont) { /* last segment */ 2186 *tail_mp = mp_cont; 2187 tail_mp = &nmp->b_next; 2188 totallen += MBLKL(mp_cont); 2189 nmp = NULL; 2190 } 2191 } 2192 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2193 "==> nxge_rx_pkts: loop: rcr channel %d " 2194 "before updating: multi %d " 2195 "nrcr_read %d " 2196 "npk read %d " 2197 "head_pp $%p index %d ", 2198 channel, 2199 multi, 2200 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 2201 comp_rd_index)); 2202 2203 if (!multi) { 2204 qlen_hw--; 2205 npkt_read++; 2206 } 2207 2208 /* 2209 * Update the next read entry. 2210 */ 2211 comp_rd_index = NEXT_ENTRY(comp_rd_index, 2212 rcr_p->comp_wrap_mask); 2213 2214 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 2215 rcr_p->rcr_desc_first_p, 2216 rcr_p->rcr_desc_last_p); 2217 2218 nrcr_read++; 2219 2220 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2221 "<== nxge_rx_pkts: (SAM, process one packet) " 2222 "nrcr_read %d", 2223 nrcr_read)); 2224 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2225 "==> nxge_rx_pkts: loop: rcr channel %d " 2226 "multi %d " 2227 "nrcr_read %d " 2228 "npk read %d " 2229 "head_pp $%p index %d ", 2230 channel, 2231 multi, 2232 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 2233 comp_rd_index)); 2234 2235 if ((bytes_to_pickup != -1) && 2236 (totallen >= bytes_to_pickup)) { 2237 break; 2238 } 2239 2240 /* limit the number of packets for interrupt */ 2241 if (!(rcr_p->poll_flag)) { 2242 if (npkt_read == nxge_max_intr_pkts) { 2243 break; 2244 } 2245 } 2246 } 2247 2248 rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 2249 rcr_p->comp_rd_index = comp_rd_index; 2250 rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 2251 2252 if ((nxgep->intr_timeout != rcr_p->intr_timeout) || 2253 (nxgep->intr_threshold != rcr_p->intr_threshold)) { 2254 rcr_p->intr_timeout = nxgep->intr_timeout; 2255 rcr_p->intr_threshold = nxgep->intr_threshold; 2256 rcr_cfg_b.value = 0x0ULL; 2257 if (rcr_p->intr_timeout) 2258 rcr_cfg_b.bits.ldw.entout = 1; 2259 rcr_cfg_b.bits.ldw.timeout = rcr_p->intr_timeout; 2260 rcr_cfg_b.bits.ldw.pthres = rcr_p->intr_threshold; 2261 RXDMA_REG_WRITE64(handle, RCRCFIG_B_REG, 2262 channel, rcr_cfg_b.value); 2263 } 2264 2265 cs.bits.ldw.pktread = npkt_read; 2266 cs.bits.ldw.ptrread = nrcr_read; 2267 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, 2268 channel, cs.value); 2269 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2270 "==> nxge_rx_pkts: EXIT: rcr channel %d " 2271 "head_pp $%p index %016llx ", 2272 channel, 2273 rcr_p->rcr_desc_rd_head_pp, 2274 rcr_p->comp_rd_index)); 2275 /* 2276 * Update RCR buffer pointer read and number of packets 2277 * read. 2278 */ 2279 2280 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_rx_pkts: return" 2281 "channel %d", rcr_p->rdc)); 2282 2283 return (head_mp); 2284 } 2285 2286 void 2287 nxge_receive_packet(p_nxge_t nxgep, 2288 p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, 2289 boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont) 2290 { 2291 p_mblk_t nmp = NULL; 2292 uint64_t multi; 2293 uint64_t dcf_err; 2294 uint8_t channel; 2295 2296 boolean_t first_entry = B_TRUE; 2297 boolean_t is_tcp_udp = B_FALSE; 2298 boolean_t buffer_free = B_FALSE; 2299 boolean_t error_send_up = B_FALSE; 2300 uint8_t error_type; 2301 uint16_t l2_len; 2302 uint16_t skip_len; 2303 uint8_t pktbufsz_type; 2304 uint64_t rcr_entry; 2305 uint64_t *pkt_buf_addr_pp; 2306 uint64_t *pkt_buf_addr_p; 2307 uint32_t buf_offset; 2308 uint32_t bsize; 2309 uint32_t error_disp_cnt; 2310 uint32_t msg_index; 2311 p_rx_rbr_ring_t rx_rbr_p; 2312 p_rx_msg_t *rx_msg_ring_p; 2313 p_rx_msg_t rx_msg_p; 2314 uint16_t sw_offset_bytes = 0, hdr_size = 0; 2315 nxge_status_t status = NXGE_OK; 2316 boolean_t is_valid = B_FALSE; 2317 p_nxge_rx_ring_stats_t rdc_stats; 2318 uint32_t bytes_read; 2319 uint64_t pkt_type; 2320 uint64_t frag; 2321 boolean_t pkt_too_long_err = B_FALSE; 2322 #ifdef NXGE_DEBUG 2323 int dump_len; 2324 #endif 2325 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_receive_packet")); 2326 first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 2327 2328 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 2329 2330 multi = (rcr_entry & RCR_MULTI_MASK); 2331 dcf_err = (rcr_entry & RCR_DCF_ERROR_MASK); 2332 pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); 2333 2334 error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 2335 frag = (rcr_entry & RCR_FRAG_MASK); 2336 2337 l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 2338 2339 pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 2340 RCR_PKTBUFSZ_SHIFT); 2341 #if defined(__i386) 2342 pkt_buf_addr_pp = (uint64_t *)(uint32_t)((rcr_entry & 2343 RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT); 2344 #else 2345 pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 2346 RCR_PKT_BUF_ADDR_SHIFT); 2347 #endif 2348 2349 channel = rcr_p->rdc; 2350 2351 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2352 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2353 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2354 "error_type 0x%x pkt_type 0x%x " 2355 "pktbufsz_type %d ", 2356 rcr_desc_rd_head_p, 2357 rcr_entry, pkt_buf_addr_pp, l2_len, 2358 multi, 2359 error_type, 2360 pkt_type, 2361 pktbufsz_type)); 2362 2363 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2364 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2365 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2366 "error_type 0x%x pkt_type 0x%x ", rcr_desc_rd_head_p, 2367 rcr_entry, pkt_buf_addr_pp, l2_len, 2368 multi, 2369 error_type, 2370 pkt_type)); 2371 2372 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2373 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2374 "full pkt_buf_addr_pp $%p l2_len %d", 2375 rcr_entry, pkt_buf_addr_pp, l2_len)); 2376 2377 /* get the stats ptr */ 2378 rdc_stats = rcr_p->rdc_stats; 2379 2380 if (!l2_len) { 2381 2382 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2383 "<== nxge_receive_packet: failed: l2 length is 0.")); 2384 return; 2385 } 2386 2387 /* 2388 * Software workaround for BMAC hardware limitation that allows 2389 * maxframe size of 1526, instead of 1522 for non-jumbo and 0x2406 2390 * instead of 0x2400 for jumbo. 2391 */ 2392 if (l2_len > nxgep->mac.maxframesize) { 2393 pkt_too_long_err = B_TRUE; 2394 } 2395 2396 /* Hardware sends us 4 bytes of CRC as no stripping is done. */ 2397 l2_len -= ETHERFCSL; 2398 2399 /* shift 6 bits to get the full io address */ 2400 #if defined(__i386) 2401 pkt_buf_addr_pp = (uint64_t *)((uint32_t)pkt_buf_addr_pp << 2402 RCR_PKT_BUF_ADDR_SHIFT_FULL); 2403 #else 2404 pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 2405 RCR_PKT_BUF_ADDR_SHIFT_FULL); 2406 #endif 2407 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2408 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2409 "full pkt_buf_addr_pp $%p l2_len %d", 2410 rcr_entry, pkt_buf_addr_pp, l2_len)); 2411 2412 rx_rbr_p = rcr_p->rx_rbr_p; 2413 rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 2414 2415 if (first_entry) { 2416 hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 2417 RXDMA_HDR_SIZE_DEFAULT); 2418 2419 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2420 "==> nxge_receive_packet: first entry 0x%016llx " 2421 "pkt_buf_addr_pp $%p l2_len %d hdr %d", 2422 rcr_entry, pkt_buf_addr_pp, l2_len, 2423 hdr_size)); 2424 } 2425 2426 MUTEX_ENTER(&rx_rbr_p->lock); 2427 2428 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2429 "==> (rbr 1) nxge_receive_packet: entry 0x%0llx " 2430 "full pkt_buf_addr_pp $%p l2_len %d", 2431 rcr_entry, pkt_buf_addr_pp, l2_len)); 2432 2433 /* 2434 * Packet buffer address in the completion entry points 2435 * to the starting buffer address (offset 0). 2436 * Use the starting buffer address to locate the corresponding 2437 * kernel address. 2438 */ 2439 status = nxge_rxbuf_pp_to_vp(nxgep, rx_rbr_p, 2440 pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 2441 &buf_offset, 2442 &msg_index); 2443 2444 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2445 "==> (rbr 2) nxge_receive_packet: entry 0x%0llx " 2446 "full pkt_buf_addr_pp $%p l2_len %d", 2447 rcr_entry, pkt_buf_addr_pp, l2_len)); 2448 2449 if (status != NXGE_OK) { 2450 MUTEX_EXIT(&rx_rbr_p->lock); 2451 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2452 "<== nxge_receive_packet: found vaddr failed %d", 2453 status)); 2454 return; 2455 } 2456 2457 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2458 "==> (rbr 3) nxge_receive_packet: entry 0x%0llx " 2459 "full pkt_buf_addr_pp $%p l2_len %d", 2460 rcr_entry, pkt_buf_addr_pp, l2_len)); 2461 2462 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2463 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2464 "full pkt_buf_addr_pp $%p l2_len %d", 2465 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2466 2467 rx_msg_p = rx_msg_ring_p[msg_index]; 2468 2469 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2470 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2471 "full pkt_buf_addr_pp $%p l2_len %d", 2472 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2473 2474 switch (pktbufsz_type) { 2475 case RCR_PKTBUFSZ_0: 2476 bsize = rx_rbr_p->pkt_buf_size0_bytes; 2477 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2478 "==> nxge_receive_packet: 0 buf %d", bsize)); 2479 break; 2480 case RCR_PKTBUFSZ_1: 2481 bsize = rx_rbr_p->pkt_buf_size1_bytes; 2482 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2483 "==> nxge_receive_packet: 1 buf %d", bsize)); 2484 break; 2485 case RCR_PKTBUFSZ_2: 2486 bsize = rx_rbr_p->pkt_buf_size2_bytes; 2487 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2488 "==> nxge_receive_packet: 2 buf %d", bsize)); 2489 break; 2490 case RCR_SINGLE_BLOCK: 2491 bsize = rx_msg_p->block_size; 2492 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2493 "==> nxge_receive_packet: single %d", bsize)); 2494 2495 break; 2496 default: 2497 MUTEX_EXIT(&rx_rbr_p->lock); 2498 return; 2499 } 2500 2501 DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 2502 (buf_offset + sw_offset_bytes), 2503 (hdr_size + l2_len), 2504 DDI_DMA_SYNC_FORCPU); 2505 2506 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2507 "==> nxge_receive_packet: after first dump:usage count")); 2508 2509 if (rx_msg_p->cur_usage_cnt == 0) { 2510 if (rx_rbr_p->rbr_use_bcopy) { 2511 atomic_inc_32(&rx_rbr_p->rbr_consumed); 2512 if (rx_rbr_p->rbr_consumed < 2513 rx_rbr_p->rbr_threshold_hi) { 2514 if (rx_rbr_p->rbr_threshold_lo == 0 || 2515 ((rx_rbr_p->rbr_consumed >= 2516 rx_rbr_p->rbr_threshold_lo) && 2517 (rx_rbr_p->rbr_bufsize_type >= 2518 pktbufsz_type))) { 2519 rx_msg_p->rx_use_bcopy = B_TRUE; 2520 } 2521 } else { 2522 rx_msg_p->rx_use_bcopy = B_TRUE; 2523 } 2524 } 2525 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2526 "==> nxge_receive_packet: buf %d (new block) ", 2527 bsize)); 2528 2529 rx_msg_p->pkt_buf_size_code = pktbufsz_type; 2530 rx_msg_p->pkt_buf_size = bsize; 2531 rx_msg_p->cur_usage_cnt = 1; 2532 if (pktbufsz_type == RCR_SINGLE_BLOCK) { 2533 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2534 "==> nxge_receive_packet: buf %d " 2535 "(single block) ", 2536 bsize)); 2537 /* 2538 * Buffer can be reused once the free function 2539 * is called. 2540 */ 2541 rx_msg_p->max_usage_cnt = 1; 2542 buffer_free = B_TRUE; 2543 } else { 2544 rx_msg_p->max_usage_cnt = rx_msg_p->block_size/bsize; 2545 if (rx_msg_p->max_usage_cnt == 1) { 2546 buffer_free = B_TRUE; 2547 } 2548 } 2549 } else { 2550 rx_msg_p->cur_usage_cnt++; 2551 if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 2552 buffer_free = B_TRUE; 2553 } 2554 } 2555 2556 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2557 "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 2558 msg_index, l2_len, 2559 rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 2560 2561 if ((error_type) || (dcf_err) || (pkt_too_long_err)) { 2562 rdc_stats->ierrors++; 2563 if (dcf_err) { 2564 rdc_stats->dcf_err++; 2565 #ifdef NXGE_DEBUG 2566 if (!rdc_stats->dcf_err) { 2567 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2568 "nxge_receive_packet: channel %d dcf_err rcr" 2569 " 0x%llx", channel, rcr_entry)); 2570 } 2571 #endif 2572 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 2573 NXGE_FM_EREPORT_RDMC_DCF_ERR); 2574 } else if (pkt_too_long_err) { 2575 rdc_stats->pkt_too_long_err++; 2576 NXGE_DEBUG_MSG((nxgep, RX_CTL, " nxge_receive_packet:" 2577 " channel %d packet length [%d] > " 2578 "maxframesize [%d]", channel, l2_len + ETHERFCSL, 2579 nxgep->mac.maxframesize)); 2580 } else { 2581 /* Update error stats */ 2582 error_disp_cnt = NXGE_ERROR_SHOW_MAX; 2583 rdc_stats->errlog.compl_err_type = error_type; 2584 2585 switch (error_type) { 2586 /* 2587 * Do not send FMA ereport for RCR_L2_ERROR and 2588 * RCR_L4_CSUM_ERROR because most likely they indicate 2589 * back pressure rather than HW failures. 2590 */ 2591 case RCR_L2_ERROR: 2592 rdc_stats->l2_err++; 2593 if (rdc_stats->l2_err < 2594 error_disp_cnt) { 2595 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2596 " nxge_receive_packet:" 2597 " channel %d RCR L2_ERROR", 2598 channel)); 2599 } 2600 break; 2601 case RCR_L4_CSUM_ERROR: 2602 error_send_up = B_TRUE; 2603 rdc_stats->l4_cksum_err++; 2604 if (rdc_stats->l4_cksum_err < 2605 error_disp_cnt) { 2606 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2607 " nxge_receive_packet:" 2608 " channel %d" 2609 " RCR L4_CSUM_ERROR", channel)); 2610 } 2611 break; 2612 /* 2613 * Do not send FMA ereport for RCR_FFLP_SOFT_ERROR and 2614 * RCR_ZCP_SOFT_ERROR because they reflect the same 2615 * FFLP and ZCP errors that have been reported by 2616 * nxge_fflp.c and nxge_zcp.c. 2617 */ 2618 case RCR_FFLP_SOFT_ERROR: 2619 error_send_up = B_TRUE; 2620 rdc_stats->fflp_soft_err++; 2621 if (rdc_stats->fflp_soft_err < 2622 error_disp_cnt) { 2623 NXGE_ERROR_MSG((nxgep, 2624 NXGE_ERR_CTL, 2625 " nxge_receive_packet:" 2626 " channel %d" 2627 " RCR FFLP_SOFT_ERROR", channel)); 2628 } 2629 break; 2630 case RCR_ZCP_SOFT_ERROR: 2631 error_send_up = B_TRUE; 2632 rdc_stats->fflp_soft_err++; 2633 if (rdc_stats->zcp_soft_err < 2634 error_disp_cnt) 2635 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2636 " nxge_receive_packet: Channel %d" 2637 " RCR ZCP_SOFT_ERROR", channel)); 2638 break; 2639 default: 2640 rdc_stats->rcr_unknown_err++; 2641 if (rdc_stats->rcr_unknown_err 2642 < error_disp_cnt) { 2643 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2644 " nxge_receive_packet: Channel %d" 2645 " RCR entry 0x%llx error 0x%x", 2646 rcr_entry, channel, error_type)); 2647 } 2648 break; 2649 } 2650 } 2651 2652 /* 2653 * Update and repost buffer block if max usage 2654 * count is reached. 2655 */ 2656 if (error_send_up == B_FALSE) { 2657 atomic_inc_32(&rx_msg_p->ref_cnt); 2658 if (buffer_free == B_TRUE) { 2659 rx_msg_p->free = B_TRUE; 2660 } 2661 2662 MUTEX_EXIT(&rx_rbr_p->lock); 2663 nxge_freeb(rx_msg_p); 2664 return; 2665 } 2666 } 2667 2668 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2669 "==> nxge_receive_packet: DMA sync second ")); 2670 2671 bytes_read = rcr_p->rcvd_pkt_bytes; 2672 skip_len = sw_offset_bytes + hdr_size; 2673 if (!rx_msg_p->rx_use_bcopy) { 2674 /* 2675 * For loaned up buffers, the driver reference count 2676 * will be incremented first and then the free state. 2677 */ 2678 if ((nmp = nxge_dupb(rx_msg_p, buf_offset, bsize)) != NULL) { 2679 if (first_entry) { 2680 nmp->b_rptr = &nmp->b_rptr[skip_len]; 2681 if (l2_len < bsize - skip_len) { 2682 nmp->b_wptr = &nmp->b_rptr[l2_len]; 2683 } else { 2684 nmp->b_wptr = &nmp->b_rptr[bsize 2685 - skip_len]; 2686 } 2687 } else { 2688 if (l2_len - bytes_read < bsize) { 2689 nmp->b_wptr = 2690 &nmp->b_rptr[l2_len - bytes_read]; 2691 } else { 2692 nmp->b_wptr = &nmp->b_rptr[bsize]; 2693 } 2694 } 2695 } 2696 } else { 2697 if (first_entry) { 2698 nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, 2699 l2_len < bsize - skip_len ? 2700 l2_len : bsize - skip_len); 2701 } else { 2702 nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset, 2703 l2_len - bytes_read < bsize ? 2704 l2_len - bytes_read : bsize); 2705 } 2706 } 2707 if (nmp != NULL) { 2708 if (first_entry) { 2709 /* 2710 * Jumbo packets may be received with more than one 2711 * buffer, increment ipackets for the first entry only. 2712 */ 2713 rdc_stats->ipackets++; 2714 2715 /* Update ibytes for kstat. */ 2716 rdc_stats->ibytes += skip_len 2717 + l2_len < bsize ? l2_len : bsize; 2718 /* 2719 * Update the number of bytes read so far for the 2720 * current frame. 2721 */ 2722 bytes_read = nmp->b_wptr - nmp->b_rptr; 2723 } else { 2724 rdc_stats->ibytes += l2_len - bytes_read < bsize ? 2725 l2_len - bytes_read : bsize; 2726 bytes_read += nmp->b_wptr - nmp->b_rptr; 2727 } 2728 2729 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2730 "==> nxge_receive_packet after dupb: " 2731 "rbr consumed %d " 2732 "pktbufsz_type %d " 2733 "nmp $%p rptr $%p wptr $%p " 2734 "buf_offset %d bzise %d l2_len %d skip_len %d", 2735 rx_rbr_p->rbr_consumed, 2736 pktbufsz_type, 2737 nmp, nmp->b_rptr, nmp->b_wptr, 2738 buf_offset, bsize, l2_len, skip_len)); 2739 } else { 2740 cmn_err(CE_WARN, "!nxge_receive_packet: " 2741 "update stats (error)"); 2742 atomic_inc_32(&rx_msg_p->ref_cnt); 2743 if (buffer_free == B_TRUE) { 2744 rx_msg_p->free = B_TRUE; 2745 } 2746 MUTEX_EXIT(&rx_rbr_p->lock); 2747 nxge_freeb(rx_msg_p); 2748 return; 2749 } 2750 2751 if (buffer_free == B_TRUE) { 2752 rx_msg_p->free = B_TRUE; 2753 } 2754 2755 is_valid = (nmp != NULL); 2756 2757 rcr_p->rcvd_pkt_bytes = bytes_read; 2758 2759 MUTEX_EXIT(&rx_rbr_p->lock); 2760 2761 if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 2762 atomic_inc_32(&rx_msg_p->ref_cnt); 2763 nxge_freeb(rx_msg_p); 2764 } 2765 2766 if (is_valid) { 2767 nmp->b_cont = NULL; 2768 if (first_entry) { 2769 *mp = nmp; 2770 *mp_cont = NULL; 2771 } else { 2772 *mp_cont = nmp; 2773 } 2774 } 2775 2776 /* 2777 * ERROR, FRAG and PKT_TYPE are only reported in the first entry. 2778 * If a packet is not fragmented and no error bit is set, then 2779 * L4 checksum is OK. 2780 */ 2781 2782 if (is_valid && !multi) { 2783 /* 2784 * If the checksum flag nxge_chksum_offload 2785 * is 1, TCP and UDP packets can be sent 2786 * up with good checksum. If the checksum flag 2787 * is set to 0, checksum reporting will apply to 2788 * TCP packets only (workaround for a hardware bug). 2789 * If the checksum flag nxge_cksum_offload is 2790 * greater than 1, both TCP and UDP packets 2791 * will not be reported its hardware checksum results. 2792 */ 2793 if (nxge_cksum_offload == 1) { 2794 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP || 2795 pkt_type == RCR_PKT_IS_UDP) ? 2796 B_TRUE: B_FALSE); 2797 } else if (!nxge_cksum_offload) { 2798 /* TCP checksum only. */ 2799 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP) ? 2800 B_TRUE: B_FALSE); 2801 } 2802 2803 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_receive_packet: " 2804 "is_valid 0x%x multi 0x%llx pkt %d frag %d error %d", 2805 is_valid, multi, is_tcp_udp, frag, error_type)); 2806 2807 if (is_tcp_udp && !frag && !error_type) { 2808 (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 2809 HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 2810 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2811 "==> nxge_receive_packet: Full tcp/udp cksum " 2812 "is_valid 0x%x multi 0x%llx pkt %d frag %d " 2813 "error %d", 2814 is_valid, multi, is_tcp_udp, frag, error_type)); 2815 } 2816 } 2817 2818 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2819 "==> nxge_receive_packet: *mp 0x%016llx", *mp)); 2820 2821 *multi_p = (multi == RCR_MULTI_MASK); 2822 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_receive_packet: " 2823 "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 2824 *multi_p, nmp, *mp, *mp_cont)); 2825 } 2826 2827 /* 2828 * Enable polling for a ring. Interrupt for the ring is disabled when 2829 * the nxge interrupt comes (see nxge_rx_intr). 2830 */ 2831 int 2832 nxge_enable_poll(void *arg) 2833 { 2834 p_nxge_ring_handle_t ring_handle = (p_nxge_ring_handle_t)arg; 2835 p_rx_rcr_ring_t ringp; 2836 p_nxge_t nxgep; 2837 p_nxge_ldg_t ldgp; 2838 uint32_t channel; 2839 2840 if (ring_handle == NULL) { 2841 return (0); 2842 } 2843 2844 nxgep = ring_handle->nxgep; 2845 channel = nxgep->pt_config.hw_config.start_rdc + ring_handle->index; 2846 ringp = nxgep->rx_rcr_rings->rcr_rings[channel]; 2847 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2848 "==> nxge_enable_poll: rdc %d ", ringp->rdc)); 2849 ldgp = ringp->ldgp; 2850 if (ldgp == NULL) { 2851 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2852 "==> nxge_enable_poll: rdc %d NULL ldgp: no change", 2853 ringp->rdc)); 2854 return (0); 2855 } 2856 2857 MUTEX_ENTER(&ringp->lock); 2858 /* enable polling */ 2859 if (ringp->poll_flag == 0) { 2860 ringp->poll_flag = 1; 2861 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2862 "==> nxge_enable_poll: rdc %d set poll flag to 1", 2863 ringp->rdc)); 2864 } 2865 2866 MUTEX_EXIT(&ringp->lock); 2867 return (0); 2868 } 2869 /* 2870 * Disable polling for a ring and enable its interrupt. 2871 */ 2872 int 2873 nxge_disable_poll(void *arg) 2874 { 2875 p_nxge_ring_handle_t ring_handle = (p_nxge_ring_handle_t)arg; 2876 p_rx_rcr_ring_t ringp; 2877 p_nxge_t nxgep; 2878 uint32_t channel; 2879 2880 if (ring_handle == NULL) { 2881 return (0); 2882 } 2883 2884 nxgep = ring_handle->nxgep; 2885 channel = nxgep->pt_config.hw_config.start_rdc + ring_handle->index; 2886 ringp = nxgep->rx_rcr_rings->rcr_rings[channel]; 2887 2888 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2889 "==> nxge_disable_poll: rdc %d poll_flag %d", ringp->rdc)); 2890 2891 MUTEX_ENTER(&ringp->lock); 2892 2893 /* disable polling: enable interrupt */ 2894 if (ringp->poll_flag) { 2895 npi_handle_t handle; 2896 rx_dma_ctl_stat_t cs; 2897 uint8_t channel; 2898 p_nxge_ldg_t ldgp; 2899 2900 /* 2901 * Get the control and status for this channel. 2902 */ 2903 handle = NXGE_DEV_NPI_HANDLE(nxgep); 2904 channel = ringp->rdc; 2905 RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, 2906 channel, &cs.value); 2907 2908 /* 2909 * Enable mailbox update 2910 * Since packets were not read and the hardware uses 2911 * bits pktread and ptrread to update the queue 2912 * length, we need to set both bits to 0. 2913 */ 2914 cs.bits.ldw.pktread = 0; 2915 cs.bits.ldw.ptrread = 0; 2916 cs.bits.hdw.mex = 1; 2917 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, 2918 cs.value); 2919 2920 /* 2921 * Rearm this logical group if this is a single device 2922 * group. 2923 */ 2924 ldgp = ringp->ldgp; 2925 if (ldgp == NULL) { 2926 ringp->poll_flag = 0; 2927 MUTEX_EXIT(&ringp->lock); 2928 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2929 "==> nxge_disable_poll: no ldgp rdc %d " 2930 "(still set poll to 0", ringp->rdc)); 2931 return (0); 2932 } 2933 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2934 "==> nxge_disable_poll: rdc %d ldgp $%p (enable intr)", 2935 ringp->rdc, ldgp)); 2936 if (ldgp->nldvs == 1) { 2937 ldgimgm_t mgm; 2938 mgm.value = 0; 2939 mgm.bits.ldw.arm = 1; 2940 mgm.bits.ldw.timer = ldgp->ldg_timer; 2941 NXGE_REG_WR64(handle, 2942 LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), mgm.value); 2943 } 2944 ringp->poll_flag = 0; 2945 } 2946 2947 MUTEX_EXIT(&ringp->lock); 2948 return (0); 2949 } 2950 2951 /* 2952 * Poll 'bytes_to_pickup' bytes of message from the rx ring. 2953 */ 2954 mblk_t * 2955 nxge_rx_poll(void *arg, int bytes_to_pickup) 2956 { 2957 p_nxge_ring_handle_t ring_handle = (p_nxge_ring_handle_t)arg; 2958 p_rx_rcr_ring_t rcr_p; 2959 p_nxge_t nxgep; 2960 npi_handle_t handle; 2961 rx_dma_ctl_stat_t cs; 2962 mblk_t *mblk; 2963 p_nxge_ldv_t ldvp; 2964 uint32_t channel; 2965 2966 nxgep = ring_handle->nxgep; 2967 2968 /* 2969 * Get the control and status for this channel. 2970 */ 2971 handle = NXGE_DEV_NPI_HANDLE(nxgep); 2972 channel = nxgep->pt_config.hw_config.start_rdc + ring_handle->index; 2973 rcr_p = nxgep->rx_rcr_rings->rcr_rings[channel]; 2974 MUTEX_ENTER(&rcr_p->lock); 2975 ASSERT(rcr_p->poll_flag == 1); 2976 2977 RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, rcr_p->rdc, &cs.value); 2978 2979 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2980 "==> nxge_rx_poll: calling nxge_rx_pkts: rdc %d poll_flag %d", 2981 rcr_p->rdc, rcr_p->poll_flag)); 2982 mblk = nxge_rx_pkts(nxgep, rcr_p, cs, bytes_to_pickup); 2983 2984 ldvp = rcr_p->ldvp; 2985 /* error events. */ 2986 if (ldvp && (cs.value & RX_DMA_CTL_STAT_ERROR)) { 2987 (void) nxge_rx_err_evnts(nxgep, ldvp->vdma_index, cs); 2988 } 2989 2990 MUTEX_EXIT(&rcr_p->lock); 2991 2992 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2993 "<== nxge_rx_poll: rdc %d mblk $%p", rcr_p->rdc, mblk)); 2994 return (mblk); 2995 } 2996 2997 2998 /*ARGSUSED*/ 2999 static nxge_status_t 3000 nxge_rx_err_evnts(p_nxge_t nxgep, int channel, rx_dma_ctl_stat_t cs) 3001 { 3002 p_nxge_rx_ring_stats_t rdc_stats; 3003 npi_handle_t handle; 3004 npi_status_t rs; 3005 boolean_t rxchan_fatal = B_FALSE; 3006 boolean_t rxport_fatal = B_FALSE; 3007 uint8_t portn; 3008 nxge_status_t status = NXGE_OK; 3009 uint32_t error_disp_cnt = NXGE_ERROR_SHOW_MAX; 3010 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_err_evnts")); 3011 3012 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3013 portn = nxgep->mac.portnum; 3014 rdc_stats = &nxgep->statsp->rdc_stats[channel]; 3015 3016 if (cs.bits.hdw.rbr_tmout) { 3017 rdc_stats->rx_rbr_tmout++; 3018 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3019 NXGE_FM_EREPORT_RDMC_RBR_TMOUT); 3020 rxchan_fatal = B_TRUE; 3021 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3022 "==> nxge_rx_err_evnts: rx_rbr_timeout")); 3023 } 3024 if (cs.bits.hdw.rsp_cnt_err) { 3025 rdc_stats->rsp_cnt_err++; 3026 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3027 NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR); 3028 rxchan_fatal = B_TRUE; 3029 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3030 "==> nxge_rx_err_evnts(channel %d): " 3031 "rsp_cnt_err", channel)); 3032 } 3033 if (cs.bits.hdw.byte_en_bus) { 3034 rdc_stats->byte_en_bus++; 3035 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3036 NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS); 3037 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3038 "==> nxge_rx_err_evnts(channel %d): " 3039 "fatal error: byte_en_bus", channel)); 3040 rxchan_fatal = B_TRUE; 3041 } 3042 if (cs.bits.hdw.rsp_dat_err) { 3043 rdc_stats->rsp_dat_err++; 3044 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3045 NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR); 3046 rxchan_fatal = B_TRUE; 3047 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3048 "==> nxge_rx_err_evnts(channel %d): " 3049 "fatal error: rsp_dat_err", channel)); 3050 } 3051 if (cs.bits.hdw.rcr_ack_err) { 3052 rdc_stats->rcr_ack_err++; 3053 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3054 NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR); 3055 rxchan_fatal = B_TRUE; 3056 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3057 "==> nxge_rx_err_evnts(channel %d): " 3058 "fatal error: rcr_ack_err", channel)); 3059 } 3060 if (cs.bits.hdw.dc_fifo_err) { 3061 rdc_stats->dc_fifo_err++; 3062 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3063 NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR); 3064 /* This is not a fatal error! */ 3065 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3066 "==> nxge_rx_err_evnts(channel %d): " 3067 "dc_fifo_err", channel)); 3068 rxport_fatal = B_TRUE; 3069 } 3070 if ((cs.bits.hdw.rcr_sha_par) || (cs.bits.hdw.rbr_pre_par)) { 3071 if ((rs = npi_rxdma_ring_perr_stat_get(handle, 3072 &rdc_stats->errlog.pre_par, 3073 &rdc_stats->errlog.sha_par)) 3074 != NPI_SUCCESS) { 3075 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3076 "==> nxge_rx_err_evnts(channel %d): " 3077 "rcr_sha_par: get perr", channel)); 3078 return (NXGE_ERROR | rs); 3079 } 3080 if (cs.bits.hdw.rcr_sha_par) { 3081 rdc_stats->rcr_sha_par++; 3082 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3083 NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 3084 rxchan_fatal = B_TRUE; 3085 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3086 "==> nxge_rx_err_evnts(channel %d): " 3087 "fatal error: rcr_sha_par", channel)); 3088 } 3089 if (cs.bits.hdw.rbr_pre_par) { 3090 rdc_stats->rbr_pre_par++; 3091 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3092 NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 3093 rxchan_fatal = B_TRUE; 3094 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3095 "==> nxge_rx_err_evnts(channel %d): " 3096 "fatal error: rbr_pre_par", channel)); 3097 } 3098 } 3099 /* 3100 * The Following 4 status bits are for information, the system 3101 * is running fine. There is no need to send FMA ereports or 3102 * log messages. 3103 */ 3104 if (cs.bits.hdw.port_drop_pkt) { 3105 rdc_stats->port_drop_pkt++; 3106 } 3107 if (cs.bits.hdw.wred_drop) { 3108 rdc_stats->wred_drop++; 3109 } 3110 if (cs.bits.hdw.rbr_pre_empty) { 3111 rdc_stats->rbr_pre_empty++; 3112 } 3113 if (cs.bits.hdw.rcr_shadow_full) { 3114 rdc_stats->rcr_shadow_full++; 3115 } 3116 if (cs.bits.hdw.config_err) { 3117 rdc_stats->config_err++; 3118 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3119 NXGE_FM_EREPORT_RDMC_CONFIG_ERR); 3120 rxchan_fatal = B_TRUE; 3121 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3122 "==> nxge_rx_err_evnts(channel %d): " 3123 "config error", channel)); 3124 } 3125 if (cs.bits.hdw.rcrincon) { 3126 rdc_stats->rcrincon++; 3127 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3128 NXGE_FM_EREPORT_RDMC_RCRINCON); 3129 rxchan_fatal = B_TRUE; 3130 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3131 "==> nxge_rx_err_evnts(channel %d): " 3132 "fatal error: rcrincon error", channel)); 3133 } 3134 if (cs.bits.hdw.rcrfull) { 3135 rdc_stats->rcrfull++; 3136 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3137 NXGE_FM_EREPORT_RDMC_RCRFULL); 3138 rxchan_fatal = B_TRUE; 3139 if (rdc_stats->rcrfull < error_disp_cnt) 3140 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3141 "==> nxge_rx_err_evnts(channel %d): " 3142 "fatal error: rcrfull error", channel)); 3143 } 3144 if (cs.bits.hdw.rbr_empty) { 3145 /* 3146 * This bit is for information, there is no need 3147 * send FMA ereport or log a message. 3148 */ 3149 rdc_stats->rbr_empty++; 3150 } 3151 if (cs.bits.hdw.rbrfull) { 3152 rdc_stats->rbrfull++; 3153 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3154 NXGE_FM_EREPORT_RDMC_RBRFULL); 3155 rxchan_fatal = B_TRUE; 3156 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3157 "==> nxge_rx_err_evnts(channel %d): " 3158 "fatal error: rbr_full error", channel)); 3159 } 3160 if (cs.bits.hdw.rbrlogpage) { 3161 rdc_stats->rbrlogpage++; 3162 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3163 NXGE_FM_EREPORT_RDMC_RBRLOGPAGE); 3164 rxchan_fatal = B_TRUE; 3165 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3166 "==> nxge_rx_err_evnts(channel %d): " 3167 "fatal error: rbr logical page error", channel)); 3168 } 3169 if (cs.bits.hdw.cfiglogpage) { 3170 rdc_stats->cfiglogpage++; 3171 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 3172 NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE); 3173 rxchan_fatal = B_TRUE; 3174 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3175 "==> nxge_rx_err_evnts(channel %d): " 3176 "fatal error: cfig logical page error", channel)); 3177 } 3178 3179 if (rxport_fatal) { 3180 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3181 " nxge_rx_err_evnts: fatal error on Port #%d\n", 3182 portn)); 3183 if (isLDOMguest(nxgep)) { 3184 status = NXGE_ERROR; 3185 } else { 3186 status = nxge_ipp_fatal_err_recover(nxgep); 3187 if (status == NXGE_OK) { 3188 FM_SERVICE_RESTORED(nxgep); 3189 } 3190 } 3191 } 3192 3193 if (rxchan_fatal) { 3194 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3195 " nxge_rx_err_evnts: fatal error on Channel #%d\n", 3196 channel)); 3197 if (isLDOMguest(nxgep)) { 3198 status = NXGE_ERROR; 3199 } else { 3200 status = nxge_rxdma_fatal_err_recover(nxgep, channel); 3201 if (status == NXGE_OK) { 3202 FM_SERVICE_RESTORED(nxgep); 3203 } 3204 } 3205 } 3206 3207 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rx_err_evnts")); 3208 3209 return (status); 3210 } 3211 3212 /* 3213 * nxge_rdc_hvio_setup 3214 * 3215 * This code appears to setup some Hypervisor variables. 3216 * 3217 * Arguments: 3218 * nxgep 3219 * channel 3220 * 3221 * Notes: 3222 * What does NIU_LP_WORKAROUND mean? 3223 * 3224 * NPI/NXGE function calls: 3225 * na 3226 * 3227 * Context: 3228 * Any domain 3229 */ 3230 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3231 static void 3232 nxge_rdc_hvio_setup( 3233 nxge_t *nxgep, int channel) 3234 { 3235 nxge_dma_common_t *dma_common; 3236 nxge_dma_common_t *dma_control; 3237 rx_rbr_ring_t *ring; 3238 3239 ring = nxgep->rx_rbr_rings->rbr_rings[channel]; 3240 dma_common = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 3241 3242 ring->hv_set = B_FALSE; 3243 3244 ring->hv_rx_buf_base_ioaddr_pp = (uint64_t) 3245 dma_common->orig_ioaddr_pp; 3246 ring->hv_rx_buf_ioaddr_size = (uint64_t) 3247 dma_common->orig_alength; 3248 3249 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma_channel: " 3250 "channel %d data buf base io $%lx ($%p) size 0x%lx (%ld 0x%lx)", 3251 channel, ring->hv_rx_buf_base_ioaddr_pp, 3252 dma_common->ioaddr_pp, ring->hv_rx_buf_ioaddr_size, 3253 dma_common->orig_alength, dma_common->orig_alength)); 3254 3255 dma_control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 3256 3257 ring->hv_rx_cntl_base_ioaddr_pp = 3258 (uint64_t)dma_control->orig_ioaddr_pp; 3259 ring->hv_rx_cntl_ioaddr_size = 3260 (uint64_t)dma_control->orig_alength; 3261 3262 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma_channel: " 3263 "channel %d cntl base io $%p ($%p) size 0x%llx (%d 0x%x)", 3264 channel, ring->hv_rx_cntl_base_ioaddr_pp, 3265 dma_control->ioaddr_pp, ring->hv_rx_cntl_ioaddr_size, 3266 dma_control->orig_alength, dma_control->orig_alength)); 3267 } 3268 #endif 3269 3270 /* 3271 * nxge_map_rxdma 3272 * 3273 * Map an RDC into our kernel space. 3274 * 3275 * Arguments: 3276 * nxgep 3277 * channel The channel to map. 3278 * 3279 * Notes: 3280 * 1. Allocate & initialise a memory pool, if necessary. 3281 * 2. Allocate however many receive buffers are required. 3282 * 3. Setup buffers, descriptors, and mailbox. 3283 * 3284 * NPI/NXGE function calls: 3285 * nxge_alloc_rx_mem_pool() 3286 * nxge_alloc_rbb() 3287 * nxge_map_rxdma_channel() 3288 * 3289 * Registers accessed: 3290 * 3291 * Context: 3292 * Any domain 3293 */ 3294 static nxge_status_t 3295 nxge_map_rxdma(p_nxge_t nxgep, int channel) 3296 { 3297 nxge_dma_common_t **data; 3298 nxge_dma_common_t **control; 3299 rx_rbr_ring_t **rbr_ring; 3300 rx_rcr_ring_t **rcr_ring; 3301 rx_mbox_t **mailbox; 3302 uint32_t chunks; 3303 3304 nxge_status_t status; 3305 3306 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma")); 3307 3308 if (!nxgep->rx_buf_pool_p) { 3309 if (nxge_alloc_rx_mem_pool(nxgep) != NXGE_OK) { 3310 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3311 "<== nxge_map_rxdma: buf not allocated")); 3312 return (NXGE_ERROR); 3313 } 3314 } 3315 3316 if (nxge_alloc_rxb(nxgep, channel) != NXGE_OK) 3317 return (NXGE_ERROR); 3318 3319 /* 3320 * Timeout should be set based on the system clock divider. 3321 * The following timeout value of 1 assumes that the 3322 * granularity (1000) is 3 microseconds running at 300MHz. 3323 */ 3324 3325 nxgep->intr_threshold = RXDMA_RCR_PTHRES_DEFAULT; 3326 nxgep->intr_timeout = RXDMA_RCR_TO_DEFAULT; 3327 3328 /* 3329 * Map descriptors from the buffer polls for each dma channel. 3330 */ 3331 3332 /* 3333 * Set up and prepare buffer blocks, descriptors 3334 * and mailbox. 3335 */ 3336 data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 3337 rbr_ring = &nxgep->rx_rbr_rings->rbr_rings[channel]; 3338 chunks = nxgep->rx_buf_pool_p->num_chunks[channel]; 3339 3340 control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 3341 rcr_ring = &nxgep->rx_rcr_rings->rcr_rings[channel]; 3342 3343 mailbox = &nxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 3344 3345 status = nxge_map_rxdma_channel(nxgep, channel, data, rbr_ring, 3346 chunks, control, rcr_ring, mailbox); 3347 if (status != NXGE_OK) { 3348 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3349 "==> nxge_map_rxdma: nxge_map_rxdma_channel(%d) " 3350 "returned 0x%x", 3351 channel, status)); 3352 return (status); 3353 } 3354 nxgep->rx_rbr_rings->rbr_rings[channel]->index = (uint16_t)channel; 3355 nxgep->rx_rcr_rings->rcr_rings[channel]->index = (uint16_t)channel; 3356 nxgep->rx_rcr_rings->rcr_rings[channel]->rdc_stats = 3357 &nxgep->statsp->rdc_stats[channel]; 3358 3359 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3360 if (!isLDOMguest(nxgep)) 3361 nxge_rdc_hvio_setup(nxgep, channel); 3362 #endif 3363 3364 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3365 "<== nxge_map_rxdma: (status 0x%x channel %d)", status, channel)); 3366 3367 return (status); 3368 } 3369 3370 static void 3371 nxge_unmap_rxdma(p_nxge_t nxgep, int channel) 3372 { 3373 rx_rbr_ring_t *rbr_ring; 3374 rx_rcr_ring_t *rcr_ring; 3375 rx_mbox_t *mailbox; 3376 3377 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_unmap_rxdma(%d)", channel)); 3378 3379 if (!nxgep->rx_rbr_rings || !nxgep->rx_rcr_rings || 3380 !nxgep->rx_mbox_areas_p) 3381 return; 3382 3383 rbr_ring = nxgep->rx_rbr_rings->rbr_rings[channel]; 3384 rcr_ring = nxgep->rx_rcr_rings->rcr_rings[channel]; 3385 mailbox = nxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 3386 3387 if (!rbr_ring || !rcr_ring || !mailbox) 3388 return; 3389 3390 (void) nxge_unmap_rxdma_channel( 3391 nxgep, channel, rbr_ring, rcr_ring, mailbox); 3392 3393 nxge_free_rxb(nxgep, channel); 3394 3395 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma")); 3396 } 3397 3398 nxge_status_t 3399 nxge_map_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 3400 p_nxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 3401 uint32_t num_chunks, 3402 p_nxge_dma_common_t *dma_cntl_p, p_rx_rcr_ring_t *rcr_p, 3403 p_rx_mbox_t *rx_mbox_p) 3404 { 3405 int status = NXGE_OK; 3406 3407 /* 3408 * Set up and prepare buffer blocks, descriptors 3409 * and mailbox. 3410 */ 3411 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3412 "==> nxge_map_rxdma_channel (channel %d)", channel)); 3413 /* 3414 * Receive buffer blocks 3415 */ 3416 status = nxge_map_rxdma_channel_buf_ring(nxgep, channel, 3417 dma_buf_p, rbr_p, num_chunks); 3418 if (status != NXGE_OK) { 3419 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3420 "==> nxge_map_rxdma_channel (channel %d): " 3421 "map buffer failed 0x%x", channel, status)); 3422 goto nxge_map_rxdma_channel_exit; 3423 } 3424 3425 /* 3426 * Receive block ring, completion ring and mailbox. 3427 */ 3428 status = nxge_map_rxdma_channel_cfg_ring(nxgep, channel, 3429 dma_cntl_p, rbr_p, rcr_p, rx_mbox_p); 3430 if (status != NXGE_OK) { 3431 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3432 "==> nxge_map_rxdma_channel (channel %d): " 3433 "map config failed 0x%x", channel, status)); 3434 goto nxge_map_rxdma_channel_fail2; 3435 } 3436 3437 goto nxge_map_rxdma_channel_exit; 3438 3439 nxge_map_rxdma_channel_fail3: 3440 /* Free rbr, rcr */ 3441 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3442 "==> nxge_map_rxdma_channel: free rbr/rcr " 3443 "(status 0x%x channel %d)", 3444 status, channel)); 3445 nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3446 *rcr_p, *rx_mbox_p); 3447 3448 nxge_map_rxdma_channel_fail2: 3449 /* Free buffer blocks */ 3450 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3451 "==> nxge_map_rxdma_channel: free rx buffers" 3452 "(nxgep 0x%x status 0x%x channel %d)", 3453 nxgep, status, channel)); 3454 nxge_unmap_rxdma_channel_buf_ring(nxgep, *rbr_p); 3455 3456 status = NXGE_ERROR; 3457 3458 nxge_map_rxdma_channel_exit: 3459 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3460 "<== nxge_map_rxdma_channel: " 3461 "(nxgep 0x%x status 0x%x channel %d)", 3462 nxgep, status, channel)); 3463 3464 return (status); 3465 } 3466 3467 /*ARGSUSED*/ 3468 static void 3469 nxge_unmap_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 3470 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3471 { 3472 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3473 "==> nxge_unmap_rxdma_channel (channel %d)", channel)); 3474 3475 /* 3476 * unmap receive block ring, completion ring and mailbox. 3477 */ 3478 (void) nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3479 rcr_p, rx_mbox_p); 3480 3481 /* unmap buffer blocks */ 3482 (void) nxge_unmap_rxdma_channel_buf_ring(nxgep, rbr_p); 3483 3484 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma_channel")); 3485 } 3486 3487 /*ARGSUSED*/ 3488 static nxge_status_t 3489 nxge_map_rxdma_channel_cfg_ring(p_nxge_t nxgep, uint16_t dma_channel, 3490 p_nxge_dma_common_t *dma_cntl_p, p_rx_rbr_ring_t *rbr_p, 3491 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 3492 { 3493 p_rx_rbr_ring_t rbrp; 3494 p_rx_rcr_ring_t rcrp; 3495 p_rx_mbox_t mboxp; 3496 p_nxge_dma_common_t cntl_dmap; 3497 p_nxge_dma_common_t dmap; 3498 p_rx_msg_t *rx_msg_ring; 3499 p_rx_msg_t rx_msg_p; 3500 p_rbr_cfig_a_t rcfga_p; 3501 p_rbr_cfig_b_t rcfgb_p; 3502 p_rcrcfig_a_t cfga_p; 3503 p_rcrcfig_b_t cfgb_p; 3504 p_rxdma_cfig1_t cfig1_p; 3505 p_rxdma_cfig2_t cfig2_p; 3506 p_rbr_kick_t kick_p; 3507 uint32_t dmaaddrp; 3508 uint32_t *rbr_vaddrp; 3509 uint32_t bkaddr; 3510 nxge_status_t status = NXGE_OK; 3511 int i; 3512 uint32_t nxge_port_rcr_size; 3513 3514 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3515 "==> nxge_map_rxdma_channel_cfg_ring")); 3516 3517 cntl_dmap = *dma_cntl_p; 3518 3519 /* Map in the receive block ring */ 3520 rbrp = *rbr_p; 3521 dmap = (p_nxge_dma_common_t)&rbrp->rbr_desc; 3522 nxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 3523 /* 3524 * Zero out buffer block ring descriptors. 3525 */ 3526 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3527 3528 rcfga_p = &(rbrp->rbr_cfga); 3529 rcfgb_p = &(rbrp->rbr_cfgb); 3530 kick_p = &(rbrp->rbr_kick); 3531 rcfga_p->value = 0; 3532 rcfgb_p->value = 0; 3533 kick_p->value = 0; 3534 rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 3535 rcfga_p->value = (rbrp->rbr_addr & 3536 (RBR_CFIG_A_STDADDR_MASK | 3537 RBR_CFIG_A_STDADDR_BASE_MASK)); 3538 rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 3539 3540 rcfgb_p->bits.ldw.bufsz0 = rbrp->pkt_buf_size0; 3541 rcfgb_p->bits.ldw.vld0 = 1; 3542 rcfgb_p->bits.ldw.bufsz1 = rbrp->pkt_buf_size1; 3543 rcfgb_p->bits.ldw.vld1 = 1; 3544 rcfgb_p->bits.ldw.bufsz2 = rbrp->pkt_buf_size2; 3545 rcfgb_p->bits.ldw.vld2 = 1; 3546 rcfgb_p->bits.ldw.bksize = nxgep->rx_bksize_code; 3547 3548 /* 3549 * For each buffer block, enter receive block address to the ring. 3550 */ 3551 rbr_vaddrp = (uint32_t *)dmap->kaddrp; 3552 rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 3553 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3554 "==> nxge_map_rxdma_channel_cfg_ring: channel %d " 3555 "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 3556 3557 rx_msg_ring = rbrp->rx_msg_ring; 3558 for (i = 0; i < rbrp->tnblocks; i++) { 3559 rx_msg_p = rx_msg_ring[i]; 3560 rx_msg_p->nxgep = nxgep; 3561 rx_msg_p->rx_rbr_p = rbrp; 3562 bkaddr = (uint32_t) 3563 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress 3564 >> RBR_BKADDR_SHIFT)); 3565 rx_msg_p->free = B_FALSE; 3566 rx_msg_p->max_usage_cnt = 0xbaddcafe; 3567 3568 *rbr_vaddrp++ = bkaddr; 3569 } 3570 3571 kick_p->bits.ldw.bkadd = rbrp->rbb_max; 3572 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 3573 3574 rbrp->rbr_rd_index = 0; 3575 3576 rbrp->rbr_consumed = 0; 3577 rbrp->rbr_use_bcopy = B_TRUE; 3578 rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 3579 /* 3580 * Do bcopy on packets greater than bcopy size once 3581 * the lo threshold is reached. 3582 * This lo threshold should be less than the hi threshold. 3583 * 3584 * Do bcopy on every packet once the hi threshold is reached. 3585 */ 3586 if (nxge_rx_threshold_lo >= nxge_rx_threshold_hi) { 3587 /* default it to use hi */ 3588 nxge_rx_threshold_lo = nxge_rx_threshold_hi; 3589 } 3590 3591 if (nxge_rx_buf_size_type > NXGE_RBR_TYPE2) { 3592 nxge_rx_buf_size_type = NXGE_RBR_TYPE2; 3593 } 3594 rbrp->rbr_bufsize_type = nxge_rx_buf_size_type; 3595 3596 switch (nxge_rx_threshold_hi) { 3597 default: 3598 case NXGE_RX_COPY_NONE: 3599 /* Do not do bcopy at all */ 3600 rbrp->rbr_use_bcopy = B_FALSE; 3601 rbrp->rbr_threshold_hi = rbrp->rbb_max; 3602 break; 3603 3604 case NXGE_RX_COPY_1: 3605 case NXGE_RX_COPY_2: 3606 case NXGE_RX_COPY_3: 3607 case NXGE_RX_COPY_4: 3608 case NXGE_RX_COPY_5: 3609 case NXGE_RX_COPY_6: 3610 case NXGE_RX_COPY_7: 3611 rbrp->rbr_threshold_hi = 3612 rbrp->rbb_max * 3613 (nxge_rx_threshold_hi)/NXGE_RX_BCOPY_SCALE; 3614 break; 3615 3616 case NXGE_RX_COPY_ALL: 3617 rbrp->rbr_threshold_hi = 0; 3618 break; 3619 } 3620 3621 switch (nxge_rx_threshold_lo) { 3622 default: 3623 case NXGE_RX_COPY_NONE: 3624 /* Do not do bcopy at all */ 3625 if (rbrp->rbr_use_bcopy) { 3626 rbrp->rbr_use_bcopy = B_FALSE; 3627 } 3628 rbrp->rbr_threshold_lo = rbrp->rbb_max; 3629 break; 3630 3631 case NXGE_RX_COPY_1: 3632 case NXGE_RX_COPY_2: 3633 case NXGE_RX_COPY_3: 3634 case NXGE_RX_COPY_4: 3635 case NXGE_RX_COPY_5: 3636 case NXGE_RX_COPY_6: 3637 case NXGE_RX_COPY_7: 3638 rbrp->rbr_threshold_lo = 3639 rbrp->rbb_max * 3640 (nxge_rx_threshold_lo)/NXGE_RX_BCOPY_SCALE; 3641 break; 3642 3643 case NXGE_RX_COPY_ALL: 3644 rbrp->rbr_threshold_lo = 0; 3645 break; 3646 } 3647 3648 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3649 "nxge_map_rxdma_channel_cfg_ring: channel %d " 3650 "rbb_max %d " 3651 "rbrp->rbr_bufsize_type %d " 3652 "rbb_threshold_hi %d " 3653 "rbb_threshold_lo %d", 3654 dma_channel, 3655 rbrp->rbb_max, 3656 rbrp->rbr_bufsize_type, 3657 rbrp->rbr_threshold_hi, 3658 rbrp->rbr_threshold_lo)); 3659 3660 rbrp->page_valid.value = 0; 3661 rbrp->page_mask_1.value = rbrp->page_mask_2.value = 0; 3662 rbrp->page_value_1.value = rbrp->page_value_2.value = 0; 3663 rbrp->page_reloc_1.value = rbrp->page_reloc_2.value = 0; 3664 rbrp->page_hdl.value = 0; 3665 3666 rbrp->page_valid.bits.ldw.page0 = 1; 3667 rbrp->page_valid.bits.ldw.page1 = 1; 3668 3669 /* Map in the receive completion ring */ 3670 rcrp = (p_rx_rcr_ring_t) 3671 KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 3672 rcrp->rdc = dma_channel; 3673 3674 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 3675 rcrp->comp_size = nxge_port_rcr_size; 3676 rcrp->comp_wrap_mask = nxge_port_rcr_size - 1; 3677 3678 rcrp->max_receive_pkts = nxge_max_rx_pkts; 3679 3680 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 3681 nxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 3682 sizeof (rcr_entry_t)); 3683 rcrp->comp_rd_index = 0; 3684 rcrp->comp_wt_index = 0; 3685 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 3686 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3687 #if defined(__i386) 3688 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3689 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3690 #else 3691 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3692 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3693 #endif 3694 3695 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 3696 (nxge_port_rcr_size - 1); 3697 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 3698 (nxge_port_rcr_size - 1); 3699 3700 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3701 "==> nxge_map_rxdma_channel_cfg_ring: " 3702 "channel %d " 3703 "rbr_vaddrp $%p " 3704 "rcr_desc_rd_head_p $%p " 3705 "rcr_desc_rd_head_pp $%p " 3706 "rcr_desc_rd_last_p $%p " 3707 "rcr_desc_rd_last_pp $%p ", 3708 dma_channel, 3709 rbr_vaddrp, 3710 rcrp->rcr_desc_rd_head_p, 3711 rcrp->rcr_desc_rd_head_pp, 3712 rcrp->rcr_desc_last_p, 3713 rcrp->rcr_desc_last_pp)); 3714 3715 /* 3716 * Zero out buffer block ring descriptors. 3717 */ 3718 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3719 rcrp->intr_timeout = nxgep->intr_timeout; 3720 rcrp->intr_threshold = nxgep->intr_threshold; 3721 rcrp->full_hdr_flag = B_FALSE; 3722 rcrp->sw_priv_hdr_len = 0; 3723 3724 cfga_p = &(rcrp->rcr_cfga); 3725 cfgb_p = &(rcrp->rcr_cfgb); 3726 cfga_p->value = 0; 3727 cfgb_p->value = 0; 3728 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 3729 cfga_p->value = (rcrp->rcr_addr & 3730 (RCRCFIG_A_STADDR_MASK | 3731 RCRCFIG_A_STADDR_BASE_MASK)); 3732 3733 rcfga_p->value |= ((uint64_t)rcrp->comp_size << 3734 RCRCFIG_A_LEN_SHIF); 3735 3736 /* 3737 * Timeout should be set based on the system clock divider. 3738 * The following timeout value of 1 assumes that the 3739 * granularity (1000) is 3 microseconds running at 300MHz. 3740 */ 3741 cfgb_p->bits.ldw.pthres = rcrp->intr_threshold; 3742 cfgb_p->bits.ldw.timeout = rcrp->intr_timeout; 3743 cfgb_p->bits.ldw.entout = 1; 3744 3745 /* Map in the mailbox */ 3746 mboxp = (p_rx_mbox_t) 3747 KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 3748 dmap = (p_nxge_dma_common_t)&mboxp->rx_mbox; 3749 nxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 3750 cfig1_p = (p_rxdma_cfig1_t)&mboxp->rx_cfg1; 3751 cfig2_p = (p_rxdma_cfig2_t)&mboxp->rx_cfg2; 3752 cfig1_p->value = cfig2_p->value = 0; 3753 3754 mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 3755 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3756 "==> nxge_map_rxdma_channel_cfg_ring: " 3757 "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 3758 dma_channel, cfig1_p->value, cfig2_p->value, 3759 mboxp->mbox_addr)); 3760 3761 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress >> 32 3762 & 0xfff); 3763 cfig1_p->bits.ldw.mbaddr_h = dmaaddrp; 3764 3765 3766 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 3767 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 3768 RXDMA_CFIG2_MBADDR_L_MASK); 3769 3770 cfig2_p->bits.ldw.mbaddr = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 3771 3772 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3773 "==> nxge_map_rxdma_channel_cfg_ring: " 3774 "channel %d damaddrp $%p " 3775 "cfg1 0x%016llx cfig2 0x%016llx", 3776 dma_channel, dmaaddrp, 3777 cfig1_p->value, cfig2_p->value)); 3778 3779 cfig2_p->bits.ldw.full_hdr = rcrp->full_hdr_flag; 3780 cfig2_p->bits.ldw.offset = rcrp->sw_priv_hdr_len; 3781 3782 rbrp->rx_rcr_p = rcrp; 3783 rcrp->rx_rbr_p = rbrp; 3784 *rcr_p = rcrp; 3785 *rx_mbox_p = mboxp; 3786 3787 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3788 "<== nxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 3789 3790 return (status); 3791 } 3792 3793 /*ARGSUSED*/ 3794 static void 3795 nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t nxgep, 3796 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3797 { 3798 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3799 "==> nxge_unmap_rxdma_channel_cfg_ring: channel %d", 3800 rcr_p->rdc)); 3801 3802 KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 3803 KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 3804 3805 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3806 "<== nxge_unmap_rxdma_channel_cfg_ring")); 3807 } 3808 3809 static nxge_status_t 3810 nxge_map_rxdma_channel_buf_ring(p_nxge_t nxgep, uint16_t channel, 3811 p_nxge_dma_common_t *dma_buf_p, 3812 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 3813 { 3814 p_rx_rbr_ring_t rbrp; 3815 p_nxge_dma_common_t dma_bufp, tmp_bufp; 3816 p_rx_msg_t *rx_msg_ring; 3817 p_rx_msg_t rx_msg_p; 3818 p_mblk_t mblk_p; 3819 3820 rxring_info_t *ring_info; 3821 nxge_status_t status = NXGE_OK; 3822 int i, j, index; 3823 uint32_t size, bsize, nblocks, nmsgs; 3824 3825 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3826 "==> nxge_map_rxdma_channel_buf_ring: channel %d", 3827 channel)); 3828 3829 dma_bufp = tmp_bufp = *dma_buf_p; 3830 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3831 " nxge_map_rxdma_channel_buf_ring: channel %d to map %d " 3832 "chunks bufp 0x%016llx", 3833 channel, num_chunks, dma_bufp)); 3834 3835 nmsgs = 0; 3836 for (i = 0; i < num_chunks; i++, tmp_bufp++) { 3837 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3838 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3839 "bufp 0x%016llx nblocks %d nmsgs %d", 3840 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 3841 nmsgs += tmp_bufp->nblocks; 3842 } 3843 if (!nmsgs) { 3844 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3845 "<== nxge_map_rxdma_channel_buf_ring: channel %d " 3846 "no msg blocks", 3847 channel)); 3848 status = NXGE_ERROR; 3849 goto nxge_map_rxdma_channel_buf_ring_exit; 3850 } 3851 3852 rbrp = (p_rx_rbr_ring_t)KMEM_ZALLOC(sizeof (*rbrp), KM_SLEEP); 3853 3854 size = nmsgs * sizeof (p_rx_msg_t); 3855 rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 3856 ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 3857 KM_SLEEP); 3858 3859 MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 3860 (void *)nxgep->interrupt_cookie); 3861 MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 3862 (void *)nxgep->interrupt_cookie); 3863 rbrp->rdc = channel; 3864 rbrp->num_blocks = num_chunks; 3865 rbrp->tnblocks = nmsgs; 3866 rbrp->rbb_max = nmsgs; 3867 rbrp->rbr_max_size = nmsgs; 3868 rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 3869 3870 /* 3871 * Buffer sizes suggested by NIU architect. 3872 * 256, 512 and 2K. 3873 */ 3874 3875 rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 3876 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 3877 rbrp->npi_pkt_buf_size0 = SIZE_256B; 3878 3879 rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 3880 rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 3881 rbrp->npi_pkt_buf_size1 = SIZE_1KB; 3882 3883 rbrp->block_size = nxgep->rx_default_block_size; 3884 3885 if (!nxge_jumbo_enable && !nxgep->param_arr[param_accept_jumbo].value) { 3886 rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 3887 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 3888 rbrp->npi_pkt_buf_size2 = SIZE_2KB; 3889 } else { 3890 if (rbrp->block_size >= 0x2000) { 3891 rbrp->pkt_buf_size2 = RBR_BUFSZ2_8K; 3892 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_8K_BYTES; 3893 rbrp->npi_pkt_buf_size2 = SIZE_8KB; 3894 } else { 3895 rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 3896 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 3897 rbrp->npi_pkt_buf_size2 = SIZE_4KB; 3898 } 3899 } 3900 3901 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3902 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3903 "actual rbr max %d rbb_max %d nmsgs %d " 3904 "rbrp->block_size %d default_block_size %d " 3905 "(config nxge_rbr_size %d nxge_rbr_spare_size %d)", 3906 channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 3907 rbrp->block_size, nxgep->rx_default_block_size, 3908 nxge_rbr_size, nxge_rbr_spare_size)); 3909 3910 /* Map in buffers from the buffer pool. */ 3911 index = 0; 3912 for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 3913 bsize = dma_bufp->block_size; 3914 nblocks = dma_bufp->nblocks; 3915 #if defined(__i386) 3916 ring_info->buffer[i].dvma_addr = (uint32_t)dma_bufp->ioaddr_pp; 3917 #else 3918 ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 3919 #endif 3920 ring_info->buffer[i].buf_index = i; 3921 ring_info->buffer[i].buf_size = dma_bufp->alength; 3922 ring_info->buffer[i].start_index = index; 3923 #if defined(__i386) 3924 ring_info->buffer[i].kaddr = (uint32_t)dma_bufp->kaddrp; 3925 #else 3926 ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 3927 #endif 3928 3929 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3930 " nxge_map_rxdma_channel_buf_ring: map channel %d " 3931 "chunk %d" 3932 " nblocks %d chunk_size %x block_size 0x%x " 3933 "dma_bufp $%p", channel, i, 3934 dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize, 3935 dma_bufp)); 3936 3937 for (j = 0; j < nblocks; j++) { 3938 if ((rx_msg_p = nxge_allocb(bsize, BPRI_LO, 3939 dma_bufp)) == NULL) { 3940 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3941 "allocb failed (index %d i %d j %d)", 3942 index, i, j)); 3943 goto nxge_map_rxdma_channel_buf_ring_fail1; 3944 } 3945 rx_msg_ring[index] = rx_msg_p; 3946 rx_msg_p->block_index = index; 3947 rx_msg_p->shifted_addr = (uint32_t) 3948 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 3949 RBR_BKADDR_SHIFT)); 3950 3951 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3952 "index %d j %d rx_msg_p $%p mblk %p", 3953 index, j, rx_msg_p, rx_msg_p->rx_mblk_p)); 3954 3955 mblk_p = rx_msg_p->rx_mblk_p; 3956 mblk_p->b_wptr = mblk_p->b_rptr + bsize; 3957 3958 rbrp->rbr_ref_cnt++; 3959 index++; 3960 rx_msg_p->buf_dma.dma_channel = channel; 3961 } 3962 3963 rbrp->rbr_alloc_type = DDI_MEM_ALLOC; 3964 if (dma_bufp->contig_alloc_type) { 3965 rbrp->rbr_alloc_type = CONTIG_MEM_ALLOC; 3966 } 3967 3968 if (dma_bufp->kmem_alloc_type) { 3969 rbrp->rbr_alloc_type = KMEM_ALLOC; 3970 } 3971 3972 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3973 " nxge_map_rxdma_channel_buf_ring: map channel %d " 3974 "chunk %d" 3975 " nblocks %d chunk_size %x block_size 0x%x " 3976 "dma_bufp $%p", 3977 channel, i, 3978 dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize, 3979 dma_bufp)); 3980 } 3981 if (i < rbrp->num_blocks) { 3982 goto nxge_map_rxdma_channel_buf_ring_fail1; 3983 } 3984 3985 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3986 "nxge_map_rxdma_channel_buf_ring: done buf init " 3987 "channel %d msg block entries %d", 3988 channel, index)); 3989 ring_info->block_size_mask = bsize - 1; 3990 rbrp->rx_msg_ring = rx_msg_ring; 3991 rbrp->dma_bufp = dma_buf_p; 3992 rbrp->ring_info = ring_info; 3993 3994 status = nxge_rxbuf_index_info_init(nxgep, rbrp); 3995 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3996 " nxge_map_rxdma_channel_buf_ring: " 3997 "channel %d done buf info init", channel)); 3998 3999 /* 4000 * Finally, permit nxge_freeb() to call nxge_post_page(). 4001 */ 4002 rbrp->rbr_state = RBR_POSTING; 4003 4004 *rbr_p = rbrp; 4005 goto nxge_map_rxdma_channel_buf_ring_exit; 4006 4007 nxge_map_rxdma_channel_buf_ring_fail1: 4008 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4009 " nxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 4010 channel, status)); 4011 4012 index--; 4013 for (; index >= 0; index--) { 4014 rx_msg_p = rx_msg_ring[index]; 4015 if (rx_msg_p != NULL) { 4016 freeb(rx_msg_p->rx_mblk_p); 4017 rx_msg_ring[index] = NULL; 4018 } 4019 } 4020 nxge_map_rxdma_channel_buf_ring_fail: 4021 MUTEX_DESTROY(&rbrp->post_lock); 4022 MUTEX_DESTROY(&rbrp->lock); 4023 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 4024 KMEM_FREE(rx_msg_ring, size); 4025 KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 4026 4027 status = NXGE_ERROR; 4028 4029 nxge_map_rxdma_channel_buf_ring_exit: 4030 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4031 "<== nxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 4032 4033 return (status); 4034 } 4035 4036 /*ARGSUSED*/ 4037 static void 4038 nxge_unmap_rxdma_channel_buf_ring(p_nxge_t nxgep, 4039 p_rx_rbr_ring_t rbr_p) 4040 { 4041 p_rx_msg_t *rx_msg_ring; 4042 p_rx_msg_t rx_msg_p; 4043 rxring_info_t *ring_info; 4044 int i; 4045 uint32_t size; 4046 #ifdef NXGE_DEBUG 4047 int num_chunks; 4048 #endif 4049 4050 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4051 "==> nxge_unmap_rxdma_channel_buf_ring")); 4052 if (rbr_p == NULL) { 4053 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4054 "<== nxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 4055 return; 4056 } 4057 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4058 "==> nxge_unmap_rxdma_channel_buf_ring: channel %d", 4059 rbr_p->rdc)); 4060 4061 rx_msg_ring = rbr_p->rx_msg_ring; 4062 ring_info = rbr_p->ring_info; 4063 4064 if (rx_msg_ring == NULL || ring_info == NULL) { 4065 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4066 "<== nxge_unmap_rxdma_channel_buf_ring: " 4067 "rx_msg_ring $%p ring_info $%p", 4068 rx_msg_p, ring_info)); 4069 return; 4070 } 4071 4072 #ifdef NXGE_DEBUG 4073 num_chunks = rbr_p->num_blocks; 4074 #endif 4075 size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 4076 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4077 " nxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 4078 "tnblocks %d (max %d) size ptrs %d ", 4079 rbr_p->rdc, num_chunks, 4080 rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 4081 4082 for (i = 0; i < rbr_p->tnblocks; i++) { 4083 rx_msg_p = rx_msg_ring[i]; 4084 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4085 " nxge_unmap_rxdma_channel_buf_ring: " 4086 "rx_msg_p $%p", 4087 rx_msg_p)); 4088 if (rx_msg_p != NULL) { 4089 freeb(rx_msg_p->rx_mblk_p); 4090 rx_msg_ring[i] = NULL; 4091 } 4092 } 4093 4094 /* 4095 * We no longer may use the mutex <post_lock>. By setting 4096 * <rbr_state> to anything but POSTING, we prevent 4097 * nxge_post_page() from accessing a dead mutex. 4098 */ 4099 rbr_p->rbr_state = RBR_UNMAPPING; 4100 MUTEX_DESTROY(&rbr_p->post_lock); 4101 4102 MUTEX_DESTROY(&rbr_p->lock); 4103 4104 if (rbr_p->rbr_ref_cnt == 0) { 4105 /* 4106 * This is the normal state of affairs. 4107 * Need to free the following buffers: 4108 * - data buffers 4109 * - rx_msg ring 4110 * - ring_info 4111 * - rbr ring 4112 */ 4113 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4114 "unmap_rxdma_buf_ring: No outstanding - freeing ")); 4115 nxge_rxdma_databuf_free(rbr_p); 4116 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 4117 KMEM_FREE(rx_msg_ring, size); 4118 KMEM_FREE(rbr_p, sizeof (*rbr_p)); 4119 } else { 4120 /* 4121 * Some of our buffers are still being used. 4122 * Therefore, tell nxge_freeb() this ring is 4123 * unmapped, so it may free <rbr_p> for us. 4124 */ 4125 rbr_p->rbr_state = RBR_UNMAPPED; 4126 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4127 "unmap_rxdma_buf_ring: %d %s outstanding.", 4128 rbr_p->rbr_ref_cnt, 4129 rbr_p->rbr_ref_cnt == 1 ? "msg" : "msgs")); 4130 } 4131 4132 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4133 "<== nxge_unmap_rxdma_channel_buf_ring")); 4134 } 4135 4136 /* 4137 * nxge_rxdma_hw_start_common 4138 * 4139 * Arguments: 4140 * nxgep 4141 * 4142 * Notes: 4143 * 4144 * NPI/NXGE function calls: 4145 * nxge_init_fzc_rx_common(); 4146 * nxge_init_fzc_rxdma_port(); 4147 * 4148 * Registers accessed: 4149 * 4150 * Context: 4151 * Service domain 4152 */ 4153 static nxge_status_t 4154 nxge_rxdma_hw_start_common(p_nxge_t nxgep) 4155 { 4156 nxge_status_t status = NXGE_OK; 4157 4158 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 4159 4160 /* 4161 * Load the sharable parameters by writing to the 4162 * function zero control registers. These FZC registers 4163 * should be initialized only once for the entire chip. 4164 */ 4165 (void) nxge_init_fzc_rx_common(nxgep); 4166 4167 /* 4168 * Initialize the RXDMA port specific FZC control configurations. 4169 * These FZC registers are pertaining to each port. 4170 */ 4171 (void) nxge_init_fzc_rxdma_port(nxgep); 4172 4173 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 4174 4175 return (status); 4176 } 4177 4178 static nxge_status_t 4179 nxge_rxdma_hw_start(p_nxge_t nxgep, int channel) 4180 { 4181 int i, ndmas; 4182 p_rx_rbr_rings_t rx_rbr_rings; 4183 p_rx_rbr_ring_t *rbr_rings; 4184 p_rx_rcr_rings_t rx_rcr_rings; 4185 p_rx_rcr_ring_t *rcr_rings; 4186 p_rx_mbox_areas_t rx_mbox_areas_p; 4187 p_rx_mbox_t *rx_mbox_p; 4188 nxge_status_t status = NXGE_OK; 4189 4190 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start")); 4191 4192 rx_rbr_rings = nxgep->rx_rbr_rings; 4193 rx_rcr_rings = nxgep->rx_rcr_rings; 4194 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 4195 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4196 "<== nxge_rxdma_hw_start: NULL ring pointers")); 4197 return (NXGE_ERROR); 4198 } 4199 ndmas = rx_rbr_rings->ndmas; 4200 if (ndmas == 0) { 4201 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4202 "<== nxge_rxdma_hw_start: no dma channel allocated")); 4203 return (NXGE_ERROR); 4204 } 4205 4206 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4207 "==> nxge_rxdma_hw_start (ndmas %d)", ndmas)); 4208 4209 rbr_rings = rx_rbr_rings->rbr_rings; 4210 rcr_rings = rx_rcr_rings->rcr_rings; 4211 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 4212 if (rx_mbox_areas_p) { 4213 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 4214 } 4215 4216 i = channel; 4217 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4218 "==> nxge_rxdma_hw_start (ndmas %d) channel %d", 4219 ndmas, channel)); 4220 status = nxge_rxdma_start_channel(nxgep, channel, 4221 (p_rx_rbr_ring_t)rbr_rings[i], 4222 (p_rx_rcr_ring_t)rcr_rings[i], 4223 (p_rx_mbox_t)rx_mbox_p[i]); 4224 if (status != NXGE_OK) { 4225 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4226 "==> nxge_rxdma_hw_start: disable " 4227 "(status 0x%x channel %d)", status, channel)); 4228 return (status); 4229 } 4230 4231 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start: " 4232 "rx_rbr_rings 0x%016llx rings 0x%016llx", 4233 rx_rbr_rings, rx_rcr_rings)); 4234 4235 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4236 "==> nxge_rxdma_hw_start: (status 0x%x)", status)); 4237 4238 return (status); 4239 } 4240 4241 static void 4242 nxge_rxdma_hw_stop(p_nxge_t nxgep, int channel) 4243 { 4244 p_rx_rbr_rings_t rx_rbr_rings; 4245 p_rx_rcr_rings_t rx_rcr_rings; 4246 4247 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop")); 4248 4249 rx_rbr_rings = nxgep->rx_rbr_rings; 4250 rx_rcr_rings = nxgep->rx_rcr_rings; 4251 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 4252 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4253 "<== nxge_rxdma_hw_stop: NULL ring pointers")); 4254 return; 4255 } 4256 4257 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4258 "==> nxge_rxdma_hw_stop(channel %d)", 4259 channel)); 4260 (void) nxge_rxdma_stop_channel(nxgep, channel); 4261 4262 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop: " 4263 "rx_rbr_rings 0x%016llx rings 0x%016llx", 4264 rx_rbr_rings, rx_rcr_rings)); 4265 4266 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_hw_stop")); 4267 } 4268 4269 4270 static nxge_status_t 4271 nxge_rxdma_start_channel(p_nxge_t nxgep, uint16_t channel, 4272 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 4273 4274 { 4275 npi_handle_t handle; 4276 npi_status_t rs = NPI_SUCCESS; 4277 rx_dma_ctl_stat_t cs; 4278 rx_dma_ent_msk_t ent_mask; 4279 nxge_status_t status = NXGE_OK; 4280 4281 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel")); 4282 4283 handle = NXGE_DEV_NPI_HANDLE(nxgep); 4284 4285 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "nxge_rxdma_start_channel: " 4286 "npi handle addr $%p acc $%p", 4287 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 4288 4289 /* Reset RXDMA channel, but not if you're a guest. */ 4290 if (!isLDOMguest(nxgep)) { 4291 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4292 if (rs != NPI_SUCCESS) { 4293 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4294 "==> nxge_init_fzc_rdc: " 4295 "npi_rxdma_cfg_rdc_reset(%d) returned 0x%08x", 4296 channel, rs)); 4297 return (NXGE_ERROR | rs); 4298 } 4299 4300 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4301 "==> nxge_rxdma_start_channel: reset done: channel %d", 4302 channel)); 4303 } 4304 4305 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 4306 if (isLDOMguest(nxgep)) 4307 (void) nxge_rdc_lp_conf(nxgep, channel); 4308 #endif 4309 4310 /* 4311 * Initialize the RXDMA channel specific FZC control 4312 * configurations. These FZC registers are pertaining 4313 * to each RX channel (logical pages). 4314 */ 4315 if (!isLDOMguest(nxgep)) { 4316 status = nxge_init_fzc_rxdma_channel(nxgep, channel); 4317 if (status != NXGE_OK) { 4318 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4319 "==> nxge_rxdma_start_channel: " 4320 "init fzc rxdma failed (0x%08x channel %d)", 4321 status, channel)); 4322 return (status); 4323 } 4324 4325 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4326 "==> nxge_rxdma_start_channel: fzc done")); 4327 } 4328 4329 /* Set up the interrupt event masks. */ 4330 ent_mask.value = 0; 4331 ent_mask.value |= RX_DMA_ENT_MSK_RBREMPTY_MASK; 4332 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 4333 &ent_mask); 4334 if (rs != NPI_SUCCESS) { 4335 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4336 "==> nxge_rxdma_start_channel: " 4337 "init rxdma event masks failed " 4338 "(0x%08x channel %d)", 4339 status, channel)); 4340 return (NXGE_ERROR | rs); 4341 } 4342 4343 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4344 "==> nxge_rxdma_start_channel: " 4345 "event done: channel %d (mask 0x%016llx)", 4346 channel, ent_mask.value)); 4347 4348 /* Initialize the receive DMA control and status register */ 4349 cs.value = 0; 4350 cs.bits.hdw.mex = 1; 4351 cs.bits.hdw.rcrthres = 1; 4352 cs.bits.hdw.rcrto = 1; 4353 cs.bits.hdw.rbr_empty = 1; 4354 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs); 4355 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 4356 "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 4357 if (status != NXGE_OK) { 4358 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4359 "==> nxge_rxdma_start_channel: " 4360 "init rxdma control register failed (0x%08x channel %d", 4361 status, channel)); 4362 return (status); 4363 } 4364 4365 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 4366 "control done - channel %d cs 0x%016llx", channel, cs.value)); 4367 4368 /* 4369 * Load RXDMA descriptors, buffers, mailbox, 4370 * initialise the receive DMA channels and 4371 * enable each DMA channel. 4372 */ 4373 status = nxge_enable_rxdma_channel(nxgep, 4374 channel, rbr_p, rcr_p, mbox_p); 4375 4376 if (status != NXGE_OK) { 4377 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4378 " nxge_rxdma_start_channel: " 4379 " enable rxdma failed (0x%08x channel %d)", 4380 status, channel)); 4381 return (status); 4382 } 4383 4384 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4385 "==> nxge_rxdma_start_channel: enabled channel %d")); 4386 4387 if (isLDOMguest(nxgep)) { 4388 /* Add interrupt handler for this channel. */ 4389 if (nxge_hio_intr_add(nxgep, VP_BOUND_RX, channel) 4390 != NXGE_OK) { 4391 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4392 " nxge_rxdma_start_channel: " 4393 " nxge_hio_intr_add failed (0x%08x channel %d)", 4394 status, channel)); 4395 } 4396 } 4397 4398 ent_mask.value = 0; 4399 ent_mask.value |= (RX_DMA_ENT_MSK_WRED_DROP_MASK | 4400 RX_DMA_ENT_MSK_PTDROP_PKT_MASK); 4401 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 4402 &ent_mask); 4403 if (rs != NPI_SUCCESS) { 4404 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4405 "==> nxge_rxdma_start_channel: " 4406 "init rxdma event masks failed (0x%08x channel %d)", 4407 status, channel)); 4408 return (NXGE_ERROR | rs); 4409 } 4410 4411 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 4412 "control done - channel %d cs 0x%016llx", channel, cs.value)); 4413 4414 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_start_channel")); 4415 4416 return (NXGE_OK); 4417 } 4418 4419 static nxge_status_t 4420 nxge_rxdma_stop_channel(p_nxge_t nxgep, uint16_t channel) 4421 { 4422 npi_handle_t handle; 4423 npi_status_t rs = NPI_SUCCESS; 4424 rx_dma_ctl_stat_t cs; 4425 rx_dma_ent_msk_t ent_mask; 4426 nxge_status_t status = NXGE_OK; 4427 4428 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel")); 4429 4430 handle = NXGE_DEV_NPI_HANDLE(nxgep); 4431 4432 NXGE_DEBUG_MSG((nxgep, RX_CTL, "nxge_rxdma_stop_channel: " 4433 "npi handle addr $%p acc $%p", 4434 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 4435 4436 if (!isLDOMguest(nxgep)) { 4437 /* 4438 * Stop RxMAC = A.9.2.6 4439 */ 4440 if (nxge_rx_mac_disable(nxgep) != NXGE_OK) { 4441 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4442 "nxge_rxdma_stop_channel: " 4443 "Failed to disable RxMAC")); 4444 } 4445 4446 /* 4447 * Drain IPP Port = A.9.3.6 4448 */ 4449 (void) nxge_ipp_drain(nxgep); 4450 } 4451 4452 /* Reset RXDMA channel */ 4453 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4454 if (rs != NPI_SUCCESS) { 4455 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4456 " nxge_rxdma_stop_channel: " 4457 " reset rxdma failed (0x%08x channel %d)", 4458 rs, channel)); 4459 return (NXGE_ERROR | rs); 4460 } 4461 4462 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4463 "==> nxge_rxdma_stop_channel: reset done")); 4464 4465 /* Set up the interrupt event masks. */ 4466 ent_mask.value = RX_DMA_ENT_MSK_ALL; 4467 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 4468 &ent_mask); 4469 if (rs != NPI_SUCCESS) { 4470 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4471 "==> nxge_rxdma_stop_channel: " 4472 "set rxdma event masks failed (0x%08x channel %d)", 4473 rs, channel)); 4474 return (NXGE_ERROR | rs); 4475 } 4476 4477 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4478 "==> nxge_rxdma_stop_channel: event done")); 4479 4480 /* 4481 * Initialize the receive DMA control and status register 4482 */ 4483 cs.value = 0; 4484 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs); 4485 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel: control " 4486 " to default (all 0s) 0x%08x", cs.value)); 4487 if (status != NXGE_OK) { 4488 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4489 " nxge_rxdma_stop_channel: init rxdma" 4490 " control register failed (0x%08x channel %d", 4491 status, channel)); 4492 return (status); 4493 } 4494 4495 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4496 "==> nxge_rxdma_stop_channel: control done")); 4497 4498 /* 4499 * Make sure channel is disabled. 4500 */ 4501 status = nxge_disable_rxdma_channel(nxgep, channel); 4502 4503 if (status != NXGE_OK) { 4504 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4505 " nxge_rxdma_stop_channel: " 4506 " init enable rxdma failed (0x%08x channel %d)", 4507 status, channel)); 4508 return (status); 4509 } 4510 4511 if (!isLDOMguest(nxgep)) { 4512 /* 4513 * Enable RxMAC = A.9.2.10 4514 */ 4515 if (nxge_rx_mac_enable(nxgep) != NXGE_OK) { 4516 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4517 "nxge_rxdma_stop_channel: Rx MAC still disabled")); 4518 } 4519 } 4520 4521 NXGE_DEBUG_MSG((nxgep, 4522 RX_CTL, "==> nxge_rxdma_stop_channel: disable done")); 4523 4524 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_channel")); 4525 4526 return (NXGE_OK); 4527 } 4528 4529 nxge_status_t 4530 nxge_rxdma_handle_sys_errors(p_nxge_t nxgep) 4531 { 4532 npi_handle_t handle; 4533 p_nxge_rdc_sys_stats_t statsp; 4534 rx_ctl_dat_fifo_stat_t stat; 4535 uint32_t zcp_err_status; 4536 uint32_t ipp_err_status; 4537 nxge_status_t status = NXGE_OK; 4538 npi_status_t rs = NPI_SUCCESS; 4539 boolean_t my_err = B_FALSE; 4540 4541 handle = nxgep->npi_handle; 4542 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4543 4544 rs = npi_rxdma_rxctl_fifo_error_intr_get(handle, &stat); 4545 4546 if (rs != NPI_SUCCESS) 4547 return (NXGE_ERROR | rs); 4548 4549 if (stat.bits.ldw.id_mismatch) { 4550 statsp->id_mismatch++; 4551 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 4552 NXGE_FM_EREPORT_RDMC_ID_MISMATCH); 4553 /* Global fatal error encountered */ 4554 } 4555 4556 if ((stat.bits.ldw.zcp_eop_err) || (stat.bits.ldw.ipp_eop_err)) { 4557 switch (nxgep->mac.portnum) { 4558 case 0: 4559 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT0) || 4560 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT0)) { 4561 my_err = B_TRUE; 4562 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4563 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4564 } 4565 break; 4566 case 1: 4567 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT1) || 4568 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT1)) { 4569 my_err = B_TRUE; 4570 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4571 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4572 } 4573 break; 4574 case 2: 4575 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT2) || 4576 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT2)) { 4577 my_err = B_TRUE; 4578 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4579 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4580 } 4581 break; 4582 case 3: 4583 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT3) || 4584 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT3)) { 4585 my_err = B_TRUE; 4586 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4587 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4588 } 4589 break; 4590 default: 4591 return (NXGE_ERROR); 4592 } 4593 } 4594 4595 if (my_err) { 4596 status = nxge_rxdma_handle_port_errors(nxgep, ipp_err_status, 4597 zcp_err_status); 4598 if (status != NXGE_OK) 4599 return (status); 4600 } 4601 4602 return (NXGE_OK); 4603 } 4604 4605 static nxge_status_t 4606 nxge_rxdma_handle_port_errors(p_nxge_t nxgep, uint32_t ipp_status, 4607 uint32_t zcp_status) 4608 { 4609 boolean_t rxport_fatal = B_FALSE; 4610 p_nxge_rdc_sys_stats_t statsp; 4611 nxge_status_t status = NXGE_OK; 4612 uint8_t portn; 4613 4614 portn = nxgep->mac.portnum; 4615 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4616 4617 if (ipp_status & (0x1 << portn)) { 4618 statsp->ipp_eop_err++; 4619 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4620 NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR); 4621 rxport_fatal = B_TRUE; 4622 } 4623 4624 if (zcp_status & (0x1 << portn)) { 4625 statsp->zcp_eop_err++; 4626 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4627 NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR); 4628 rxport_fatal = B_TRUE; 4629 } 4630 4631 if (rxport_fatal) { 4632 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4633 " nxge_rxdma_handle_port_error: " 4634 " fatal error on Port #%d\n", 4635 portn)); 4636 status = nxge_rx_port_fatal_err_recover(nxgep); 4637 if (status == NXGE_OK) { 4638 FM_SERVICE_RESTORED(nxgep); 4639 } 4640 } 4641 4642 return (status); 4643 } 4644 4645 static nxge_status_t 4646 nxge_rxdma_fatal_err_recover(p_nxge_t nxgep, uint16_t channel) 4647 { 4648 npi_handle_t handle; 4649 npi_status_t rs = NPI_SUCCESS; 4650 nxge_status_t status = NXGE_OK; 4651 p_rx_rbr_ring_t rbrp; 4652 p_rx_rcr_ring_t rcrp; 4653 p_rx_mbox_t mboxp; 4654 rx_dma_ent_msk_t ent_mask; 4655 p_nxge_dma_common_t dmap; 4656 int ring_idx; 4657 uint32_t ref_cnt; 4658 p_rx_msg_t rx_msg_p; 4659 int i; 4660 uint32_t nxge_port_rcr_size; 4661 4662 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fatal_err_recover")); 4663 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4664 "Recovering from RxDMAChannel#%d error...", channel)); 4665 4666 /* 4667 * Stop the dma channel waits for the stop done. 4668 * If the stop done bit is not set, then create 4669 * an error. 4670 */ 4671 4672 handle = NXGE_DEV_NPI_HANDLE(nxgep); 4673 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Rx DMA stop...")); 4674 4675 ring_idx = nxge_rxdma_get_ring_index(nxgep, channel); 4676 rbrp = (p_rx_rbr_ring_t)nxgep->rx_rbr_rings->rbr_rings[ring_idx]; 4677 rcrp = (p_rx_rcr_ring_t)nxgep->rx_rcr_rings->rcr_rings[ring_idx]; 4678 4679 MUTEX_ENTER(&rcrp->lock); 4680 MUTEX_ENTER(&rbrp->lock); 4681 MUTEX_ENTER(&rbrp->post_lock); 4682 4683 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA channel...")); 4684 4685 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 4686 if (rs != NPI_SUCCESS) { 4687 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4688 "nxge_disable_rxdma_channel:failed")); 4689 goto fail; 4690 } 4691 4692 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA interrupt...")); 4693 4694 /* Disable interrupt */ 4695 ent_mask.value = RX_DMA_ENT_MSK_ALL; 4696 rs = npi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 4697 if (rs != NPI_SUCCESS) { 4698 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4699 "nxge_rxdma_stop_channel: " 4700 "set rxdma event masks failed (channel %d)", 4701 channel)); 4702 } 4703 4704 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel reset...")); 4705 4706 /* Reset RXDMA channel */ 4707 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4708 if (rs != NPI_SUCCESS) { 4709 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4710 "nxge_rxdma_fatal_err_recover: " 4711 " reset rxdma failed (channel %d)", channel)); 4712 goto fail; 4713 } 4714 4715 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 4716 4717 mboxp = 4718 (p_rx_mbox_t)nxgep->rx_mbox_areas_p->rxmbox_areas[ring_idx]; 4719 4720 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 4721 rbrp->rbr_rd_index = 0; 4722 4723 rcrp->comp_rd_index = 0; 4724 rcrp->comp_wt_index = 0; 4725 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 4726 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 4727 #if defined(__i386) 4728 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 4729 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4730 #else 4731 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 4732 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4733 #endif 4734 4735 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 4736 (nxge_port_rcr_size - 1); 4737 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 4738 (nxge_port_rcr_size - 1); 4739 4740 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 4741 bzero((caddr_t)dmap->kaddrp, dmap->alength); 4742 4743 cmn_err(CE_NOTE, "!rbr entries = %d\n", rbrp->rbr_max_size); 4744 4745 for (i = 0; i < rbrp->rbr_max_size; i++) { 4746 rx_msg_p = rbrp->rx_msg_ring[i]; 4747 ref_cnt = rx_msg_p->ref_cnt; 4748 if (ref_cnt != 1) { 4749 if (rx_msg_p->cur_usage_cnt != 4750 rx_msg_p->max_usage_cnt) { 4751 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4752 "buf[%d]: cur_usage_cnt = %d " 4753 "max_usage_cnt = %d\n", i, 4754 rx_msg_p->cur_usage_cnt, 4755 rx_msg_p->max_usage_cnt)); 4756 } else { 4757 /* Buffer can be re-posted */ 4758 rx_msg_p->free = B_TRUE; 4759 rx_msg_p->cur_usage_cnt = 0; 4760 rx_msg_p->max_usage_cnt = 0xbaddcafe; 4761 rx_msg_p->pkt_buf_size = 0; 4762 } 4763 } 4764 } 4765 4766 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel re-start...")); 4767 4768 status = nxge_rxdma_start_channel(nxgep, channel, rbrp, rcrp, mboxp); 4769 if (status != NXGE_OK) { 4770 goto fail; 4771 } 4772 4773 MUTEX_EXIT(&rbrp->post_lock); 4774 MUTEX_EXIT(&rbrp->lock); 4775 MUTEX_EXIT(&rcrp->lock); 4776 4777 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4778 "Recovery Successful, RxDMAChannel#%d Restored", 4779 channel)); 4780 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fatal_err_recover")); 4781 4782 return (NXGE_OK); 4783 fail: 4784 MUTEX_EXIT(&rbrp->post_lock); 4785 MUTEX_EXIT(&rbrp->lock); 4786 MUTEX_EXIT(&rcrp->lock); 4787 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4788 4789 return (NXGE_ERROR | rs); 4790 } 4791 4792 nxge_status_t 4793 nxge_rx_port_fatal_err_recover(p_nxge_t nxgep) 4794 { 4795 nxge_grp_set_t *set = &nxgep->rx_set; 4796 nxge_status_t status = NXGE_OK; 4797 int rdc; 4798 4799 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_port_fatal_err_recover")); 4800 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4801 "Recovering from RxPort error...")); 4802 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disabling RxMAC...\n")); 4803 4804 if (nxge_rx_mac_disable(nxgep) != NXGE_OK) 4805 goto fail; 4806 4807 NXGE_DELAY(1000); 4808 4809 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Stopping all RxDMA channels...")); 4810 4811 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 4812 if ((1 << rdc) & set->owned.map) { 4813 if (nxge_rxdma_fatal_err_recover(nxgep, rdc) 4814 != NXGE_OK) { 4815 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4816 "Could not recover channel %d", rdc)); 4817 } 4818 } 4819 } 4820 4821 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Resetting IPP...")); 4822 4823 /* Reset IPP */ 4824 if (nxge_ipp_reset(nxgep) != NXGE_OK) { 4825 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4826 "nxge_rx_port_fatal_err_recover: " 4827 "Failed to reset IPP")); 4828 goto fail; 4829 } 4830 4831 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset RxMAC...")); 4832 4833 /* Reset RxMAC */ 4834 if (nxge_rx_mac_reset(nxgep) != NXGE_OK) { 4835 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4836 "nxge_rx_port_fatal_err_recover: " 4837 "Failed to reset RxMAC")); 4838 goto fail; 4839 } 4840 4841 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize IPP...")); 4842 4843 /* Re-Initialize IPP */ 4844 if (nxge_ipp_init(nxgep) != NXGE_OK) { 4845 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4846 "nxge_rx_port_fatal_err_recover: " 4847 "Failed to init IPP")); 4848 goto fail; 4849 } 4850 4851 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize RxMAC...")); 4852 4853 /* Re-Initialize RxMAC */ 4854 if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) { 4855 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4856 "nxge_rx_port_fatal_err_recover: " 4857 "Failed to reset RxMAC")); 4858 goto fail; 4859 } 4860 4861 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-enable RxMAC...")); 4862 4863 /* Re-enable RxMAC */ 4864 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) { 4865 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4866 "nxge_rx_port_fatal_err_recover: " 4867 "Failed to enable RxMAC")); 4868 goto fail; 4869 } 4870 4871 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4872 "Recovery Successful, RxPort Restored")); 4873 4874 return (NXGE_OK); 4875 fail: 4876 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4877 return (status); 4878 } 4879 4880 void 4881 nxge_rxdma_inject_err(p_nxge_t nxgep, uint32_t err_id, uint8_t chan) 4882 { 4883 rx_dma_ctl_stat_t cs; 4884 rx_ctl_dat_fifo_stat_t cdfs; 4885 4886 switch (err_id) { 4887 case NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR: 4888 case NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR: 4889 case NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR: 4890 case NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR: 4891 case NXGE_FM_EREPORT_RDMC_RBR_TMOUT: 4892 case NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR: 4893 case NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS: 4894 case NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR: 4895 case NXGE_FM_EREPORT_RDMC_RCRINCON: 4896 case NXGE_FM_EREPORT_RDMC_RCRFULL: 4897 case NXGE_FM_EREPORT_RDMC_RBRFULL: 4898 case NXGE_FM_EREPORT_RDMC_RBRLOGPAGE: 4899 case NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE: 4900 case NXGE_FM_EREPORT_RDMC_CONFIG_ERR: 4901 RXDMA_REG_READ64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4902 chan, &cs.value); 4903 if (err_id == NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR) 4904 cs.bits.hdw.rcr_ack_err = 1; 4905 else if (err_id == NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR) 4906 cs.bits.hdw.dc_fifo_err = 1; 4907 else if (err_id == NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR) 4908 cs.bits.hdw.rcr_sha_par = 1; 4909 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR) 4910 cs.bits.hdw.rbr_pre_par = 1; 4911 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_TMOUT) 4912 cs.bits.hdw.rbr_tmout = 1; 4913 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR) 4914 cs.bits.hdw.rsp_cnt_err = 1; 4915 else if (err_id == NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS) 4916 cs.bits.hdw.byte_en_bus = 1; 4917 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR) 4918 cs.bits.hdw.rsp_dat_err = 1; 4919 else if (err_id == NXGE_FM_EREPORT_RDMC_CONFIG_ERR) 4920 cs.bits.hdw.config_err = 1; 4921 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRINCON) 4922 cs.bits.hdw.rcrincon = 1; 4923 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRFULL) 4924 cs.bits.hdw.rcrfull = 1; 4925 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRFULL) 4926 cs.bits.hdw.rbrfull = 1; 4927 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRLOGPAGE) 4928 cs.bits.hdw.rbrlogpage = 1; 4929 else if (err_id == NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE) 4930 cs.bits.hdw.cfiglogpage = 1; 4931 #if defined(__i386) 4932 cmn_err(CE_NOTE, "!Write 0x%llx to RX_DMA_CTL_STAT_DBG_REG\n", 4933 cs.value); 4934 #else 4935 cmn_err(CE_NOTE, "!Write 0x%lx to RX_DMA_CTL_STAT_DBG_REG\n", 4936 cs.value); 4937 #endif 4938 RXDMA_REG_WRITE64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4939 chan, cs.value); 4940 break; 4941 case NXGE_FM_EREPORT_RDMC_ID_MISMATCH: 4942 case NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR: 4943 case NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR: 4944 cdfs.value = 0; 4945 if (err_id == NXGE_FM_EREPORT_RDMC_ID_MISMATCH) 4946 cdfs.bits.ldw.id_mismatch = (1 << nxgep->mac.portnum); 4947 else if (err_id == NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR) 4948 cdfs.bits.ldw.zcp_eop_err = (1 << nxgep->mac.portnum); 4949 else if (err_id == NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR) 4950 cdfs.bits.ldw.ipp_eop_err = (1 << nxgep->mac.portnum); 4951 #if defined(__i386) 4952 cmn_err(CE_NOTE, 4953 "!Write 0x%llx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 4954 cdfs.value); 4955 #else 4956 cmn_err(CE_NOTE, 4957 "!Write 0x%lx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 4958 cdfs.value); 4959 #endif 4960 NXGE_REG_WR64(nxgep->npi_handle, 4961 RX_CTL_DAT_FIFO_STAT_DBG_REG, cdfs.value); 4962 break; 4963 case NXGE_FM_EREPORT_RDMC_DCF_ERR: 4964 break; 4965 case NXGE_FM_EREPORT_RDMC_RCR_ERR: 4966 break; 4967 } 4968 } 4969 4970 static void 4971 nxge_rxdma_databuf_free(p_rx_rbr_ring_t rbr_p) 4972 { 4973 rxring_info_t *ring_info; 4974 int index; 4975 uint32_t chunk_size; 4976 uint64_t kaddr; 4977 uint_t num_blocks; 4978 4979 NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_rxdma_databuf_free")); 4980 4981 if (rbr_p == NULL) { 4982 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4983 "==> nxge_rxdma_databuf_free: NULL rbr pointer")); 4984 return; 4985 } 4986 4987 if (rbr_p->rbr_alloc_type == DDI_MEM_ALLOC) { 4988 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4989 "==> nxge_rxdma_databuf_free: DDI")); 4990 return; 4991 } 4992 4993 ring_info = rbr_p->ring_info; 4994 if (ring_info == NULL) { 4995 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 4996 "==> nxge_rxdma_databuf_free: NULL ring info")); 4997 return; 4998 } 4999 num_blocks = rbr_p->num_blocks; 5000 for (index = 0; index < num_blocks; index++) { 5001 kaddr = ring_info->buffer[index].kaddr; 5002 chunk_size = ring_info->buffer[index].buf_size; 5003 NXGE_DEBUG_MSG((NULL, DMA_CTL, 5004 "==> nxge_rxdma_databuf_free: free chunk %d " 5005 "kaddrp $%p chunk size %d", 5006 index, kaddr, chunk_size)); 5007 if (kaddr == NULL) continue; 5008 nxge_free_buf(rbr_p->rbr_alloc_type, kaddr, chunk_size); 5009 ring_info->buffer[index].kaddr = NULL; 5010 } 5011 5012 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_databuf_free")); 5013 } 5014 5015 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 5016 extern void contig_mem_free(void *, size_t); 5017 #endif 5018 5019 void 5020 nxge_free_buf(buf_alloc_type_t alloc_type, uint64_t kaddr, uint32_t buf_size) 5021 { 5022 NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_free_buf")); 5023 5024 if (kaddr == NULL || !buf_size) { 5025 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 5026 "==> nxge_free_buf: invalid kaddr $%p size to free %d", 5027 kaddr, buf_size)); 5028 return; 5029 } 5030 5031 switch (alloc_type) { 5032 case KMEM_ALLOC: 5033 NXGE_DEBUG_MSG((NULL, DMA_CTL, 5034 "==> nxge_free_buf: freeing kmem $%p size %d", 5035 kaddr, buf_size)); 5036 #if defined(__i386) 5037 KMEM_FREE((void *)(uint32_t)kaddr, buf_size); 5038 #else 5039 KMEM_FREE((void *)kaddr, buf_size); 5040 #endif 5041 break; 5042 5043 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 5044 case CONTIG_MEM_ALLOC: 5045 NXGE_DEBUG_MSG((NULL, DMA_CTL, 5046 "==> nxge_free_buf: freeing contig_mem kaddr $%p size %d", 5047 kaddr, buf_size)); 5048 contig_mem_free((void *)kaddr, buf_size); 5049 break; 5050 #endif 5051 5052 default: 5053 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 5054 "<== nxge_free_buf: unsupported alloc type %d", 5055 alloc_type)); 5056 return; 5057 } 5058 5059 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_free_buf")); 5060 } 5061