1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <inet/common.h> 30 #include <inet/mi.h> 31 #include <inet/nd.h> 32 33 extern uint64_t npi_debug_level; 34 35 #define NXGE_PARAM_MAC_RW \ 36 NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 37 NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 38 39 #define NXGE_PARAM_MAC_DONT_SHOW \ 40 NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 41 42 #define NXGE_PARAM_RXDMA_RW \ 43 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 44 NXGE_PARAM_READ_PROP 45 46 #define NXGE_PARAM_RXDMA_RWC \ 47 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 48 NXGE_PARAM_READ_PROP 49 50 #define NXGE_PARAM_L2CLASS_CFG \ 51 NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 52 NXGE_PARAM_NDD_WR_OK 53 54 #define NXGE_PARAM_CLASS_RWS \ 55 NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 56 57 #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 58 59 #define SET_RX_INTR_TIME_DISABLE 0 60 #define SET_RX_INTR_TIME_ENABLE 1 61 #define SET_RX_INTR_PKTS 2 62 63 #define BASE_ANY 0 64 #define BASE_BINARY 2 65 #define BASE_HEX 16 66 #define BASE_DECIMAL 10 67 #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 68 #define ALL_FF_32 0xFFFFFFFFUL 69 70 #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 71 #define NXGE_NDD_INFODUMP_BUFF_8K 8192 72 #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 73 #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 74 75 #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 76 ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 77 78 #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 79 ((mblk_t *)pmp)->b_wptr += plen; \ 80 rlen -= plen; \ 81 } 82 83 static int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *, 84 mblk_t *, char *, caddr_t); 85 static int nxge_param_rx_intr_time(p_nxge_t, queue_t *, 86 mblk_t *, char *, caddr_t); 87 static int nxge_param_set_mac(p_nxge_t, queue_t *, 88 mblk_t *, char *, caddr_t); 89 static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 90 mblk_t *, char *, caddr_t); 91 static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 92 mblk_t *, char *, caddr_t); 93 static int nxge_param_set_ether_usr(p_nxge_t, 94 queue_t *, mblk_t *, char *, caddr_t); 95 static int nxge_param_set_ip_usr(p_nxge_t, 96 queue_t *, mblk_t *, char *, caddr_t); 97 static int nxge_param_set_ip_opt(p_nxge_t, 98 queue_t *, mblk_t *, char *, caddr_t); 99 static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 100 queue_t *, mblk_t *, char *, caddr_t); 101 static int nxge_param_set_mac_rdcgrp(p_nxge_t, 102 queue_t *, mblk_t *, char *, caddr_t); 103 static int nxge_param_fflp_hash_init(p_nxge_t, 104 queue_t *, mblk_t *, char *, caddr_t); 105 static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 106 mblk_t *, char *, caddr_t); 107 static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 108 mblk_t *, char *, caddr_t); 109 static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 110 mblk_t *, char *, caddr_t); 111 static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 112 static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 113 static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 114 p_mblk_t, caddr_t); 115 static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 116 p_mblk_t, caddr_t); 117 static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 118 p_mblk_t, caddr_t); 119 static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 120 p_mblk_t, caddr_t); 121 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 122 p_mblk_t, caddr_t); 123 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 124 static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 125 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 126 static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 127 char *, caddr_t); 128 static int nxge_param_set_npi_debug_flag(p_nxge_t, 129 queue_t *, mblk_t *, char *, caddr_t); 130 static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 131 static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 132 static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 133 static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 134 static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 135 static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 136 static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 137 static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 138 static boolean_t nxge_param_link_update(p_nxge_t); 139 140 /* 141 * Global array of Neptune changable parameters. 142 * This array is initialized to correspond to the default 143 * Neptune 4 port configuration. This array would be copied 144 * into each port's parameter structure and modifed per 145 * fcode and nxge.conf configuration. Later, the parameters are 146 * exported to ndd to display and run-time configuration (at least 147 * some of them). 148 * 149 */ 150 151 static nxge_param_t nxge_param_arr[] = { 152 /* 153 * min max value old hw-name conf-name 154 */ 155 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 156 0, 999, 1000, 0, "instance", "instance"}, 157 158 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 159 0, 999, 1000, 0, "main-instance", "main_instance"}, 160 161 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 162 0, 3, 0, 0, "function-number", "function_number"}, 163 164 /* Partition Id */ 165 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 166 0, 8, 0, 0, "partition-id", "partition_id"}, 167 168 /* Read Write Permission Mode */ 169 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 170 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 171 172 { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 173 0, 32, 0, 0, "version", "fw_version"}, 174 175 { nxge_param_get_port_mode, NULL, NXGE_PARAM_READ, 176 0, 32, 0, 0, "port-mode", "port_mode"}, 177 178 /* hw cfg types */ 179 /* control the DMA config of Neptune/NIU */ 180 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 181 CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 182 "niu-cfg-type", "niu_cfg_type"}, 183 184 /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 185 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 186 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 187 "tx-qcfg-type", "tx_qcfg_type"}, 188 189 /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 190 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 191 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 192 "rx-qcfg-type", "rx_qcfg_type"}, 193 194 { nxge_param_get_mac, nxge_param_set_mac, 195 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 196 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 197 198 { nxge_param_get_mac, nxge_param_set_mac, 199 NXGE_PARAM_DONT_SHOW, 200 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 201 202 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 203 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 204 205 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 206 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 207 208 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 209 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 210 211 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 212 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 213 214 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 215 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 216 217 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 218 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 219 220 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 221 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 222 223 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 224 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 225 226 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 227 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 228 229 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 230 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 231 232 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 233 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 234 235 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 236 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 237 238 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 239 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 240 241 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 242 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 243 244 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 245 0, 255, 8, 8, "ipg0", "ipg0"}, 246 247 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 248 0, 255, 8, 8, "ipg1", "ipg1"}, 249 250 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 251 0, 255, 4, 4, "ipg2", "ipg2"}, 252 253 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 254 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 255 256 /* Transmit DMA channels */ 257 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 258 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 259 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 260 261 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 262 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 263 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 264 265 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 266 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 267 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 268 { nxge_param_get_txdma_info, NULL, 269 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 270 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 271 272 /* Receive DMA channels */ 273 { nxge_param_get_generic, NULL, 274 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 275 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 276 277 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 278 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 279 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 280 281 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 282 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 283 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 284 "rx-drr-weight", "rx_drr_weight"}, 285 286 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 287 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 288 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 289 290 { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 291 NXGE_PARAM_DONT_SHOW, 292 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 293 294 { nxge_param_get_rxdma_info, NULL, 295 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 296 NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 297 "rx-rbr-size", "rx_rbr_size"}, 298 299 { nxge_param_get_rxdma_info, NULL, 300 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 301 NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 302 "rx-rcr-size", "rx_rcr_size"}, 303 304 { nxge_param_get_generic, nxge_param_set_port_rdc, 305 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 306 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 307 308 { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 309 NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 310 RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 311 312 { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 313 NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 314 RXDMA_RCR_PTHRES_DEFAULT, 0, 315 "rxdma-intr-pkts", "rxdma_intr_pkts"}, 316 317 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 318 NXGE_PARAM_DONT_SHOW, 319 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 320 321 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 322 NXGE_PARAM_DONT_SHOW, 323 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 324 325 { nxge_param_get_generic, nxge_param_set_grp_rdc, 326 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 327 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 328 329 { nxge_param_get_generic, nxge_param_set_grp_rdc, 330 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 331 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 332 333 { nxge_param_get_generic, nxge_param_set_grp_rdc, 334 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 335 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 336 337 { nxge_param_get_generic, nxge_param_set_grp_rdc, 338 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 339 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 340 341 { nxge_param_get_generic, nxge_param_set_grp_rdc, 342 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 343 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 344 345 { nxge_param_get_generic, nxge_param_set_grp_rdc, 346 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 347 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 348 349 { nxge_param_get_generic, nxge_param_set_grp_rdc, 350 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 351 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 352 353 { nxge_param_get_generic, nxge_param_set_grp_rdc, 354 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 355 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 356 357 { nxge_param_get_rxdma_rdcgrp_info, NULL, 358 NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 359 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 360 361 /* Logical device groups */ 362 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 363 0, 63, 0, 0, "start-ldg", "start_ldg"}, 364 365 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 366 0, 64, 0, 0, "max-ldg", "max_ldg" }, 367 368 /* MAC table information */ 369 { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 370 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 371 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 372 373 /* VLAN table information */ 374 { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 375 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 376 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 377 378 { nxge_param_get_generic, NULL, 379 NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 380 NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 381 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 382 383 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 384 NXGE_PARAM_DONT_SHOW, 385 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 386 387 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 388 NXGE_PARAM_DONT_SHOW, 389 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 390 391 { nxge_param_get_generic, nxge_param_tcam_enable, 392 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 394 395 { nxge_param_get_generic, nxge_param_hash_lookup_enable, 396 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 397 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 398 399 { nxge_param_get_generic, nxge_param_llc_snap_enable, 400 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 401 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 402 403 { nxge_param_get_generic, nxge_param_fflp_hash_init, 404 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 405 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 406 407 { nxge_param_get_generic, nxge_param_fflp_hash_init, 408 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 409 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 410 411 { nxge_param_get_generic, nxge_param_set_ether_usr, 412 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 413 0, ALL_FF_32, 0x0, 0, 414 "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 415 416 { nxge_param_get_generic, nxge_param_set_ether_usr, 417 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 418 0, ALL_FF_32, 0x0, 0, 419 "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 420 421 { nxge_param_get_generic, nxge_param_set_ip_usr, 422 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 423 0, ALL_FF_32, 0x0, 0, 424 "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 425 426 { nxge_param_get_generic, nxge_param_set_ip_usr, 427 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 428 0, ALL_FF_32, 0x0, 0, 429 "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 430 431 { nxge_param_get_generic, nxge_param_set_ip_usr, 432 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 433 0, ALL_FF_32, 0x0, 0, 434 "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 435 436 { nxge_param_get_generic, nxge_param_set_ip_usr, 437 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 438 0, ALL_FF_32, 0x0, 0, 439 "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 440 441 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 442 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 443 0, ALL_FF_32, 0x0, 0, 444 "class-opt-ip-usr4", "class_opt_ip_usr4"}, 445 446 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 447 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 448 0, ALL_FF_32, 0x0, 0, 449 "class-opt-ip-usr5", "class_opt_ip_usr5"}, 450 451 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 452 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 453 0, ALL_FF_32, 0x0, 0, 454 "class-opt-ip-usr6", "class_opt_ip_usr6"}, 455 456 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 457 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 458 0, ALL_FF_32, 0x0, 0, 459 "class-opt-ip-usr7", "class_opt_ip_usr7"}, 460 461 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 462 NXGE_PARAM_CLASS_RWS, 463 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 464 "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 465 466 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 467 NXGE_PARAM_CLASS_RWS, 468 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 469 "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 470 471 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 472 NXGE_PARAM_CLASS_RWS, 473 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 474 "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 475 476 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 477 NXGE_PARAM_CLASS_RWS, 478 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 479 "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 480 481 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 482 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 483 "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 484 485 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 486 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 487 "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 488 489 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 490 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 491 "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 492 493 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 494 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 495 "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 496 497 { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 498 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 499 0ULL, ALL_FF_64, 0ULL, 0ULL, 500 "nxge-debug-flag", "nxge_debug_flag"}, 501 502 { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 503 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 504 0ULL, ALL_FF_64, 0ULL, 0ULL, 505 "npi-debug-flag", "npi_debug_flag"}, 506 507 { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 508 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 509 510 { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 511 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 512 513 { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 514 NXGE_PARAM_DONT_SHOW, 515 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 516 517 { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 518 NXGE_PARAM_DONT_SHOW, 519 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 520 521 { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 522 NXGE_PARAM_DONT_SHOW, 523 0, 0x0fffffff, 0x0fffffff, 0, 524 "dump-fflp-regs", "dump_fflp_regs"}, 525 526 { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 527 NXGE_PARAM_DONT_SHOW, 528 0, 0x0fffffff, 0x0fffffff, 0, 529 "dump-vlan-table", "dump_vlan_table"}, 530 531 { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 532 NXGE_PARAM_DONT_SHOW, 533 0, 0x0fffffff, 0x0fffffff, 0, 534 "dump-rdc-table", "dump_rdc_table"}, 535 536 { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 537 NXGE_PARAM_DONT_SHOW, 538 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 539 540 { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 541 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 542 }; 543 544 extern void *nxge_list; 545 546 void 547 nxge_get_param_soft_properties(p_nxge_t nxgep) 548 { 549 550 p_nxge_param_t param_arr; 551 uint_t prop_len; 552 int i, j; 553 uint32_t param_count; 554 uint32_t *int_prop_val; 555 556 NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 557 558 param_arr = nxgep->param_arr; 559 param_count = nxgep->param_count; 560 for (i = 0; i < param_count; i++) { 561 if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 562 continue; 563 if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 564 continue; 565 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 566 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 567 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 568 nxgep->dip, 0, param_arr[i].fcode_name, 569 (int **)&int_prop_val, 570 (uint_t *)&prop_len) 571 == DDI_PROP_SUCCESS) { 572 uint32_t *cfg_value; 573 uint64_t prop_count; 574 575 if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 576 prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 577 #if defined(__i386) 578 cfg_value = 579 (uint32_t *)(int32_t)param_arr[i].value; 580 #else 581 cfg_value = (uint32_t *)param_arr[i].value; 582 #endif 583 for (j = 0; j < prop_len; j++) { 584 cfg_value[j] = int_prop_val[j]; 585 } 586 prop_count = prop_len; 587 param_arr[i].type |= 588 (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 589 ddi_prop_free(int_prop_val); 590 } 591 continue; 592 } 593 594 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 595 param_arr[i].fcode_name, 596 (int **)&int_prop_val, 597 &prop_len) == DDI_PROP_SUCCESS) { 598 if ((*int_prop_val >= param_arr[i].minimum) && 599 (*int_prop_val <= param_arr[i].maximum)) 600 param_arr[i].value = *int_prop_val; 601 #ifdef NXGE_DEBUG_ERROR 602 else { 603 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 604 "nxge%d: 'prom' file parameter error\n", 605 nxgep->instance)); 606 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 607 "Parameter keyword '%s'" 608 " is outside valid range\n", 609 param_arr[i].name)); 610 } 611 #endif 612 ddi_prop_free(int_prop_val); 613 } 614 615 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 616 param_arr[i].name, 617 (int **)&int_prop_val, 618 &prop_len) == DDI_PROP_SUCCESS) { 619 if ((*int_prop_val >= param_arr[i].minimum) && 620 (*int_prop_val <= param_arr[i].maximum)) 621 param_arr[i].value = *int_prop_val; 622 #ifdef NXGE_DEBUG_ERROR 623 else { 624 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 625 "nxge%d: 'conf' file parameter error\n", 626 nxgep->instance)); 627 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 628 "Parameter keyword '%s'" 629 "is outside valid range\n", 630 param_arr[i].name)); 631 } 632 #endif 633 ddi_prop_free(int_prop_val); 634 } 635 } 636 } 637 638 static int 639 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 640 { 641 int status = B_TRUE; 642 int channel; 643 uint8_t grp; 644 char *prop_name; 645 char *end; 646 uint32_t name_chars; 647 648 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 649 "nxge_private_param_register %s", param_arr->name)); 650 651 if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 652 return (B_TRUE); 653 654 prop_name = param_arr->name; 655 if (param_arr->type & NXGE_PARAM_RXDMA) { 656 if (strncmp("rxdma_intr", prop_name, 10) == 0) 657 return (B_TRUE); 658 name_chars = strlen("default_grp"); 659 if (strncmp("default_grp", prop_name, name_chars) == 0) { 660 prop_name += name_chars; 661 grp = mi_strtol(prop_name, &end, 10); 662 /* now check if this rdcgrp is in config */ 663 return (nxge_check_rdcgrp_port_member(nxgep, grp)); 664 } 665 name_chars = strlen(prop_name); 666 if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 667 return (B_TRUE); 668 } 669 return (B_FALSE); 670 } 671 672 if (param_arr->type & NXGE_PARAM_TXDMA) { 673 name_chars = strlen("txdma"); 674 if (strncmp("txdma", prop_name, name_chars) == 0) { 675 prop_name += name_chars; 676 channel = mi_strtol(prop_name, &end, 10); 677 /* now check if this rdc is in config */ 678 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 679 " nxge_private_param_register: %d", 680 channel)); 681 return (nxge_check_txdma_port_member(nxgep, channel)); 682 } 683 return (B_FALSE); 684 } 685 686 status = B_FALSE; 687 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 688 689 return (status); 690 } 691 692 void 693 nxge_setup_param(p_nxge_t nxgep) 694 { 695 p_nxge_param_t param_arr; 696 int i; 697 pfi_t set_pfi; 698 699 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 700 701 /* 702 * Make sure the param_instance is set to a valid device instance. 703 */ 704 if (nxge_param_arr[param_instance].value == 1000) 705 nxge_param_arr[param_instance].value = nxgep->instance; 706 707 param_arr = nxgep->param_arr; 708 param_arr[param_instance].value = nxgep->instance; 709 param_arr[param_function_number].value = nxgep->function_num; 710 711 for (i = 0; i < nxgep->param_count; i++) { 712 if ((param_arr[i].type & NXGE_PARAM_PRIV) && 713 (nxge_private_param_register(nxgep, 714 ¶m_arr[i]) == B_FALSE)) { 715 param_arr[i].setf = NULL; 716 param_arr[i].getf = NULL; 717 } 718 719 if (param_arr[i].type & NXGE_PARAM_CMPLX) 720 param_arr[i].setf = NULL; 721 722 if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 723 param_arr[i].setf = NULL; 724 param_arr[i].getf = NULL; 725 } 726 727 set_pfi = (pfi_t)param_arr[i].setf; 728 729 if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 730 set_pfi = NULL; 731 } 732 733 if (!nxge_nd_load(&nxgep->param_list, param_arr[i].name, 734 (pfi_t)param_arr[i].getf, set_pfi, 735 (caddr_t)¶m_arr[i])) { 736 (void) nxge_nd_free(&nxgep->param_list); 737 break; 738 } 739 } 740 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 741 } 742 743 void 744 nxge_init_param(p_nxge_t nxgep) 745 { 746 p_nxge_param_t param_arr; 747 int i, alloc_size; 748 uint64_t alloc_count; 749 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 750 /* 751 * Make sure the param_instance is set to a valid device instance. 752 */ 753 if (nxge_param_arr[param_instance].value == 1000) 754 nxge_param_arr[param_instance].value = nxgep->instance; 755 756 param_arr = nxgep->param_arr; 757 if (param_arr == NULL) { 758 param_arr = (p_nxge_param_t) 759 KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 760 } 761 762 for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 763 param_arr[i] = nxge_param_arr[i]; 764 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 765 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 766 alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 767 alloc_size = alloc_count * sizeof (uint64_t); 768 param_arr[i].value = 769 #if defined(__i386) 770 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 771 KM_SLEEP); 772 #else 773 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 774 #endif 775 param_arr[i].old_value = 776 #if defined(__i386) 777 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 778 KM_SLEEP); 779 #else 780 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 781 #endif 782 param_arr[i].type |= 783 (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 784 } 785 } 786 787 nxgep->param_arr = param_arr; 788 nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 789 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 790 nxgep->param_count)); 791 } 792 793 void 794 nxge_destroy_param(p_nxge_t nxgep) 795 { 796 int i; 797 uint64_t free_size, free_count; 798 799 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 800 801 if (nxgep->param_arr == NULL) 802 return; 803 /* 804 * Make sure the param_instance is set to a valid device instance. 805 */ 806 if (nxge_param_arr[param_instance].value == nxgep->instance) { 807 for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 808 if ((ddi_get_soft_state(nxge_list, i) != NULL) && 809 (i != nxgep->instance)) 810 break; 811 } 812 nxge_param_arr[param_instance].value = i; 813 } 814 815 if (nxgep->param_list) 816 nxge_nd_free(&nxgep->param_list); 817 for (i = 0; i < nxgep->param_count; i++) 818 if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 819 (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 820 free_count = ((nxgep->param_arr[i].type & 821 NXGE_PARAM_ARRAY_ALLOC_MASK) >> 822 NXGE_PARAM_ARRAY_ALLOC_SHIFT); 823 free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 824 free_size = sizeof (uint64_t) * free_count; 825 #if defined(__i386) 826 KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value, 827 free_size); 828 #else 829 KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 830 #endif 831 #if defined(__i386) 832 KMEM_FREE((void *)(uint32_t) 833 nxgep->param_arr[i].old_value, free_size); 834 #else 835 KMEM_FREE((void *)nxgep->param_arr[i].old_value, 836 free_size); 837 #endif 838 } 839 840 KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 841 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 842 } 843 844 /* 845 * Extracts the value from the 'nxge' parameter array and prints the 846 * parameter value. cp points to the required parameter. 847 */ 848 849 /* ARGSUSED */ 850 int 851 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 852 { 853 p_nxge_param_t pa = (p_nxge_param_t)cp; 854 855 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 856 "==> nxge_param_get_generic name %s ", pa->name)); 857 858 if (pa->value > 0xffffffff) 859 (void) mi_mpprintf(mp, "%x%x", 860 (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 861 else 862 (void) mi_mpprintf(mp, "%x", (int)pa->value); 863 864 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 865 return (0); 866 } 867 868 /* ARGSUSED */ 869 static int 870 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 871 { 872 p_nxge_param_t pa = (p_nxge_param_t)cp; 873 874 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 875 876 (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 877 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 878 return (0); 879 } 880 881 /* ARGSUSED */ 882 static int 883 nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 884 { 885 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 886 887 (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 888 nxgep->instance, nxgep->vpd_info.ver); 889 890 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 891 return (0); 892 } 893 894 /* ARGSUSED */ 895 static int 896 nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 897 { 898 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode")); 899 900 switch (nxgep->mac.portmode) { 901 case PORT_1G_COPPER: 902 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Copper\n", 903 nxgep->instance); 904 break; 905 case PORT_1G_FIBER: 906 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Fiber\n", 907 nxgep->instance); 908 break; 909 case PORT_10G_COPPER: 910 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Copper\n", 911 nxgep->instance); 912 break; 913 case PORT_10G_FIBER: 914 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Fiber\n", 915 nxgep->instance); 916 break; 917 case PORT_10G_SERDES: 918 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Serdes\n", 919 nxgep->instance); 920 break; 921 case PORT_1G_SERDES: 922 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Serdes\n", 923 nxgep->instance); 924 break; 925 case PORT_1G_RGMII_FIBER: 926 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G RGMII " 927 "Fiber\n", nxgep->instance); 928 break; 929 default: 930 (void) mi_mpprintf(mp, "Port mode for nxge%d: Unknown\n", 931 nxgep->instance); 932 break; 933 } 934 935 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode")); 936 return (0); 937 } 938 939 /* ARGSUSED */ 940 int 941 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 942 { 943 944 uint_t print_len, buf_len; 945 p_mblk_t np; 946 int tdc; 947 948 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 949 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 950 951 (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 952 nxgep->function_num); 953 954 955 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 956 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 957 return (0); 958 } 959 960 buf_len = buff_alloc_size; 961 mp->b_cont = np; 962 963 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 964 "Total TDCs\t %d\n", nxgep->ntdc); 965 966 ((mblk_t *)np)->b_wptr += print_len; 967 buf_len -= print_len; 968 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 969 "TDC\t HW TDC\t\n"); 970 ((mblk_t *)np)->b_wptr += print_len; 971 972 buf_len -= print_len; 973 for (tdc = 0; tdc < nxgep->ntdc; tdc++) { 974 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 975 buf_len, "%d\t %d\n", 976 tdc, nxgep->tdc[tdc]); 977 ((mblk_t *)np)->b_wptr += print_len; 978 buf_len -= print_len; 979 } 980 981 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 982 return (0); 983 } 984 985 /* ARGSUSED */ 986 int 987 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 988 { 989 uint_t print_len, buf_len; 990 p_mblk_t np; 991 int rdc; 992 p_nxge_dma_pt_cfg_t p_dma_cfgp; 993 p_nxge_hw_pt_cfg_t p_cfgp; 994 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 995 p_rx_rcr_rings_t rx_rcr_rings; 996 p_rx_rcr_ring_t *rcr_rings; 997 p_rx_rbr_rings_t rx_rbr_rings; 998 p_rx_rbr_ring_t *rbr_rings; 999 1000 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 1001 1002 (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 1003 nxgep->function_num); 1004 1005 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1006 /* The following may work even if we cannot get a large buf. */ 1007 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1008 return (0); 1009 } 1010 1011 buf_len = buff_alloc_size; 1012 mp->b_cont = np; 1013 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1014 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1015 1016 rx_rcr_rings = nxgep->rx_rcr_rings; 1017 rcr_rings = rx_rcr_rings->rcr_rings; 1018 rx_rbr_rings = nxgep->rx_rbr_rings; 1019 rbr_rings = rx_rbr_rings->rbr_rings; 1020 1021 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1022 "Total RDCs\t %d\n", p_cfgp->max_rdcs); 1023 1024 ((mblk_t *)np)->b_wptr += print_len; 1025 buf_len -= print_len; 1026 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1027 "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 1028 "chunks\t RCR ptr\n"); 1029 1030 ((mblk_t *)np)->b_wptr += print_len; 1031 buf_len -= print_len; 1032 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 1033 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1034 " %d\t %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 1035 rdc, nxgep->rdc[rdc], 1036 p_dma_cfgp->rcr_timeout[rdc], 1037 p_dma_cfgp->rcr_threshold[rdc], 1038 rbr_rings[rdc], 1039 rbr_rings[rdc]->num_blocks, rcr_rings[rdc]); 1040 ((mblk_t *)np)->b_wptr += print_len; 1041 buf_len -= print_len; 1042 } 1043 1044 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 1045 return (0); 1046 } 1047 1048 /* ARGSUSED */ 1049 int 1050 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 1051 p_mblk_t mp, caddr_t cp) 1052 { 1053 uint_t print_len, buf_len; 1054 p_mblk_t np; 1055 int offset, rdc, i, rdc_grp; 1056 p_nxge_rdc_grp_t rdc_grp_p; 1057 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1058 p_nxge_hw_pt_cfg_t p_cfgp; 1059 1060 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1061 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1062 "==> nxge_param_get_rxdma_rdcgrp_info")); 1063 1064 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1065 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1066 1067 (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 1068 nxgep->function_num); 1069 1070 rdc_grp = p_cfgp->start_rdc_grpid; 1071 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1072 /* The following may work even if we cannot get a large buf. */ 1073 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1074 return (0); 1075 } 1076 1077 buf_len = buff_alloc_size; 1078 mp->b_cont = np; 1079 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1080 "Total RDC Groups\t %d \n" 1081 "start RDC group\t %d\n", 1082 p_cfgp->max_rdc_grpids, 1083 p_cfgp->start_rdc_grpid); 1084 1085 ((mblk_t *)np)->b_wptr += print_len; 1086 buf_len -= print_len; 1087 1088 for (i = 0, rdc_grp = p_cfgp->start_rdc_grpid; 1089 rdc_grp < (p_cfgp->max_rdc_grpids + p_cfgp->start_rdc_grpid); 1090 rdc_grp++, i++) { 1091 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 1092 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1093 "\nRDC Group Info for Group [%d] %d\n" 1094 "RDC Count %d\tstart RDC %d\n" 1095 "RDC Group Population Information" 1096 " (offsets 0 - 15)\n", 1097 i, rdc_grp, rdc_grp_p->max_rdcs, 1098 rdc_grp_p->start_rdc); 1099 1100 ((mblk_t *)np)->b_wptr += print_len; 1101 buf_len -= print_len; 1102 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1103 buf_len, "\n"); 1104 ((mblk_t *)np)->b_wptr += print_len; 1105 buf_len -= print_len; 1106 1107 for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1108 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1109 buf_len, "[%d]=%d ", rdc, 1110 rdc_grp_p->start_rdc + rdc); 1111 ((mblk_t *)np)->b_wptr += print_len; 1112 buf_len -= print_len; 1113 } 1114 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1115 buf_len, "\n"); 1116 ((mblk_t *)np)->b_wptr += print_len; 1117 buf_len -= print_len; 1118 1119 for (offset = 0; offset < 16; offset++) { 1120 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1121 buf_len, " %2d ", 1122 rdc_grp_p->rdc[offset]); 1123 ((mblk_t *)np)->b_wptr += print_len; 1124 buf_len -= print_len; 1125 } 1126 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1127 buf_len, "\n"); 1128 ((mblk_t *)np)->b_wptr += print_len; 1129 buf_len -= print_len; 1130 } 1131 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1132 "<== nxge_param_get_rxdma_rdcgrp_info")); 1133 return (0); 1134 } 1135 1136 int 1137 nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 1138 { 1139 p_mblk_t tmp; 1140 1141 tmp = mp; 1142 while (tmp->b_cont) 1143 tmp = tmp->b_cont; 1144 if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 1145 tmp->b_cont = allocb(1024, BPRI_HI); 1146 tmp = tmp->b_cont; 1147 if (!tmp) 1148 return (ENOMEM); 1149 } 1150 1151 *nmp = tmp; 1152 return (0); 1153 } 1154 1155 /* 1156 * Sets the ge parameter to the value in the nxge_param_register using 1157 * nxge_nd_load(). 1158 */ 1159 1160 /* ARGSUSED */ 1161 int 1162 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1163 char *value, caddr_t cp) 1164 { 1165 char *end; 1166 uint32_t new_value; 1167 p_nxge_param_t pa = (p_nxge_param_t)cp; 1168 1169 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 1170 new_value = (uint32_t)mi_strtol(value, &end, 10); 1171 if (end == value || new_value < pa->minimum || 1172 new_value > pa->maximum) { 1173 return (EINVAL); 1174 } 1175 pa->value = new_value; 1176 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 1177 return (0); 1178 } 1179 1180 /* 1181 * Sets the ge parameter to the value in the nxge_param_register using 1182 * nxge_nd_load(). 1183 */ 1184 1185 /* ARGSUSED */ 1186 int 1187 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1188 char *value, caddr_t cp) 1189 { 1190 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 1191 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 1192 return (0); 1193 } 1194 1195 /* 1196 * Sets the ge parameter to the value in the nxge_param_register using 1197 * nxge_nd_load(). 1198 */ 1199 1200 /* ARGSUSED */ 1201 int 1202 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1203 char *value, caddr_t cp) 1204 { 1205 char *end; 1206 uint32_t new_value; 1207 int status = 0; 1208 p_nxge_param_t pa = (p_nxge_param_t)cp; 1209 1210 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 1211 new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 1212 if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 1213 return (EINVAL); 1214 } 1215 1216 if (pa->value != new_value) { 1217 pa->old_value = pa->value; 1218 pa->value = new_value; 1219 } 1220 1221 if (!nxge_param_link_update(nxgep)) { 1222 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1223 " false ret from nxge_param_link_update")); 1224 status = EINVAL; 1225 } 1226 1227 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 1228 return (status); 1229 } 1230 1231 /* ARGSUSED */ 1232 static int 1233 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1234 char *value, caddr_t cp) 1235 { 1236 char *end; 1237 uint32_t cfg_value; 1238 p_nxge_param_t pa = (p_nxge_param_t)cp; 1239 1240 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 1241 1242 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1243 1244 if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 1245 (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 1246 return (EINVAL); 1247 } 1248 1249 if ((pa->value != cfg_value)) { 1250 pa->old_value = pa->value; 1251 pa->value = cfg_value; 1252 nxgep->intr_threshold = pa->value; 1253 } 1254 1255 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 1256 return (0); 1257 } 1258 1259 /* ARGSUSED */ 1260 static int 1261 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1262 char *value, caddr_t cp) 1263 { 1264 char *end; 1265 uint32_t cfg_value; 1266 p_nxge_param_t pa = (p_nxge_param_t)cp; 1267 1268 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 1269 1270 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1271 1272 if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 1273 (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 1274 return (EINVAL); 1275 } 1276 1277 if ((pa->value != cfg_value)) { 1278 pa->old_value = pa->value; 1279 pa->value = cfg_value; 1280 nxgep->intr_timeout = pa->value; 1281 } 1282 1283 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 1284 return (0); 1285 } 1286 1287 /* ARGSUSED */ 1288 static int 1289 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1290 mblk_t *mp, char *value, caddr_t cp) 1291 { 1292 char *end; 1293 uint32_t status = 0, cfg_value; 1294 p_nxge_param_t pa = (p_nxge_param_t)cp; 1295 uint32_t cfg_it = B_FALSE; 1296 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1297 p_nxge_hw_pt_cfg_t p_cfgp; 1298 uint32_t *val_ptr, *old_val_ptr; 1299 nxge_param_map_t *mac_map; 1300 p_nxge_class_pt_cfg_t p_class_cfgp; 1301 nxge_mv_cfg_t *mac_host_info; 1302 1303 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 1304 1305 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1306 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1307 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1308 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1309 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1310 1311 /* 1312 * now do decoding 1313 */ 1314 mac_map = (nxge_param_map_t *)&cfg_value; 1315 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1316 cfg_value, mac_map->param_id, mac_map->map_to)); 1317 1318 if ((mac_map->param_id < p_cfgp->max_macs) && 1319 (mac_map->map_to < (p_cfgp->max_rdc_grpids + 1320 p_cfgp->start_rdc_grpid)) && (mac_map->map_to >= 1321 p_cfgp->start_rdc_grpid)) { 1322 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1323 " nxge_param_set_mac_rdcgrp mapping" 1324 " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1325 #if defined(__i386) 1326 val_ptr = (uint32_t *)(uint32_t)pa->value; 1327 #else 1328 val_ptr = (uint32_t *)pa->value; 1329 #endif 1330 #if defined(__i386) 1331 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1332 #else 1333 old_val_ptr = (uint32_t *)pa->old_value; 1334 #endif 1335 if (val_ptr[mac_map->param_id] != cfg_value) { 1336 old_val_ptr[mac_map->param_id] = 1337 val_ptr[mac_map->param_id]; 1338 val_ptr[mac_map->param_id] = cfg_value; 1339 mac_host_info[mac_map->param_id].mpr_npr = 1340 mac_map->pref; 1341 mac_host_info[mac_map->param_id].flag = 1; 1342 mac_host_info[mac_map->param_id].rdctbl = 1343 mac_map->map_to; 1344 cfg_it = B_TRUE; 1345 } 1346 } else { 1347 return (EINVAL); 1348 } 1349 1350 if (cfg_it == B_TRUE) { 1351 status = nxge_logical_mac_assign_rdc_table(nxgep, 1352 (uint8_t)mac_map->param_id); 1353 if (status != NXGE_OK) 1354 return (EINVAL); 1355 } 1356 1357 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 1358 return (0); 1359 } 1360 1361 /* ARGSUSED */ 1362 static int 1363 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1364 mblk_t *mp, char *value, caddr_t cp) 1365 { 1366 char *end; 1367 uint32_t status = 0, cfg_value; 1368 p_nxge_param_t pa = (p_nxge_param_t)cp; 1369 uint32_t cfg_it = B_FALSE; 1370 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1371 p_nxge_hw_pt_cfg_t p_cfgp; 1372 uint32_t *val_ptr, *old_val_ptr; 1373 nxge_param_map_t *vmap, *old_map; 1374 p_nxge_class_pt_cfg_t p_class_cfgp; 1375 uint64_t cfgd_vlans; 1376 int i, inc = 0, cfg_position; 1377 nxge_mv_cfg_t *vlan_tbl; 1378 1379 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1380 1381 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1382 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1383 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1384 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1385 1386 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1387 1388 /* now do decoding */ 1389 cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1390 NXGE_PARAM_ARRAY_CNT_SHIFT); 1391 1392 if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 1393 /* 1394 * for now, we process only upto max 1395 * NXGE_PARAM_ARRAY_INIT_SIZE parameters 1396 * In the future, we may want to expand 1397 * the storage array and continue 1398 */ 1399 return (EINVAL); 1400 } 1401 1402 vmap = (nxge_param_map_t *)&cfg_value; 1403 if ((vmap->param_id) && 1404 (vmap->param_id < NXGE_MAX_VLANS) && 1405 (vmap->map_to < p_cfgp->max_rdc_grpids)) { 1406 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1407 "nxge_param_set_vlan_rdcgrp mapping" 1408 " id %d grp %d", 1409 vmap->param_id, vmap->map_to)); 1410 #if defined(__i386) 1411 val_ptr = (uint32_t *)(uint32_t)pa->value; 1412 #else 1413 val_ptr = (uint32_t *)pa->value; 1414 #endif 1415 #if defined(__i386) 1416 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1417 #else 1418 old_val_ptr = (uint32_t *)pa->old_value; 1419 #endif 1420 1421 /* search to see if this vlan id is already configured */ 1422 for (i = 0; i < cfgd_vlans; i++) { 1423 old_map = (nxge_param_map_t *)&val_ptr[i]; 1424 if ((old_map->param_id == 0) || 1425 (vmap->param_id == old_map->param_id) || 1426 (vlan_tbl[vmap->param_id].flag)) { 1427 cfg_position = i; 1428 break; 1429 } 1430 } 1431 1432 if (cfgd_vlans == 0) { 1433 cfg_position = 0; 1434 inc++; 1435 } 1436 1437 if (i == cfgd_vlans) { 1438 cfg_position = i; 1439 inc++; 1440 } 1441 1442 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1443 "set_vlan_rdcgrp mapping" 1444 " i %d cfgd_vlans %llx position %d ", 1445 i, cfgd_vlans, cfg_position)); 1446 if (val_ptr[cfg_position] != cfg_value) { 1447 old_val_ptr[cfg_position] = val_ptr[cfg_position]; 1448 val_ptr[cfg_position] = cfg_value; 1449 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 1450 vlan_tbl[vmap->param_id].flag = 1; 1451 vlan_tbl[vmap->param_id].rdctbl = 1452 vmap->map_to + p_cfgp->start_rdc_grpid; 1453 cfg_it = B_TRUE; 1454 if (inc) { 1455 cfgd_vlans++; 1456 pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 1457 pa->type |= (cfgd_vlans << 1458 NXGE_PARAM_ARRAY_CNT_SHIFT); 1459 1460 } 1461 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1462 "after: param_set_vlan_rdcgrp " 1463 " cfg_vlans %llx position %d \n", 1464 cfgd_vlans, cfg_position)); 1465 } 1466 } else { 1467 return (EINVAL); 1468 } 1469 1470 if (cfg_it == B_TRUE) { 1471 status = nxge_fflp_config_vlan_table(nxgep, 1472 (uint16_t)vmap->param_id); 1473 if (status != NXGE_OK) 1474 return (EINVAL); 1475 } 1476 1477 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 1478 return (0); 1479 } 1480 1481 /* ARGSUSED */ 1482 static int 1483 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1484 mblk_t *mp, caddr_t cp) 1485 { 1486 1487 uint_t print_len, buf_len; 1488 p_mblk_t np; 1489 int i; 1490 uint32_t *val_ptr; 1491 nxge_param_map_t *vmap; 1492 p_nxge_param_t pa = (p_nxge_param_t)cp; 1493 p_nxge_class_pt_cfg_t p_class_cfgp; 1494 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1495 p_nxge_hw_pt_cfg_t p_cfgp; 1496 uint64_t cfgd_vlans = 0; 1497 nxge_mv_cfg_t *vlan_tbl; 1498 int buff_alloc_size = 1499 NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1500 1501 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1502 (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1503 nxgep->function_num); 1504 1505 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1506 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1507 return (0); 1508 } 1509 1510 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1511 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1512 1513 buf_len = buff_alloc_size; 1514 mp->b_cont = np; 1515 cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1516 NXGE_PARAM_ARRAY_CNT_SHIFT; 1517 1518 i = (int)cfgd_vlans; 1519 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1520 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1521 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1522 "Configured VLANs %d\n" 1523 "VLAN ID\t RDC GRP (Actual/Port)\t" 1524 " Prefernce\n", i); 1525 ((mblk_t *)np)->b_wptr += print_len; 1526 buf_len -= print_len; 1527 #if defined(__i386) 1528 val_ptr = (uint32_t *)(uint32_t)pa->value; 1529 #else 1530 val_ptr = (uint32_t *)pa->value; 1531 #endif 1532 1533 for (i = 0; i < cfgd_vlans; i++) { 1534 vmap = (nxge_param_map_t *)&val_ptr[i]; 1535 if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 1536 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1537 buf_len, 1538 " %d\t\t %d/%d\t\t %d\n", 1539 vmap->param_id, 1540 vlan_tbl[vmap->param_id].rdctbl, 1541 vlan_tbl[vmap->param_id].rdctbl - 1542 p_cfgp->start_rdc_grpid, 1543 vlan_tbl[vmap->param_id].mpr_npr); 1544 ((mblk_t *)np)->b_wptr += print_len; 1545 buf_len -= print_len; 1546 } 1547 } 1548 1549 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 1550 return (0); 1551 } 1552 1553 /* ARGSUSED */ 1554 static int 1555 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1556 mblk_t *mp, caddr_t cp) 1557 { 1558 uint_t print_len, buf_len; 1559 p_mblk_t np; 1560 int i; 1561 p_nxge_class_pt_cfg_t p_class_cfgp; 1562 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1563 p_nxge_hw_pt_cfg_t p_cfgp; 1564 nxge_mv_cfg_t *mac_host_info; 1565 1566 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1567 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 1568 (void) mi_mpprintf(mp, 1569 "MAC ADDR RDC Mapping Information for Port\t %d\n", 1570 nxgep->function_num); 1571 1572 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1573 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1574 return (0); 1575 } 1576 1577 buf_len = buff_alloc_size; 1578 mp->b_cont = np; 1579 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1580 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1581 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1582 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1583 print_len = snprintf((char *)np->b_wptr, buf_len, 1584 "MAC ID\t RDC GRP (Actual/Port)\t" 1585 " Prefernce\n"); 1586 ((mblk_t *)np)->b_wptr += print_len; 1587 buf_len -= print_len; 1588 for (i = 0; i < p_cfgp->max_macs; i++) { 1589 if (mac_host_info[i].flag) { 1590 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1591 buf_len, 1592 " %d\t %d/%d\t\t %d\n", 1593 i, mac_host_info[i].rdctbl, 1594 mac_host_info[i].rdctbl - 1595 p_cfgp->start_rdc_grpid, 1596 mac_host_info[i].mpr_npr); 1597 ((mblk_t *)np)->b_wptr += print_len; 1598 buf_len -= print_len; 1599 } 1600 } 1601 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1602 "Done Info Dumping \n"); 1603 ((mblk_t *)np)->b_wptr += print_len; 1604 buf_len -= print_len; 1605 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 1606 return (0); 1607 } 1608 1609 /* ARGSUSED */ 1610 static int 1611 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1612 mblk_t *mp, char *value, caddr_t cp) 1613 { 1614 uint32_t status = 0, cfg_value; 1615 p_nxge_param_t pa = (p_nxge_param_t)cp; 1616 uint32_t cfg_it = B_FALSE; 1617 char *end; 1618 1619 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 1620 1621 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1622 if (pa->value != cfg_value) { 1623 pa->old_value = pa->value; 1624 pa->value = cfg_value; 1625 cfg_it = B_TRUE; 1626 } 1627 1628 if (cfg_it == B_TRUE) { 1629 if (pa->value) 1630 status = nxge_fflp_config_tcam_enable(nxgep); 1631 else 1632 status = nxge_fflp_config_tcam_disable(nxgep); 1633 if (status != NXGE_OK) 1634 return (EINVAL); 1635 } 1636 1637 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 1638 return (0); 1639 } 1640 1641 /* ARGSUSED */ 1642 static int 1643 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1644 mblk_t *mp, char *value, caddr_t cp) 1645 { 1646 uint32_t status = 0, cfg_value; 1647 p_nxge_param_t pa = (p_nxge_param_t)cp; 1648 uint32_t cfg_it = B_FALSE; 1649 char *end; 1650 1651 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 1652 1653 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1654 if (pa->value != cfg_value) { 1655 pa->old_value = pa->value; 1656 pa->value = cfg_value; 1657 cfg_it = B_TRUE; 1658 } 1659 1660 if (cfg_it == B_TRUE) { 1661 if (pa->value) 1662 status = nxge_fflp_config_hash_lookup_enable(nxgep); 1663 else 1664 status = nxge_fflp_config_hash_lookup_disable(nxgep); 1665 if (status != NXGE_OK) 1666 return (EINVAL); 1667 } 1668 1669 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 1670 return (0); 1671 } 1672 1673 /* ARGSUSED */ 1674 static int 1675 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1676 mblk_t *mp, char *value, caddr_t cp) 1677 { 1678 char *end; 1679 uint32_t status = 0, cfg_value; 1680 p_nxge_param_t pa = (p_nxge_param_t)cp; 1681 uint32_t cfg_it = B_FALSE; 1682 1683 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 1684 1685 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1686 if (pa->value != cfg_value) { 1687 pa->old_value = pa->value; 1688 pa->value = cfg_value; 1689 cfg_it = B_TRUE; 1690 } 1691 1692 if (cfg_it == B_TRUE) { 1693 if (pa->value) 1694 status = nxge_fflp_config_tcam_enable(nxgep); 1695 else 1696 status = nxge_fflp_config_tcam_disable(nxgep); 1697 if (status != NXGE_OK) 1698 return (EINVAL); 1699 } 1700 1701 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 1702 return (0); 1703 } 1704 1705 /* ARGSUSED */ 1706 static int 1707 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1708 mblk_t *mp, char *value, caddr_t cp) 1709 { 1710 char *end; 1711 uint8_t ether_class; 1712 uint32_t status = 0, cfg_value; 1713 p_nxge_param_t pa = (p_nxge_param_t)cp; 1714 uint8_t cfg_it = B_FALSE; 1715 1716 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 1717 1718 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1719 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1720 return (EINVAL); 1721 } 1722 1723 if (pa->value != cfg_value) { 1724 pa->old_value = pa->value; 1725 pa->value = cfg_value; 1726 cfg_it = B_TRUE; 1727 } 1728 1729 /* do the actual hw setup */ 1730 if (cfg_it == B_TRUE) { 1731 ether_class = mi_strtol(pa->name, &end, 10); 1732 #ifdef lint 1733 ether_class = ether_class; 1734 #endif 1735 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 1736 } 1737 1738 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 1739 return (status); 1740 } 1741 1742 /* ARGSUSED */ 1743 static int 1744 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1745 mblk_t *mp, char *value, caddr_t cp) 1746 { 1747 char *end; 1748 tcam_class_t class; 1749 uint32_t status, cfg_value; 1750 p_nxge_param_t pa = (p_nxge_param_t)cp; 1751 uint32_t cfg_it = B_FALSE; 1752 1753 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 1754 1755 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1756 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1757 return (EINVAL); 1758 } 1759 1760 if (pa->value != cfg_value) { 1761 pa->old_value = pa->value; 1762 pa->value = cfg_value; 1763 cfg_it = B_TRUE; 1764 } 1765 1766 /* do the actual hw setup with cfg_value. */ 1767 if (cfg_it == B_TRUE) { 1768 class = mi_strtol(pa->name, &end, 10); 1769 status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 1770 } 1771 1772 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 1773 return (status); 1774 } 1775 1776 /* ARGSUSED */ 1777 static int 1778 nxge_class_name_2value(p_nxge_t nxgep, char *name) 1779 { 1780 int i; 1781 int class_instance = param_class_opt_ip_usr4; 1782 p_nxge_param_t param_arr; 1783 1784 param_arr = nxgep->param_arr; 1785 for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 1786 if (strcmp(param_arr[class_instance].name, name) == 0) 1787 return (i); 1788 class_instance++; 1789 } 1790 return (-1); 1791 } 1792 1793 /* ARGSUSED */ 1794 static int 1795 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1796 mblk_t *mp, char *value, caddr_t cp) 1797 { 1798 char *end; 1799 uint32_t status, cfg_value; 1800 p_nxge_param_t pa = (p_nxge_param_t)cp; 1801 tcam_class_t class; 1802 uint32_t cfg_it = B_FALSE; 1803 1804 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 1805 1806 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1807 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1808 return (EINVAL); 1809 } 1810 1811 if (pa->value != cfg_value) { 1812 pa->old_value = pa->value; 1813 pa->value = cfg_value; 1814 cfg_it = B_TRUE; 1815 } 1816 1817 if (cfg_it == B_TRUE) { 1818 /* do the actual hw setup */ 1819 class = nxge_class_name_2value(nxgep, pa->name); 1820 if (class == -1) 1821 return (EINVAL); 1822 1823 status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 1824 if (status != NXGE_OK) 1825 return (EINVAL); 1826 } 1827 1828 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 1829 return (0); 1830 } 1831 1832 /* ARGSUSED */ 1833 static int 1834 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1835 mblk_t *mp, caddr_t cp) 1836 { 1837 uint32_t status, cfg_value; 1838 p_nxge_param_t pa = (p_nxge_param_t)cp; 1839 tcam_class_t class; 1840 1841 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 1842 1843 /* do the actual hw setup */ 1844 class = nxge_class_name_2value(nxgep, pa->name); 1845 if (class == -1) 1846 return (EINVAL); 1847 1848 cfg_value = 0; 1849 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 1850 if (status != NXGE_OK) 1851 return (EINVAL); 1852 1853 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1854 "nxge_param_get_ip_opt_get %x ", cfg_value)); 1855 1856 pa->value = cfg_value; 1857 (void) mi_mpprintf(mp, "%x", cfg_value); 1858 1859 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 1860 return (0); 1861 } 1862 1863 /* ARGSUSED */ 1864 static int 1865 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1866 mblk_t *mp, char *value, caddr_t cp) 1867 { 1868 char *end; 1869 uint32_t status, cfg_value; 1870 p_nxge_param_t pa = (p_nxge_param_t)cp; 1871 tcam_class_t class; 1872 uint32_t cfg_it = B_FALSE; 1873 1874 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 1875 1876 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1877 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1878 return (EINVAL); 1879 } 1880 1881 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1882 "nxge_param_fflp_hash_init value %x", cfg_value)); 1883 1884 if (pa->value != cfg_value) { 1885 pa->old_value = pa->value; 1886 pa->value = cfg_value; 1887 cfg_it = B_TRUE; 1888 } 1889 1890 if (cfg_it == B_TRUE) { 1891 char *h_name; 1892 1893 /* do the actual hw setup */ 1894 h_name = pa->name; 1895 h_name++; 1896 class = mi_strtol(h_name, &end, 10); 1897 switch (class) { 1898 case 1: 1899 status = nxge_fflp_set_hash1(nxgep, 1900 (uint32_t)pa->value); 1901 break; 1902 case 2: 1903 status = nxge_fflp_set_hash2(nxgep, 1904 (uint16_t)pa->value); 1905 break; 1906 1907 default: 1908 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1909 " nxge_param_fflp_hash_init" 1910 " %s Wrong hash var %d", 1911 pa->name, class)); 1912 return (EINVAL); 1913 } 1914 if (status != NXGE_OK) 1915 return (EINVAL); 1916 } 1917 1918 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 1919 return (0); 1920 } 1921 1922 /* ARGSUSED */ 1923 static int 1924 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1925 mblk_t *mp, char *value, caddr_t cp) 1926 { 1927 char *end; 1928 uint32_t status = 0, cfg_value; 1929 p_nxge_param_t pa = (p_nxge_param_t)cp; 1930 uint32_t cfg_it = B_FALSE; 1931 int rdc_grp; 1932 uint8_t real_rdc; 1933 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1934 p_nxge_hw_pt_cfg_t p_cfgp; 1935 p_nxge_rdc_grp_t rdc_grp_p; 1936 1937 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1938 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1939 1940 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 1941 1942 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1943 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1944 return (EINVAL); 1945 } 1946 1947 if (cfg_value >= p_cfgp->max_rdcs) { 1948 return (EINVAL); 1949 } 1950 1951 if (pa->value != cfg_value) { 1952 pa->old_value = pa->value; 1953 pa->value = cfg_value; 1954 cfg_it = B_TRUE; 1955 } 1956 1957 if (cfg_it == B_TRUE) { 1958 char *grp_name; 1959 grp_name = pa->name; 1960 grp_name += strlen("default-grp"); 1961 rdc_grp = mi_strtol(grp_name, &end, 10); 1962 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 1963 real_rdc = rdc_grp_p->start_rdc + cfg_value; 1964 if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1965 cfg_value) == B_FALSE) { 1966 pa->value = pa->old_value; 1967 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1968 " nxge_param_set_grp_rdc" 1969 " %d read %d actual %d outof range", 1970 rdc_grp, cfg_value, real_rdc)); 1971 return (EINVAL); 1972 } 1973 status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 1974 real_rdc); 1975 if (status != NXGE_OK) 1976 return (EINVAL); 1977 } 1978 1979 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 1980 return (0); 1981 } 1982 1983 /* ARGSUSED */ 1984 static int 1985 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 1986 mblk_t *mp, char *value, caddr_t cp) 1987 { 1988 char *end; 1989 uint32_t status = B_TRUE, cfg_value; 1990 p_nxge_param_t pa = (p_nxge_param_t)cp; 1991 uint32_t cfg_it = B_FALSE; 1992 1993 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1994 p_nxge_hw_pt_cfg_t p_cfgp; 1995 1996 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 1997 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1998 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1999 2000 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 2001 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2002 return (EINVAL); 2003 } 2004 2005 if (pa->value != cfg_value) { 2006 if (cfg_value >= p_cfgp->max_rdcs) 2007 return (EINVAL); 2008 pa->old_value = pa->value; 2009 pa->value = cfg_value; 2010 cfg_it = B_TRUE; 2011 } 2012 2013 if (cfg_it == B_TRUE) { 2014 status = nxge_rxdma_cfg_port_default_rdc(nxgep, 2015 nxgep->function_num, 2016 nxgep->rdc[cfg_value]); 2017 if (status != NXGE_OK) 2018 return (EINVAL); 2019 } 2020 2021 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 2022 return (0); 2023 } 2024 2025 /* ARGSUSED */ 2026 static int 2027 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 2028 mblk_t *mp, char *value, caddr_t cp) 2029 { 2030 char *end; 2031 uint32_t status = 0; 2032 uint64_t cfg_value = 0; 2033 p_nxge_param_t pa = (p_nxge_param_t)cp; 2034 uint32_t cfg_it = B_FALSE; 2035 2036 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 2037 cfg_value = mi_strtol(value, &end, BASE_HEX); 2038 2039 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2040 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2041 " nxge_param_set_nxge_debug_flag" 2042 " outof range %llx", cfg_value)); 2043 return (EINVAL); 2044 } 2045 if (pa->value != cfg_value) { 2046 pa->old_value = pa->value; 2047 pa->value = cfg_value; 2048 cfg_it = B_TRUE; 2049 } 2050 2051 if (cfg_it == B_TRUE) { 2052 nxgep->nxge_debug_level = pa->value; 2053 } 2054 2055 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 2056 return (status); 2057 } 2058 2059 /* ARGSUSED */ 2060 static int 2061 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2062 { 2063 int status = 0; 2064 p_nxge_param_t pa = (p_nxge_param_t)cp; 2065 2066 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 2067 2068 if (pa->value > 0xffffffff) 2069 (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 2070 (int)(pa->value & 0xffffffff)); 2071 else 2072 (void) mi_mpprintf(mp, "%x", (int)pa->value); 2073 2074 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 2075 return (status); 2076 } 2077 2078 /* ARGSUSED */ 2079 static int 2080 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 2081 mblk_t *mp, char *value, caddr_t cp) 2082 { 2083 char *end; 2084 uint32_t status = 0; 2085 uint64_t cfg_value = 0; 2086 p_nxge_param_t pa; 2087 uint32_t cfg_it = B_FALSE; 2088 2089 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 2090 cfg_value = mi_strtol(value, &end, BASE_HEX); 2091 pa = (p_nxge_param_t)cp; 2092 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2093 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 2094 " outof range %llx", cfg_value)); 2095 return (EINVAL); 2096 } 2097 if (pa->value != cfg_value) { 2098 pa->old_value = pa->value; 2099 pa->value = cfg_value; 2100 cfg_it = B_TRUE; 2101 } 2102 2103 if (cfg_it == B_TRUE) { 2104 npi_debug_level = pa->value; 2105 } 2106 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 2107 return (status); 2108 } 2109 2110 /* ARGSUSED */ 2111 static int 2112 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2113 { 2114 uint_t rdc; 2115 2116 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 2117 2118 (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2119 for (rdc = 0; rdc < nxgep->nrdc; rdc++) 2120 (void) nxge_dump_rxdma_channel(nxgep, nxgep->rdc[rdc]); 2121 2122 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 2123 return (0); 2124 } 2125 2126 /* ARGSUSED */ 2127 static int 2128 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2129 { 2130 uint_t tdc; 2131 2132 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 2133 2134 for (tdc = 0; tdc < nxgep->ntdc; tdc++) 2135 (void) nxge_txdma_regs_dump(nxgep, nxgep->tdc[tdc]); 2136 2137 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 2138 return (0); 2139 } 2140 2141 /* ARGSUSED */ 2142 static int 2143 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2144 { 2145 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 2146 2147 (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2148 2149 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 2150 return (0); 2151 } 2152 2153 /* ARGSUSED */ 2154 static int 2155 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2156 { 2157 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 2158 2159 (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2160 nxgep->function_num); 2161 2162 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 2163 return (0); 2164 } 2165 2166 /* ARGSUSED */ 2167 static int 2168 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2169 { 2170 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 2171 2172 (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2173 nxgep->function_num); 2174 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 2175 return (0); 2176 } 2177 2178 /* ARGSUSED */ 2179 static int 2180 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2181 { 2182 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 2183 2184 (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 2185 2186 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 2187 return (0); 2188 } 2189 2190 /* ARGSUSED */ 2191 static int 2192 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2193 { 2194 uint8_t table; 2195 2196 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 2197 for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 2198 (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 2199 table); 2200 } 2201 2202 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 2203 return (0); 2204 } 2205 2206 typedef struct block_info { 2207 char *name; 2208 uint32_t offset; 2209 } block_info_t; 2210 2211 block_info_t reg_block[] = { 2212 {"PIO", PIO}, 2213 {"FZC_PIO", FZC_PIO}, 2214 {"FZC_XMAC", FZC_MAC}, 2215 {"FZC_IPP", FZC_IPP}, 2216 {"FFLP", FFLP}, 2217 {"FZC_FFLP", FZC_FFLP}, 2218 {"PIO_VADDR", PIO_VADDR}, 2219 {"ZCP", ZCP}, 2220 {"FZC_ZCP", FZC_ZCP}, 2221 {"DMC", DMC}, 2222 {"FZC_DMC", FZC_DMC}, 2223 {"TXC", TXC}, 2224 {"FZC_TXC", FZC_TXC}, 2225 {"PIO_LDSV", PIO_LDSV}, 2226 {"PIO_LDGIM", PIO_LDGIM}, 2227 {"PIO_IMASK0", PIO_IMASK0}, 2228 {"PIO_IMASK1", PIO_IMASK1}, 2229 {"FZC_PROM", FZC_PROM}, 2230 {"END", ALL_FF_32}, 2231 }; 2232 2233 /* ARGSUSED */ 2234 static int 2235 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2236 { 2237 uint_t print_len, buf_len; 2238 p_mblk_t np; 2239 int rdc, tdc, block; 2240 uint64_t base; 2241 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2242 p_nxge_hw_pt_cfg_t p_cfgp; 2243 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 2244 p_tx_ring_t *tx_rings; 2245 p_rx_rcr_rings_t rx_rcr_rings; 2246 p_rx_rcr_ring_t *rcr_rings; 2247 p_rx_rbr_rings_t rx_rbr_rings; 2248 p_rx_rbr_ring_t *rbr_rings; 2249 2250 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2251 "==> nxge_param_dump_ptrs")); 2252 2253 (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2254 nxgep->function_num); 2255 2256 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 2257 /* The following may work even if we cannot get a large buf. */ 2258 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 2259 return (0); 2260 } 2261 2262 buf_len = buff_alloc_size; 2263 mp->b_cont = np; 2264 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2265 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2266 2267 rx_rcr_rings = nxgep->rx_rcr_rings; 2268 rcr_rings = rx_rcr_rings->rcr_rings; 2269 rx_rbr_rings = nxgep->rx_rbr_rings; 2270 rbr_rings = rx_rbr_rings->rbr_rings; 2271 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2272 "nxgep (nxge_t) $%p\n" 2273 "dev_regs (dev_regs_t) $%p\n", 2274 nxgep, nxgep->dev_regs); 2275 2276 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2277 2278 /* do register pointers */ 2279 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2280 "reg base (npi_reg_ptr_t) $%p\t " 2281 "pci reg (npi_reg_ptr_t) $%p\n", 2282 nxgep->dev_regs->nxge_regp, 2283 nxgep->dev_regs->nxge_pciregp); 2284 2285 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2286 2287 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2288 "\nBlock \t Offset \n"); 2289 2290 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2291 block = 0; 2292 #if defined(__i386) 2293 base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp; 2294 #else 2295 base = (uint64_t)nxgep->dev_regs->nxge_regp; 2296 #endif 2297 while (reg_block[block].offset != ALL_FF_32) { 2298 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2299 "%9s\t 0x%llx\n", 2300 reg_block[block].name, 2301 (unsigned long long)(reg_block[block].offset + base)); 2302 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2303 block++; 2304 } 2305 2306 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2307 "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2308 "rbrp (rx_rbr_ring_t)\n"); 2309 2310 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2311 2312 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 2313 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2314 " %d\t $%p\t\t $%p\n", 2315 rdc, rcr_rings[rdc], 2316 rbr_rings[rdc]); 2317 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2318 } 2319 2320 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2321 "\nTDC\t tdcp (tx_ring_t)\n"); 2322 2323 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2324 tx_rings = nxgep->tx_rings->rings; 2325 for (tdc = 0; tdc < p_cfgp->max_tdcs; tdc++) { 2326 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2327 " %d\t $%p\n", tdc, tx_rings[tdc]); 2328 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2329 } 2330 2331 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 2332 2333 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2334 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 2335 return (0); 2336 } 2337 2338 /* 2339 * Load 'name' into the named dispatch table pointed to by 'ndp'. 2340 * 'ndp' should be the address of a char pointer cell. If the table 2341 * does not exist (*ndp == 0), a new table is allocated and 'ndp' 2342 * is stuffed. If there is not enough space in the table for a new 2343 * entry, more space is allocated. 2344 */ 2345 /* ARGSUSED */ 2346 boolean_t 2347 nxge_nd_load(caddr_t *pparam, char *name, 2348 pfi_t get_pfi, pfi_t set_pfi, caddr_t data) 2349 { 2350 ND *nd; 2351 NDE *nde; 2352 2353 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " ==> nxge_nd_load")); 2354 if (!pparam) 2355 return (B_FALSE); 2356 2357 if ((nd = (ND *)*pparam) == NULL) { 2358 if ((nd = (ND *)KMEM_ZALLOC(sizeof (ND), KM_NOSLEEP)) == NULL) 2359 return (B_FALSE); 2360 *pparam = (caddr_t)nd; 2361 } 2362 2363 if (nd->nd_tbl) { 2364 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2365 if (strcmp(name, nde->nde_name) == 0) 2366 goto fill_it; 2367 } 2368 } 2369 2370 if (nd->nd_free_count <= 1) { 2371 if ((nde = (NDE *)KMEM_ZALLOC(nd->nd_size + 2372 NDE_ALLOC_SIZE, KM_NOSLEEP)) == NULL) 2373 return (B_FALSE); 2374 nd->nd_free_count += NDE_ALLOC_COUNT; 2375 if (nd->nd_tbl) { 2376 bcopy((char *)nd->nd_tbl, (char *)nde, nd->nd_size); 2377 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2378 } else { 2379 nd->nd_free_count--; 2380 nde->nde_name = "?"; 2381 nde->nde_get_pfi = nxge_nd_get_names; 2382 nde->nde_set_pfi = nxge_set_default; 2383 } 2384 nde->nde_data = (caddr_t)nd; 2385 nd->nd_tbl = nde; 2386 nd->nd_size += NDE_ALLOC_SIZE; 2387 } 2388 for (nde = nd->nd_tbl; nde->nde_name; nde++) 2389 noop; 2390 nd->nd_free_count--; 2391 fill_it: 2392 nde->nde_name = name; 2393 nde->nde_get_pfi = get_pfi; 2394 nde->nde_set_pfi = set_pfi; 2395 nde->nde_data = data; 2396 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " <== nxge_nd_load")); 2397 2398 return (B_TRUE); 2399 } 2400 2401 /* 2402 * Free the table pointed to by 'pparam' 2403 */ 2404 void 2405 nxge_nd_free(caddr_t *pparam) 2406 { 2407 ND *nd; 2408 2409 if ((nd = (ND *)*pparam) != NULL) { 2410 if (nd->nd_tbl) 2411 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2412 KMEM_FREE((char *)nd, sizeof (ND)); 2413 *pparam = nil(caddr_t); 2414 } 2415 } 2416 2417 int 2418 nxge_nd_getset(p_nxge_t nxgep, queue_t *q, caddr_t param, p_mblk_t mp) 2419 { 2420 int err; 2421 IOCP iocp; 2422 p_mblk_t mp1, mp2; 2423 ND *nd; 2424 NDE *nde; 2425 char *valp; 2426 size_t avail; 2427 2428 if (!param) { 2429 return (B_FALSE); 2430 } 2431 2432 nd = (ND *)param; 2433 iocp = (IOCP)mp->b_rptr; 2434 if ((iocp->ioc_count == 0) || !(mp1 = mp->b_cont)) { 2435 mp->b_datap->db_type = M_IOCACK; 2436 iocp->ioc_count = 0; 2437 iocp->ioc_error = EINVAL; 2438 return (B_FALSE); 2439 } 2440 2441 /* 2442 * NOTE - logic throughout nd_xxx assumes single data block for ioctl. 2443 * However, existing code sends in some big buffers. 2444 */ 2445 avail = iocp->ioc_count; 2446 if (mp1->b_cont) { 2447 freemsg(mp1->b_cont); 2448 mp1->b_cont = NULL; 2449 } 2450 2451 mp1->b_datap->db_lim[-1] = '\0'; /* Force null termination */ 2452 for (valp = (char *)mp1->b_rptr; *valp != '\0'; valp++) { 2453 if (*valp == '-') 2454 *valp = '_'; 2455 } 2456 2457 valp = (char *)mp1->b_rptr; 2458 2459 for (nde = nd->nd_tbl; /* */; nde++) { 2460 if (!nde->nde_name) 2461 return (B_FALSE); 2462 if (strcmp(nde->nde_name, valp) == 0) 2463 break; 2464 } 2465 err = EINVAL; 2466 while (*valp++) 2467 noop; 2468 if (!*valp || valp >= (char *)mp1->b_wptr) 2469 valp = nilp(char); 2470 switch (iocp->ioc_cmd) { 2471 case ND_GET: 2472 /* 2473 * (temporary) hack: "*valp" is size of user buffer for 2474 * copyout. If result of action routine is too big, free 2475 * excess and return ioc_rval as buffer size needed. 2476 * Return as many mblocks as will fit, free the rest. For 2477 * backward compatibility, assume size of original ioctl 2478 * buffer if "*valp" bad or not given. 2479 */ 2480 if (valp) 2481 avail = mi_strtol(valp, (char **)0, 10); 2482 /* 2483 * We overwrite the name/value with the reply data 2484 */ 2485 mp2 = mp1; 2486 while (mp2) { 2487 mp2->b_wptr = mp2->b_rptr; 2488 mp2 = mp2->b_cont; 2489 } 2490 2491 if (nde->nde_get_pfi) { 2492 err = (*nde->nde_get_pfi)(nxgep, q, mp1, nde->nde_data); 2493 } 2494 2495 if (!err) { 2496 size_t size_out = 0; 2497 ssize_t excess; 2498 2499 iocp->ioc_rval = 0; 2500 2501 /* Tack on the null */ 2502 err = nxge_mk_mblk_tail_space(mp1, &mp2, 1); 2503 if (!err) { 2504 *mp2->b_wptr++ = '\0'; 2505 size_out = msgdsize(mp1); 2506 excess = size_out - avail; 2507 if (excess > 0) { 2508 iocp->ioc_rval = (int)size_out; 2509 size_out -= excess; 2510 (void) adjmsg(mp1, -(excess + 1)); 2511 err = nxge_mk_mblk_tail_space( 2512 mp1, &mp2, 1); 2513 if (!err) 2514 *mp2->b_wptr++ = '\0'; 2515 else 2516 size_out = 0; 2517 } 2518 } else 2519 size_out = 0; 2520 iocp->ioc_count = size_out; 2521 } 2522 break; 2523 2524 case ND_SET: 2525 if (valp) { 2526 if (nde->nde_set_pfi) { 2527 err = (*nde->nde_set_pfi)(nxgep, q, mp1, valp, 2528 nde->nde_data); 2529 iocp->ioc_count = 0; 2530 freemsg(mp1); 2531 mp->b_cont = NULL; 2532 } 2533 } 2534 break; 2535 2536 default: 2537 break; 2538 } 2539 iocp->ioc_error = err; 2540 mp->b_datap->db_type = M_IOCACK; 2541 return (B_TRUE); 2542 } 2543 2544 /* ARGSUSED */ 2545 int 2546 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 2547 { 2548 ND *nd; 2549 NDE *nde; 2550 char *rwtag; 2551 boolean_t get_ok, set_ok; 2552 size_t param_len; 2553 int status = 0; 2554 2555 nd = (ND *)param; 2556 if (!nd) 2557 return (ENOENT); 2558 2559 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2560 get_ok = (nde->nde_get_pfi != nxge_get_default) && 2561 (nde->nde_get_pfi != NULL); 2562 set_ok = (nde->nde_set_pfi != nxge_set_default) && 2563 (nde->nde_set_pfi != NULL); 2564 if (get_ok) { 2565 if (set_ok) 2566 rwtag = "read and write"; 2567 else 2568 rwtag = "read only"; 2569 } else if (set_ok) 2570 rwtag = "write only"; 2571 else { 2572 continue; 2573 } 2574 param_len = strlen(rwtag); 2575 param_len += strlen(nde->nde_name); 2576 param_len += 4; 2577 2578 (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 2579 } 2580 return (status); 2581 } 2582 2583 /* ARGSUSED */ 2584 int 2585 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 2586 { 2587 return (EACCES); 2588 } 2589 2590 /* ARGSUSED */ 2591 int 2592 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2593 caddr_t data) 2594 { 2595 return (EACCES); 2596 } 2597 2598 void 2599 nxge_param_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2600 { 2601 int cmd; 2602 int status = B_FALSE; 2603 2604 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_ioctl")); 2605 cmd = iocp->ioc_cmd; 2606 2607 switch (cmd) { 2608 default: 2609 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2610 "nxge_param_ioctl: bad cmd 0x%0x", cmd)); 2611 break; 2612 2613 case ND_GET: 2614 case ND_SET: 2615 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2616 "nxge_param_ioctl: cmd 0x%0x", cmd)); 2617 if (!nxge_nd_getset(nxgep, wq, nxgep->param_list, mp)) { 2618 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2619 "false ret from nxge_nd_getset")); 2620 break; 2621 } 2622 status = B_TRUE; 2623 break; 2624 } 2625 2626 if (status) { 2627 qreply(wq, mp); 2628 } else { 2629 miocnak(wq, mp, 0, EINVAL); 2630 } 2631 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_ioctl")); 2632 } 2633 2634 /* ARGSUSED */ 2635 static boolean_t 2636 nxge_param_link_update(p_nxge_t nxgep) 2637 { 2638 p_nxge_param_t param_arr; 2639 nxge_param_index_t i; 2640 boolean_t update_xcvr; 2641 boolean_t update_dev; 2642 int instance; 2643 boolean_t status = B_TRUE; 2644 2645 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_link_update")); 2646 2647 param_arr = nxgep->param_arr; 2648 instance = nxgep->instance; 2649 update_xcvr = B_FALSE; 2650 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 2651 update_xcvr |= param_arr[i].value; 2652 } 2653 2654 if (update_xcvr) { 2655 update_xcvr = B_FALSE; 2656 for (i = param_autoneg; i < param_enable_ipg0; i++) { 2657 update_xcvr |= 2658 (param_arr[i].value != param_arr[i].old_value); 2659 param_arr[i].old_value = param_arr[i].value; 2660 } 2661 if (update_xcvr) { 2662 RW_ENTER_WRITER(&nxgep->filter_lock); 2663 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2664 (void) nxge_link_init(nxgep); 2665 (void) nxge_mac_init(nxgep); 2666 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 2667 RW_EXIT(&nxgep->filter_lock); 2668 } 2669 } else { 2670 cmn_err(CE_WARN, " Last setting will leave nxge%d with " 2671 " no link capabilities.", instance); 2672 cmn_err(CE_WARN, " Restoring previous setting."); 2673 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 2674 param_arr[i].value = param_arr[i].old_value; 2675 } 2676 2677 update_dev = B_FALSE; 2678 2679 if (update_dev) { 2680 RW_ENTER_WRITER(&nxgep->filter_lock); 2681 (void) nxge_rx_mac_disable(nxgep); 2682 (void) nxge_tx_mac_disable(nxgep); 2683 (void) nxge_tx_mac_enable(nxgep); 2684 (void) nxge_rx_mac_enable(nxgep); 2685 RW_EXIT(&nxgep->filter_lock); 2686 } 2687 2688 nxge_param_hw_update_exit: 2689 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2690 "<== nxge_param_link_update status = 0x%08x", status)); 2691 return (status); 2692 } 2693