1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 NetXen, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 /* 27 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 28 * Use is subject to license terms. 29 */ 30 31 #ifndef _UNM_NIC_ 32 #define _UNM_NIC_ 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include <sys/inttypes.h> 39 #include <sys/rwlock.h> 40 #include <sys/mutex.h> 41 #include <sys/ddi.h> 42 43 #include <sys/sunddi.h> 44 #include <sys/types.h> 45 #include <sys/stream.h> 46 #include <sys/strsun.h> 47 #include <sys/strsubr.h> 48 #include <sys/dlpi.h> 49 #include <sys/devops.h> 50 #include <sys/stat.h> 51 #include <sys/pci.h> 52 #include <sys/note.h> 53 #include <sys/modctl.h> 54 #include <sys/kstat.h> 55 #include <sys/ethernet.h> 56 #include <sys/errno.h> 57 #include <netinet/ip6.h> 58 #include <inet/common.h> 59 #include <sys/pattr.h> 60 #include <inet/mi.h> 61 #include <inet/nd.h> 62 63 #include <sys/mac_provider.h> 64 #include <sys/mac_ether.h> 65 #include <sys/miiregs.h> /* by fjlite out of intel */ 66 67 #include "unm_nic_hw.h" 68 #include "nic_cmn.h" 69 #include "unm_inc.h" /* For MAX_RCV_CTX */ 70 #include "unm_brdcfg.h" 71 #include "unm_version.h" 72 #include "nic_phan_reg.h" 73 #include "unm_nic_ioctl.h" 74 75 #define MAX_ADDR_LEN 6 76 77 #define ADDR_IN_WINDOW1(off) \ 78 ((off > UNM_CRB_PCIX_HOST2) && (off < UNM_CRB_MAX)) ? 1 : 0 79 80 typedef unsigned long uptr_t; 81 82 #define FIRST_PAGE_GROUP_START 0 83 #define FIRST_PAGE_GROUP_END 0x100000 84 85 #define SECOND_PAGE_GROUP_START 0x6000000 86 #define SECOND_PAGE_GROUP_END 0x68BC000 87 88 #define THIRD_PAGE_GROUP_START 0x70E4000 89 #define THIRD_PAGE_GROUP_END 0x8000000 90 91 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START 92 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START 93 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START 94 95 /* 96 * normalize a 64MB crb address to 32MB PCI window 97 * To use CRB_NORMALIZE, window _must_ be set to 1 98 */ 99 #define CRB_NORMAL(reg) \ 100 (reg) - UNM_CRB_PCIX_HOST2 + UNM_CRB_PCIX_HOST 101 #define CRB_NORMALIZE(adapter, reg) \ 102 (void *)(unsigned long)(pci_base_offset(adapter, CRB_NORMAL(reg))) 103 104 #define DB_NORMALIZE(adapter, off) \ 105 (void *)((unsigned long)adapter->ahw.db_base + (off)) 106 107 #define find_diff_among(a, b, range) \ 108 ((a) < (b)?((b)-(a)):((b)+(range)-(a))) 109 110 #define __FUNCTION__ __func__ 111 #define nx_msleep(_msecs_) delay(drv_usectohz(_msecs_ * 1000)) 112 113 #define HOST_TO_LE_64 LE_64 114 #define HOST_TO_LE_32 LE_32 115 #define LE_TO_HOST_32 LE_32 116 #define HOST_TO_LE_16 LE_16 117 #define LE_TO_HOST_16 LE_16 118 119 #define dbwritel(DATA, ADDRESS) \ 120 ddi_put32(adapter->db_handle, (uint32_t *)(ADDRESS), (DATA)) 121 122 /* 123 * Following macros require the mapped addresses to access 124 * the Phantom memory. 125 */ 126 #define UNM_NIC_PCI_READ_8(ADDRESS) \ 127 ddi_get8(adapter->regs_handle, (uint8_t *)(ADDRESS)) 128 #define UNM_NIC_PCI_READ_16(ADDRESS) \ 129 ddi_get16(adapter->regs_handle, (uint16_t *)(ADDRESS)) 130 #define UNM_NIC_PCI_READ_32(ADDRESS) \ 131 ddi_get32(adapter->regs_handle, (uint32_t *)(ADDRESS)) 132 #define UNM_NIC_PCI_READ_64(ADDRESS) \ 133 ddi_get64(adapter->regs_handle, (uint64_t *)(ADDRESS)) 134 135 #define UNM_NIC_PCI_WRITE_8(DATA, ADDRESS) \ 136 ddi_put8(adapter->regs_handle, (uint8_t *)(ADDRESS), (DATA)) 137 #define UNM_NIC_PCI_WRITE_16(DATA, ADDRESS) \ 138 ddi_put16(adapter->regs_handle, (uint16_t *)(ADDRESS), (DATA)) 139 #define UNM_NIC_PCI_WRITE_32(DATA, ADDRESS) \ 140 ddi_put32(adapter->regs_handle, (uint32_t *)(ADDRESS), (DATA)) 141 #define UNM_NIC_PCI_WRITE_64(DATA, ADDRESS) \ 142 ddi_put64(adapter->regs_handle, (uint64_t *)(ADDRESS), (DATA)) 143 144 #ifdef DEBUG_LEVEL 145 #define DPRINTF(n, args) if (DEBUG_LEVEL > (n)) cmn_err args; 146 #else 147 #define DPRINTF(n, args) 148 #endif 149 150 #define UNM_SPIN_LOCK(_lp_) mutex_enter((_lp_)) 151 #define UNM_SPIN_UNLOCK(_lp_) mutex_exit((_lp_)) 152 #define UNM_SPIN_LOCK_ISR(_lp_) mutex_enter((_lp_)) 153 #define UNM_SPIN_UNLOCK_ISR(_lp_) mutex_exit((_lp_)) 154 155 #define UNM_WRITE_LOCK(_lp_) rw_enter((_lp_), RW_WRITER) 156 #define UNM_WRITE_UNLOCK(_lp_) rw_exit((_lp_)) 157 #define UNM_READ_LOCK(_lp_) rw_enter((_lp_), RW_READER) 158 #define UNM_READ_UNLOCK(_lp_) rw_exit((_lp_)) 159 #define UNM_WRITE_LOCK_IRQS(_lp_, _fl_) rw_enter((_lp_), RW_WRITER) 160 #define UNM_WRITE_UNLOCK_IRQR(_lp_, _fl_) rw_exit((_lp_)) 161 162 extern char unm_nic_driver_name[]; 163 extern int verbmsg; 164 165 typedef struct unm_dmah_node { 166 struct unm_dmah_node *next; 167 ddi_dma_handle_t dmahdl; 168 }unm_dmah_node_t; 169 170 typedef struct dma_area { 171 ddi_acc_handle_t acc_hdl; /* handle for memory */ 172 ddi_dma_handle_t dma_hdl; /* DMA handle */ 173 uint32_t ncookies; 174 u64 dma_addr; 175 void *vaddr; 176 } dma_area_t; 177 178 struct unm_cmd_buffer { 179 dma_area_t dma_area; 180 mblk_t *msg; 181 unm_dmah_node_t *head, *tail; 182 }; 183 184 typedef struct pkt_info { 185 uint32_t total_len; 186 uint16_t mblk_no; 187 uint16_t etype; 188 uint16_t mac_hlen; 189 uint16_t ip_hlen; 190 uint16_t l4_proto; 191 } pktinfo_t; 192 193 typedef struct unm_rcv_desc_context_s unm_rcv_desc_ctx_t; 194 typedef struct unm_adapter_s unm_adapter; 195 196 typedef struct unm_rx_buffer { 197 struct unm_rx_buffer *next; 198 dma_area_t dma_info; 199 frtn_t rx_recycle; /* recycle function */ 200 mblk_t *mp; 201 unm_rcv_desc_ctx_t *rcv_desc; 202 unm_adapter *adapter; 203 }unm_rx_buffer_t; 204 205 /* Board types */ 206 #define UNM_NIC_GBE 0x01 207 #define UNM_NIC_XGBE 0x02 208 209 /* 210 * One hardware_context{} per adapter 211 * contains interrupt info as well shared hardware info. 212 */ 213 typedef struct _hardware_context { 214 unsigned long pci_base0; 215 unsigned long pci_len0; 216 unsigned long pci_base1; 217 unsigned long pci_len1; 218 unsigned long pci_base2; 219 unsigned long pci_len2; 220 unsigned long first_page_group_end; 221 unsigned long first_page_group_start; 222 uint8_t revision_id; 223 uint8_t cut_through; 224 uint16_t board_type; 225 int pci_func; 226 uint16_t max_ports; 227 unm_board_info_t boardcfg; 228 uint32_t linkup; 229 230 struct unm_adapter_s *adapter; 231 cmdDescType0_t *cmdDescHead; 232 233 uint32_t cmdProducer; 234 uint32_t cmdConsumer; 235 uint32_t rcvFlag; 236 uint32_t crb_base; 237 unsigned long db_base; /* base of mapped db memory */ 238 unsigned long db_len; /* length of mapped db memory */ 239 240 241 uint64_t cmdDesc_physAddr; 242 int qdr_sn_window, ddr_mn_window; 243 unsigned long mn_win_crb, ms_win_crb; 244 ddi_dma_handle_t cmd_desc_dma_handle; 245 ddi_acc_handle_t cmd_desc_acc_handle; 246 ddi_dma_cookie_t cmd_desc_dma_cookie; 247 } hardware_context, *phardware_context; 248 249 #define NX_CT_DEFAULT_RX_BUF_LEN 2048 250 #define MTU_SIZE 1500 251 #define MAX_COOKIES_PER_CMD 16 252 #define UNM_DB_MAPSIZE_BYTES 0x1000 253 #define EXTRA_HANDLES 512 254 #define UNM_TX_BCOPY_THRESHOLD 128 255 #define UNM_RX_BCOPY_THRESHOLD 128 256 #define NX_MIN_DRIVER_RDS_SIZE 64 257 258 typedef struct unm_pauseparam { 259 uint16_t rx_pause; 260 uint16_t tx_pause; 261 } unm_pauseparam_t; 262 263 /* 264 * The driver supports the NDD ioctls ND_GET/ND_SET, and the loopback 265 * ioctls LB_GET_INFO_SIZE/LB_GET_INFO/LB_GET_MODE/LB_SET_MODE 266 * 267 * These are the values to use with LD_SET_MODE. 268 */ 269 #define UNM_LOOP_NONE 0 270 #define UNM_LOOP_INTERNAL_PHY 1 271 #define UNM_LOOP_INTERNAL_MAC 2 272 273 /* 274 * Named Data (ND) Parameter Management Structure 275 */ 276 typedef struct { 277 int ndp_info; 278 int ndp_min; 279 int ndp_max; 280 int ndp_val; 281 char *ndp_name; 282 } nd_param_t; /* 0x18 (24) bytes */ 283 284 /* 285 * NDD parameter indexes, divided into: 286 * 287 * read-only parameters describing the hardware's capabilities 288 * read-write parameters controlling the advertised capabilities 289 * read-only parameters describing the partner's capabilities 290 * read-only parameters describing the link state 291 */ 292 enum { 293 PARAM_AUTONEG_CAP = 0, 294 PARAM_PAUSE_CAP, 295 PARAM_ASYM_PAUSE_CAP, 296 PARAM_10000FDX_CAP, 297 PARAM_1000FDX_CAP, 298 PARAM_1000HDX_CAP, 299 PARAM_100T4_CAP, 300 PARAM_100FDX_CAP, 301 PARAM_100HDX_CAP, 302 PARAM_10FDX_CAP, 303 PARAM_10HDX_CAP, 304 305 PARAM_ADV_AUTONEG_CAP, 306 PARAM_ADV_PAUSE_CAP, 307 PARAM_ADV_ASYM_PAUSE_CAP, 308 PARAM_ADV_10000FDX_CAP, 309 PARAM_ADV_1000FDX_CAP, 310 PARAM_ADV_1000HDX_CAP, 311 PARAM_ADV_100T4_CAP, 312 PARAM_ADV_100FDX_CAP, 313 PARAM_ADV_100HDX_CAP, 314 PARAM_ADV_10FDX_CAP, 315 PARAM_ADV_10HDX_CAP, 316 317 PARAM_LINK_STATUS, 318 PARAM_LINK_SPEED, 319 PARAM_LINK_DUPLEX, 320 321 PARAM_LOOP_MODE, 322 323 PARAM_COUNT 324 }; 325 326 struct unm_adapter_stats { 327 uint64_t rcvdbadmsg; 328 uint64_t xmitcalled; 329 uint64_t xmitedframes; 330 uint64_t xmitfinished; 331 uint64_t badmsglen; 332 uint64_t nocmddescriptor; 333 uint64_t polled; 334 uint64_t uphappy; 335 uint64_t updropped; 336 uint64_t uplcong; 337 uint64_t uphcong; 338 uint64_t upmcong; 339 uint64_t updunno; 340 uint64_t msgfreed; 341 uint64_t txdropped; 342 uint64_t txnullmsg; 343 uint64_t csummed; 344 uint64_t no_rcv; 345 uint64_t rxbytes; 346 uint64_t txbytes; 347 uint64_t ints; 348 uint64_t desballocfailed; 349 uint64_t txcopyed; 350 uint64_t txmapped; 351 uint64_t outoftxdmahdl; 352 uint64_t outofcmddesc; 353 uint64_t rxcopyed; 354 uint64_t rxmapped; 355 uint64_t outofrxbuf; 356 uint64_t promiscmode; 357 uint64_t rxbufshort; 358 uint64_t allocbfailed; 359 }; 360 361 /* descriptor types */ 362 #define RCV_RING_STD RCV_DESC_NORMAL 363 #define RCV_RING_JUMBO RCV_DESC_JUMBO 364 #define RCV_RING_LRO RCV_DESC_LRO 365 366 /* 367 * Rcv Descriptor Context. One such per Rcv Descriptor. There may 368 * be one Rcv Descriptor for normal packets, one for jumbo, 369 * one for LRO and may be expanded. 370 */ 371 struct unm_rcv_desc_context_s { 372 uint32_t producer; 373 374 uint64_t phys_addr; 375 dev_info_t *phys_pdev; 376 /* address of rx ring in Phantom */ 377 rcvDesc_t *desc_head; 378 379 uint32_t MaxRxDescCount; 380 uint32_t rx_desc_handled; 381 uint32_t rx_buf_card; 382 uint32_t rx_buf_total; 383 uint32_t rx_buf_free; 384 uint32_t rx_buf_recycle; 385 unm_rx_buffer_t *rx_buf_pool; 386 unm_rx_buffer_t *pool_list; 387 unm_rx_buffer_t *recycle_list; 388 kmutex_t pool_lock[1]; /* buffer pool lock */ 389 kmutex_t recycle_lock[1]; /* buffer recycle lock */ 390 /* size of the receive buf */ 391 uint32_t buf_size; 392 /* rx buffers for receive */ 393 394 ddi_dma_handle_t rx_desc_dma_handle; 395 ddi_acc_handle_t rx_desc_acc_handle; 396 ddi_dma_cookie_t rx_desc_dma_cookie; 397 uint32_t host_rx_producer; 398 uint32_t dma_size; 399 }; 400 401 /* 402 * Receive context. There is one such structure per instance of the 403 * receive processing. Any state information that is relevant to 404 * the receive, and is must be in this structure. The global data may be 405 * present elsewhere. 406 */ 407 typedef struct unm_recv_context_s { 408 unm_rcv_desc_ctx_t rcv_desc[NUM_RCV_DESC_RINGS]; 409 410 uint32_t statusRxConsumer; 411 412 uint64_t rcvStatusDesc_physAddr; 413 statusDesc_t *rcvStatusDescHead; 414 415 ddi_dma_handle_t status_desc_dma_handle; 416 ddi_acc_handle_t status_desc_acc_handle; 417 ddi_dma_cookie_t status_desc_dma_cookie; 418 419 uint32_t state, host_sds_consumer; 420 uint16_t context_id, virt_port; 421 } unm_recv_context_t; 422 423 #define UNM_NIC_MSI_ENABLED 0x02 424 #define UNM_NIC_MSIX_ENABLED 0x04 425 #define UNM_IS_MSI_FAMILY(ADAPTER) \ 426 ((ADAPTER)->flags & (UNM_NIC_MSI_ENABLED | UNM_NIC_MSIX_ENABLED)) 427 428 #define NX_USE_MSIX 429 430 /* msix defines */ 431 #define MSIX_ENTRIES_PER_ADAPTER 8 432 #define UNM_MSIX_TBL_SPACE 8192 433 #define UNM_PCI_REG_MSIX_TBL 0x44 434 435 /* 436 * Bug: word or char write on MSI-X capcabilities register (0x40) in PCI config 437 * space has no effect on register values. Need to write dword. 438 */ 439 #define UNM_HWBUG_8_WORKAROUND 440 441 /* 442 * Bug: Can not reset bit 32 (msix enable bit) on MSI-X capcabilities 443 * register (0x40) independently. 444 * Need to write 0x0 (zero) to MSI-X capcabilities register in order to reset 445 * msix enable bit. On writing zero rest of the bits are not touched. 446 */ 447 #define UNM_HWBUG_9_WORKAROUND 448 449 #define UNM_MC_COUNT 38 /* == ((UNM_ADDR_L2LU_COUNT-1)/4) -2 */ 450 451 /* Following structure is for specific port information */ 452 struct unm_adapter_s { 453 hardware_context ahw; 454 uint8_t id[32]; 455 uint16_t portnum; 456 uint16_t physical_port; 457 uint16_t link_speed; 458 uint16_t link_duplex; 459 460 struct unm_adapter_stats stats; 461 int rx_csum; 462 int status; 463 kmutex_t stats_lock; 464 unsigned char mac_addr[MAX_ADDR_LEN]; 465 int mtu; /* active mtu */ 466 int maxmtu; /* max possible mtu value */ 467 uint32_t promisc; 468 469 mac_resource_handle_t mac_rx_ring_ha; 470 mac_handle_t mach; 471 int flags; 472 473 int instance; 474 dev_info_t *dip; 475 ddi_acc_handle_t pci_cfg_handle; 476 ddi_acc_handle_t regs_handle; 477 ddi_dma_attr_t gc_dma_attr_desc; 478 479 struct ddi_device_acc_attr gc_attr_desc; 480 ddi_iblock_cookie_t iblock_cookie; 481 const char *name; 482 ddi_acc_handle_t db_handle; 483 484 ddi_intr_handle_t intr_handle; 485 int intr_type; 486 uint_t intr_pri; 487 unm_dmah_node_t *dmahdl_pool; 488 unm_dmah_node_t tx_dma_hdls[MAX_CMD_DESCRIPTORS+EXTRA_HANDLES]; 489 uint64_t freehdls; 490 uint64_t freecmds; 491 int tx_bcopy_threshold; 492 kmutex_t tx_lock; 493 krwlock_t adapter_lock; 494 kmutex_t lock; 495 struct nx_legacy_intr_set legacy_intr; 496 timeout_id_t watchdog_timer; 497 kstat_t *kstats[1]; 498 499 uint32_t curr_window; 500 uint32_t crb_win; 501 uint32_t cmdProducer; 502 uint32_t *cmdConsumer; 503 504 uint32_t interrupt_crb; 505 uint32_t fw_major; 506 uint32_t crb_addr_cmd_producer; 507 uint32_t crb_addr_cmd_consumer; 508 uint16_t tx_context_id; 509 short context_alloced; 510 int max_rds_rings; 511 512 uint32_t lastCmdConsumer; 513 /* Num of bufs posted in phantom */ 514 uint32_t pendingCmdCount; 515 uint32_t MaxTxDescCount; 516 uint32_t MaxRxDescCount; 517 uint32_t MaxJumboRxDescCount; 518 uint32_t MaxLroRxDescCount; 519 /* Num of instances active on cmd buffer ring */ 520 int resched_needed; 521 522 int driver_mismatch; 523 uint32_t temp; 524 525 struct unm_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */ 526 int rx_bcopy_threshold; 527 528 /* 529 * Receive instances. These can be either one per port, 530 * or one per peg, etc. 531 */ 532 unm_recv_context_t recv_ctx[MAX_RCV_CTX]; 533 int is_up; 534 535 /* context interface shared between card and host */ 536 RingContext *ctxDesc; 537 uint64_t ctxDesc_physAddr; 538 ddi_dma_handle_t ctxDesc_dma_handle; 539 ddi_acc_handle_t ctxDesc_acc_handle; 540 541 struct { 542 void *addr; 543 uint64_t phys_addr; 544 ddi_dma_handle_t dma_handle; 545 ddi_acc_handle_t acc_handle; 546 } dummy_dma; 547 548 void (*unm_nic_pci_change_crbwindow)(struct unm_adapter_s *, 549 uint32_t); 550 int (*unm_crb_writelit_adapter)(struct unm_adapter_s *, 551 unsigned long, int); 552 unsigned long long 553 (*unm_nic_pci_set_window)(struct unm_adapter_s *, 554 unsigned long long); 555 int (*unm_nic_fill_statistics)(struct unm_adapter_s *, 556 struct unm_statistics *); 557 int (*unm_nic_clear_statistics)(struct unm_adapter_s *); 558 int (*unm_nic_hw_write_wx)(struct unm_adapter_s *, u64, 559 void *, int); 560 int (*unm_nic_hw_read_wx)(struct unm_adapter_s *, u64, void *, int); 561 int (*unm_nic_hw_write_ioctl)(struct unm_adapter_s *, u64, void *, 562 int); 563 int (*unm_nic_hw_read_ioctl)(struct unm_adapter_s *, u64, void *, 564 int); 565 int (*unm_nic_pci_mem_write)(struct unm_adapter_s *, u64, void *, 566 int); 567 int (*unm_nic_pci_mem_read)(struct unm_adapter_s *, u64, void *, 568 int); 569 int (*unm_nic_pci_write_immediate)(struct unm_adapter_s *, u64, 570 u32 *); 571 int (*unm_nic_pci_read_immediate)(struct unm_adapter_s *, u64, 572 u32 *); 573 void (*unm_nic_pci_write_normalize)(struct unm_adapter_s *, u64, 574 u32); 575 u32 (*unm_nic_pci_read_normalize)(struct unm_adapter_s *, u64); 576 577 caddr_t nd_data_p; 578 nd_param_t nd_params[PARAM_COUNT]; 579 }; /* unm_adapter structure */ 580 581 #define UNM_HOST_DUMMY_DMA_SIZE 1024 582 583 /* Following structure is for specific port information */ 584 585 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ 586 ((adapter)->ahw.pci_base0 + off) 587 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ 588 ((adapter)->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START) 589 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \ 590 ((adapter)->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START) 591 592 #define pci_base_offset(adapter, off) \ 593 ((((off) < ((adapter)->ahw.first_page_group_end)) && \ 594 ((off) >= ((adapter)->ahw.first_page_group_start))) ? \ 595 ((adapter)->ahw.pci_base0 + (off)) : \ 596 ((((off) < SECOND_PAGE_GROUP_END) && \ 597 ((off) >= SECOND_PAGE_GROUP_START)) ? \ 598 ((adapter)->ahw.pci_base1 + \ 599 (off) - SECOND_PAGE_GROUP_START) : \ 600 ((((off) < THIRD_PAGE_GROUP_END) && \ 601 ((off) >= THIRD_PAGE_GROUP_START)) ? \ 602 ((adapter)->ahw.pci_base2 + (off) - \ 603 THIRD_PAGE_GROUP_START) : \ 604 0))) 605 #define unm_nic_reg_write(_adp_, _off_, _val_) \ 606 { \ 607 __uint32_t _v1_ = (_val_); \ 608 ((_adp_)->unm_nic_hw_write_wx((_adp_), (_off_), \ 609 &_v1_, 4)); \ 610 } 611 612 #define unm_nic_reg_read(_adp_, _off_, _ptr_) \ 613 ((_adp_)->unm_nic_hw_read_wx((_adp_), (_off_), (_ptr_), 4)) 614 615 616 #define unm_nic_write_w0(_adp_, _idx_, _val_) \ 617 ((_adp_)->unm_nic_hw_write_wx((_adp_), (_idx_), &(_val_), 4)) 618 619 #define unm_nic_read_w0(_adp_, _idx_, _val_) \ 620 ((_adp_)->unm_nic_hw_read_wx((_adp_), (_idx_), (_val_), 4)) 621 622 /* Functions available from unm_nic_hw.c */ 623 int unm_nic_get_board_info(struct unm_adapter_s *adapter); 624 void _unm_nic_write_crb(struct unm_adapter_s *adapter, uint32_t index, 625 uint32_t value); 626 void unm_nic_write_crb(struct unm_adapter_s *adapter, uint32_t index, 627 uint32_t value); 628 void _unm_nic_read_crb(struct unm_adapter_s *adapter, uint32_t index, 629 uint32_t *value); 630 void unm_nic_read_crb(struct unm_adapter_s *adapter, uint32_t index, 631 uint32_t *value); 632 // int unm_nic_reg_read (unm_adapter *adapter, u64 off); 633 int _unm_nic_hw_write(struct unm_adapter_s *adapter, 634 u64 off, void *data, int len); 635 int unm_nic_hw_write(struct unm_adapter_s *adapter, 636 u64 off, void *data, int len); 637 int _unm_nic_hw_read(struct unm_adapter_s *adapter, 638 u64 off, void *data, int len); 639 int unm_nic_hw_read(struct unm_adapter_s *adapter, 640 u64 off, void *data, int len); 641 void _unm_nic_hw_block_read(struct unm_adapter_s *adapter, 642 u64 off, void *data, int num_words); 643 void unm_nic_hw_block_read(struct unm_adapter_s *adapter, 644 u64 off, void *data, int num_words); 645 void _unm_nic_hw_block_write(struct unm_adapter_s *adapter, 646 u64 off, void *data, int num_words); 647 void unm_nic_hw_block_write(struct unm_adapter_s *adapter, 648 u64 off, void *data, int num_words); 649 int unm_nic_pci_mem_write(struct unm_adapter_s *adapter, 650 u64 off, void *data, int size); 651 void unm_nic_mem_block_read(struct unm_adapter_s *adapter, u64 off, 652 void *data, int num_words); 653 void unm_nic_mem_block_write(struct unm_adapter_s *adapter, u64 off, 654 void *data, int num_words); 655 int unm_nic_hw_read_ioctl(unm_adapter *adapter, u64 off, void *data, int len); 656 int unm_nic_hw_write_ioctl(unm_adapter *adapter, u64 off, void *data, int len); 657 int unm_nic_macaddr_set(struct unm_adapter_s *, __uint8_t *addr); 658 void unm_tcl_resetall(struct unm_adapter_s *adapter); 659 void unm_tcl_phaninit(struct unm_adapter_s *adapter); 660 void unm_tcl_postimage(struct unm_adapter_s *adapter); 661 int unm_nic_set_mtu(struct unm_adapter_s *adapter, int new_mtu); 662 long unm_nic_phy_read(unm_adapter *adapter, long reg, __uint32_t *); 663 long unm_nic_init_port(struct unm_adapter_s *adapter); 664 void unm_crb_write_adapter(unsigned long off, void *data, 665 struct unm_adapter_s *adapter); 666 int unm_crb_read_adapter(unsigned long off, void *data, 667 struct unm_adapter_s *adapter); 668 int unm_crb_read_val_adapter(unsigned long off, 669 struct unm_adapter_s *adapter); 670 void unm_nic_stop_port(struct unm_adapter_s *adapter); 671 int unm_nic_set_promisc_mode(struct unm_adapter_s *adapter); 672 int unm_nic_unset_promisc_mode(struct unm_adapter_s *adapter); 673 674 /* unm_nic_hw.c */ 675 void unm_nic_pci_change_crbwindow_128M(unm_adapter *adapter, uint32_t wndw); 676 int unm_crb_writelit_adapter_128M(struct unm_adapter_s *, unsigned long, int); 677 int unm_nic_hw_write_wx_128M(unm_adapter *adapter, u64 off, void *data, 678 int len); 679 int unm_nic_hw_read_wx_128M(unm_adapter *adapter, u64 off, void *data, int len); 680 int unm_nic_hw_write_ioctl_128M(unm_adapter *adapter, u64 off, void *data, 681 int len); 682 int unm_nic_hw_read_ioctl_128M(unm_adapter *adapter, u64 off, void *data, 683 int len); 684 int unm_nic_pci_mem_write_128M(struct unm_adapter_s *adapter, u64 off, 685 void *data, int size); 686 int unm_nic_pci_mem_read_128M(struct unm_adapter_s *adapter, u64 off, 687 void *data, int size); 688 void unm_nic_pci_write_normalize_128M(unm_adapter *adapter, u64 off, u32 data); 689 u32 unm_nic_pci_read_normalize_128M(unm_adapter *adapter, u64 off); 690 int unm_nic_pci_write_immediate_128M(unm_adapter *adapter, u64 off, u32 *data); 691 int unm_nic_pci_read_immediate_128M(unm_adapter *adapter, u64 off, u32 *data); 692 unsigned long long unm_nic_pci_set_window_128M(unm_adapter *adapter, 693 unsigned long long addr); 694 int unm_nic_clear_statistics_128M(struct unm_adapter_s *adapter); 695 int unm_nic_fill_statistics_128M(struct unm_adapter_s *adapter, 696 struct unm_statistics *unm_stats); 697 698 void unm_nic_pci_change_crbwindow_2M(unm_adapter *adapter, uint32_t wndw); 699 int unm_crb_writelit_adapter_2M(struct unm_adapter_s *, unsigned long, int); 700 int unm_nic_hw_write_wx_2M(unm_adapter *adapter, u64 off, void *data, int len); 701 int unm_nic_pci_mem_write_2M(struct unm_adapter_s *adapter, u64 off, 702 void *data, int size); 703 int unm_nic_pci_mem_read_2M(struct unm_adapter_s *adapter, u64 off, 704 void *data, int size); 705 int unm_nic_hw_read_wx_2M(unm_adapter *adapter, u64 off, void *data, int len); 706 void unm_nic_pci_write_normalize_2M(unm_adapter *adapter, u64 off, u32 data); 707 u32 unm_nic_pci_read_normalize_2M(unm_adapter *adapter, u64 off); 708 int unm_nic_pci_write_immediate_2M(unm_adapter *adapter, u64 off, u32 *data); 709 int unm_nic_pci_read_immediate_2M(unm_adapter *adapter, u64 off, u32 *data); 710 unsigned long long unm_nic_pci_set_window_2M(unm_adapter *adapter, 711 unsigned long long addr); 712 int unm_nic_clear_statistics_2M(struct unm_adapter_s *adapter); 713 int unm_nic_fill_statistics_2M(struct unm_adapter_s *adapter, 714 struct unm_statistics *unm_stats); 715 void nx_p3_nic_set_multi(unm_adapter *adapter); 716 717 /* unm_nic_init.c */ 718 int phantom_init(struct unm_adapter_s *adapter, int first_time); 719 int load_from_flash(struct unm_adapter_s *adapter); 720 int pinit_from_rom(unm_adapter *adapter, int verbose); 721 int rom_fast_read(struct unm_adapter_s *adapter, int addr, int *valp); 722 723 /* unm_nic_isr.c */ 724 void unm_nic_handle_phy_intr(unm_adapter *adapter); 725 726 /* niu.c */ 727 native_t unm_niu_set_promiscuous_mode(struct unm_adapter_s *adapter, 728 unm_niu_prom_mode_t mode); 729 native_t unm_niu_xg_set_promiscuous_mode(struct unm_adapter_s *adapter, 730 unm_niu_prom_mode_t mode); 731 732 int unm_niu_xg_macaddr_set(struct unm_adapter_s *adapter, 733 unm_ethernet_macaddr_t addr); 734 native_t unm_niu_disable_xg_port(struct unm_adapter_s *adapter); 735 736 long unm_niu_gbe_init_port(long port); 737 native_t unm_niu_enable_gbe_port(struct unm_adapter_s *adapter, 738 unm_niu_gbe_ifmode_t mode); 739 native_t unm_niu_disable_gbe_port(struct unm_adapter_s *adapter); 740 741 int unm_niu_macaddr_get(struct unm_adapter_s *adapter, unsigned char *addr); 742 int unm_niu_macaddr_set(struct unm_adapter_s *adapter, 743 unm_ethernet_macaddr_t addr); 744 745 int unm_niu_xg_set_tx_flow_ctl(struct unm_adapter_s *adapter, int enable); 746 int unm_niu_gbe_set_rx_flow_ctl(struct unm_adapter_s *adapter, int enable); 747 int unm_niu_gbe_set_tx_flow_ctl(struct unm_adapter_s *adapter, int enable); 748 long unm_niu_gbe_disable_phy_interrupts(struct unm_adapter_s *); 749 long unm_niu_gbe_phy_read(struct unm_adapter_s *, 750 long reg, unm_crbword_t *readval); 751 752 /* unm_nic_ctx.c */ 753 int netxen_create_rxtx(struct unm_adapter_s *adapter); 754 void netxen_destroy_rxtx(struct unm_adapter_s *adapter); 755 int nx_fw_cmd_set_mtu(struct unm_adapter_s *adapter, int mtu); 756 757 /* unm_nic_main.c */ 758 int receive_peg_ready(struct unm_adapter_s *adapter); 759 void unm_nic_update_cmd_producer(struct unm_adapter_s *adapter, 760 uint32_t crb_producer); 761 void unm_desc_dma_sync(ddi_dma_handle_t handle, uint_t start, uint_t count, 762 uint_t range, uint_t unit_size, uint_t direction); 763 int unm_pci_alloc_consistent(unm_adapter *, int, caddr_t *, 764 ddi_dma_cookie_t *, ddi_dma_handle_t *, ddi_acc_handle_t *); 765 void unm_pci_free_consistent(ddi_dma_handle_t *, ddi_acc_handle_t *); 766 767 /* unm_ndd.c */ 768 int unm_nd_init(unm_adapter *adapter); 769 enum ioc_reply unm_nd_ioctl(unm_adapter *adapter, queue_t *wq, 770 mblk_t *mp, struct iocblk *iocp); 771 void unm_nd_cleanup(unm_adapter *adapter); 772 773 /* unm_gem.c */ 774 void unm_destroy_intr(unm_adapter *adapter); 775 void unm_free_dummy_dma(unm_adapter *adapter); 776 777 /* 778 * (Internal) return values from ioctl subroutines 779 */ 780 enum ioc_reply { 781 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 782 IOC_DONE, /* OK, reply sent */ 783 IOC_ACK, /* OK, just send ACK */ 784 IOC_REPLY, /* OK, just send reply */ 785 IOC_RESTART_ACK, /* OK, restart & ACK */ 786 IOC_RESTART_REPLY /* OK, restart & reply */ 787 }; 788 789 /* 790 * Shorthand for the NDD parameters 791 */ 792 #define param_adv_autoneg nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val 793 #define param_adv_pause nd_params[PARAM_ADV_PAUSE_CAP].ndp_val 794 #define param_adv_asym_pause nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val 795 #define param_adv_10000fdx nd_params[PARAM_ADV_10000FDX_CAP].ndp_val 796 #define param_adv_1000fdx nd_params[PARAM_ADV_1000FDX_CAP].ndp_val 797 #define param_adv_1000hdx nd_params[PARAM_ADV_1000HDX_CAP].ndp_val 798 #define param_adv_100fdx nd_params[PARAM_ADV_100FDX_CAP].ndp_val 799 #define param_adv_100hdx nd_params[PARAM_ADV_100HDX_CAP].ndp_val 800 #define param_adv_10fdx nd_params[PARAM_ADV_10FDX_CAP].ndp_val 801 #define param_adv_10hdx nd_params[PARAM_ADV_10HDX_CAP].ndp_val 802 #define param_link_up nd_params[PARAM_LINK_STATUS].ndp_val 803 #define param_link_speed nd_params[PARAM_LINK_SPEED].ndp_val 804 #define param_link_duplex nd_params[PARAM_LINK_DUPLEX].ndp_val 805 #define param_loop_mode nd_params[PARAM_LOOP_MODE].ndp_val 806 807 /* 808 * Property lookups 809 */ 810 #define UNM_PROP_EXISTS(d, n) \ 811 ddi_prop_exists(DDI_DEV_T_ANY, (d), DDI_PROP_DONTPASS, (n)) 812 #define UNM_PROP_GET_INT(d, n) \ 813 ddi_prop_get_int(DDI_DEV_T_ANY, (d), DDI_PROP_DONTPASS, (n), -1) 814 815 /* 816 * Bit flags in the 'debug' word ... 817 */ 818 #define UNM_DBG_TRACE 0x00000002 /* general flow tracing */ 819 #define UNM_DBG_NDD 0x20000000 /* NDD operations */ 820 821 #define MBPS_10 10 822 #define MBPS_100 100 823 #define MBPS_1000 1000 824 825 #ifdef __cplusplus 826 } 827 #endif 828 829 #endif /* !_UNM_NIC_ */ 830