xref: /titanic_51/usr/src/uts/common/io/e1000g/e1000g_sw.h (revision c8e261054d98729a8718903716b9b8a512d8b693)
1 /*
2  * This file is provided under a CDDLv1 license.  When using or
3  * redistributing this file, you may do so under this license.
4  * In redistributing this file this license must be included
5  * and no other modification of this header file is permitted.
6  *
7  * CDDL LICENSE SUMMARY
8  *
9  * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved.
10  *
11  * The contents of this file are subject to the terms of Version
12  * 1.0 of the Common Development and Distribution License (the "License").
13  *
14  * You should have received a copy of the License with this software.
15  * You can obtain a copy of the License at
16  *	http://www.opensolaris.org/os/licensing.
17  * See the License for the specific language governing permissions
18  * and limitations under the License.
19  */
20 
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms of the CDDLv1.
24  */
25 
26 #ifndef _E1000G_SW_H
27 #define	_E1000G_SW_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34 
35 /*
36  * **********************************************************************
37  * Module Name:								*
38  *   e1000g_sw.h							*
39  *									*
40  * Abstract:								*
41  *   This header file contains Software-related data structures		*
42  *   definitions.							*
43  *									*
44  * **********************************************************************
45  */
46 
47 #include <sys/types.h>
48 #include <sys/conf.h>
49 #include <sys/debug.h>
50 #include <sys/stropts.h>
51 #include <sys/stream.h>
52 #include <sys/strsun.h>
53 #include <sys/strlog.h>
54 #include <sys/kmem.h>
55 #include <sys/stat.h>
56 #include <sys/kstat.h>
57 #include <sys/modctl.h>
58 #include <sys/errno.h>
59 #include <sys/mac.h>
60 #include <sys/mac_ether.h>
61 #include <sys/vlan.h>
62 #include <sys/ddi.h>
63 #include <sys/sunddi.h>
64 #include <sys/pci.h>
65 #include <sys/sdt.h>
66 #include <sys/ethernet.h>
67 #include <sys/pattr.h>
68 #include <sys/strsubr.h>
69 #include <sys/netlb.h>
70 #include <inet/common.h>
71 #include <inet/ip.h>
72 #include <inet/mi.h>
73 #include <inet/nd.h>
74 #include <sys/ddifm.h>
75 #include <sys/fm/protocol.h>
76 #include <sys/fm/util.h>
77 #include <sys/fm/io/ddi.h>
78 #include "e1000_api.h"
79 
80 
81 #define	JUMBO_FRAG_LENGTH		4096
82 
83 #define	LAST_RAR_ENTRY			(E1000_RAR_ENTRIES - 1)
84 #define	MAX_NUM_UNICAST_ADDRESSES	E1000_RAR_ENTRIES
85 #define	MAX_NUM_MULTICAST_ADDRESSES	256
86 
87 #define	MAX_TX_DESC_PER_PACKET		16
88 
89 /*
90  * constants used in setting flow control thresholds
91  */
92 #define	E1000_PBA_MASK		0xffff
93 #define	E1000_PBA_SHIFT		10
94 #define	E1000_FC_HIGH_DIFF	0x1638 /* High: 5688 bytes below Rx FIFO size */
95 #define	E1000_FC_LOW_DIFF	0x1640 /* Low: 5696 bytes below Rx FIFO size */
96 #define	E1000_FC_PAUSE_TIME	0x0680 /* 858 usec */
97 
98 #define	MAX_NUM_TX_DESCRIPTOR		4096
99 #define	MAX_NUM_RX_DESCRIPTOR		4096
100 #define	MAX_NUM_RX_FREELIST		4096
101 #define	MAX_NUM_TX_FREELIST		4096
102 #define	MAX_RX_LIMIT_ON_INTR		4096
103 #define	MAX_RX_INTR_DELAY		65535
104 #define	MAX_RX_INTR_ABS_DELAY		65535
105 #define	MAX_TX_INTR_DELAY		65535
106 #define	MAX_TX_INTR_ABS_DELAY		65535
107 #define	MAX_INTR_THROTTLING		65535
108 #define	MAX_RX_BCOPY_THRESHOLD		E1000_RX_BUFFER_SIZE_2K
109 #define	MAX_TX_BCOPY_THRESHOLD		E1000_TX_BUFFER_SIZE_2K
110 
111 #define	MIN_NUM_TX_DESCRIPTOR		80
112 #define	MIN_NUM_RX_DESCRIPTOR		80
113 #define	MIN_NUM_RX_FREELIST		64
114 #define	MIN_NUM_TX_FREELIST		80
115 #define	MIN_RX_LIMIT_ON_INTR		16
116 #define	MIN_RX_INTR_DELAY		0
117 #define	MIN_RX_INTR_ABS_DELAY		0
118 #define	MIN_TX_INTR_DELAY		0
119 #define	MIN_TX_INTR_ABS_DELAY		0
120 #define	MIN_INTR_THROTTLING		0
121 #define	MIN_RX_BCOPY_THRESHOLD		0
122 #define	MIN_TX_BCOPY_THRESHOLD		MINIMUM_ETHERNET_PACKET_SIZE
123 
124 #define	DEFAULT_NUM_RX_DESCRIPTOR	2048
125 #define	DEFAULT_NUM_TX_DESCRIPTOR	2048
126 #define	DEFAULT_NUM_RX_FREELIST		4096
127 #define	DEFAULT_NUM_TX_FREELIST		2048
128 #define	DEFAULT_RX_LIMIT_ON_INTR	256
129 #define	DEFAULT_RX_INTR_DELAY		0
130 #define	DEFAULT_RX_INTR_ABS_DELAY	0
131 #define	DEFAULT_TX_INTR_DELAY		300
132 #define	DEFAULT_TX_INTR_ABS_DELAY	0
133 #define	DEFAULT_INTR_THROTTLING		0x225
134 #define	DEFAULT_RX_BCOPY_THRESHOLD	0
135 #define	DEFAULT_TX_BCOPY_THRESHOLD	512
136 
137 #define	DEFAULT_TX_RECYCLE_LOW_WATER	64
138 #define	DEFAULT_TX_RECYCLE_NUM		128
139 #define	DEFAULT_TX_INTR_ENABLE		1
140 #define	DEFAULT_FLOW_CONTROL		3
141 #define	DEFAULT_MASTER_LATENCY_TIMER	0	/* BIOS should decide */
142 						/* which is normally 0x040 */
143 #define	DEFAULT_TBI_COMPAT_ENABLE	1	/* Enable SBP workaround */
144 #define	DEFAULT_MSI_ENABLE		1	/* MSI Enable */
145 
146 #define	TX_DRAIN_TIME		(200)	/* # milliseconds xmit drain */
147 
148 /*
149  * The size of the receive/transmite buffers
150  */
151 #define	E1000_RX_BUFFER_SIZE_2K		(2048)
152 #define	E1000_RX_BUFFER_SIZE_4K		(4096)
153 #define	E1000_RX_BUFFER_SIZE_8K		(8192)
154 #define	E1000_RX_BUFFER_SIZE_16K	(16384)
155 
156 #define	E1000_TX_BUFFER_SIZE_2K		(2048)
157 #define	E1000_TX_BUFFER_SIZE_4K		(4096)
158 #define	E1000_TX_BUFFER_SIZE_8K		(8192)
159 #define	E1000_TX_BUFFER_SIZE_16K	(16384)
160 
161 #define	FORCE_BCOPY_EXCEED_FRAGS	0x1
162 #define	FORCE_BCOPY_UNDER_SIZE		0x2
163 
164 #define	E1000G_RX_SW_FREE		0x0
165 #define	E1000G_RX_SW_SENDUP		0x1
166 #define	E1000G_RX_SW_STOP		0x2
167 #define	E1000G_RX_SW_DETACH		0x3
168 
169 /*
170  * definitions for smartspeed workaround
171  */
172 #define	  E1000_SMARTSPEED_MAX		30	/* 30 watchdog iterations */
173 						/* or 30 seconds */
174 #define	  E1000_SMARTSPEED_DOWNSHIFT	6	/* 6 watchdog iterations */
175 						/* or 6 seconds */
176 
177 /*
178  * Definitions for module_info.
179  */
180 #define	 WSNAME			"e1000g"	/* module name */
181 
182 /*
183  * Defined for IP header alignment. We also need to preserve space for
184  * VLAN tag (4 bytes)
185  */
186 #define	E1000G_IPALIGNROOM		6
187 #define	E1000G_IPALIGNPRESERVEROOM	64
188 
189 #define	E1000G_IMS_TX_INTR	(E1000_IMS_TXDW | E1000_IMS_TXQE)
190 #define	E1000G_ICR_TX_INTR	(E1000_ICR_TXDW | E1000_ICR_TXQE)
191 
192 /*
193  * bit flags for 'attach_progress' which is a member variable in struct e1000g
194  */
195 #define	ATTACH_PROGRESS_PCI_CONFIG	0x0001	/* PCI config setup */
196 #define	ATTACH_PROGRESS_REGS_MAP	0x0002	/* Registers mapped */
197 #define	ATTACH_PROGRESS_SETUP		0x0004	/* Setup driver parameters */
198 #define	ATTACH_PROGRESS_ADD_INTR	0x0008	/* Interrupt added */
199 #define	ATTACH_PROGRESS_LOCKS		0x0010	/* Locks initialized */
200 #define	ATTACH_PROGRESS_SOFT_INTR	0x0020	/* Soft interrupt added */
201 #define	ATTACH_PROGRESS_KSTATS		0x0040	/* Kstats created */
202 #define	ATTACH_PROGRESS_ALLOC		0x0080	/* DMA resources allocated */
203 #define	ATTACH_PROGRESS_INIT		0x0100	/* Driver initialization */
204 #define	ATTACH_PROGRESS_NDD		0x0200	/* NDD initialized */
205 #define	ATTACH_PROGRESS_MAC		0x0400	/* MAC registered */
206 #define	ATTACH_PROGRESS_ENABLE_INTR	0x0800	/* DDI interrupts enabled */
207 #define	ATTACH_PROGRESS_FMINIT		0x1000	/* FMA initiated */
208 
209 /*
210  * Speed and Duplex Settings
211  */
212 #define	GDIAG_10_HALF		1
213 #define	GDIAG_10_FULL		2
214 #define	GDIAG_100_HALF		3
215 #define	GDIAG_100_FULL		4
216 #define	GDIAG_1000_FULL		6
217 #define	GDIAG_ANY		7
218 
219 /*
220  * Coexist Workaround RP: 07/04/03
221  * 82544 Workaround : Co-existence
222  */
223 #define	MAX_TX_BUF_SIZE		(8 * 1024)
224 
225 #define	ROUNDOFF		0x1000
226 
227 /*
228  * Defines for Jumbo Frame
229  */
230 #define	FRAME_SIZE_UPTO_2K	2048
231 #define	FRAME_SIZE_UPTO_4K	4096
232 #define	FRAME_SIZE_UPTO_8K	8192
233 #define	FRAME_SIZE_UPTO_16K	16384
234 #define	FRAME_SIZE_UPTO_9K	9234
235 
236 /* The sizes (in bytes) of a ethernet packet */
237 #define	MAXIMUM_ETHERNET_FRAME_SIZE	1518 /* With FCS */
238 #define	MINIMUM_ETHERNET_FRAME_SIZE	64   /* With FCS */
239 #define	ETHERNET_FCS_SIZE		4
240 #define	MAXIMUM_ETHERNET_PACKET_SIZE	\
241 	(MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
242 #define	MINIMUM_ETHERNET_PACKET_SIZE	\
243 	(MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
244 #define	CRC_LENGTH			ETHERNET_FCS_SIZE
245 
246 /* Defines for Tx stall check */
247 #define	E1000G_STALL_WATCHDOG_COUNT	8
248 
249 #define	MAX_TX_LINK_DOWN_TIMEOUT	8
250 
251 /* Defines for DVMA */
252 #ifdef __sparc
253 #define	E1000G_DEFAULT_DVMA_PAGE_NUM	2
254 #endif
255 
256 /*
257  * Loopback definitions
258  */
259 #define	E1000G_LB_NONE			0
260 #define	E1000G_LB_EXTERNAL_1000		1
261 #define	E1000G_LB_EXTERNAL_100		2
262 #define	E1000G_LB_EXTERNAL_10		3
263 #define	E1000G_LB_INTERNAL_PHY		4
264 
265 /*
266  * Private dip list definitions
267  */
268 #define	E1000G_PRIV_DEVI_ATTACH	0x0
269 #define	E1000G_PRIV_DEVI_DETACH	0x1
270 
271 /*
272  * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL.
273  */
274 #define	QUEUE_INIT_LIST(_LH)	\
275 	(_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0
276 
277 /*
278  * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty.
279  */
280 #define	IS_QUEUE_EMPTY(_LH)	\
281 	((_LH)->Flink == (PSINGLE_LIST_LINK)0)
282 
283 /*
284  * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does
285  * not remove the head from the queue.
286  */
287 #define	QUEUE_GET_HEAD(_LH)	((PSINGLE_LIST_LINK)((_LH)->Flink))
288 
289 /*
290  * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue.
291  */
292 #define	QUEUE_REMOVE_HEAD(_LH)	\
293 { \
294 	PSINGLE_LIST_LINK ListElem; \
295 	if (ListElem = (_LH)->Flink) \
296 	{ \
297 		if (!((_LH)->Flink = ListElem->Flink)) \
298 			(_LH)->Blink = (PSINGLE_LIST_LINK) 0; \
299 	} \
300 }
301 
302 /*
303  * QUEUE_POP_HEAD -- Macro which  will pop the head off of a queue (list),
304  *	and return it (this differs from QUEUE_REMOVE_HEAD only in
305  *	the 1st line).
306  */
307 #define	QUEUE_POP_HEAD(_LH)	\
308 	(PSINGLE_LIST_LINK)(_LH)->Flink; \
309 	{ \
310 		PSINGLE_LIST_LINK ListElem; \
311 		ListElem = (_LH)->Flink; \
312 		if (ListElem) \
313 		{ \
314 			(_LH)->Flink = ListElem->Flink; \
315 			if (!(_LH)->Flink) \
316 				(_LH)->Blink = (PSINGLE_LIST_LINK)0; \
317 		} \
318 	}
319 
320 /*
321  * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not
322  *	remove the tail from the queue.
323  */
324 #define	QUEUE_GET_TAIL(_LH)	((PSINGLE_LIST_LINK)((_LH)->Blink))
325 
326 /*
327  * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue
328  */
329 #define	QUEUE_PUSH_TAIL(_LH, _E)	\
330 	if ((_LH)->Blink) \
331 	{ \
332 		((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \
333 			(PSINGLE_LIST_LINK)(_E); \
334 		(_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \
335 	} else { \
336 		(_LH)->Flink = \
337 			(_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \
338 	} \
339 	(_E)->Flink = (PSINGLE_LIST_LINK)0;
340 
341 /*
342  * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue.
343  */
344 #define	QUEUE_PUSH_HEAD(_LH, _E)	\
345 	if (!((_E)->Flink = (_LH)->Flink)) \
346 	{ \
347 		(_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \
348 	} \
349 	(_LH)->Flink = (PSINGLE_LIST_LINK)(_E);
350 
351 /*
352  * QUEUE_GET_NEXT -- Macro which returns the next element linked to the
353  *	current element.
354  */
355 #define	QUEUE_GET_NEXT(_LH, _E)		\
356 	(PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \
357 	(0) : ((_E)->Flink))
358 
359 /*
360  * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue
361  */
362 #define	QUEUE_APPEND(_LH1, _LH2)	\
363 	if ((_LH2)->Flink) { \
364 		if ((_LH1)->Flink) { \
365 			((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \
366 				((PSINGLE_LIST_LINK)(_LH2)->Flink); \
367 		} else { \
368 			(_LH1)->Flink = \
369 				((PSINGLE_LIST_LINK)(_LH2)->Flink); \
370 		} \
371 		(_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \
372 	}
373 
374 /*
375  * Property lookups
376  */
377 #define	E1000G_PROP_EXISTS(d, n)	ddi_prop_exists(DDI_DEV_T_ANY, (d), \
378 						DDI_PROP_DONTPASS, (n))
379 #define	E1000G_PROP_GET_INT(d, n)	ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
380 						DDI_PROP_DONTPASS, (n), -1)
381 
382 /*
383  * Shorthand for the NDD parameters
384  */
385 #define	param_adv_autoneg	nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val
386 #define	param_adv_pause		nd_params[PARAM_ADV_PAUSE_CAP].ndp_val
387 #define	param_adv_asym_pause	nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val
388 #define	param_adv_1000fdx	nd_params[PARAM_ADV_1000FDX_CAP].ndp_val
389 #define	param_adv_1000hdx	nd_params[PARAM_ADV_1000HDX_CAP].ndp_val
390 #define	param_adv_100fdx	nd_params[PARAM_ADV_100FDX_CAP].ndp_val
391 #define	param_adv_100hdx	nd_params[PARAM_ADV_100HDX_CAP].ndp_val
392 #define	param_adv_10fdx		nd_params[PARAM_ADV_10FDX_CAP].ndp_val
393 #define	param_adv_10hdx		nd_params[PARAM_ADV_10HDX_CAP].ndp_val
394 #define	param_force_speed_duplex nd_params[PARAM_FORCE_SPEED_DUPLEX].ndp_val
395 
396 #ifdef E1000G_DEBUG
397 /*
398  * E1000G-specific ioctls ...
399  */
400 #define	E1000G_IOC		((((((('E' << 4) + '1') << 4) \
401 				+ 'K') << 4) + 'G') << 4)
402 
403 /*
404  * These diagnostic IOCTLS are enabled only in DEBUG drivers
405  */
406 #define	E1000G_IOC_REG_PEEK	(E1000G_IOC | 1)
407 #define	E1000G_IOC_REG_POKE	(E1000G_IOC | 2)
408 #define	E1000G_IOC_CHIP_RESET	(E1000G_IOC | 3)
409 
410 #define	E1000G_PP_SPACE_REG	0	/* PCI memory space	*/
411 #define	E1000G_PP_SPACE_E1000G	1	/* driver's soft state	*/
412 
413 typedef struct {
414 	uint64_t pp_acc_size;	/* It's 1, 2, 4 or 8	*/
415 	uint64_t pp_acc_space;	/* See #defines below	*/
416 	uint64_t pp_acc_offset;	/* See regs definition	*/
417 	uint64_t pp_acc_data;	/* output for peek	*/
418 				/* input for poke	*/
419 } e1000g_peekpoke_t;
420 #endif	/* E1000G_DEBUG */
421 
422 /*
423  * (Internal) return values from ioctl subroutines
424  */
425 enum ioc_reply {
426 	IOC_INVAL = -1,		/* bad, NAK with EINVAL	*/
427 	IOC_DONE,		/* OK, reply sent	*/
428 	IOC_ACK,		/* OK, just send ACK	*/
429 	IOC_REPLY		/* OK, just send reply	*/
430 };
431 
432 /*
433  * Named Data (ND) Parameter Management Structure
434  */
435 typedef struct {
436 	uint32_t ndp_info;
437 	uint32_t ndp_min;
438 	uint32_t ndp_max;
439 	uint32_t ndp_val;
440 	struct e1000g *ndp_instance;
441 	char *ndp_name;
442 } nd_param_t;
443 
444 /*
445  * NDD parameter indexes, divided into:
446  *
447  *	read-only parameters describing the hardware's capabilities
448  *	read-write parameters controlling the advertised capabilities
449  *	read-only parameters describing the partner's capabilities
450  *	read-write parameters controlling the force speed and duplex
451  *	read-only parameters describing the link state
452  *	read-only parameters describing the driver properties
453  *	read-write parameters controlling the driver properties
454  */
455 enum {
456 	PARAM_AUTONEG_CAP,
457 	PARAM_PAUSE_CAP,
458 	PARAM_ASYM_PAUSE_CAP,
459 	PARAM_1000FDX_CAP,
460 	PARAM_1000HDX_CAP,
461 	PARAM_100T4_CAP,
462 	PARAM_100FDX_CAP,
463 	PARAM_100HDX_CAP,
464 	PARAM_10FDX_CAP,
465 	PARAM_10HDX_CAP,
466 
467 	PARAM_ADV_AUTONEG_CAP,
468 	PARAM_ADV_PAUSE_CAP,
469 	PARAM_ADV_ASYM_PAUSE_CAP,
470 	PARAM_ADV_1000FDX_CAP,
471 	PARAM_ADV_1000HDX_CAP,
472 	PARAM_ADV_100T4_CAP,
473 	PARAM_ADV_100FDX_CAP,
474 	PARAM_ADV_100HDX_CAP,
475 	PARAM_ADV_10FDX_CAP,
476 	PARAM_ADV_10HDX_CAP,
477 
478 	PARAM_LP_AUTONEG_CAP,
479 	PARAM_LP_PAUSE_CAP,
480 	PARAM_LP_ASYM_PAUSE_CAP,
481 	PARAM_LP_1000FDX_CAP,
482 	PARAM_LP_1000HDX_CAP,
483 	PARAM_LP_100T4_CAP,
484 	PARAM_LP_100FDX_CAP,
485 	PARAM_LP_100HDX_CAP,
486 	PARAM_LP_10FDX_CAP,
487 	PARAM_LP_10HDX_CAP,
488 
489 	PARAM_FORCE_SPEED_DUPLEX,
490 
491 	PARAM_LINK_STATUS,
492 	PARAM_LINK_SPEED,
493 	PARAM_LINK_DUPLEX,
494 	PARAM_LINK_AUTONEG,
495 
496 	PARAM_MAX_FRAME_SIZE,
497 	PARAM_LOOP_MODE,
498 	PARAM_INTR_TYPE,
499 
500 	PARAM_TX_BCOPY_THRESHOLD,
501 	PARAM_TX_INTR_ENABLE,
502 	PARAM_TX_TIDV,
503 	PARAM_TX_TADV,
504 	PARAM_RX_BCOPY_THRESHOLD,
505 	PARAM_RX_PKT_ON_INTR,
506 	PARAM_RX_RDTR,
507 	PARAM_RX_RADV,
508 
509 	PARAM_COUNT
510 };
511 
512 /*
513  * The entry of the private dip list
514  */
515 typedef struct _private_devi_list {
516 	dev_info_t *priv_dip;
517 	uint16_t flag;
518 	struct _private_devi_list *next;
519 } private_devi_list_t;
520 
521 /*
522  * A structure that points to the next entry in the queue.
523  */
524 typedef struct _SINGLE_LIST_LINK {
525 	struct _SINGLE_LIST_LINK *Flink;
526 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK;
527 
528 /*
529  * A "ListHead" structure that points to the head and tail of a queue
530  */
531 typedef struct _LIST_DESCRIBER {
532 	struct _SINGLE_LIST_LINK *volatile Flink;
533 	struct _SINGLE_LIST_LINK *volatile Blink;
534 } LIST_DESCRIBER, *PLIST_DESCRIBER;
535 
536 /*
537  * Address-Length pair structure that stores descriptor info
538  */
539 typedef struct _sw_desc {
540 	uint64_t address;
541 	uint32_t length;
542 } sw_desc_t, *p_sw_desc_t;
543 
544 typedef struct _desc_array {
545 	sw_desc_t descriptor[4];
546 	uint32_t elements;
547 } desc_array_t, *p_desc_array_t;
548 
549 typedef enum {
550 	USE_NONE,
551 	USE_BCOPY,
552 	USE_DVMA,
553 	USE_DMA
554 } dma_type_t;
555 
556 typedef enum {
557 	E1000G_STOP,
558 	E1000G_START,
559 	E1000G_ERROR
560 } chip_state_t;
561 
562 typedef struct _dma_buffer {
563 	caddr_t address;
564 	uint64_t dma_address;
565 	ddi_acc_handle_t acc_handle;
566 	ddi_dma_handle_t dma_handle;
567 	size_t size;
568 	size_t len;
569 } dma_buffer_t, *p_dma_buffer_t;
570 
571 /*
572  * Transmit Control Block (TCB), Ndis equiv of SWPacket This
573  * structure stores the additional information that is
574  * associated with every packet to be transmitted. It stores the
575  * message block pointer and the TBD addresses associated with
576  * the m_blk and also the link to the next tcb in the chain
577  */
578 typedef struct _tx_sw_packet {
579 	/* Link to the next tx_sw_packet in the list */
580 	SINGLE_LIST_LINK Link;
581 	mblk_t *mp;
582 	uint32_t num_desc;
583 	uint32_t num_mblk_frag;
584 	dma_type_t dma_type;
585 	dma_type_t data_transfer_type;
586 	ddi_dma_handle_t tx_dma_handle;
587 	dma_buffer_t tx_buf[1];
588 	sw_desc_t desc[MAX_TX_DESC_PER_PACKET];
589 } tx_sw_packet_t, *p_tx_sw_packet_t;
590 
591 /*
592  * This structure is similar to the rx_sw_packet structure used
593  * for Ndis. This structure stores information about the 2k
594  * aligned receive buffer into which the FX1000 DMA's frames.
595  * This structure is maintained as a linked list of many
596  * receiver buffer pointers.
597  */
598 typedef struct _rx_sw_packet {
599 	/* Link to the next rx_sw_packet_t in the list */
600 	SINGLE_LIST_LINK Link;
601 	struct _rx_sw_packet *next;
602 	uint16_t flag;
603 	mblk_t *mp;
604 	caddr_t rx_ring;
605 	dma_type_t dma_type;
606 	frtn_t free_rtn;
607 	dma_buffer_t rx_buf[1];
608 } rx_sw_packet_t, *p_rx_sw_packet_t;
609 
610 typedef struct _mblk_list {
611 	mblk_t *head;
612 	mblk_t *tail;
613 } mblk_list_t, *p_mblk_list_t;
614 
615 typedef struct _cksum_data {
616 	uint32_t ether_header_size;
617 	uint32_t cksum_flags;
618 	uint32_t cksum_start;
619 	uint32_t cksum_stuff;
620 } cksum_data_t;
621 
622 typedef union _e1000g_ether_addr {
623 	struct {
624 		uint32_t high;
625 		uint32_t low;
626 	} reg;
627 	struct {
628 		uint8_t set;
629 		uint8_t redundant;
630 		uint8_t addr[ETHERADDRL];
631 	} mac;
632 } e1000g_ether_addr_t;
633 
634 typedef struct _e1000g_stat {
635 
636 	kstat_named_t link_speed;	/* Link Speed */
637 	kstat_named_t reset_count;	/* Reset Count */
638 
639 	kstat_named_t rx_error;		/* Rx Error in Packet */
640 	kstat_named_t rx_exceed_pkt;	/* Rx Exceed Max Pkt Count */
641 	kstat_named_t rx_esballoc_fail;	/* Rx Desballoc Failure */
642 	kstat_named_t rx_allocb_fail;	/* Rx Allocb Failure */
643 
644 	kstat_named_t tx_no_desc;	/* Tx No Desc */
645 	kstat_named_t tx_no_swpkt;	/* Tx No Pkt Buffer */
646 	kstat_named_t tx_send_fail;	/* Tx SendPkt Failure */
647 	kstat_named_t tx_over_size;	/* Tx Pkt Too Long */
648 	kstat_named_t tx_reschedule;	/* Tx Reschedule */
649 
650 #ifdef E1000G_DEBUG
651 	kstat_named_t rx_none;		/* Rx No Incoming Data */
652 	kstat_named_t rx_multi_desc;	/* Rx Multi Spanned Pkt */
653 	kstat_named_t rx_no_freepkt;	/* Rx No Free Pkt */
654 	kstat_named_t rx_avail_freepkt;	/* Rx Freelist Avail Buffers */
655 
656 	kstat_named_t tx_under_size;	/* Tx Packet Under Size */
657 	kstat_named_t tx_empty_frags;	/* Tx Empty Frags */
658 	kstat_named_t tx_exceed_frags;	/* Tx Exceed Max Frags */
659 	kstat_named_t tx_recycle;	/* Tx Recycle */
660 	kstat_named_t tx_recycle_intr;	/* Tx Recycle in Intr */
661 	kstat_named_t tx_recycle_retry;	/* Tx Recycle Retry */
662 	kstat_named_t tx_recycle_none;	/* Tx No Desc Recycled */
663 	kstat_named_t tx_copy;		/* Tx Send Copy */
664 	kstat_named_t tx_bind;		/* Tx Send Bind */
665 	kstat_named_t tx_multi_copy;	/* Tx Copy Multi Fragments */
666 	kstat_named_t tx_multi_cookie;	/* Tx Pkt Span Multi Cookies */
667 	kstat_named_t tx_lack_desc;	/* Tx Lack of Desc */
668 #endif
669 
670 	kstat_named_t Crcerrs;	/* CRC Error Count */
671 	kstat_named_t Symerrs;	/* Symbol Error Count */
672 	kstat_named_t Mpc;	/* Missed Packet Count */
673 	kstat_named_t Scc;	/* Single Collision Count */
674 	kstat_named_t Ecol;	/* Excessive Collision Count */
675 	kstat_named_t Mcc;	/* Multiple Collision Count */
676 	kstat_named_t Latecol;	/* Late Collision Count */
677 	kstat_named_t Colc;	/* Collision Count */
678 	kstat_named_t Dc;	/* Defer Count */
679 	kstat_named_t Sec;	/* Sequence Error Count */
680 	kstat_named_t Rlec;	/* Receive Length Error Count */
681 	kstat_named_t Xonrxc;	/* XON Received Count */
682 	kstat_named_t Xontxc;	/* XON Xmitted Count */
683 	kstat_named_t Xoffrxc;	/* XOFF Received Count */
684 	kstat_named_t Xofftxc;	/* Xoff Xmitted Count */
685 	kstat_named_t Fcruc;	/* Unknown Flow Conrol Packet Rcvd Count */
686 	kstat_named_t Prc64;	/* Packets Received - 64b */
687 	kstat_named_t Prc127;	/* Packets Received - 65-127b */
688 	kstat_named_t Prc255;	/* Packets Received - 127-255b */
689 	kstat_named_t Prc511;	/* Packets Received - 256-511b */
690 	kstat_named_t Prc1023;	/* Packets Received - 511-1023b */
691 	kstat_named_t Prc1522;	/* Packets Received - 1024-1522b */
692 	kstat_named_t Gprc;	/* Good Packets Received Count */
693 	kstat_named_t Bprc;	/* Broadcasts Pkts Received Count */
694 	kstat_named_t Mprc;	/* Multicast Pkts Received Count */
695 	kstat_named_t Gptc;	/* Good Packets Xmitted Count */
696 	kstat_named_t Gorl;	/* Good Octets Recvd Lo Count */
697 	kstat_named_t Gorh;	/* Good Octets Recvd Hi Count */
698 	kstat_named_t Gotl;	/* Good Octets Xmitd Lo Count */
699 	kstat_named_t Goth;	/* Good Octets Xmitd Hi Count */
700 	kstat_named_t Rnbc;	/* Receive No Buffers Count */
701 	kstat_named_t Ruc;	/* Receive Undersize Count */
702 	kstat_named_t Rfc;	/* Receive Frag Count */
703 	kstat_named_t Roc;	/* Receive Oversize Count */
704 	kstat_named_t Rjc;	/* Receive Jabber Count */
705 	kstat_named_t Torl;	/* Total Octets Recvd Lo Count */
706 	kstat_named_t Torh;	/* Total Octets Recvd Hi Count */
707 	kstat_named_t Totl;	/* Total Octets Xmted Lo Count */
708 	kstat_named_t Toth;	/* Total Octets Xmted Hi Count */
709 	kstat_named_t Tpr;	/* Total Packets Received */
710 	kstat_named_t Tpt;	/* Total Packets Xmitted */
711 	kstat_named_t Ptc64;	/* Packets Xmitted (64b) */
712 	kstat_named_t Ptc127;	/* Packets Xmitted (64-127b) */
713 	kstat_named_t Ptc255;	/* Packets Xmitted (128-255b) */
714 	kstat_named_t Ptc511;	/* Packets Xmitted (255-511b) */
715 	kstat_named_t Ptc1023;	/* Packets Xmitted (512-1023b) */
716 	kstat_named_t Ptc1522;	/* Packets Xmitted (1024-1522b */
717 	kstat_named_t Mptc;	/* Multicast Packets Xmited Count */
718 	kstat_named_t Bptc;	/* Broadcast Packets Xmited Count */
719 	kstat_named_t Algnerrc;	/* Alignment Error count */
720 	kstat_named_t Tuc;	/* Transmit Underrun count */
721 	kstat_named_t Rxerrc;	/* Rx Error Count */
722 	kstat_named_t Tncrs;	/* Transmit with no CRS */
723 	kstat_named_t Cexterr;	/* Carrier Extension Error count */
724 	kstat_named_t Rutec;	/* Receive DMA too Early count */
725 	kstat_named_t Tsctc;	/* TCP seg contexts xmit count */
726 	kstat_named_t Tsctfc;	/* TCP seg contexts xmit fail count */
727 } e1000g_stat_t, *p_e1000g_stat_t;
728 
729 typedef struct _e1000g_tx_ring {
730 	kmutex_t tx_lock;
731 	kmutex_t freelist_lock;
732 	kmutex_t usedlist_lock;
733 	kmutex_t mblks_lock;
734 	/*
735 	 * Descriptor queue definitions
736 	 */
737 	ddi_dma_handle_t tbd_dma_handle;
738 	ddi_acc_handle_t tbd_acc_handle;
739 	struct e1000_tx_desc *tbd_area;
740 	uint64_t tbd_dma_addr;
741 	struct e1000_tx_desc *tbd_first;
742 	struct e1000_tx_desc *tbd_last;
743 	struct e1000_tx_desc *tbd_oldest;
744 	struct e1000_tx_desc *tbd_next;
745 	uint32_t tbd_avail;
746 	/*
747 	 * Software packet structures definitions
748 	 */
749 	p_tx_sw_packet_t packet_area;
750 	LIST_DESCRIBER used_list;
751 	LIST_DESCRIBER free_list;
752 	/*
753 	 * TCP/UDP checksum offload
754 	 */
755 	cksum_data_t cksum_data;
756 	/*
757 	 * Timer definitions for 82547
758 	 */
759 	timeout_id_t timer_id_82547;
760 	boolean_t timer_enable_82547;
761 	/*
762 	 * reschedule when tx resource is available
763 	 */
764 	boolean_t resched_needed;
765 	uint32_t recycle_low_water;
766 	uint32_t recycle_num;
767 	uint32_t frags_limit;
768 	uint32_t stall_watchdog;
769 	uint32_t recycle_fail;
770 	mblk_list_t mblks;
771 	/*
772 	 * Statistics
773 	 */
774 	uint32_t stat_no_swpkt;
775 	uint32_t stat_no_desc;
776 	uint32_t stat_send_fail;
777 	uint32_t stat_reschedule;
778 	uint32_t stat_over_size;
779 #ifdef E1000G_DEBUG
780 	uint32_t stat_under_size;
781 	uint32_t stat_exceed_frags;
782 	uint32_t stat_empty_frags;
783 	uint32_t stat_recycle;
784 	uint32_t stat_recycle_intr;
785 	uint32_t stat_recycle_retry;
786 	uint32_t stat_recycle_none;
787 	uint32_t stat_copy;
788 	uint32_t stat_bind;
789 	uint32_t stat_multi_copy;
790 	uint32_t stat_multi_cookie;
791 	uint32_t stat_lack_desc;
792 #endif
793 	/*
794 	 * Pointer to the adapter
795 	 */
796 	struct e1000g *adapter;
797 } e1000g_tx_ring_t, *pe1000g_tx_ring_t;
798 
799 typedef struct _e1000g_rx_ring {
800 	kmutex_t rx_lock;
801 	kmutex_t freelist_lock;
802 	/*
803 	 * Descriptor queue definitions
804 	 */
805 	ddi_dma_handle_t rbd_dma_handle;
806 	ddi_acc_handle_t rbd_acc_handle;
807 	struct e1000_rx_desc *rbd_area;
808 	uint64_t rbd_dma_addr;
809 	struct e1000_rx_desc *rbd_first;
810 	struct e1000_rx_desc *rbd_last;
811 	struct e1000_rx_desc *rbd_next;
812 	/*
813 	 * Software packet structures definitions
814 	 */
815 	p_rx_sw_packet_t packet_area;
816 	LIST_DESCRIBER recv_list;
817 	LIST_DESCRIBER free_list;
818 
819 	p_rx_sw_packet_t pending_list;
820 	uint32_t pending_count;
821 	uint32_t avail_freepkt;
822 	uint32_t rx_mblk_len;
823 	mblk_t *rx_mblk;
824 	mblk_t *rx_mblk_tail;
825 	/*
826 	 * Statistics
827 	 */
828 	uint32_t stat_error;
829 	uint32_t stat_esballoc_fail;
830 	uint32_t stat_allocb_fail;
831 	uint32_t stat_exceed_pkt;
832 #ifdef E1000G_DEBUG
833 	uint32_t stat_none;
834 	uint32_t stat_multi_desc;
835 	uint32_t stat_no_freepkt;
836 #endif
837 	/*
838 	 * Pointer to the adapter
839 	 */
840 	struct e1000g *adapter;
841 } e1000g_rx_ring_t, *pe1000g_rx_ring_t;
842 
843 typedef struct e1000g {
844 	int instance;
845 	dev_info_t *dip;
846 	dev_info_t *priv_dip;
847 	mac_handle_t mh;
848 	mac_resource_handle_t mrh;
849 	struct e1000_hw shared;
850 	struct e1000g_osdep osdep;
851 
852 	chip_state_t chip_state;
853 	boolean_t e1000g_promisc;
854 	boolean_t strip_crc;
855 	boolean_t rx_buffer_setup;
856 	link_state_t link_state;
857 	uint32_t link_speed;
858 	uint32_t link_duplex;
859 	uint32_t master_latency_timer;
860 	uint32_t smartspeed;	/* smartspeed w/a counter */
861 	uint32_t init_count;
862 	uint32_t reset_count;
863 	uint32_t attach_progress;	/* attach tracking */
864 	uint32_t loopback_mode;
865 
866 	uint32_t tx_desc_num;
867 	uint32_t tx_freelist_num;
868 	uint32_t rx_desc_num;
869 	uint32_t rx_freelist_num;
870 	uint32_t tx_buffer_size;
871 	uint32_t rx_buffer_size;
872 
873 	uint32_t tx_link_down_timeout;
874 	uint32_t tx_bcopy_thresh;
875 	uint32_t rx_limit_onintr;
876 	uint32_t rx_bcopy_thresh;
877 #ifndef NO_82542_SUPPORT
878 	uint32_t rx_buf_align;
879 #endif
880 
881 	boolean_t intr_adaptive;
882 	boolean_t tx_intr_enable;
883 	uint32_t tx_intr_delay;
884 	uint32_t tx_intr_abs_delay;
885 	uint32_t rx_intr_delay;
886 	uint32_t rx_intr_abs_delay;
887 	uint32_t intr_throttling_rate;
888 
889 	boolean_t watchdog_timer_enabled;
890 	boolean_t watchdog_timer_started;
891 	timeout_id_t watchdog_tid;
892 	boolean_t link_complete;
893 	timeout_id_t link_tid;
894 
895 	e1000g_rx_ring_t rx_ring[1];
896 	e1000g_tx_ring_t tx_ring[1];
897 
898 	/*
899 	 * The watchdog_lock must be held when updateing the
900 	 * timeout fields in struct e1000g, that is,
901 	 * watchdog_tid, watchdog_timer_started.
902 	 */
903 	kmutex_t watchdog_lock;
904 	/*
905 	 * The link_lock protects the link fields in struct e1000g,
906 	 * such as link_state, link_speed, link_duplex, link_complete, and
907 	 * link_tid.
908 	 */
909 	kmutex_t link_lock;
910 	/*
911 	 * The chip_lock assures that the Rx/Tx process must be
912 	 * stopped while other functions change the hardware
913 	 * configuration of e1000g card, such as e1000g_reset(),
914 	 * e1000g_reset_hw() etc are executed.
915 	 */
916 	krwlock_t chip_lock;
917 
918 	boolean_t unicst_init;
919 	uint32_t unicst_avail;
920 	uint32_t unicst_total;
921 	e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
922 
923 	uint32_t mcast_count;
924 	struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
925 
926 #ifdef __sparc
927 	ulong_t sys_page_sz;
928 	uint_t dvma_page_num;
929 #endif
930 
931 	boolean_t msi_enabled;
932 	int intr_type;
933 	int intr_cnt;
934 	int intr_cap;
935 	size_t intr_size;
936 	uint_t intr_pri;
937 	ddi_intr_handle_t *htable;
938 
939 	int tx_softint_pri;
940 	ddi_softint_handle_t tx_softint_handle;
941 
942 	kstat_t *e1000g_ksp;
943 
944 	/*
945 	 * NDD parameters
946 	 */
947 	caddr_t nd_data;
948 	nd_param_t nd_params[PARAM_COUNT];
949 
950 	uint16_t phy_ctrl;		/* contents of PHY_CTRL */
951 	uint16_t phy_status;		/* contents of PHY_STATUS */
952 	uint16_t phy_an_adv;		/* contents of PHY_AUTONEG_ADV */
953 	uint16_t phy_an_exp;		/* contents of PHY_AUTONEG_EXP */
954 	uint16_t phy_ext_status;	/* contents of PHY_EXT_STATUS */
955 	uint16_t phy_1000t_ctrl;	/* contents of PHY_1000T_CTRL */
956 	uint16_t phy_1000t_status;	/* contents of PHY_1000T_STATUS */
957 	uint16_t phy_lp_able;		/* contents of PHY_LP_ABILITY */
958 
959 	/*
960 	 * FMA capabilities
961 	 */
962 	int fm_capabilities;
963 } e1000g_t;
964 
965 
966 /*
967  * Function prototypes
968  */
969 int e1000g_alloc_dma_resources(struct e1000g *Adapter);
970 void e1000g_release_dma_resources(struct e1000g *Adapter);
971 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet);
972 void e1000g_tx_setup(struct e1000g *Adapter);
973 void e1000g_rx_setup(struct e1000g *Adapter);
974 void e1000g_setup_multicast(struct e1000g *Adapter);
975 boolean_t e1000g_reset(struct e1000g *Adapter);
976 
977 int e1000g_recycle(e1000g_tx_ring_t *tx_ring);
978 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet);
979 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring);
980 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2);
981 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp);
982 mblk_t *e1000g_receive(struct e1000g *Adapter);
983 void e1000g_rxfree_func(p_rx_sw_packet_t packet);
984 
985 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val);
986 int e1000g_init_stats(struct e1000g *Adapter);
987 void e1000_tbi_adjust_stats(struct e1000g *Adapter,
988     uint32_t frame_len, uint8_t *mac_addr);
989 enum ioc_reply e1000g_nd_ioctl(struct e1000g *Adapter,
990     queue_t *wq, mblk_t *mp, struct iocblk *iocp);
991 void e1000g_nd_cleanup(struct e1000g *Adapter);
992 int e1000g_nd_init(struct e1000g *Adapter);
993 
994 void e1000g_clear_interrupt(struct e1000g *Adapter);
995 void e1000g_mask_interrupt(struct e1000g *Adapter);
996 void e1000g_clear_all_interrupts(struct e1000g *Adapter);
997 void e1000g_clear_tx_interrupt(struct e1000g *Adapter);
998 void e1000g_mask_tx_interrupt(struct e1000g *Adapter);
999 void phy_spd_state(struct e1000_hw *hw, boolean_t enable);
1000 void e1000_enable_pciex_master(struct e1000_hw *hw);
1001 void e1000g_get_driver_control(struct e1000_hw *hw);
1002 int e1000g_check_acc_handle(ddi_acc_handle_t handle);
1003 int e1000g_check_dma_handle(ddi_dma_handle_t handle);
1004 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail);
1005 void e1000g_set_fma_flags(struct e1000g *Adapter, int acc_flag, int dma_flag);
1006 
1007 #pragma inline(e1000_rar_set)
1008 
1009 /*
1010  * Global variables
1011  */
1012 extern boolean_t e1000g_force_detach;
1013 extern uint32_t e1000g_mblks_pending;
1014 extern krwlock_t e1000g_rx_detach_lock;
1015 extern private_devi_list_t *e1000g_private_devi_list;
1016 
1017 #ifdef __cplusplus
1018 }
1019 #endif
1020 
1021 #endif	/* _E1000G_SW_H */
1022