xref: /titanic_51/usr/src/uts/common/io/e1000api/e1000_82571.h (revision ce0d9371c4da921f289a8bc7fd846d3bf1b8cca7)
1 /******************************************************************************
2 
3   Copyright (c) 2001-2014, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
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10       this list of conditions and the following disclaimer.
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14       documentation and/or other materials provided with the distribution.
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17       contributors may be used to endorse or promote products derived from
18       this software without specific prior written permission.
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20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #ifndef _E1000_82571_H_
36 #define _E1000_82571_H_
37 
38 #define ID_LED_RESERVED_F746	0xF746
39 #define ID_LED_DEFAULT_82573	((ID_LED_DEF1_DEF2 << 12) | \
40 				 (ID_LED_OFF1_ON2  <<  8) | \
41 				 (ID_LED_DEF1_DEF2 <<  4) | \
42 				 (ID_LED_DEF1_DEF2))
43 
44 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX	0x08000000
45 #define AN_RETRY_COUNT		5 /* Autoneg Retry Count value */
46 
47 /* Intr Throttling - RW */
48 #define E1000_EITR_82574(_n)	(0x000E8 + (0x4 * (_n)))
49 
50 #define E1000_EIAC_82574	0x000DC /* Ext. Interrupt Auto Clear - RW */
51 #define E1000_EIAC_MASK_82574	0x01F00000
52 
53 #define E1000_IVAR_INT_ALLOC_VALID	0x8
54 
55 /* Manageability Operation Mode mask */
56 #define E1000_NVM_INIT_CTRL2_MNGM	0x6000
57 
58 #define E1000_BASE1000T_STATUS		10
59 #define E1000_IDLE_ERROR_COUNT_MASK	0xFF
60 #define E1000_RECEIVE_ERROR_COUNTER	21
61 #define E1000_RECEIVE_ERROR_MAX		0xFFFF
62 bool e1000_check_phy_82574(struct e1000_hw *hw);
63 bool e1000_get_laa_state_82571(struct e1000_hw *hw);
64 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state);
65 
66 #endif
67