xref: /titanic_51/usr/src/uts/common/io/bge/bge_chip2.c (revision dd51520e127b452179a2ce4ea3bd8dee949f9afe)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24  */
25 
26 #include "bge_impl.h"
27 
28 #define	PIO_ADDR(bgep, offset)	((void *)((caddr_t)(bgep)->io_regs+(offset)))
29 
30 /*
31  * Future features ... ?
32  */
33 #define	BGE_CFG_IO8	1	/* 8/16-bit cfg space BIS/BIC	*/
34 #define	BGE_IND_IO32	1	/* indirect access code		*/
35 #define	BGE_SEE_IO32	1	/* SEEPROM access code		*/
36 #define	BGE_FLASH_IO32	1	/* FLASH access code		*/
37 
38 /*
39  * BGE MSI tunable:
40  *
41  * By default MSI is enabled on all supported platforms but it is disabled
42  * for some Broadcom chips due to known MSI hardware issues. Currently MSI
43  * is enabled only for 5714C A2 and 5715C A2 broadcom chips.
44  */
45 boolean_t bge_enable_msi = B_TRUE;
46 
47 /*
48  * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver
49  */
50 boolean_t bge_relaxed_ordering = B_TRUE;
51 
52 /*
53  * Property names
54  */
55 static char knownids_propname[] = "bge-known-subsystems";
56 
57 /*
58  * Patchable globals:
59  *
60  *	bge_autorecover
61  *		Enables/disables automatic recovery after fault detection
62  *
63  *	bge_mlcr_default
64  *		Value to program into the MLCR; controls the chip's GPIO pins
65  *
66  *	bge_dma_{rd,wr}prio
67  *		Relative priorities of DMA reads & DMA writes respectively.
68  *		These may each be patched to any value 0-3.  Equal values
69  *		will give "fair" (round-robin) arbitration for PCI access.
70  *		Unequal values will give one or the other function priority.
71  *
72  *	bge_dma_rwctrl
73  *		Value to put in the Read/Write DMA control register.  See
74  *	        the Broadcom PRM for things you can fiddle with in this
75  *		register ...
76  *
77  *	bge_{tx,rx}_{count,ticks}_{norm,intr}
78  *		Send/receive interrupt coalescing parameters.  Counts are
79  *		#s of descriptors, ticks are in microseconds.  *norm* values
80  *		apply between status updates/interrupts; the *intr* values
81  *		refer to the 'during-interrupt' versions - see the PRM.
82  *
83  *		NOTE: these values have been determined by measurement. They
84  *		differ significantly from the values recommended in the PRM.
85  */
86 static uint32_t bge_autorecover = 1;
87 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714;
88 
89 static uint32_t bge_dma_rdprio = 1;
90 static uint32_t bge_dma_wrprio = 0;
91 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT;
92 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721;
93 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714;
94 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715;
95 
96 uint32_t bge_rx_ticks_norm = 128;
97 uint32_t bge_tx_ticks_norm = 2048;		/* 8 for FJ2+ !?!?	*/
98 uint32_t bge_rx_count_norm = 8;
99 uint32_t bge_tx_count_norm = 128;
100 
101 static uint32_t bge_rx_ticks_intr = 128;
102 static uint32_t bge_tx_ticks_intr = 0;		/* 8 for FJ2+ !?!?	*/
103 static uint32_t bge_rx_count_intr = 2;
104 static uint32_t bge_tx_count_intr = 0;
105 
106 /*
107  * Memory pool configuration parameters.
108  *
109  * These are generally specific to each member of the chip family, since
110  * each one may have a different memory size/configuration.
111  *
112  * Setting the mbuf pool length for a specific type of chip to 0 inhibits
113  * the driver from programming the various registers; instead they are left
114  * at their hardware defaults.  This is the preferred option for later chips
115  * (5705+), whereas the older chips *required* these registers to be set,
116  * since the h/w default was 0 ;-(
117  */
118 static uint32_t bge_mbuf_pool_base	= MBUF_POOL_BASE_DEFAULT;
119 static uint32_t bge_mbuf_pool_base_5704	= MBUF_POOL_BASE_5704;
120 static uint32_t bge_mbuf_pool_base_5705	= MBUF_POOL_BASE_5705;
121 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721;
122 static uint32_t bge_mbuf_pool_len	= MBUF_POOL_LENGTH_DEFAULT;
123 static uint32_t bge_mbuf_pool_len_5704	= MBUF_POOL_LENGTH_5704;
124 static uint32_t bge_mbuf_pool_len_5705	= 0;	/* use h/w default	*/
125 static uint32_t bge_mbuf_pool_len_5721	= 0;
126 
127 /*
128  * Various high and low water marks, thresholds, etc ...
129  *
130  * Note: these are taken from revision 7 of the PRM, and some are different
131  * from both the values in earlier PRMs *and* those determined experimentally
132  * and used in earlier versions of this driver ...
133  */
134 static uint32_t bge_mbuf_hi_water	= MBUF_HIWAT_DEFAULT;
135 static uint32_t bge_mbuf_lo_water_rmac	= MAC_RX_MBUF_LOWAT_DEFAULT;
136 static uint32_t bge_mbuf_lo_water_rdma	= RDMA_MBUF_LOWAT_DEFAULT;
137 
138 static uint32_t bge_dmad_lo_water	= DMAD_POOL_LOWAT_DEFAULT;
139 static uint32_t bge_dmad_hi_water	= DMAD_POOL_HIWAT_DEFAULT;
140 static uint32_t bge_lowat_recv_frames	= LOWAT_MAX_RECV_FRAMES_DEFAULT;
141 
142 static uint32_t bge_replenish_std	= STD_RCV_BD_REPLENISH_DEFAULT;
143 static uint32_t bge_replenish_mini	= MINI_RCV_BD_REPLENISH_DEFAULT;
144 static uint32_t bge_replenish_jumbo	= JUMBO_RCV_BD_REPLENISH_DEFAULT;
145 
146 static uint32_t	bge_watchdog_count	= 1 << 16;
147 static uint16_t bge_dma_miss_limit	= 20;
148 
149 static uint32_t bge_stop_start_on_sync	= 0;
150 
151 /*
152  * bge_intr_max_loop controls the maximum loop number within bge_intr.
153  * When loading NIC with heavy network traffic, it is useful.
154  * Increasing this value could have positive effect to throughput,
155  * but it might also increase ticks of a bge ISR stick on CPU, which might
156  * lead to bad UI interactive experience. So tune this with caution.
157  */
158 static int bge_intr_max_loop = 1;
159 
160 /*
161  * ========== Low-level chip & ring buffer manipulation ==========
162  */
163 
164 #define	BGE_DBG		BGE_DBG_REGS	/* debug flag for this code	*/
165 
166 
167 /*
168  * Config space read-modify-write routines
169  */
170 
171 #if	BGE_CFG_IO8
172 
173 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits);
174 #pragma	inline(bge_cfg_clr16)
175 
176 static void
177 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits)
178 {
179 	uint16_t regval;
180 
181 	BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)",
182 	    (void *)bgep, regno, bits));
183 
184 	regval = pci_config_get16(bgep->cfg_handle, regno);
185 
186 	BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
187 	    (void *)bgep, regno, bits, regval, regval & ~bits));
188 
189 	regval &= ~bits;
190 	pci_config_put16(bgep->cfg_handle, regno, regval);
191 }
192 
193 #endif	/* BGE_CFG_IO8 */
194 
195 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
196 #pragma	inline(bge_cfg_clr32)
197 
198 static void
199 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
200 {
201 	uint32_t regval;
202 
203 	BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)",
204 	    (void *)bgep, regno, bits));
205 
206 	regval = pci_config_get32(bgep->cfg_handle, regno);
207 
208 	BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
209 	    (void *)bgep, regno, bits, regval, regval & ~bits));
210 
211 	regval &= ~bits;
212 	pci_config_put32(bgep->cfg_handle, regno, regval);
213 }
214 
215 #if	BGE_IND_IO32
216 
217 /*
218  * Indirect access to registers & RISC scratchpads, using config space
219  * accesses only.
220  *
221  * This isn't currently used, but someday we might want to use it for
222  * restoring the Subsystem Device/Vendor registers (which aren't directly
223  * writable in Config Space), or for downloading firmware into the RISCs
224  *
225  * In any case there are endian issues to be resolved before this code is
226  * enabled; the bizarre way that bytes get twisted by this chip AND by
227  * the PCI bridge in SPARC systems mean that we shouldn't enable it until
228  * it's been thoroughly tested for all access sizes on all supported
229  * architectures (SPARC *and* x86!).
230  */
231 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno);
232 #pragma	inline(bge_ind_get32)
233 
234 uint32_t
235 bge_ind_get32(bge_t *bgep, bge_regno_t regno)
236 {
237 	uint32_t val;
238 
239 	BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno));
240 
241 #ifdef __sparc
242 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
243 		regno = LE_32(regno);
244 #endif
245 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
246 	val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR);
247 
248 	BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x",
249 	    (void *)bgep, regno, val));
250 
251 	val = LE_32(val);
252 
253 	return (val);
254 }
255 
256 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val);
257 #pragma	inline(bge_ind_put32)
258 
259 void
260 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val)
261 {
262 	BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)",
263 	    (void *)bgep, regno, val));
264 
265 	val = LE_32(val);
266 #ifdef __sparc
267 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
268 		regno = LE_32(regno);
269 #endif
270 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
271 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val);
272 }
273 
274 #endif	/* BGE_IND_IO32 */
275 
276 #if	BGE_DEBUGGING
277 
278 static void bge_pci_check(bge_t *bgep);
279 #pragma	no_inline(bge_pci_check)
280 
281 static void
282 bge_pci_check(bge_t *bgep)
283 {
284 	uint16_t pcistatus;
285 
286 	pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT);
287 	if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0)
288 		BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x",
289 		    (void *)bgep, pcistatus));
290 }
291 
292 #endif	/* BGE_DEBUGGING */
293 
294 /*
295  * Perform first-stage chip (re-)initialisation, using only config-space
296  * accesses:
297  *
298  * + Read the vendor/device/revision/subsystem/cache-line-size registers,
299  *   returning the data in the structure pointed to by <idp>.
300  * + Configure the target-mode endianness (swap) options.
301  * + Disable interrupts and enable Memory Space accesses.
302  * + Enable or disable Bus Mastering according to the <enable_dma> flag.
303  *
304  * This sequence is adapted from Broadcom document 570X-PG102-R,
305  * page 102, steps 1-3, 6-8 and 11-13.  The omitted parts of the sequence
306  * are 4 and 5 (Reset Core and wait) which are handled elsewhere.
307  *
308  * This function MUST be called before any non-config-space accesses
309  * are made; on this first call <enable_dma> is B_FALSE, and it
310  * effectively performs steps 3-1(!) of the initialisation sequence
311  * (the rest are not required but should be harmless).
312  *
313  * It MUST also be called after a chip reset, as this disables
314  * Memory Space cycles!  In this case, <enable_dma> is B_TRUE, and
315  * it is effectively performing steps 6-8.
316  */
317 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma);
318 #pragma	no_inline(bge_chip_cfg_init)
319 
320 void
321 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
322 {
323 	ddi_acc_handle_t handle;
324 	uint16_t command;
325 	uint32_t mhcr;
326 	uint16_t value16;
327 	int i;
328 
329 	BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)",
330 	    (void *)bgep, (void *)cidp, enable_dma));
331 
332 	/*
333 	 * Step 3: save PCI cache line size and subsystem vendor ID
334 	 *
335 	 * Read all the config-space registers that characterise the
336 	 * chip, specifically vendor/device/revision/subsystem vendor
337 	 * and subsystem device id.  We expect (but don't check) that
338 	 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704)
339 	 *
340 	 * Also save all bus-transaction related registers (cache-line
341 	 * size, bus-grant/latency parameters, etc).  Some of these are
342 	 * cleared by reset, so we'll have to restore them later.  This
343 	 * comes from the Broadcom document 570X-PG102-R ...
344 	 *
345 	 * Note: Broadcom document 570X-PG102-R seems to be in error
346 	 * here w.r.t. the offsets of the Subsystem Vendor ID and
347 	 * Subsystem (Device) ID registers, which are the opposite way
348 	 * round according to the PCI standard.  For good measure, we
349 	 * save/restore both anyway.
350 	 */
351 	handle = bgep->cfg_handle;
352 
353 	/*
354 	 * For some chipsets (e.g., BCM5718), if MHCR_ENABLE_ENDIAN_BYTE_SWAP
355 	 * has been set in PCI_CONF_COMM already, we need to write the
356 	 * byte-swapped value to it. So we just write zero first for simplicity.
357 	 */
358 	cidp->device = pci_config_get16(handle, PCI_CONF_DEVID);
359 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
360 		pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
361 	mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR);
362 	cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK;
363 	cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);
364 	cidp->command = pci_config_get16(handle, PCI_CONF_COMM);
365 
366 	cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID);
367 	cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID);
368 	cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID);
369 	cidp->revision = pci_config_get8(handle, PCI_CONF_REVID);
370 	cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ);
371 	cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER);
372 
373 	BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s",
374 	    cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X",
375 	    cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow",
376 	    cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide",
377 	    cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low"));
378 	BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x",
379 	    cidp->vendor, cidp->device, cidp->revision));
380 	BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x",
381 	    cidp->subven, cidp->subdev, cidp->asic_rev));
382 	BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x",
383 	    cidp->clsize, cidp->latency, cidp->command));
384 
385 	/*
386 	 * Step 2 (also step 6): disable and clear interrupts.
387 	 * Steps 11-13: configure PIO endianness options, and enable
388 	 * indirect register access.  We'll also select any other
389 	 * options controlled by the MHCR (e.g. tagged status, mask
390 	 * interrupt mode) at this stage ...
391 	 *
392 	 * Note: internally, the chip is 64-bit and BIG-endian, but
393 	 * since it talks to the host over a (LITTLE-endian) PCI bus,
394 	 * it normally swaps bytes around at the PCI interface.
395 	 * However, the PCI host bridge on SPARC systems normally
396 	 * swaps the byte lanes around too, since SPARCs are also
397 	 * BIG-endian.  So it turns out that on SPARC, the right
398 	 * option is to tell the chip to swap (and the host bridge
399 	 * will swap back again), whereas on x86 we ask the chip
400 	 * NOT to swap, so the natural little-endianness of the
401 	 * PCI bus is assumed.  Then the only thing that doesn't
402 	 * automatically work right is access to an 8-byte register
403 	 * by a little-endian host; but we don't want to set the
404 	 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte
405 	 * accesses don't go where expected ;-(  So we live with
406 	 * that, and perform word-swaps in software in the few cases
407 	 * where a chip register is defined as an 8-byte value --
408 	 * see the code below for details ...
409 	 *
410 	 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't
411 	 * very clear in the register description in the PRM, but
412 	 * Broadcom document 570X-PG104-R page 248 explains a little
413 	 * more (under "Broadcom Mask Mode").  The bit changes the way
414 	 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE
415 	 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same
416 	 * way as the 5700 did, which isn't very convenient.  Setting
417 	 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT
418 	 * bit do just what its name says -- MASK the PCI #INTA output
419 	 * (i.e. deassert the signal at the pin) leaving all internal
420 	 * state unchanged.  This is much more convenient for our
421 	 * interrupt handler, so we set MASK_INTERRUPT_MODE here.
422 	 *
423 	 * Note: the inconvenient semantics of the interrupt mailbox
424 	 * (nonzero disables and acknowledges/clears the interrupt,
425 	 * zero enables AND CLEARS it) would make race conditions
426 	 * likely in the interrupt handler:
427 	 *
428 	 * (1)	acknowledge & disable interrupts
429 	 * (2)	while (more to do)
430 	 * 		process packets
431 	 * (3)	enable interrupts -- also clears pending
432 	 *
433 	 * If the chip received more packets and internally generated
434 	 * an interrupt between the check at (2) and the mbox write
435 	 * at (3), this interrupt would be lost :-(
436 	 *
437 	 * The best way to avoid this is to use TAGGED STATUS mode,
438 	 * where the chip includes a unique tag in each status block
439 	 * update, and the host, when re-enabling interrupts, passes
440 	 * the last tag it saw back to the chip; then the chip can
441 	 * see whether the host is truly up to date, and regenerate
442 	 * its interrupt if not.
443 	 */
444 	mhcr =	MHCR_ENABLE_INDIRECT_ACCESS |
445 	    MHCR_ENABLE_TAGGED_STATUS_MODE |
446 	    MHCR_MASK_INTERRUPT_MODE |
447 	    MHCR_CLEAR_INTERRUPT_INTA;
448 
449 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
450 		mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
451 
452 #ifdef	_BIG_ENDIAN
453 	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
454 #endif	/* _BIG_ENDIAN */
455 
456 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
457 		pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
458 	pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr);
459 
460 #ifdef BGE_IPMI_ASF
461 	bgep->asf_wordswapped = B_FALSE;
462 #endif
463 	/*
464 	 * Step 1 (also step 7): Enable PCI Memory Space accesses
465 	 *			 Disable Memory Write/Invalidate
466 	 *			 Enable or disable Bus Mastering
467 	 *
468 	 * Note that all other bits are taken from the original value saved
469 	 * the first time through here, rather than from the current register
470 	 * value, 'cos that will have been cleared by a soft RESET since.
471 	 * In this way we preserve the OBP/nexus-parent's preferred settings
472 	 * of the parity-error and system-error enable bits across multiple
473 	 * chip RESETs.
474 	 */
475 	command = bgep->chipid.command | PCI_COMM_MAE;
476 	command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL);
477 	if (enable_dma)
478 		command |= PCI_COMM_ME;
479 	/*
480 	 * on BCM5714 revision A0, false parity error gets generated
481 	 * due to a logic bug. Provide a workaround by disabling parity
482 	 * error.
483 	 */
484 	if (((cidp->device == DEVICE_ID_5714C) ||
485 	    (cidp->device == DEVICE_ID_5714S)) &&
486 	    (cidp->revision == REVISION_ID_5714_A0)) {
487 		command &= ~PCI_COMM_PARITY_DETECT;
488 	}
489 	pci_config_put16(handle, PCI_CONF_COMM, command);
490 
491 	/*
492 	 * On some PCI-E device, there were instances when
493 	 * the device was still link training.
494 	 */
495 	if (bgep->chipid.pci_type == BGE_PCI_E) {
496 		i = 0;
497 		value16 = pci_config_get16(handle, PCI_CONF_COMM);
498 		while ((value16 != command) && (i < 100)) {
499 			drv_usecwait(200);
500 			value16 = pci_config_get16(handle, PCI_CONF_COMM);
501 			++i;
502 		}
503 	}
504 
505 	/*
506 	 * Clear any remaining error status bits
507 	 */
508 	pci_config_put16(handle, PCI_CONF_STAT, ~0);
509 
510 	/*
511 	 * Do following if and only if the device is NOT BCM5714C OR
512 	 * BCM5715C
513 	 */
514 	if (!((cidp->device == DEVICE_ID_5714C) ||
515 	    (cidp->device == DEVICE_ID_5715C))) {
516 		/*
517 		 * Make sure these indirect-access registers are sane
518 		 * rather than random after power-up or reset
519 		 */
520 		pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0);
521 		pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0);
522 	}
523 	/*
524 	 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering
525 	 */
526 	bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED);
527 
528 	if (cidp->pci_type == BGE_PCI_E) {
529 		if (DEVICE_5723_SERIES_CHIPSETS(bgep)) {
530 			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723,
531 			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
532 		} else
533 			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL,
534 			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
535 	}
536 }
537 
538 #ifdef __amd64
539 /*
540  * Distinguish CPU types
541  *
542  * These use to  distinguish AMD64 or Intel EM64T of CPU running mode.
543  * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine
544  * for PCI-Express based network interface card. This is the work-around
545  * for those nics.
546  */
547 static boolean_t bge_get_em64t_type(void);
548 #pragma	inline(bge_get_em64t_type)
549 
550 static boolean_t
551 bge_get_em64t_type(void)
552 {
553 
554 	return (x86_vendor == X86_VENDOR_Intel);
555 }
556 #endif
557 
558 /*
559  * Operating register get/set access routines
560  */
561 
562 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno);
563 #pragma	inline(bge_reg_get32)
564 
565 uint32_t
566 bge_reg_get32(bge_t *bgep, bge_regno_t regno)
567 {
568 	BGE_TRACE(("bge_reg_get32($%p, 0x%lx)",
569 	    (void *)bgep, regno));
570 
571 	return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)));
572 }
573 
574 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data);
575 #pragma	inline(bge_reg_put32)
576 
577 void
578 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data)
579 {
580 	BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)",
581 	    (void *)bgep, regno, data));
582 
583 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data);
584 	BGE_PCICHK(bgep);
585 }
586 
587 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
588 #pragma	inline(bge_reg_set32)
589 
590 void
591 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
592 {
593 	uint32_t regval;
594 
595 	BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)",
596 	    (void *)bgep, regno, bits));
597 
598 	regval = bge_reg_get32(bgep, regno);
599 	regval |= bits;
600 	bge_reg_put32(bgep, regno, regval);
601 }
602 
603 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
604 #pragma	inline(bge_reg_clr32)
605 
606 void
607 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
608 {
609 	uint32_t regval;
610 
611 	BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)",
612 	    (void *)bgep, regno, bits));
613 
614 	regval = bge_reg_get32(bgep, regno);
615 	regval &= ~bits;
616 	bge_reg_put32(bgep, regno, regval);
617 }
618 
619 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno);
620 #pragma	inline(bge_reg_get64)
621 
622 static uint64_t
623 bge_reg_get64(bge_t *bgep, bge_regno_t regno)
624 {
625 	uint64_t regval;
626 
627 #ifdef	__amd64
628 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
629 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
630 		regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
631 		regval <<= 32;
632 		regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
633 	} else {
634 		regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
635 	}
636 #elif defined(__sparc)
637 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
638 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
639 		regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
640 		regval <<= 32;
641 		regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
642 	} else {
643 		regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
644 	}
645 #else
646 	regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
647 #endif
648 
649 #ifdef	_LITTLE_ENDIAN
650 	regval = (regval >> 32) | (regval << 32);
651 #endif	/* _LITTLE_ENDIAN */
652 
653 	BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx",
654 	    (void *)bgep, regno, regval));
655 
656 	return (regval);
657 }
658 
659 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data);
660 #pragma	inline(bge_reg_put64)
661 
662 static void
663 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data)
664 {
665 	BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)",
666 	    (void *)bgep, regno, data));
667 
668 #ifdef	_LITTLE_ENDIAN
669 	data = ((data >> 32) | (data << 32));
670 #endif	/* _LITTLE_ENDIAN */
671 
672 #ifdef	__amd64
673 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
674 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
675 		ddi_put32(bgep->io_handle,
676 		    PIO_ADDR(bgep, regno), (uint32_t)data);
677 		BGE_PCICHK(bgep);
678 		ddi_put32(bgep->io_handle,
679 		    PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32));
680 
681 	} else {
682 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
683 	}
684 #elif defined(__sparc)
685 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
686 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
687 		ddi_put32(bgep->io_handle,
688 		    PIO_ADDR(bgep, regno + 4), (uint32_t)data);
689 		BGE_PCICHK(bgep);
690 		ddi_put32(bgep->io_handle,
691 		    PIO_ADDR(bgep, regno), (uint32_t)(data >> 32));
692 	} else {
693 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
694 	}
695 #else
696 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
697 #endif
698 
699 	BGE_PCICHK(bgep);
700 }
701 
702 /*
703  * The DDI doesn't provide get/put functions for 128 bit data
704  * so we put RCBs out as two 64-bit chunks instead.
705  */
706 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
707 #pragma	inline(bge_reg_putrcb)
708 
709 static void
710 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
711 {
712 	uint64_t *p;
713 
714 	BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
715 	    (void *)bgep, addr, rcbp->host_ring_addr,
716 	    rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
717 
718 	ASSERT((addr % sizeof (*rcbp)) == 0);
719 
720 	p = (void *)rcbp;
721 	bge_reg_put64(bgep, addr, *p++);
722 	bge_reg_put64(bgep, addr+8, *p);
723 }
724 
725 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data);
726 #pragma	inline(bge_mbx_put)
727 
728 void
729 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data)
730 {
731 	if (DEVICE_5906_SERIES_CHIPSETS(bgep))
732 		regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4;
733 
734 	BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)",
735 	    (void *)bgep, regno, data));
736 
737 	/*
738 	 * Mailbox registers are nominally 64 bits on the 5701, but
739 	 * the MSW isn't used.  On the 5703, they're only 32 bits
740 	 * anyway.  So here we just write the lower(!) 32 bits -
741 	 * remembering that the chip is big-endian, even though the
742 	 * PCI bus is little-endian ...
743 	 */
744 #ifdef	_BIG_ENDIAN
745 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data);
746 #else
747 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data);
748 #endif	/* _BIG_ENDIAN */
749 	BGE_PCICHK(bgep);
750 }
751 
752 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno);
753 #pragma inline(bge_mbx_get)
754 
755 uint32_t
756 bge_mbx_get(bge_t *bgep, bge_regno_t regno)
757 {
758 	uint32_t val32;
759 
760 	if (DEVICE_5906_SERIES_CHIPSETS(bgep))
761 		regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4;
762 
763 	BGE_TRACE(("bge_mbx_get($%p, 0x%lx)",
764 	    (void *)bgep, regno));
765 
766 #ifdef	_BIG_ENDIAN
767 	val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4));
768 #else
769 	val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
770 #endif	/* _BIG_ENDIAN */
771 	BGE_PCICHK(bgep);
772 
773 	BGE_DEBUG(("bge_mbx_get($%p, 0x%lx) => 0x%08x",
774 	    (void *)bgep, regno, val32));
775 
776 	return (val32);
777 }
778 
779 
780 #if	BGE_DEBUGGING
781 
782 void bge_led_mark(bge_t *bgep);
783 #pragma	no_inline(bge_led_mark)
784 
785 void
786 bge_led_mark(bge_t *bgep)
787 {
788 	uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK |
789 	    LED_CONTROL_1000MBPS_LED |
790 	    LED_CONTROL_100MBPS_LED |
791 	    LED_CONTROL_10MBPS_LED;
792 
793 	/*
794 	 * Blink all three LINK LEDs on simultaneously, then all off,
795 	 * then restore to automatic hardware control.  This is used
796 	 * in laboratory testing to trigger a logic analyser or scope.
797 	 */
798 	bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
799 	led_ctrl ^= LED_CONTROL_OVERRIDE_LINK;
800 	bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
801 	led_ctrl = LED_CONTROL_OVERRIDE_LINK;
802 	bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
803 }
804 
805 #endif	/* BGE_DEBUGGING */
806 
807 /*
808  * NIC on-chip memory access routines
809  *
810  * Only 32K of NIC memory is visible at a time, controlled by the
811  * Memory Window Base Address Register (in PCI config space).  Once
812  * this is set, the 32K region of NIC-local memory that it refers
813  * to can be directly addressed in the upper 32K of the 64K of PCI
814  * memory space used for the device.
815  */
816 
817 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base);
818 #pragma	inline(bge_nic_setwin)
819 
820 static void
821 bge_nic_setwin(bge_t *bgep, bge_regno_t base)
822 {
823 	chip_id_t *cidp;
824 
825 	BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)",
826 	    (void *)bgep, base));
827 
828 	ASSERT((base & MWBAR_GRANULE_MASK) == 0);
829 
830 	/*
831 	 * Don't do repeated zero data writes,
832 	 * if the device is BCM5714C/15C.
833 	 */
834 	cidp = &bgep->chipid;
835 	if ((cidp->device == DEVICE_ID_5714C) ||
836 	    (cidp->device == DEVICE_ID_5715C)) {
837 		if (bgep->lastWriteZeroData && (base == (bge_regno_t)0))
838 			return;
839 		/* Adjust lastWriteZeroData */
840 		bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ?
841 		    B_TRUE : B_FALSE);
842 	}
843 #ifdef __sparc
844 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
845 		base = LE_32(base);
846 #endif
847 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base);
848 }
849 
850 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr);
851 #pragma	inline(bge_nic_get32)
852 
853 static uint32_t
854 bge_nic_get32(bge_t *bgep, bge_regno_t addr)
855 {
856 	uint32_t data;
857 
858 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
859 	if (bgep->asf_enabled && !bgep->asf_wordswapped) {
860 		/* workaround for word swap error */
861 		if (addr & 4)
862 			addr = addr - 4;
863 		else
864 			addr = addr + 4;
865 	}
866 #endif
867 
868 #ifdef __sparc
869 	data = bge_nic_read32(bgep, addr);
870 #else
871 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
872 	addr &= MWBAR_GRANULE_MASK;
873 	addr += NIC_MEM_WINDOW_OFFSET;
874 
875 	data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
876 #endif
877 
878 	BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x",
879 	    (void *)bgep, addr, data));
880 
881 	return (data);
882 }
883 
884 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data);
885 #pragma inline(bge_nic_put32)
886 
887 void
888 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data)
889 {
890 	BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)",
891 	    (void *)bgep, addr, data));
892 
893 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
894 	if (bgep->asf_enabled && !bgep->asf_wordswapped) {
895 		/* workaround for word swap error */
896 		if (addr & 4)
897 			addr = addr - 4;
898 		else
899 			addr = addr + 4;
900 	}
901 #endif
902 
903 #ifdef __sparc
904 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
905 		addr = LE_32(addr);
906 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
907 	data = LE_32(data);
908 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data);
909 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
910 #else
911 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
912 	addr &= MWBAR_GRANULE_MASK;
913 	addr += NIC_MEM_WINDOW_OFFSET;
914 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data);
915 	BGE_PCICHK(bgep);
916 #endif
917 }
918 
919 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr);
920 #pragma	inline(bge_nic_get64)
921 
922 static uint64_t
923 bge_nic_get64(bge_t *bgep, bge_regno_t addr)
924 {
925 	uint64_t data;
926 
927 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
928 	addr &= MWBAR_GRANULE_MASK;
929 	addr += NIC_MEM_WINDOW_OFFSET;
930 
931 #ifdef	__amd64
932 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
933 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
934 		data = ddi_get32(bgep->io_handle,
935 		    PIO_ADDR(bgep, addr + 4));
936 		data <<= 32;
937 		data |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
938 	} else {
939 		data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
940 	}
941 #elif defined(__sparc)
942 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
943 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
944 		data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
945 		data <<= 32;
946 		data |= ddi_get32(bgep->io_handle,
947 		    PIO_ADDR(bgep, addr + 4));
948 	} else {
949 		data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
950 	}
951 #else
952 	data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
953 #endif
954 
955 	BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx",
956 	    (void *)bgep, addr, data));
957 
958 	return (data);
959 }
960 
961 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data);
962 #pragma	inline(bge_nic_put64)
963 
964 static void
965 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data)
966 {
967 	BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)",
968 	    (void *)bgep, addr, data));
969 
970 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
971 	addr &= MWBAR_GRANULE_MASK;
972 	addr += NIC_MEM_WINDOW_OFFSET;
973 
974 #ifdef	__amd64
975 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
976 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
977 		ddi_put32(bgep->io_handle,
978 		    PIO_ADDR(bgep, addr + 4), (uint32_t)data);
979 		BGE_PCICHK(bgep);
980 		ddi_put32(bgep->io_handle,
981 		    PIO_ADDR(bgep, addr), (uint32_t)(data >> 32));
982 	} else {
983 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
984 	}
985 #elif defined(__sparc)
986 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
987 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
988 		ddi_put32(bgep->io_handle,
989 		    PIO_ADDR(bgep, addr + 4), (uint32_t)data);
990 		BGE_PCICHK(bgep);
991 		ddi_put32(bgep->io_handle,
992 		    PIO_ADDR(bgep, addr), (uint32_t)(data >> 32));
993 	} else {
994 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
995 	}
996 #else
997 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
998 #endif
999 
1000 	BGE_PCICHK(bgep);
1001 }
1002 
1003 /*
1004  * The DDI doesn't provide get/put functions for 128 bit data
1005  * so we put RCBs out as two 64-bit chunks instead.
1006  */
1007 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
1008 #pragma	inline(bge_nic_putrcb)
1009 
1010 static void
1011 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
1012 {
1013 	uint64_t *p;
1014 
1015 	BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
1016 	    (void *)bgep, addr, rcbp->host_ring_addr,
1017 	    rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
1018 
1019 	ASSERT((addr % sizeof (*rcbp)) == 0);
1020 
1021 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1022 	addr &= MWBAR_GRANULE_MASK;
1023 	addr += NIC_MEM_WINDOW_OFFSET;
1024 
1025 	p = (void *)rcbp;
1026 #ifdef	__amd64
1027 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
1028 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
1029 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
1030 		    (uint32_t)(*p));
1031 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
1032 		    (uint32_t)(*p++ >> 32));
1033 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
1034 		    (uint32_t)(*p));
1035 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
1036 		    (uint32_t)(*p >> 32));
1037 
1038 	} else {
1039 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1040 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p);
1041 	}
1042 #elif defined(__sparc)
1043 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1044 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
1045 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
1046 		    (uint32_t)(*p));
1047 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
1048 		    (uint32_t)(*p++ >> 32));
1049 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
1050 		    (uint32_t)(*p));
1051 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
1052 		    (uint32_t)(*p >> 32));
1053 	} else {
1054 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1055 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
1056 	}
1057 #else
1058 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1059 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
1060 #endif
1061 
1062 	BGE_PCICHK(bgep);
1063 }
1064 
1065 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes);
1066 #pragma	inline(bge_nic_zero)
1067 
1068 static void
1069 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes)
1070 {
1071 	BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)",
1072 	    (void *)bgep, addr, nbytes));
1073 
1074 	ASSERT((addr & ~MWBAR_GRANULE_MASK) ==
1075 	    ((addr+nbytes) & ~MWBAR_GRANULE_MASK));
1076 
1077 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1078 	addr &= MWBAR_GRANULE_MASK;
1079 	addr += NIC_MEM_WINDOW_OFFSET;
1080 
1081 	(void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr),
1082 	    nbytes, 1, DDI_DATA_SZ08_ACC);
1083 	BGE_PCICHK(bgep);
1084 }
1085 
1086 /*
1087  * MII (PHY) register get/set access routines
1088  *
1089  * These use the chip's MII auto-access method, controlled by the
1090  * MII Communication register at 0x044c, so the CPU doesn't have
1091  * to fiddle with the individual bits.
1092  */
1093 
1094 #undef	BGE_DBG
1095 #define	BGE_DBG		BGE_DBG_MII	/* debug flag for this code	*/
1096 
1097 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno,
1098 				uint16_t data, uint32_t cmd);
1099 #pragma	no_inline(bge_mii_access)
1100 
1101 static uint16_t
1102 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd)
1103 {
1104 	uint32_t timeout;
1105 	uint32_t regval1;
1106 	uint32_t regval2;
1107 
1108 	BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)",
1109 	    (void *)bgep, regno, data, cmd));
1110 
1111 	ASSERT(mutex_owned(bgep->genlock));
1112 
1113 	/*
1114 	 * Assemble the command ...
1115 	 */
1116 	cmd |= data << MI_COMMS_DATA_SHIFT;
1117 	cmd |= regno << MI_COMMS_REGISTER_SHIFT;
1118 	cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT;
1119 	cmd |= MI_COMMS_START;
1120 
1121 	/*
1122 	 * Wait for any command already in progress ...
1123 	 *
1124 	 * Note: this *shouldn't* ever find that there is a command
1125 	 * in progress, because we already hold the <genlock> mutex.
1126 	 * Nonetheless, we have sometimes seen the MI_COMMS_START
1127 	 * bit set here -- it seems that the chip can initiate MII
1128 	 * accesses internally, even with polling OFF.
1129 	 */
1130 	regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1131 	for (timeout = 100; ; ) {
1132 		if ((regval2 & MI_COMMS_START) == 0) {
1133 			bge_reg_put32(bgep, MI_COMMS_REG, cmd);
1134 			break;
1135 		}
1136 		if (--timeout == 0)
1137 			break;
1138 		drv_usecwait(10);
1139 		regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1140 	}
1141 
1142 	if (timeout == 0)
1143 		return ((uint16_t)~0u);
1144 
1145 	if (timeout != 100)
1146 		BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1147 		    "MI_COMMS_START set for %d us; 0x%x->0x%x",
1148 		    cmd, 10*(100-timeout), regval1, regval2));
1149 
1150 	regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1151 	for (timeout = 1000; ; ) {
1152 		if ((regval1 & MI_COMMS_START) == 0)
1153 			break;
1154 		if (--timeout == 0)
1155 			break;
1156 		drv_usecwait(10);
1157 		regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1158 	}
1159 
1160 	/*
1161 	 * Drop out early if the READ FAILED bit is set -- this chip
1162 	 * could be a 5703/4S, with a SerDes instead of a PHY!
1163 	 */
1164 	if (regval2 & MI_COMMS_READ_FAILED)
1165 		return ((uint16_t)~0u);
1166 
1167 	if (timeout == 0)
1168 		return ((uint16_t)~0u);
1169 
1170 	/*
1171 	 * The PRM says to wait 5us after seeing the START bit clear
1172 	 * and then re-read the register to get the final value of the
1173 	 * data field, in order to avoid a race condition where the
1174 	 * START bit is clear but the data field isn't yet valid.
1175 	 *
1176 	 * Note: we don't actually seem to be encounter this race;
1177 	 * except when the START bit is seen set again (see below),
1178 	 * the data field doesn't change during this 5us interval.
1179 	 */
1180 	drv_usecwait(5);
1181 	regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1182 
1183 	/*
1184 	 * Unfortunately, when following the PRMs instructions above,
1185 	 * we have occasionally seen the START bit set again(!) in the
1186 	 * value read after the 5us delay. This seems to be due to the
1187 	 * chip autonomously starting another MII access internally.
1188 	 * In such cases, the command/data/etc fields relate to the
1189 	 * internal command, rather than the one that we thought had
1190 	 * just finished.  So in this case, we fall back to returning
1191 	 * the data from the original read that showed START clear.
1192 	 */
1193 	if (regval2 & MI_COMMS_START) {
1194 		BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1195 		    "MI_COMMS_START set after transaction; 0x%x->0x%x",
1196 		    cmd, regval1, regval2));
1197 		regval2 = regval1;
1198 	}
1199 
1200 	if (regval2 & MI_COMMS_START)
1201 		return ((uint16_t)~0u);
1202 
1203 	if (regval2 & MI_COMMS_READ_FAILED)
1204 		return ((uint16_t)~0u);
1205 
1206 	return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT);
1207 }
1208 
1209 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno);
1210 #pragma	no_inline(bge_mii_get16)
1211 
1212 uint16_t
1213 bge_mii_get16(bge_t *bgep, bge_regno_t regno)
1214 {
1215 	BGE_TRACE(("bge_mii_get16($%p, 0x%lx)",
1216 	    (void *)bgep, regno));
1217 
1218 	ASSERT(mutex_owned(bgep->genlock));
1219 
1220 	if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
1221 	    (regno == MII_MSCONTROL)))
1222 		return (0);
1223 
1224 	return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ));
1225 }
1226 
1227 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data);
1228 #pragma	no_inline(bge_mii_put16)
1229 
1230 void
1231 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data)
1232 {
1233 	BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)",
1234 	    (void *)bgep, regno, data));
1235 
1236 	ASSERT(mutex_owned(bgep->genlock));
1237 
1238 	if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
1239 	    (regno == MII_MSCONTROL)))
1240 		return;
1241 
1242 	(void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE);
1243 }
1244 
1245 #undef	BGE_DBG
1246 #define	BGE_DBG		BGE_DBG_SEEPROM	/* debug flag for this code	*/
1247 
1248 #if	BGE_SEE_IO32 || BGE_FLASH_IO32
1249 
1250 /*
1251  * Basic SEEPROM get/set access routine
1252  *
1253  * This uses the chip's SEEPROM auto-access method, controlled by the
1254  * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU
1255  * doesn't have to fiddle with the individual bits.
1256  *
1257  * The caller should hold <genlock> and *also* have already acquired
1258  * the right to access the SEEPROM, via bge_nvmem_acquire() above.
1259  *
1260  * Return value:
1261  *	0 on success,
1262  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1263  *	EPROTO on other h/w or s/w errors.
1264  *
1265  * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output
1266  * from a (successful) SEEPROM_ACCESS_READ.
1267  */
1268 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1269 				uint32_t *dp);
1270 #pragma	no_inline(bge_seeprom_access)
1271 
1272 static int
1273 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1274 {
1275 	uint32_t tries;
1276 	uint32_t regval;
1277 
1278 	ASSERT(mutex_owned(bgep->genlock));
1279 
1280 	/*
1281 	 * On the newer chips that support both SEEPROM & Flash, we need
1282 	 * to specifically enable SEEPROM access (Flash is the default).
1283 	 * On older chips, we don't; SEEPROM is the only NVtype supported,
1284 	 * and the NVM control registers don't exist ...
1285 	 */
1286 	switch (bgep->chipid.nvtype) {
1287 	case BGE_NVTYPE_NONE:
1288 	case BGE_NVTYPE_UNKNOWN:
1289 		_NOTE(NOTREACHED)
1290 	case BGE_NVTYPE_SEEPROM:
1291 		break;
1292 
1293 	case BGE_NVTYPE_LEGACY_SEEPROM:
1294 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1295 	case BGE_NVTYPE_BUFFERED_FLASH:
1296 	default:
1297 		bge_reg_set32(bgep, NVM_CONFIG1_REG,
1298 		    NVM_CFG1_LEGACY_SEEPROM_MODE);
1299 		break;
1300 	}
1301 
1302 	/*
1303 	 * Check there's no command in progress.
1304 	 *
1305 	 * Note: this *shouldn't* ever find that there is a command
1306 	 * in progress, because we already hold the <genlock> mutex.
1307 	 * Also, to ensure we don't have a conflict with the chip's
1308 	 * internal firmware or a process accessing the same (shared)
1309 	 * SEEPROM through the other port of a 5704, we've already
1310 	 * been through the "software arbitration" protocol.
1311 	 * So this is just a final consistency check: we shouldn't
1312 	 * see EITHER the START bit (command started but not complete)
1313 	 * OR the COMPLETE bit (command completed but not cleared).
1314 	 */
1315 	regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1316 	if (regval & SEEPROM_ACCESS_START)
1317 		return (EPROTO);
1318 	if (regval & SEEPROM_ACCESS_COMPLETE)
1319 		return (EPROTO);
1320 
1321 	/*
1322 	 * Assemble the command ...
1323 	 */
1324 	cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK;
1325 	addr >>= SEEPROM_ACCESS_ADDRESS_SIZE;
1326 	addr <<= SEEPROM_ACCESS_DEVID_SHIFT;
1327 	cmd |= addr & SEEPROM_ACCESS_DEVID_MASK;
1328 	cmd |= SEEPROM_ACCESS_START;
1329 	cmd |= SEEPROM_ACCESS_COMPLETE;
1330 	cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK;
1331 
1332 	bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp);
1333 	bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd);
1334 
1335 	/*
1336 	 * By observation, a successful access takes ~20us on a 5703/4,
1337 	 * but apparently much longer (up to 1000us) on the obsolescent
1338 	 * BCM5700/BCM5701.  We want to be sure we don't get any false
1339 	 * timeouts here; but OTOH, we don't want a bogus access to lock
1340 	 * out interrupts for longer than necessary. So we'll allow up
1341 	 * to 1000us ...
1342 	 */
1343 	for (tries = 0; tries < 1000; ++tries) {
1344 		regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1345 		if (regval & SEEPROM_ACCESS_COMPLETE)
1346 			break;
1347 		drv_usecwait(1);
1348 	}
1349 
1350 	if (regval & SEEPROM_ACCESS_COMPLETE) {
1351 		/*
1352 		 * All OK; read the SEEPROM data register, then write back
1353 		 * the value read from the address register in order to
1354 		 * clear the <complete> bit and leave the SEEPROM access
1355 		 * state machine idle, ready for the next access ...
1356 		 */
1357 		BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries));
1358 		*dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG);
1359 		bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval);
1360 		return (0);
1361 	}
1362 
1363 	/*
1364 	 * Hmm ... what happened here?
1365 	 *
1366 	 * Most likely, the user addressed a non-existent SEEPROM. Or
1367 	 * maybe the SEEPROM was busy internally (e.g. processing a write)
1368 	 * and didn't respond to being addressed. Either way, it's left
1369 	 * the SEEPROM access state machine wedged. So we'll reset it
1370 	 * before we leave, so it's ready for next time ...
1371 	 */
1372 	BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries));
1373 	bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
1374 	return (ENODATA);
1375 }
1376 
1377 /*
1378  * Basic Flash get/set access routine
1379  *
1380  * These use the chip's Flash auto-access method, controlled by the
1381  * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to
1382  * fiddle with the individual bits.
1383  *
1384  * The caller should hold <genlock> and *also* have already acquired
1385  * the right to access the Flash, via bge_nvmem_acquire() above.
1386  *
1387  * Return value:
1388  *	0 on success,
1389  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1390  *	ENODEV if the NVmem device is missing or otherwise unusable
1391  *
1392  * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output
1393  * from a (successful) NVM_FLASH_CMD_RD.
1394  */
1395 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1396 				uint32_t *dp);
1397 #pragma	no_inline(bge_flash_access)
1398 
1399 static int
1400 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1401 {
1402 	uint32_t tries;
1403 	uint32_t regval;
1404 
1405 	ASSERT(mutex_owned(bgep->genlock));
1406 
1407 	/*
1408 	 * On the newer chips that support both SEEPROM & Flash, we need
1409 	 * to specifically disable SEEPROM access while accessing Flash.
1410 	 * The older chips don't support Flash, and the NVM registers don't
1411 	 * exist, so we shouldn't be here at all!
1412 	 */
1413 	switch (bgep->chipid.nvtype) {
1414 	case BGE_NVTYPE_NONE:
1415 	case BGE_NVTYPE_UNKNOWN:
1416 		_NOTE(NOTREACHED)
1417 	case BGE_NVTYPE_SEEPROM:
1418 		return (ENODEV);
1419 
1420 	case BGE_NVTYPE_LEGACY_SEEPROM:
1421 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1422 	case BGE_NVTYPE_BUFFERED_FLASH:
1423 	default:
1424 		bge_reg_clr32(bgep, NVM_CONFIG1_REG,
1425 		    NVM_CFG1_LEGACY_SEEPROM_MODE);
1426 		break;
1427 	}
1428 
1429 	/*
1430 	 * Assemble the command ...
1431 	 */
1432 	addr &= NVM_FLASH_ADDR_MASK;
1433 	cmd |= NVM_FLASH_CMD_DOIT;
1434 	cmd |= NVM_FLASH_CMD_FIRST;
1435 	cmd |= NVM_FLASH_CMD_LAST;
1436 	cmd |= NVM_FLASH_CMD_DONE;
1437 
1438 	bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp);
1439 	bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr);
1440 	bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd);
1441 
1442 	/*
1443 	 * Allow up to 1000ms ...
1444 	 */
1445 	for (tries = 0; tries < 1000; ++tries) {
1446 		regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG);
1447 		if (regval & NVM_FLASH_CMD_DONE)
1448 			break;
1449 		drv_usecwait(1);
1450 	}
1451 
1452 	if (regval & NVM_FLASH_CMD_DONE) {
1453 		/*
1454 		 * All OK; read the data from the Flash read register
1455 		 */
1456 		BGE_DEBUG(("bge_flash_access: complete after %d us", tries));
1457 		*dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG);
1458 		return (0);
1459 	}
1460 
1461 	/*
1462 	 * Hmm ... what happened here?
1463 	 *
1464 	 * Most likely, the user addressed a non-existent Flash. Or
1465 	 * maybe the Flash was busy internally (e.g. processing a write)
1466 	 * and didn't respond to being addressed. Either way, there's
1467 	 * nothing we can here ...
1468 	 */
1469 	BGE_DEBUG(("bge_flash_access: timed out after %d us", tries));
1470 	return (ENODATA);
1471 }
1472 
1473 /*
1474  * The next two functions regulate access to the NVram (if fitted).
1475  *
1476  * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash
1477  * (SPI) interface, but they can be accessed through either port. These
1478  * are managed by different instance of this driver and have no software
1479  * state in common.
1480  *
1481  * In addition (and even on a single core chip) the chip's internal
1482  * firmware can access the SEEPROM/Flash, most notably after a RESET
1483  * when it may download code to run internally.
1484  *
1485  * So we need to arbitrate between these various software agents.  For
1486  * this purpose, the chip provides the Software Arbitration Register,
1487  * which implements hardware(!) arbitration.
1488  *
1489  * This functionality didn't exist on older (5700/5701) chips, so there's
1490  * nothing we can do by way of arbitration on those; also, if there's no
1491  * SEEPROM/Flash fitted (or we couldn't determine what type), there's also
1492  * nothing to do.
1493  *
1494  * The internal firmware appears to use Request 0, which is the highest
1495  * priority.  So we'd like to use Request 2, leaving one higher and one
1496  * lower for any future developments ... but apparently this doesn't
1497  * always work.  So for now, the code uses Request 1 ;-(
1498  */
1499 
1500 #define	NVM_READ_REQ	NVM_READ_REQ1
1501 #define	NVM_RESET_REQ	NVM_RESET_REQ1
1502 #define	NVM_SET_REQ	NVM_SET_REQ1
1503 
1504 static void bge_nvmem_relinquish(bge_t *bgep);
1505 #pragma	no_inline(bge_nvmem_relinquish)
1506 
1507 static void
1508 bge_nvmem_relinquish(bge_t *bgep)
1509 {
1510 	ASSERT(mutex_owned(bgep->genlock));
1511 
1512 	switch (bgep->chipid.nvtype) {
1513 	case BGE_NVTYPE_NONE:
1514 	case BGE_NVTYPE_UNKNOWN:
1515 		_NOTE(NOTREACHED)
1516 		return;
1517 
1518 	case BGE_NVTYPE_SEEPROM:
1519 		/*
1520 		 * No arbitration performed, no release needed
1521 		 */
1522 		return;
1523 
1524 	case BGE_NVTYPE_LEGACY_SEEPROM:
1525 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1526 	case BGE_NVTYPE_BUFFERED_FLASH:
1527 	default:
1528 		break;
1529 	}
1530 
1531 	/*
1532 	 * Our own request should be present (whether or not granted) ...
1533 	 */
1534 	(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1535 
1536 	/*
1537 	 * ... this will make it go away.
1538 	 */
1539 	bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ);
1540 	(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1541 }
1542 
1543 /*
1544  * Arbitrate for access to the NVmem, if necessary
1545  *
1546  * Return value:
1547  *	0 on success
1548  *	EAGAIN if the device is in use (retryable)
1549  *	ENODEV if the NVmem device is missing or otherwise unusable
1550  */
1551 static int bge_nvmem_acquire(bge_t *bgep);
1552 #pragma	no_inline(bge_nvmem_acquire)
1553 
1554 static int
1555 bge_nvmem_acquire(bge_t *bgep)
1556 {
1557 	uint32_t regval;
1558 	uint32_t tries;
1559 
1560 	ASSERT(mutex_owned(bgep->genlock));
1561 
1562 	switch (bgep->chipid.nvtype) {
1563 	case BGE_NVTYPE_NONE:
1564 	case BGE_NVTYPE_UNKNOWN:
1565 		/*
1566 		 * Access denied: no (recognisable) device fitted
1567 		 */
1568 		return (ENODEV);
1569 
1570 	case BGE_NVTYPE_SEEPROM:
1571 		/*
1572 		 * Access granted: no arbitration needed (or possible)
1573 		 */
1574 		return (0);
1575 
1576 	case BGE_NVTYPE_LEGACY_SEEPROM:
1577 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1578 	case BGE_NVTYPE_BUFFERED_FLASH:
1579 	default:
1580 		/*
1581 		 * Access conditional: conduct arbitration protocol
1582 		 */
1583 		break;
1584 	}
1585 
1586 	/*
1587 	 * We're holding the per-port mutex <genlock>, so no-one other
1588 	 * thread can be attempting to access the NVmem through *this*
1589 	 * port. But it could be in use by the *other* port (of a 5704),
1590 	 * or by the chip's internal firmware, so we have to go through
1591 	 * the full (hardware) arbitration protocol ...
1592 	 *
1593 	 * Note that *because* we're holding <genlock>, the interrupt handler
1594 	 * won't be able to progress.  So we're only willing to spin for a
1595 	 * fairly short time.  Specifically:
1596 	 *
1597 	 *	We *must* wait long enough for the hardware to resolve all
1598 	 *	requests and determine the winner.  Fortunately, this is
1599 	 *	"almost instantaneous", even as observed by GHz CPUs.
1600 	 *
1601 	 *	A successful access by another Solaris thread (via either
1602 	 *	port) typically takes ~20us.  So waiting a bit longer than
1603 	 *	that will give a good chance of success, if the other user
1604 	 *	*is* another thread on the other port.
1605 	 *
1606 	 *	However, the internal firmware can hold on to the NVmem
1607 	 *	for *much* longer: at least 10 milliseconds just after a
1608 	 *	RESET, and maybe even longer if the NVmem actually contains
1609 	 *	code to download and run on the internal CPUs.
1610 	 *
1611 	 * So, we'll allow 50us; if that's not enough then it's up to the
1612 	 * caller to retry later (hence the choice of return code EAGAIN).
1613 	 */
1614 	regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1615 	bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ);
1616 
1617 	for (tries = 0; tries < 50; ++tries) {
1618 		regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1619 		if (regval & NVM_WON_REQ1)
1620 			break;
1621 		drv_usecwait(1);
1622 	}
1623 
1624 	if (regval & NVM_WON_REQ1) {
1625 		BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries));
1626 		return (0);
1627 	}
1628 
1629 	/*
1630 	 * Somebody else must be accessing the NVmem, so abandon our
1631 	 * attempt take control of it.  The caller can try again later ...
1632 	 */
1633 	BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries));
1634 	bge_nvmem_relinquish(bgep);
1635 	return (EAGAIN);
1636 }
1637 
1638 /*
1639  * This code assumes that the GPIO1 bit has been wired up to the NVmem
1640  * write protect line in such a way that the NVmem is protected when
1641  * GPIO1 is an input, or is an output but driven high.  Thus, to make the
1642  * NVmem writable we have to change GPIO1 to an output AND drive it low.
1643  *
1644  * Note: there's only one set of GPIO pins on a 5704, even though they
1645  * can be accessed through either port.  So the chip has to resolve what
1646  * happens if the two ports program a single pin differently ... the rule
1647  * it uses is that if the ports disagree about the *direction* of a pin,
1648  * "output" wins over "input", but if they disagree about its *value* as
1649  * an output, then the pin is TRISTATED instead!  In such a case, no-one
1650  * wins, and the external signal does whatever the external circuitry
1651  * defines as the default -- which we've assumed is the PROTECTED state.
1652  * So, we always change GPIO1 back to being an *input* whenever we're not
1653  * specifically using it to unprotect the NVmem. This allows either port
1654  * to update the NVmem, although obviously only one at a time!
1655  *
1656  * The caller should hold <genlock> and *also* have already acquired the
1657  * right to access the NVmem, via bge_nvmem_acquire() above.
1658  */
1659 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect);
1660 #pragma	inline(bge_nvmem_protect)
1661 
1662 static void
1663 bge_nvmem_protect(bge_t *bgep, boolean_t protect)
1664 {
1665 	uint32_t regval;
1666 
1667 	ASSERT(mutex_owned(bgep->genlock));
1668 
1669 	regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
1670 	if (protect) {
1671 		regval |= MLCR_MISC_PINS_OUTPUT_1;
1672 		regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1673 	} else {
1674 		regval &= ~MLCR_MISC_PINS_OUTPUT_1;
1675 		regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1676 	}
1677 	bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval);
1678 }
1679 
1680 /*
1681  * Now put it all together ...
1682  *
1683  * Try to acquire control of the NVmem; if successful, then:
1684  *	unprotect it (if we want to write to it)
1685  *	perform the requested access
1686  *	reprotect it (after a write)
1687  *	relinquish control
1688  *
1689  * Return value:
1690  *	0 on success,
1691  *	EAGAIN if the device is in use (retryable)
1692  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1693  *	ENODEV if the NVmem device is missing or otherwise unusable
1694  *	EPROTO on other h/w or s/w errors.
1695  */
1696 static int
1697 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1698 {
1699 	int err;
1700 
1701 	if ((err = bge_nvmem_acquire(bgep)) == 0) {
1702 		switch (cmd) {
1703 		case BGE_SEE_READ:
1704 			err = bge_seeprom_access(bgep,
1705 			    SEEPROM_ACCESS_READ, addr, dp);
1706 			break;
1707 
1708 		case BGE_SEE_WRITE:
1709 			bge_nvmem_protect(bgep, B_FALSE);
1710 			err = bge_seeprom_access(bgep,
1711 			    SEEPROM_ACCESS_WRITE, addr, dp);
1712 			bge_nvmem_protect(bgep, B_TRUE);
1713 			break;
1714 
1715 		case BGE_FLASH_READ:
1716 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1717 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1718 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1719 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1720 				bge_reg_set32(bgep, NVM_ACCESS_REG,
1721 				    NVM_ACCESS_ENABLE);
1722 			}
1723 			err = bge_flash_access(bgep,
1724 			    NVM_FLASH_CMD_RD, addr, dp);
1725 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1726 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1727 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1728 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1729 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
1730 				    NVM_ACCESS_ENABLE);
1731 			}
1732 			break;
1733 
1734 		case BGE_FLASH_WRITE:
1735 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1736 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1737 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1738 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1739 				bge_reg_set32(bgep, NVM_ACCESS_REG,
1740 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1741 			}
1742 			bge_nvmem_protect(bgep, B_FALSE);
1743 			err = bge_flash_access(bgep,
1744 			    NVM_FLASH_CMD_WR, addr, dp);
1745 			bge_nvmem_protect(bgep, B_TRUE);
1746 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1747 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1748 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1749 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1750 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
1751 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1752 			}
1753 
1754 			break;
1755 
1756 		default:
1757 			_NOTE(NOTREACHED)
1758 			break;
1759 		}
1760 		bge_nvmem_relinquish(bgep);
1761 	}
1762 
1763 	BGE_DEBUG(("bge_nvmem_rw32: err %d", err));
1764 	return (err);
1765 }
1766 
1767 /*
1768  * Attempt to get a MAC address from the SEEPROM or Flash, if any
1769  */
1770 static uint64_t bge_get_nvmac(bge_t *bgep);
1771 #pragma no_inline(bge_get_nvmac)
1772 
1773 static uint64_t
1774 bge_get_nvmac(bge_t *bgep)
1775 {
1776 	uint32_t mac_high;
1777 	uint32_t mac_low;
1778 	uint32_t addr;
1779 	uint32_t cmd;
1780 	uint64_t mac;
1781 
1782 	BGE_TRACE(("bge_get_nvmac($%p)",
1783 	    (void *)bgep));
1784 
1785 	switch (bgep->chipid.nvtype) {
1786 	case BGE_NVTYPE_NONE:
1787 	case BGE_NVTYPE_UNKNOWN:
1788 	default:
1789 		return (0ULL);
1790 
1791 	case BGE_NVTYPE_SEEPROM:
1792 	case BGE_NVTYPE_LEGACY_SEEPROM:
1793 		cmd = BGE_SEE_READ;
1794 		break;
1795 
1796 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1797 	case BGE_NVTYPE_BUFFERED_FLASH:
1798 		cmd = BGE_FLASH_READ;
1799 		break;
1800 	}
1801 
1802 	if (DEVICE_5906_SERIES_CHIPSETS(bgep))
1803 		addr = NVMEM_DATA_MAC_ADDRESS_5906;
1804 	else
1805 		addr = NVMEM_DATA_MAC_ADDRESS;
1806 
1807 	if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high))
1808 		return (0ULL);
1809 	addr += 4;
1810 	if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low))
1811 		return (0ULL);
1812 
1813 	/*
1814 	 * The Broadcom chip is natively BIG-endian, so that's how the
1815 	 * MAC address is represented in NVmem.  We may need to swap it
1816 	 * around on a little-endian host ...
1817 	 */
1818 #ifdef	_BIG_ENDIAN
1819 	mac = mac_high;
1820 	mac = mac << 32;
1821 	mac |= mac_low;
1822 #else
1823 	mac = BGE_BSWAP_32(mac_high);
1824 	mac = mac << 32;
1825 	mac |= BGE_BSWAP_32(mac_low);
1826 #endif	/* _BIG_ENDIAN */
1827 
1828 	return (mac);
1829 }
1830 
1831 #else	/* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1832 
1833 /*
1834  * Dummy version for when we're not supporting NVmem access
1835  */
1836 static uint64_t bge_get_nvmac(bge_t *bgep);
1837 #pragma inline(bge_get_nvmac)
1838 
1839 static uint64_t
1840 bge_get_nvmac(bge_t *bgep)
1841 {
1842 	_NOTE(ARGUNUSED(bgep))
1843 	return (0ULL);
1844 }
1845 
1846 #endif	/* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1847 
1848 /*
1849  * Determine the type of NVmem that is (or may be) attached to this chip,
1850  */
1851 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep);
1852 #pragma no_inline(bge_nvmem_id)
1853 
1854 static enum bge_nvmem_type
1855 bge_nvmem_id(bge_t *bgep)
1856 {
1857 	enum bge_nvmem_type nvtype;
1858 	uint32_t config1;
1859 
1860 	BGE_TRACE(("bge_nvmem_id($%p)",
1861 	    (void *)bgep));
1862 
1863 	switch (bgep->chipid.device) {
1864 	default:
1865 		/*
1866 		 * We shouldn't get here; it means we don't recognise
1867 		 * the chip, which means we don't know how to determine
1868 		 * what sort of NVmem (if any) it has.  So we'll say
1869 		 * NONE, to disable the NVmem access code ...
1870 		 */
1871 		nvtype = BGE_NVTYPE_NONE;
1872 		break;
1873 
1874 	case DEVICE_ID_5700:
1875 	case DEVICE_ID_5700x:
1876 	case DEVICE_ID_5701:
1877 		/*
1878 		 * These devices support *only* SEEPROMs
1879 		 */
1880 		nvtype = BGE_NVTYPE_SEEPROM;
1881 		break;
1882 
1883 	case DEVICE_ID_5702:
1884 	case DEVICE_ID_5702fe:
1885 	case DEVICE_ID_5703C:
1886 	case DEVICE_ID_5703S:
1887 	case DEVICE_ID_5704C:
1888 	case DEVICE_ID_5704S:
1889 	case DEVICE_ID_5704:
1890 	case DEVICE_ID_5705M:
1891 	case DEVICE_ID_5705C:
1892 	case DEVICE_ID_5705_2:
1893 	case DEVICE_ID_5717:
1894 	case DEVICE_ID_5718:
1895 	case DEVICE_ID_5724:
1896 	case DEVICE_ID_57780:
1897 	case DEVICE_ID_5780:
1898 	case DEVICE_ID_5782:
1899 	case DEVICE_ID_5785:
1900 	case DEVICE_ID_5787:
1901 	case DEVICE_ID_5787M:
1902 	case DEVICE_ID_5788:
1903 	case DEVICE_ID_5789:
1904 	case DEVICE_ID_5751:
1905 	case DEVICE_ID_5751M:
1906 	case DEVICE_ID_5752:
1907 	case DEVICE_ID_5752M:
1908 	case DEVICE_ID_5754:
1909 	case DEVICE_ID_5755:
1910 	case DEVICE_ID_5755M:
1911 	case DEVICE_ID_5756M:
1912 	case DEVICE_ID_5721:
1913 	case DEVICE_ID_5722:
1914 	case DEVICE_ID_5723:
1915 	case DEVICE_ID_5761:
1916 	case DEVICE_ID_5761E:
1917 	case DEVICE_ID_5764:
1918 	case DEVICE_ID_5714C:
1919 	case DEVICE_ID_5714S:
1920 	case DEVICE_ID_5715C:
1921 	case DEVICE_ID_5715S:
1922 		config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG);
1923 		if (config1 & NVM_CFG1_FLASH_MODE)
1924 			if (config1 & NVM_CFG1_BUFFERED_MODE)
1925 				nvtype = BGE_NVTYPE_BUFFERED_FLASH;
1926 			else
1927 				nvtype = BGE_NVTYPE_UNBUFFERED_FLASH;
1928 		else
1929 			nvtype = BGE_NVTYPE_LEGACY_SEEPROM;
1930 		break;
1931 	case DEVICE_ID_5906:
1932 	case DEVICE_ID_5906M:
1933 		nvtype = BGE_NVTYPE_BUFFERED_FLASH;
1934 		break;
1935 	}
1936 
1937 	return (nvtype);
1938 }
1939 
1940 #undef	BGE_DBG
1941 #define	BGE_DBG		BGE_DBG_CHIP	/* debug flag for this code	*/
1942 
1943 static void
1944 bge_init_recv_rule(bge_t *bgep)
1945 {
1946 	bge_recv_rule_t *rulep = bgep->recv_rules;
1947 	uint32_t i;
1948 
1949 	/*
1950 	 * Initialize receive rule registers.
1951 	 * Note that rules may persist across each bge_m_start/stop() call.
1952 	 */
1953 	for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) {
1954 		bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value);
1955 		bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control);
1956 	}
1957 }
1958 
1959 /*
1960  * Using the values captured by bge_chip_cfg_init(), and additional probes
1961  * as required, characterise the chip fully: determine the label by which
1962  * to refer to this chip, the correct settings for various registers, and
1963  * of course whether the device and/or subsystem are supported!
1964  */
1965 int bge_chip_id_init(bge_t *bgep);
1966 #pragma	no_inline(bge_chip_id_init)
1967 
1968 int
1969 bge_chip_id_init(bge_t *bgep)
1970 {
1971 	char buf[MAXPATHLEN];		/* any risk of stack overflow?	*/
1972 	boolean_t sys_ok;
1973 	boolean_t dev_ok;
1974 	chip_id_t *cidp;
1975 	uint32_t subid;
1976 	char *devname;
1977 	char *sysname;
1978 	int *ids;
1979 	int err;
1980 	uint_t i;
1981 
1982 	sys_ok = dev_ok = B_FALSE;
1983 	cidp = &bgep->chipid;
1984 
1985 	/*
1986 	 * Check the PCI device ID to determine the generic chip type and
1987 	 * select parameters that depend on this.
1988 	 *
1989 	 * Note: because the SPARC platforms in general don't fit the
1990 	 * SEEPROM 'behind' the chip, the PCI revision ID register reads
1991 	 * as zero - which is why we use <asic_rev> rather than <revision>
1992 	 * below ...
1993 	 *
1994 	 * Note: in general we can't distinguish between the Copper/SerDes
1995 	 * versions by ID alone, as some Copper devices (e.g. some but not
1996 	 * all 5703Cs) have the same ID as the SerDes equivalents.  So we
1997 	 * treat them the same here, and the MII code works out the media
1998 	 * type later on ...
1999 	 */
2000 	cidp->mbuf_base = bge_mbuf_pool_base;
2001 	cidp->mbuf_length = bge_mbuf_pool_len;
2002 	cidp->recv_slots = BGE_RECV_SLOTS_USED;
2003 	cidp->bge_dma_rwctrl = bge_dma_rwctrl;
2004 	cidp->pci_type = BGE_PCI_X;
2005 	cidp->statistic_type = BGE_STAT_BLK;
2006 	cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma;
2007 	cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac;
2008 	cidp->mbuf_hi_water = bge_mbuf_hi_water;
2009 	cidp->rx_ticks_norm = bge_rx_ticks_norm;
2010 	cidp->rx_count_norm = bge_rx_count_norm;
2011 	cidp->tx_ticks_norm = bge_tx_ticks_norm;
2012 	cidp->tx_count_norm = bge_tx_count_norm;
2013 	cidp->mask_pci_int = MHCR_MASK_PCI_INT_OUTPUT;
2014 
2015 	if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX)
2016 		cidp->rx_rings = BGE_RECV_RINGS_DEFAULT;
2017 	if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX)
2018 		cidp->tx_rings = BGE_SEND_RINGS_DEFAULT;
2019 
2020 	cidp->msi_enabled = B_FALSE;
2021 
2022 	switch (cidp->device) {
2023 	case DEVICE_ID_5717:
2024 	case DEVICE_ID_5718:
2025 	case DEVICE_ID_5724:
2026 		if (cidp->device == DEVICE_ID_5717)
2027 			cidp->chip_label = 5717;
2028 		else if (cidp->device == DEVICE_ID_5718)
2029 			cidp->chip_label = 5718;
2030 		else
2031 			cidp->chip_label = 5724;
2032 		cidp->msi_enabled = bge_enable_msi;
2033 #ifdef __sparc
2034 		cidp->mask_pci_int = LE_32(MHCR_MASK_PCI_INT_OUTPUT);
2035 #endif
2036 		cidp->bge_dma_rwctrl = LE_32(PDRWCR_VAR_5717);
2037 		cidp->pci_type = BGE_PCI_E;
2038 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2039 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5717;
2040 		cidp->mbuf_hi_water = MBUF_HIWAT_5717;
2041 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2042 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2043 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2044 		cidp->bge_mlcr_default = MLCR_DEFAULT_5717;
2045 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2046 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2047 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2048 		cidp->statistic_type = BGE_STAT_REG;
2049 		dev_ok = B_TRUE;
2050 		break;
2051 
2052 	case DEVICE_ID_5700:
2053 	case DEVICE_ID_5700x:
2054 		cidp->chip_label = 5700;
2055 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2056 		break;
2057 
2058 	case DEVICE_ID_5701:
2059 		cidp->chip_label = 5701;
2060 		dev_ok = B_TRUE;
2061 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2062 		break;
2063 
2064 	case DEVICE_ID_5702:
2065 	case DEVICE_ID_5702fe:
2066 		cidp->chip_label = 5702;
2067 		dev_ok = B_TRUE;
2068 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2069 		cidp->pci_type = BGE_PCI;
2070 		break;
2071 
2072 	case DEVICE_ID_5703C:
2073 	case DEVICE_ID_5703S:
2074 	case DEVICE_ID_5703:
2075 		/*
2076 		 * Revision A0 of the 5703/5793 had various errata
2077 		 * that we can't or don't work around, so it's not
2078 		 * supported, but all later versions are
2079 		 */
2080 		cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703;
2081 		if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0)
2082 			dev_ok = B_TRUE;
2083 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2084 		break;
2085 
2086 	case DEVICE_ID_5704C:
2087 	case DEVICE_ID_5704S:
2088 	case DEVICE_ID_5704:
2089 		cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704;
2090 		cidp->mbuf_base = bge_mbuf_pool_base_5704;
2091 		cidp->mbuf_length = bge_mbuf_pool_len_5704;
2092 		dev_ok = B_TRUE;
2093 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2094 		break;
2095 
2096 	case DEVICE_ID_5705C:
2097 	case DEVICE_ID_5705M:
2098 	case DEVICE_ID_5705MA3:
2099 	case DEVICE_ID_5705F:
2100 	case DEVICE_ID_5705_2:
2101 	case DEVICE_ID_5754:
2102 		if (cidp->device == DEVICE_ID_5754) {
2103 			cidp->chip_label = 5754;
2104 			cidp->pci_type = BGE_PCI_E;
2105 		} else {
2106 			cidp->chip_label = 5705;
2107 			cidp->pci_type = BGE_PCI;
2108 			cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2109 		}
2110 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2111 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2112 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2113 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2114 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2115 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2116 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2117 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2118 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2119 		cidp->statistic_type = BGE_STAT_REG;
2120 		dev_ok = B_TRUE;
2121 		break;
2122 
2123 	case DEVICE_ID_5906:
2124 	case DEVICE_ID_5906M:
2125 		cidp->chip_label = 5906;
2126 		cidp->pci_type = BGE_PCI_E;
2127 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906;
2128 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906;
2129 		cidp->mbuf_hi_water = MBUF_HIWAT_5906;
2130 		cidp->mbuf_base = bge_mbuf_pool_base;
2131 		cidp->mbuf_length = bge_mbuf_pool_len;
2132 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2133 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2134 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2135 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2136 		cidp->statistic_type = BGE_STAT_REG;
2137 		dev_ok = B_TRUE;
2138 		break;
2139 
2140 	case DEVICE_ID_5753:
2141 		cidp->chip_label = 5753;
2142 		cidp->pci_type = BGE_PCI_E;
2143 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2144 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2145 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2146 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2147 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2148 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2149 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2150 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2151 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2152 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2153 		cidp->statistic_type = BGE_STAT_REG;
2154 		dev_ok = B_TRUE;
2155 		break;
2156 
2157 	case DEVICE_ID_5755:
2158 	case DEVICE_ID_5755M:
2159 		cidp->chip_label = 5755;
2160 		cidp->pci_type = BGE_PCI_E;
2161 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2162 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2163 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2164 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2165 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2166 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2167 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2168 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2169 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2170 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2171 		if (cidp->device == DEVICE_ID_5755M)
2172 			cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2173 		cidp->statistic_type = BGE_STAT_REG;
2174 		dev_ok = B_TRUE;
2175 		break;
2176 
2177 	case DEVICE_ID_5756M:
2178 		/*
2179 		 * This is nearly identical to the 5755M.
2180 		 * (Actually reports the 5755 chip ID.)
2181 		 */
2182 		cidp->chip_label = 5756;
2183 		cidp->pci_type = BGE_PCI_E;
2184 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2185 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2186 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2187 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2188 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2189 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2190 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2191 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2192 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2193 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2194 		cidp->statistic_type = BGE_STAT_REG;
2195 		dev_ok = B_TRUE;
2196 		break;
2197 
2198 	case DEVICE_ID_5787:
2199 	case DEVICE_ID_5787M:
2200 		cidp->chip_label = 5787;
2201 		cidp->pci_type = BGE_PCI_E;
2202 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2203 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2204 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2205 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2206 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2207 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2208 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2209 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2210 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2211 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2212 		cidp->statistic_type = BGE_STAT_REG;
2213 		dev_ok = B_TRUE;
2214 		break;
2215 
2216 	case DEVICE_ID_5723:
2217 	case DEVICE_ID_5761:
2218 	case DEVICE_ID_5761E:
2219 	case DEVICE_ID_57780:
2220 		cidp->msi_enabled = bge_enable_msi;
2221 		/*
2222 		 * We don't use MSI for BCM5764 and BCM5785, as the
2223 		 * status block may fail to update when the network
2224 		 * traffic is heavy.
2225 		 */
2226 		/* FALLTHRU */
2227 	case DEVICE_ID_5785:
2228 	case DEVICE_ID_5764:
2229 		if (cidp->device == DEVICE_ID_5723)
2230 			cidp->chip_label = 5723;
2231 		else if (cidp->device == DEVICE_ID_5764)
2232 			cidp->chip_label = 5764;
2233 		else if (cidp->device == DEVICE_ID_5785)
2234 			cidp->chip_label = 5785;
2235 		else if (cidp->device == DEVICE_ID_57780)
2236 			cidp->chip_label = 57780;
2237 		else
2238 			cidp->chip_label = 5761;
2239 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2240 		cidp->pci_type = BGE_PCI_E;
2241 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2242 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2243 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2244 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2245 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2246 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2247 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2248 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2249 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2250 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2251 		cidp->statistic_type = BGE_STAT_REG;
2252 		dev_ok = B_TRUE;
2253 		break;
2254 
2255 	/* PCI-X device, identical to 5714 */
2256 	case DEVICE_ID_5780:
2257 		cidp->chip_label = 5780;
2258 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2259 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2260 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2261 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2262 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2263 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2264 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2265 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2266 		cidp->statistic_type = BGE_STAT_REG;
2267 		dev_ok = B_TRUE;
2268 		break;
2269 
2270 	case DEVICE_ID_5782:
2271 		/*
2272 		 * Apart from the label, we treat this as a 5705(?)
2273 		 */
2274 		cidp->chip_label = 5782;
2275 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2276 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2277 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2278 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2279 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2280 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2281 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2282 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2283 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2284 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2285 		cidp->statistic_type = BGE_STAT_REG;
2286 		dev_ok = B_TRUE;
2287 		break;
2288 
2289 	case DEVICE_ID_5788:
2290 		/*
2291 		 * Apart from the label, we treat this as a 5705(?)
2292 		 */
2293 		cidp->chip_label = 5788;
2294 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2295 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2296 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2297 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2298 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2299 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2300 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2301 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2302 		cidp->statistic_type = BGE_STAT_REG;
2303 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2304 		dev_ok = B_TRUE;
2305 		break;
2306 
2307 	case DEVICE_ID_5714C:
2308 		if (cidp->revision >= REVISION_ID_5714_A2)
2309 			cidp->msi_enabled = bge_enable_msi;
2310 		/* FALLTHRU */
2311 	case DEVICE_ID_5714S:
2312 		cidp->chip_label = 5714;
2313 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2314 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2315 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2316 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2317 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2318 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2319 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714;
2320 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
2321 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2322 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2323 		cidp->pci_type = BGE_PCI_E;
2324 		cidp->statistic_type = BGE_STAT_REG;
2325 		dev_ok = B_TRUE;
2326 		break;
2327 
2328 	case DEVICE_ID_5715C:
2329 	case DEVICE_ID_5715S:
2330 		cidp->chip_label = 5715;
2331 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2332 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2333 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2334 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2335 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2336 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2337 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715;
2338 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
2339 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2340 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2341 		cidp->pci_type = BGE_PCI_E;
2342 		cidp->statistic_type = BGE_STAT_REG;
2343 		if (cidp->revision >= REVISION_ID_5715_A2)
2344 			cidp->msi_enabled = bge_enable_msi;
2345 		dev_ok = B_TRUE;
2346 		break;
2347 
2348 	case DEVICE_ID_5721:
2349 		cidp->chip_label = 5721;
2350 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2351 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2352 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2353 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2354 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2355 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2356 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2357 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2358 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2359 		cidp->pci_type = BGE_PCI_E;
2360 		cidp->statistic_type = BGE_STAT_REG;
2361 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2362 		dev_ok = B_TRUE;
2363 		break;
2364 
2365 	case DEVICE_ID_5722:
2366 		cidp->chip_label = 5722;
2367 		cidp->pci_type = BGE_PCI_E;
2368 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2369 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2370 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2371 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2372 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2373 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2374 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2375 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2376 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2377 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2378 		cidp->statistic_type = BGE_STAT_REG;
2379 		dev_ok = B_TRUE;
2380 		break;
2381 
2382 	case DEVICE_ID_5751:
2383 	case DEVICE_ID_5751M:
2384 		cidp->chip_label = 5751;
2385 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2386 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2387 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2388 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2389 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2390 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2391 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2392 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2393 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2394 		cidp->pci_type = BGE_PCI_E;
2395 		cidp->statistic_type = BGE_STAT_REG;
2396 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2397 		dev_ok = B_TRUE;
2398 		break;
2399 
2400 	case DEVICE_ID_5752:
2401 	case DEVICE_ID_5752M:
2402 		cidp->chip_label = 5752;
2403 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2404 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2405 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2406 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2407 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2408 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2409 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2410 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2411 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2412 		cidp->pci_type = BGE_PCI_E;
2413 		cidp->statistic_type = BGE_STAT_REG;
2414 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2415 		dev_ok = B_TRUE;
2416 		break;
2417 
2418 	case DEVICE_ID_5789:
2419 		cidp->chip_label = 5789;
2420 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2421 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2422 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2423 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2424 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2425 		cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
2426 		cidp->pci_type = BGE_PCI_E;
2427 		cidp->statistic_type = BGE_STAT_REG;
2428 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2429 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2430 		cidp->msi_enabled = B_TRUE;
2431 		dev_ok = B_TRUE;
2432 		break;
2433 
2434 	}
2435 
2436 	/*
2437 	 * Setup the default jumbo parameter.
2438 	 */
2439 	cidp->ethmax_size = ETHERMAX;
2440 	cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT;
2441 	cidp->std_buf_size = BGE_STD_BUFF_SIZE;
2442 
2443 	/*
2444 	 * If jumbo is enabled and this kind of chipset supports jumbo feature,
2445 	 * setup below jumbo specific parameters.
2446 	 *
2447 	 * For BCM5714/5715, there is only one standard receive ring. So the
2448 	 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo
2449 	 * feature is enabled.
2450 	 */
2451 	if (!(cidp->flags & CHIP_FLAG_NO_JUMBO) &&
2452 	    (cidp->default_mtu > BGE_DEFAULT_MTU)) {
2453 		if (DEVICE_5714_SERIES_CHIPSETS(bgep)) {
2454 			cidp->mbuf_lo_water_rdma =
2455 			    RDMA_MBUF_LOWAT_5714_JUMBO;
2456 			cidp->mbuf_lo_water_rmac =
2457 			    MAC_RX_MBUF_LOWAT_5714_JUMBO;
2458 			cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO;
2459 			cidp->jumbo_slots = 0;
2460 			cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE;
2461 		} else {
2462 			cidp->mbuf_lo_water_rdma =
2463 			    RDMA_MBUF_LOWAT_JUMBO;
2464 			cidp->mbuf_lo_water_rmac =
2465 			    MAC_RX_MBUF_LOWAT_JUMBO;
2466 			cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO;
2467 			cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED;
2468 		}
2469 		cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE;
2470 		cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO;
2471 		cidp->ethmax_size = cidp->default_mtu +
2472 		    sizeof (struct ether_header);
2473 	}
2474 
2475 	/*
2476 	 * Identify the NV memory type: SEEPROM or Flash?
2477 	 */
2478 	cidp->nvtype = bge_nvmem_id(bgep);
2479 
2480 	/*
2481 	 * Now, we want to check whether this device is part of a
2482 	 * supported subsystem (e.g., on the motherboard of a Sun
2483 	 * branded platform).
2484 	 *
2485 	 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-)
2486 	 */
2487 	if (cidp->subven == VENDOR_ID_SUN)
2488 		sys_ok = B_TRUE;
2489 
2490 	/*
2491 	 * Rule 2: If it's on the list on known subsystems, then it's OK.
2492 	 * Note: 0x14e41647 should *not* appear in the list, but the code
2493 	 * doesn't enforce that.
2494 	 */
2495 	err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo,
2496 	    DDI_PROP_DONTPASS, knownids_propname, &ids, &i);
2497 	if (err == DDI_PROP_SUCCESS) {
2498 		/*
2499 		 * Got the list; scan for a matching subsystem vendor/device
2500 		 */
2501 		subid = (cidp->subven << 16) | cidp->subdev;
2502 		while (i--)
2503 			if (ids[i] == subid)
2504 				sys_ok = B_TRUE;
2505 		ddi_prop_free(ids);
2506 	}
2507 
2508 	/*
2509 	 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK
2510 	 *
2511 	 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram
2512 	 * the Subsystem Vendor ID, so it defaults to Broadcom.  Therefore,
2513 	 * we have to check specially for the exact device paths to the
2514 	 * motherboard devices on those platforms ;-(
2515 	 *
2516 	 * Note: we can't just use the "supported-subsystems" mechanism
2517 	 * above, because the entry would have to be 0x14e41647 -- which
2518 	 * would then accept *any* plugin card that *didn't* contain a
2519 	 * (valid) SEEPROM ;-(
2520 	 */
2521 	sysname = ddi_node_name(ddi_root_node());
2522 	devname = ddi_pathname(bgep->devinfo, buf);
2523 	ASSERT(strlen(devname) > 0);
2524 	if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0)	/* Taco */
2525 		if (strcmp(devname, "/pci@1f,700000/network@2") == 0)
2526 			sys_ok = B_TRUE;
2527 	if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0)	/* ENWS */
2528 		if (strcmp(devname, "/pci@1c,600000/network@3") == 0)
2529 			sys_ok = B_TRUE;
2530 
2531 	/*
2532 	 * Now check what we've discovered: is this truly a supported
2533 	 * chip on (the motherboard of) a supported platform?
2534 	 *
2535 	 * Possible problems here:
2536 	 * 1)	it's a completely unheard-of chip
2537 	 * 2)	it's a recognised but unsupported chip (e.g. 5701, 5703C-A0)
2538 	 * 3)	it's a chip we would support if it were on the motherboard
2539 	 *	of a Sun platform, but this one isn't ;-(
2540 	 */
2541 	if (cidp->chip_label == 0)
2542 		bge_problem(bgep,
2543 		    "Device 'pci%04x,%04x' not recognized (%d?)",
2544 		    cidp->vendor, cidp->device, cidp->device);
2545 	else if (!dev_ok)
2546 		bge_problem(bgep,
2547 		    "Device 'pci%04x,%04x' (%d) revision %d not supported",
2548 		    cidp->vendor, cidp->device, cidp->chip_label,
2549 		    cidp->revision);
2550 #if	BGE_DEBUGGING
2551 	else if (!sys_ok)
2552 		bge_problem(bgep,
2553 		    "%d-based subsystem 'pci%04x,%04x' not validated",
2554 		    cidp->chip_label, cidp->subven, cidp->subdev);
2555 #endif
2556 	else
2557 		cidp->flags |= CHIP_FLAG_SUPPORTED;
2558 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
2559 		return (EIO);
2560 	return (0);
2561 }
2562 
2563 void
2564 bge_chip_msi_trig(bge_t *bgep)
2565 {
2566 	uint32_t	regval;
2567 
2568 	regval = bgep->param_msi_cnt<<4;
2569 	bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval);
2570 	BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval));
2571 }
2572 
2573 /*
2574  * Various registers that control the chip's internal engines (state
2575  * machines) have a <reset> and <enable> bits (fortunately, in the
2576  * same place in each such register :-).
2577  *
2578  * To reset the state machine, the <reset> bit must be written with 1;
2579  * it will then read back as 1 while the reset is in progress, but
2580  * self-clear to 0 when the reset completes.
2581  *
2582  * To enable a state machine, one must set the <enable> bit, which
2583  * will continue to read back as 0 until the state machine is running.
2584  *
2585  * To disable a state machine, the <enable> bit must be cleared, but
2586  * it will continue to read back as 1 until the state machine actually
2587  * stops.
2588  *
2589  * This routine implements polling for completion of a reset, enable
2590  * or disable operation, returning B_TRUE on success (bit reached the
2591  * required state) or B_FALSE on timeout (200*100us == 20ms).
2592  */
2593 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2594 					uint32_t mask, uint32_t val);
2595 #pragma	no_inline(bge_chip_poll_engine)
2596 
2597 static boolean_t
2598 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2599 	uint32_t mask, uint32_t val)
2600 {
2601 	uint32_t regval;
2602 	uint32_t n;
2603 
2604 	BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)",
2605 	    (void *)bgep, regno, mask, val));
2606 
2607 	for (n = 200; n; --n) {
2608 		regval = bge_reg_get32(bgep, regno);
2609 		if ((regval & mask) == val)
2610 			return (B_TRUE);
2611 		drv_usecwait(100);
2612 	}
2613 
2614 	bge_problem(bgep, "bge_chip_poll_engine failed: regno = 0x%lx", regno);
2615 	bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE);
2616 	return (B_FALSE);
2617 }
2618 
2619 /*
2620  * Various registers that control the chip's internal engines (state
2621  * machines) have a <reset> bit (fortunately, in the same place in
2622  * each such register :-).  To reset the state machine, this bit must
2623  * be written with 1; it will then read back as 1 while the reset is
2624  * in progress, but self-clear to 0 when the reset completes.
2625  *
2626  * This code sets the bit, then polls for it to read back as zero.
2627  * The return value is B_TRUE on success (reset bit cleared itself),
2628  * or B_FALSE if the state machine didn't recover :(
2629  *
2630  * NOTE: the Core reset is similar to other resets, except that we
2631  * can't poll for completion, since the Core reset disables memory
2632  * access!  So we just have to assume that it will all complete in
2633  * 100us.  See Broadcom document 570X-PG102-R, p102, steps 4-5.
2634  */
2635 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno);
2636 #pragma	no_inline(bge_chip_reset_engine)
2637 
2638 static boolean_t
2639 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno)
2640 {
2641 	uint32_t regval;
2642 	uint32_t val32;
2643 
2644 	regval = bge_reg_get32(bgep, regno);
2645 
2646 	BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)",
2647 	    (void *)bgep, regno));
2648 	BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x",
2649 	    regno, regval));
2650 
2651 	regval |= STATE_MACHINE_RESET_BIT;
2652 
2653 	switch (regno) {
2654 	case MISC_CONFIG_REG:
2655 		/*
2656 		 * BCM5714/5721/5751 pcie chip special case. In order to avoid
2657 		 * resetting PCIE block and bringing PCIE link down, bit 29
2658 		 * in the register needs to be set first, and then set it again
2659 		 * while the reset bit is written.
2660 		 * See:P500 of 57xx-PG102-RDS.pdf.
2661 		 */
2662 		if (DEVICE_5705_SERIES_CHIPSETS(bgep)||
2663 		    DEVICE_5717_SERIES_CHIPSETS(bgep)||
2664 		    DEVICE_5721_SERIES_CHIPSETS(bgep)||
2665 		    DEVICE_5723_SERIES_CHIPSETS(bgep)||
2666 		    DEVICE_5714_SERIES_CHIPSETS(bgep)||
2667 		    DEVICE_5906_SERIES_CHIPSETS(bgep)) {
2668 			regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE;
2669 			if (bgep->chipid.pci_type == BGE_PCI_E) {
2670 				if (bgep->chipid.asic_rev ==
2671 				    MHCR_CHIP_REV_5751_A0 ||
2672 				    bgep->chipid.asic_rev ==
2673 				    MHCR_CHIP_REV_5721_A0 ||
2674 				    bgep->chipid.asic_rev ==
2675 				    MHCR_CHIP_REV_5755_A0) {
2676 					val32 = bge_reg_get32(bgep,
2677 					    PHY_TEST_CTRL_REG);
2678 					if (val32 == (PHY_PCIE_SCRAM_MODE |
2679 					    PHY_PCIE_LTASS_MODE))
2680 						bge_reg_put32(bgep,
2681 						    PHY_TEST_CTRL_REG,
2682 						    PHY_PCIE_SCRAM_MODE);
2683 					val32 = pci_config_get32
2684 					    (bgep->cfg_handle,
2685 					    PCI_CONF_BGE_CLKCTL);
2686 					val32 |= CLKCTL_PCIE_A0_FIX;
2687 					pci_config_put32(bgep->cfg_handle,
2688 					    PCI_CONF_BGE_CLKCTL, val32);
2689 				}
2690 				bge_reg_set32(bgep, regno,
2691 				    MISC_CONFIG_GRC_RESET_DISABLE);
2692 				regval |= MISC_CONFIG_GRC_RESET_DISABLE;
2693 			}
2694 		}
2695 
2696 		/*
2697 		 * Special case - causes Core reset
2698 		 *
2699 		 * On SPARC v9 we want to ensure that we don't start
2700 		 * timing until the I/O access has actually reached
2701 		 * the chip, otherwise we might make the next access
2702 		 * too early.  And we can't just force the write out
2703 		 * by following it with a read (even to config space)
2704 		 * because that would cause the fault we're trying
2705 		 * to avoid.  Hence the need for membar_sync() here.
2706 		 */
2707 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval);
2708 #ifdef	__sparcv9
2709 		membar_sync();
2710 #endif	/* __sparcv9 */
2711 		/*
2712 		 * On some platforms,system need about 300us for
2713 		 * link setup.
2714 		 */
2715 		drv_usecwait(300);
2716 		if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
2717 			bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET);
2718 			bge_reg_clr32(
2719 			    bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF);
2720 		}
2721 
2722 		if (bgep->chipid.pci_type == BGE_PCI_E) {
2723 			/* PCI-E device need more reset time */
2724 			drv_usecwait(120000);
2725 
2726 			/* Set PCIE max payload size and clear error status. */
2727 			if ((bgep->chipid.chip_label == 5721) ||
2728 			    (bgep->chipid.chip_label == 5751) ||
2729 			    (bgep->chipid.chip_label == 5752) ||
2730 			    (bgep->chipid.chip_label == 5789) ||
2731 			    (bgep->chipid.chip_label == 5906)) {
2732 				pci_config_put16(bgep->cfg_handle,
2733 				    PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX);
2734 				pci_config_put16(bgep->cfg_handle,
2735 				    PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS);
2736 			}
2737 
2738 			if ((bgep->chipid.chip_label == 5723) ||
2739 			    (bgep->chipid.chip_label == 5761)) {
2740 				pci_config_put16(bgep->cfg_handle,
2741 				    PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX);
2742 				pci_config_put16(bgep->cfg_handle,
2743 				    PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS);
2744 			}
2745 		}
2746 
2747 		BGE_PCICHK(bgep);
2748 		return (B_TRUE);
2749 
2750 	default:
2751 		bge_reg_put32(bgep, regno, regval);
2752 		return (bge_chip_poll_engine(bgep, regno,
2753 		    STATE_MACHINE_RESET_BIT, 0));
2754 	}
2755 }
2756 
2757 /*
2758  * Various registers that control the chip's internal engines (state
2759  * machines) have an <enable> bit (fortunately, in the same place in
2760  * each such register :-).  To stop the state machine, this bit must
2761  * be written with 0, then polled to see when the state machine has
2762  * actually stopped.
2763  *
2764  * The return value is B_TRUE on success (enable bit cleared), or
2765  * B_FALSE if the state machine didn't stop :(
2766  */
2767 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno,
2768 						uint32_t morebits);
2769 #pragma	no_inline(bge_chip_disable_engine)
2770 
2771 static boolean_t
2772 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2773 {
2774 	uint32_t regval;
2775 
2776 	BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)",
2777 	    (void *)bgep, regno, morebits));
2778 
2779 	switch (regno) {
2780 	case FTQ_RESET_REG:
2781 		/*
2782 		 * For Schumacher's bugfix CR6490108
2783 		 */
2784 #ifdef BGE_IPMI_ASF
2785 #ifdef BGE_NETCONSOLE
2786 		if (bgep->asf_enabled)
2787 			return (B_TRUE);
2788 #endif
2789 #endif
2790 		/*
2791 		 * Not quite like the others; it doesn't
2792 		 * have an <enable> bit, but instead we
2793 		 * have to set and then clear all the bits
2794 		 */
2795 		bge_reg_put32(bgep, regno, ~(uint32_t)0);
2796 		drv_usecwait(100);
2797 		bge_reg_put32(bgep, regno, 0);
2798 		return (B_TRUE);
2799 
2800 	default:
2801 		regval = bge_reg_get32(bgep, regno);
2802 		regval &= ~STATE_MACHINE_ENABLE_BIT;
2803 		regval &= ~morebits;
2804 		bge_reg_put32(bgep, regno, regval);
2805 		return (bge_chip_poll_engine(bgep, regno,
2806 		    STATE_MACHINE_ENABLE_BIT, 0));
2807 	}
2808 }
2809 
2810 /*
2811  * Various registers that control the chip's internal engines (state
2812  * machines) have an <enable> bit (fortunately, in the same place in
2813  * each such register :-).  To start the state machine, this bit must
2814  * be written with 1, then polled to see when the state machine has
2815  * actually started.
2816  *
2817  * The return value is B_TRUE on success (enable bit set), or
2818  * B_FALSE if the state machine didn't start :(
2819  */
2820 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno,
2821 					uint32_t morebits);
2822 #pragma	no_inline(bge_chip_enable_engine)
2823 
2824 static boolean_t
2825 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2826 {
2827 	uint32_t regval;
2828 
2829 	BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)",
2830 	    (void *)bgep, regno, morebits));
2831 
2832 	switch (regno) {
2833 	case FTQ_RESET_REG:
2834 #ifdef BGE_IPMI_ASF
2835 #ifdef BGE_NETCONSOLE
2836 		if (bgep->asf_enabled)
2837 			return (B_TRUE);
2838 #endif
2839 #endif
2840 		/*
2841 		 * Not quite like the others; it doesn't
2842 		 * have an <enable> bit, but instead we
2843 		 * have to set and then clear all the bits
2844 		 */
2845 		bge_reg_put32(bgep, regno, ~(uint32_t)0);
2846 		drv_usecwait(100);
2847 		bge_reg_put32(bgep, regno, 0);
2848 		return (B_TRUE);
2849 
2850 	default:
2851 		regval = bge_reg_get32(bgep, regno);
2852 		regval |= STATE_MACHINE_ENABLE_BIT;
2853 		regval |= morebits;
2854 		bge_reg_put32(bgep, regno, regval);
2855 		return (bge_chip_poll_engine(bgep, regno,
2856 		    STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT));
2857 	}
2858 }
2859 
2860 /*
2861  * Reprogram the Ethernet, Transmit, and Receive MAC
2862  * modes to match the param_* variables
2863  */
2864 void bge_sync_mac_modes(bge_t *bgep);
2865 #pragma	no_inline(bge_sync_mac_modes)
2866 
2867 void
2868 bge_sync_mac_modes(bge_t *bgep)
2869 {
2870 	uint32_t macmode;
2871 	uint32_t regval;
2872 
2873 	ASSERT(mutex_owned(bgep->genlock));
2874 
2875 	/*
2876 	 * Reprogram the Ethernet MAC mode ...
2877 	 */
2878 	macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
2879 	if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
2880 	    (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC))
2881 		if (DEVICE_5714_SERIES_CHIPSETS(bgep))
2882 			macmode |= ETHERNET_MODE_LINK_POLARITY;
2883 		else
2884 			macmode &= ~ETHERNET_MODE_LINK_POLARITY;
2885 	else
2886 		macmode |= ETHERNET_MODE_LINK_POLARITY;
2887 	macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
2888 	if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
2889 	    (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) {
2890 		if (DEVICE_5714_SERIES_CHIPSETS(bgep))
2891 			macmode |= ETHERNET_MODE_PORTMODE_GMII;
2892 		else
2893 			macmode |= ETHERNET_MODE_PORTMODE_TBI;
2894 	} else if (bgep->param_link_speed == 10 ||
2895 	    bgep->param_link_speed == 100)
2896 		macmode |= ETHERNET_MODE_PORTMODE_MII;
2897 	else
2898 		macmode |= ETHERNET_MODE_PORTMODE_GMII;
2899 	if (bgep->param_link_duplex == LINK_DUPLEX_HALF)
2900 		macmode |= ETHERNET_MODE_HALF_DUPLEX;
2901 	else
2902 		macmode &= ~ETHERNET_MODE_HALF_DUPLEX;
2903 	if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC)
2904 		macmode |= ETHERNET_MODE_MAC_LOOPBACK;
2905 	else
2906 		macmode &= ~ETHERNET_MODE_MAC_LOOPBACK;
2907 	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
2908 	BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x",
2909 	    (void *)bgep, regval, macmode));
2910 
2911 	/*
2912 	 * ... the Transmit MAC mode ...
2913 	 */
2914 	macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG);
2915 	if (bgep->param_link_tx_pause)
2916 		macmode |= TRANSMIT_MODE_FLOW_CONTROL;
2917 	else
2918 		macmode &= ~TRANSMIT_MODE_FLOW_CONTROL;
2919 	bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode);
2920 	BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x",
2921 	    (void *)bgep, regval, macmode));
2922 
2923 	/*
2924 	 * ... and the Receive MAC mode
2925 	 */
2926 	macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG);
2927 	if (bgep->param_link_rx_pause)
2928 		macmode |= RECEIVE_MODE_FLOW_CONTROL;
2929 	else
2930 		macmode &= ~RECEIVE_MODE_FLOW_CONTROL;
2931 	bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode);
2932 	BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x",
2933 	    (void *)bgep, regval, macmode));
2934 
2935 	/*
2936 	 * For BCM5785, we need to configure the link status in the MI Status
2937 	 * register with a write command when auto-polling is disabled.
2938 	 */
2939 	if (bgep->chipid.device == DEVICE_ID_5785)
2940 		if (bgep->param_link_speed == 10)
2941 			bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK
2942 			    | MI_STATUS_10MBPS);
2943 		else
2944 			bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
2945 }
2946 
2947 /*
2948  * bge_chip_sync() -- program the chip with the unicast MAC address,
2949  * the multicast hash table, the required level of promiscuity, and
2950  * the current loopback mode ...
2951  */
2952 #ifdef BGE_IPMI_ASF
2953 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive);
2954 #else
2955 int bge_chip_sync(bge_t *bgep);
2956 #endif
2957 #pragma	no_inline(bge_chip_sync)
2958 
2959 int
2960 #ifdef BGE_IPMI_ASF
2961 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive)
2962 #else
2963 bge_chip_sync(bge_t *bgep)
2964 #endif
2965 {
2966 	void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits);
2967 	boolean_t promisc;
2968 	uint64_t macaddr;
2969 	uint32_t fill = 0;
2970 	int i, j;
2971 	int retval = DDI_SUCCESS;
2972 
2973 	BGE_TRACE(("bge_chip_sync($%p)",
2974 	    (void *)bgep));
2975 
2976 	ASSERT(mutex_owned(bgep->genlock));
2977 
2978 	promisc = B_FALSE;
2979 	fill = ~(uint32_t)0;
2980 
2981 	if (bgep->promisc)
2982 		promisc = B_TRUE;
2983 	else
2984 		fill = (uint32_t)0;
2985 
2986 	/*
2987 	 * If the TX/RX MAC engines are already running, we should stop
2988 	 * them (and reset the RX engine) before changing the parameters.
2989 	 * If they're not running, this will have no effect ...
2990 	 *
2991 	 * NOTE: this is currently disabled by default because stopping
2992 	 * and restarting the Tx engine may cause an outgoing packet in
2993 	 * transit to be truncated.  Also, stopping and restarting the
2994 	 * Rx engine seems to not work correctly on the 5705.  Testing
2995 	 * has not (yet!) revealed any problems with NOT stopping and
2996 	 * restarting these engines (and Broadcom say their drivers don't
2997 	 * do this), but if it is found to cause problems, this variable
2998 	 * can be patched to re-enable the old behaviour ...
2999 	 */
3000 	if (bge_stop_start_on_sync) {
3001 #ifdef BGE_IPMI_ASF
3002 		if (!bgep->asf_enabled) {
3003 			if (!bge_chip_disable_engine(bgep,
3004 			    RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
3005 				retval = DDI_FAILURE;
3006 		} else {
3007 			if (!bge_chip_disable_engine(bgep,
3008 			    RECEIVE_MAC_MODE_REG, 0))
3009 				retval = DDI_FAILURE;
3010 		}
3011 #else
3012 		if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG,
3013 		    RECEIVE_MODE_KEEP_VLAN_TAG))
3014 			retval = DDI_FAILURE;
3015 #endif
3016 		if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3017 			retval = DDI_FAILURE;
3018 		if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG))
3019 			retval = DDI_FAILURE;
3020 	}
3021 
3022 	/*
3023 	 * Reprogram the hashed multicast address table ...
3024 	 */
3025 	for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
3026 		bge_reg_put32(bgep, MAC_HASH_REG(i), 0);
3027 
3028 	for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
3029 		bge_reg_put32(bgep, MAC_HASH_REG(i),
3030 			bgep->mcast_hash[i] | fill);
3031 
3032 #ifdef BGE_IPMI_ASF
3033 	if (!bgep->asf_enabled || !asf_keeplive) {
3034 #endif
3035 		/*
3036 		 * Transform the MAC address(es) from host to chip format, then
3037 		 * reprogram the transmit random backoff seed and the unicast
3038 		 * MAC address(es) ...
3039 		 */
3040 		for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) {
3041 			for (i = 0, macaddr = 0ull;
3042 			    i < ETHERADDRL; ++i) {
3043 				macaddr <<= 8;
3044 				macaddr |= bgep->curr_addr[j].addr[i];
3045 			}
3046 			fill += (macaddr >> 16) + (macaddr & 0xffffffff);
3047 			bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr);
3048 
3049 			BGE_DEBUG(("bge_chip_sync($%p) "
3050 			    "setting MAC address %012llx",
3051 			    (void *)bgep, macaddr));
3052 		}
3053 #ifdef BGE_IPMI_ASF
3054 	}
3055 #endif
3056 	/*
3057 	 * Set random seed of backoff interval
3058 	 *   - Writing zero means no backoff interval
3059 	 */
3060 	fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff;
3061 	if (fill == 0)
3062 		fill = 1;
3063 	bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill);
3064 
3065 	/*
3066 	 * Set or clear the PROMISCUOUS mode bit
3067 	 */
3068 	opfn = promisc ? bge_reg_set32 : bge_reg_clr32;
3069 	(*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS);
3070 
3071 	/*
3072 	 * Sync the rest of the MAC modes too ...
3073 	 */
3074 	bge_sync_mac_modes(bgep);
3075 
3076 	/*
3077 	 * Restart RX/TX MAC engines if required ...
3078 	 */
3079 	if (bgep->bge_chip_state == BGE_CHIP_RUNNING) {
3080 		if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3081 			retval = DDI_FAILURE;
3082 #ifdef BGE_IPMI_ASF
3083 		if (!bgep->asf_enabled) {
3084 			if (!bge_chip_enable_engine(bgep,
3085 			    RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
3086 				retval = DDI_FAILURE;
3087 		} else {
3088 			if (!bge_chip_enable_engine(bgep,
3089 			    RECEIVE_MAC_MODE_REG, 0))
3090 				retval = DDI_FAILURE;
3091 		}
3092 #else
3093 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
3094 		    RECEIVE_MODE_KEEP_VLAN_TAG))
3095 			retval = DDI_FAILURE;
3096 #endif
3097 	}
3098 	return (retval);
3099 }
3100 
3101 /*
3102  * This array defines the sequence of state machine control registers
3103  * in which the <enable> bit must be cleared to bring the chip to a
3104  * clean stop.  Taken from Broadcom document 570X-PG102-R, p116.
3105  */
3106 static bge_regno_t shutdown_engine_regs[] = {
3107 	RECEIVE_MAC_MODE_REG,
3108 	RCV_BD_INITIATOR_MODE_REG,
3109 	RCV_LIST_PLACEMENT_MODE_REG,
3110 	RCV_LIST_SELECTOR_MODE_REG,		/* BCM5704 series only	*/
3111 	RCV_DATA_BD_INITIATOR_MODE_REG,
3112 	RCV_DATA_COMPLETION_MODE_REG,
3113 	RCV_BD_COMPLETION_MODE_REG,
3114 
3115 	SEND_BD_SELECTOR_MODE_REG,
3116 	SEND_BD_INITIATOR_MODE_REG,
3117 	SEND_DATA_INITIATOR_MODE_REG,
3118 	READ_DMA_MODE_REG,
3119 	SEND_DATA_COMPLETION_MODE_REG,
3120 	DMA_COMPLETION_MODE_REG,		/* BCM5704 series only	*/
3121 	SEND_BD_COMPLETION_MODE_REG,
3122 	TRANSMIT_MAC_MODE_REG,
3123 
3124 	HOST_COALESCE_MODE_REG,
3125 	WRITE_DMA_MODE_REG,
3126 	MBUF_CLUSTER_FREE_MODE_REG,		/* BCM5704 series only	*/
3127 	FTQ_RESET_REG,		/* special - see code	*/
3128 	BUFFER_MANAGER_MODE_REG,		/* BCM5704 series only	*/
3129 	MEMORY_ARBITER_MODE_REG,		/* BCM5704 series only	*/
3130 	BGE_REGNO_NONE		/* terminator		*/
3131 };
3132 
3133 #ifndef __sparc
3134 static bge_regno_t quiesce_regs[] = {
3135 	READ_DMA_MODE_REG,
3136 	DMA_COMPLETION_MODE_REG,
3137 	WRITE_DMA_MODE_REG,
3138 	BGE_REGNO_NONE
3139 };
3140 
3141 void bge_chip_stop_nonblocking(bge_t *bgep);
3142 #pragma no_inline(bge_chip_stop_nonblocking)
3143 
3144 /*
3145  * This function is called by bge_quiesce(). We
3146  * turn off all the DMA engines here.
3147  */
3148 void
3149 bge_chip_stop_nonblocking(bge_t *bgep)
3150 {
3151 	bge_regno_t *rbp;
3152 
3153 	/*
3154 	 * Flag that no more activity may be initiated
3155 	 */
3156 	bgep->progress &= ~PROGRESS_READY;
3157 
3158 	rbp = quiesce_regs;
3159 	while (*rbp != BGE_REGNO_NONE) {
3160 		(void) bge_chip_disable_engine(bgep, *rbp, 0);
3161 		++rbp;
3162 	}
3163 
3164 	bgep->bge_chip_state = BGE_CHIP_STOPPED;
3165 }
3166 
3167 #endif
3168 
3169 /*
3170  * bge_chip_stop() -- stop all chip processing
3171  *
3172  * If the <fault> parameter is B_TRUE, we're stopping the chip because
3173  * we've detected a problem internally; otherwise, this is a normal
3174  * (clean) stop (at user request i.e. the last STREAM has been closed).
3175  */
3176 void bge_chip_stop(bge_t *bgep, boolean_t fault);
3177 #pragma	no_inline(bge_chip_stop)
3178 
3179 void
3180 bge_chip_stop(bge_t *bgep, boolean_t fault)
3181 {
3182 	bge_regno_t regno;
3183 	bge_regno_t *rbp;
3184 	boolean_t ok;
3185 
3186 	BGE_TRACE(("bge_chip_stop($%p)",
3187 	    (void *)bgep));
3188 
3189 	ASSERT(mutex_owned(bgep->genlock));
3190 
3191 	rbp = shutdown_engine_regs;
3192 	/*
3193 	 * When driver try to shutdown the BCM5705/5788/5721/5751/
3194 	 * 5752/5714 and 5715 chipsets,the buffer manager and the mem
3195 	 * -ory arbiter should not be disabled.
3196 	 */
3197 	for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) {
3198 			if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3199 				ok &= bge_chip_disable_engine(bgep, regno, 0);
3200 			else if ((regno != RCV_LIST_SELECTOR_MODE_REG) &&
3201 			    (regno != DMA_COMPLETION_MODE_REG) &&
3202 			    (regno != MBUF_CLUSTER_FREE_MODE_REG)&&
3203 			    (regno != BUFFER_MANAGER_MODE_REG) &&
3204 			    (regno != MEMORY_ARBITER_MODE_REG))
3205 				ok &= bge_chip_disable_engine(bgep,
3206 				    regno, 0);
3207 	}
3208 
3209 	if (!ok && !fault)
3210 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
3211 
3212 	/*
3213 	 * Finally, disable (all) MAC events & clear the MAC status
3214 	 */
3215 	bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0);
3216 	bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0);
3217 
3218 	/*
3219 	 * if we're stopping the chip because of a detected fault then do
3220 	 * appropriate actions
3221 	 */
3222 	if (fault) {
3223 		if (bgep->bge_chip_state != BGE_CHIP_FAULT) {
3224 			bgep->bge_chip_state = BGE_CHIP_FAULT;
3225 			if (!bgep->manual_reset)
3226 				ddi_fm_service_impact(bgep->devinfo,
3227 				    DDI_SERVICE_LOST);
3228 			if (bgep->bge_dma_error) {
3229 				/*
3230 				 * need to free buffers in case the fault was
3231 				 * due to a memory error in a buffer - got to
3232 				 * do a fair bit of tidying first
3233 				 */
3234 				if (bgep->progress & PROGRESS_KSTATS) {
3235 					bge_fini_kstats(bgep);
3236 					bgep->progress &= ~PROGRESS_KSTATS;
3237 				}
3238 				if (bgep->progress & PROGRESS_INTR) {
3239 					bge_intr_disable(bgep);
3240 					rw_enter(bgep->errlock, RW_WRITER);
3241 					bge_fini_rings(bgep);
3242 					rw_exit(bgep->errlock);
3243 					bgep->progress &= ~PROGRESS_INTR;
3244 				}
3245 				if (bgep->progress & PROGRESS_BUFS) {
3246 					bge_free_bufs(bgep);
3247 					bgep->progress &= ~PROGRESS_BUFS;
3248 				}
3249 				bgep->bge_dma_error = B_FALSE;
3250 			}
3251 		}
3252 	} else
3253 		bgep->bge_chip_state = BGE_CHIP_STOPPED;
3254 }
3255 
3256 /*
3257  * Poll for completion of chip's ROM firmware; also, at least on the
3258  * first time through, find and return the hardware MAC address, if any.
3259  */
3260 static uint64_t bge_poll_firmware(bge_t *bgep);
3261 #pragma	no_inline(bge_poll_firmware)
3262 
3263 static uint64_t
3264 bge_poll_firmware(bge_t *bgep)
3265 {
3266 	uint64_t magic;
3267 	uint64_t mac;
3268 	uint32_t gen, val;
3269 	uint32_t i;
3270 
3271 	/*
3272 	 * Step 19: poll for firmware completion (GENCOMM port set
3273 	 * to the ones complement of T3_MAGIC_NUMBER).
3274 	 *
3275 	 * While we're at it, we also read the MAC address register;
3276 	 * at some stage the firmware will load this with the
3277 	 * factory-set value.
3278 	 *
3279 	 * When both the magic number and the MAC address are set,
3280 	 * we're done; but we impose a time limit of one second
3281 	 * (1000*1000us) in case the firmware fails in some fashion
3282 	 * or the SEEPROM that provides that MAC address isn't fitted.
3283 	 *
3284 	 * After the first time through (chip state != INITIAL), we
3285 	 * don't need the MAC address to be set (we've already got it
3286 	 * or not, from the first time), so we don't wait for it, but
3287 	 * we still have to wait for the T3_MAGIC_NUMBER.
3288 	 *
3289 	 * Note: the magic number is only a 32-bit quantity, but the NIC
3290 	 * memory is 64-bit (and big-endian) internally.  Addressing the
3291 	 * GENCOMM word as "the upper half of a 64-bit quantity" makes
3292 	 * it work correctly on both big- and little-endian hosts.
3293 	 */
3294 	if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3295 	    MHCR_CHIP_ASIC_REV_5906) {
3296 		for (i = 0; i < 1000; ++i) {
3297 			drv_usecwait(1000);
3298 			val = bge_reg_get32(bgep, VCPU_STATUS_REG);
3299 			if (val & VCPU_INIT_DONE)
3300 				break;
3301 		}
3302 		BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops",
3303 		    (void *)bgep, i));
3304 		mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
3305 	} else {
3306 		for (i = 0; i < 1000; ++i) {
3307 			drv_usecwait(1000);
3308 			gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32;
3309 			if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep))
3310 				drv_usecwait(100000);
3311 			mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
3312 #ifdef BGE_IPMI_ASF
3313 			if (!bgep->asf_enabled) {
3314 #endif
3315 				if (gen != ~T3_MAGIC_NUMBER)
3316 					continue;
3317 #ifdef BGE_IPMI_ASF
3318 			}
3319 #endif
3320 			if (mac != 0ULL)
3321 				break;
3322 			if (bgep->bge_chip_state != BGE_CHIP_INITIAL)
3323 				break;
3324 		}
3325 	}
3326 
3327 	magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM);
3328 	BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops",
3329 	    (void *)bgep, gen, i));
3330 	BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx",
3331 	    mac, magic));
3332 
3333 	return (mac);
3334 }
3335 
3336 /*
3337  * Maximum times of trying to get the NVRAM access lock
3338  * by calling bge_nvmem_acquire()
3339  */
3340 #define	MAX_TRY_NVMEM_ACQUIRE	10000
3341 
3342 #ifdef BGE_IPMI_ASF
3343 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode);
3344 #else
3345 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma);
3346 #endif
3347 #pragma	no_inline(bge_chip_reset)
3348 
3349 int
3350 #ifdef BGE_IPMI_ASF
3351 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode)
3352 #else
3353 bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
3354 #endif
3355 {
3356 	chip_id_t chipid;
3357 	uint64_t mac;
3358 	uint64_t magic;
3359 	uint32_t modeflags;
3360 	uint32_t mhcr;
3361 	uint32_t sx0;
3362 	uint32_t i, tries;
3363 #ifdef BGE_IPMI_ASF
3364 	uint32_t mailbox;
3365 #endif
3366 	int retval = DDI_SUCCESS;
3367 
3368 	BGE_TRACE(("bge_chip_reset($%p, %d)",
3369 		(void *)bgep, enable_dma));
3370 
3371 	ASSERT(mutex_owned(bgep->genlock));
3372 
3373 	BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d",
3374 		(void *)bgep, enable_dma, bgep->bge_chip_state));
3375 
3376 	/*
3377 	 * Do we need to stop the chip cleanly before resetting?
3378 	 */
3379 	switch (bgep->bge_chip_state) {
3380 	default:
3381 		_NOTE(NOTREACHED)
3382 		return (DDI_FAILURE);
3383 
3384 	case BGE_CHIP_INITIAL:
3385 	case BGE_CHIP_STOPPED:
3386 	case BGE_CHIP_RESET:
3387 		break;
3388 
3389 	case BGE_CHIP_RUNNING:
3390 	case BGE_CHIP_ERROR:
3391 	case BGE_CHIP_FAULT:
3392 		bge_chip_stop(bgep, B_FALSE);
3393 		break;
3394 	}
3395 
3396 #ifdef BGE_IPMI_ASF
3397 	if (bgep->asf_enabled) {
3398 #ifdef __sparc
3399 		mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3400 			MHCR_ENABLE_TAGGED_STATUS_MODE |
3401 			MHCR_MASK_INTERRUPT_MODE |
3402 			MHCR_MASK_PCI_INT_OUTPUT |
3403 			MHCR_CLEAR_INTERRUPT_INTA |
3404 			MHCR_ENABLE_ENDIAN_WORD_SWAP |
3405 			MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3406 		if (DEVICE_5717_SERIES_CHIPSETS(bgep))
3407 			pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR,
3408 					0);
3409 		pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3410 		bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3411 			bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) |
3412 			MEMORY_ARBITER_ENABLE);
3413 #endif
3414 		if (asf_mode == ASF_MODE_INIT) {
3415 			bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
3416 		} else if (asf_mode == ASF_MODE_SHUTDOWN) {
3417 			bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET);
3418 		}
3419 	}
3420 #endif
3421 	/*
3422 	 * Adapted from Broadcom document 570X-PG102-R, pp 102-116.
3423 	 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159.
3424 	 *
3425 	 * Before reset Core clock,it is
3426 	 * also required to initialize the Memory Arbiter as specified in step9
3427 	 * and Misc Host Control Register as specified in step-13
3428 	 * Step 4-5: reset Core clock & wait for completion
3429 	 * Steps 6-8: are done by bge_chip_cfg_init()
3430 	 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset
3431 	 */
3432 	if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3433 		retval = DDI_FAILURE;
3434 
3435 	mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3436 	    MHCR_ENABLE_TAGGED_STATUS_MODE |
3437 	    MHCR_MASK_INTERRUPT_MODE |
3438 	    MHCR_MASK_PCI_INT_OUTPUT |
3439 	    MHCR_CLEAR_INTERRUPT_INTA;
3440 #ifdef  _BIG_ENDIAN
3441 	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3442 #endif  /* _BIG_ENDIAN */
3443 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
3444 		pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 0);
3445 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3446 #ifdef BGE_IPMI_ASF
3447 	if (bgep->asf_enabled)
3448 		bgep->asf_wordswapped = B_FALSE;
3449 #endif
3450 	/*
3451 	 * NVRAM Corruption Workaround
3452 	 */
3453 	for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++)
3454 		if (bge_nvmem_acquire(bgep) != EAGAIN)
3455 			break;
3456 	if (tries >= MAX_TRY_NVMEM_ACQUIRE)
3457 		BGE_DEBUG(("%s: fail to acquire nvram lock",
3458 			bgep->ifname));
3459 
3460 #ifdef BGE_IPMI_ASF
3461 	if (!bgep->asf_enabled) {
3462 #endif
3463 		magic = (uint64_t)T3_MAGIC_NUMBER << 32;
3464 		bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic);
3465 #ifdef BGE_IPMI_ASF
3466 	}
3467 #endif
3468 
3469 	if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG))
3470 		retval = DDI_FAILURE;
3471 	bge_chip_cfg_init(bgep, &chipid, enable_dma);
3472 
3473 	/*
3474 	 * Step 8a: This may belong elsewhere, but BCM5721 needs
3475 	 * a bit set to avoid a fifo overflow/underflow bug.
3476 	 */
3477 	if ((bgep->chipid.chip_label == 5721) ||
3478 		(bgep->chipid.chip_label == 5751) ||
3479 		(bgep->chipid.chip_label == 5752) ||
3480 		(bgep->chipid.chip_label == 5755) ||
3481 		(bgep->chipid.chip_label == 5756) ||
3482 		(bgep->chipid.chip_label == 5789) ||
3483 		(bgep->chipid.chip_label == 5906))
3484 		bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT);
3485 
3486 
3487 	/*
3488 	 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should
3489 	 * not be changed.
3490 	 */
3491 	if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3492 		retval = DDI_FAILURE;
3493 
3494 	/*
3495 	 * Steps 10-11: configure PIO endianness options and
3496 	 * enable indirect register access -- already done
3497 	 * Steps 12-13: enable writing to the PCI state & clock
3498 	 * control registers -- not required; we aren't going to
3499 	 * use those features.
3500 	 * Steps 14-15: Configure DMA endianness options.  See
3501 	 * the comments on the setting of the MHCR above.
3502 	 */
3503 #ifdef	_BIG_ENDIAN
3504 	modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME |
3505 		    MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME;
3506 #else
3507 	modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME;
3508 #endif	/* _BIG_ENDIAN */
3509 #ifdef BGE_IPMI_ASF
3510 	if (bgep->asf_enabled)
3511 		modeflags |= MODE_HOST_STACK_UP;
3512 #endif
3513 	bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags);
3514 
3515 #ifdef BGE_IPMI_ASF
3516 	if (bgep->asf_enabled) {
3517 #ifdef __sparc
3518 		bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3519 			MEMORY_ARBITER_ENABLE |
3520 			bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG));
3521 #endif
3522 
3523 #ifdef  BGE_NETCONSOLE
3524 		if (!bgep->asf_newhandshake) {
3525 			if ((asf_mode == ASF_MODE_INIT) ||
3526 			(asf_mode == ASF_MODE_POST_INIT)) {
3527 				bge_asf_post_reset_old_mode(bgep,
3528 					BGE_INIT_RESET);
3529 			} else {
3530 				bge_asf_post_reset_old_mode(bgep,
3531 					BGE_SHUTDOWN_RESET);
3532 			}
3533 		}
3534 #endif
3535 
3536 		/* Wait for NVRAM init */
3537 		i = 0;
3538 		drv_usecwait(5000);
3539 		mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX);
3540 
3541 		while ((mailbox != (uint32_t)
3542 			~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) &&
3543 			(i < 10000)) {
3544 			drv_usecwait(100);
3545 			mailbox = bge_nic_get32(bgep,
3546 				BGE_FIRMWARE_MAILBOX);
3547 			i++;
3548 		}
3549 
3550 #ifndef BGE_NETCONSOLE
3551 		if (!bgep->asf_newhandshake) {
3552 			if ((asf_mode == ASF_MODE_INIT) ||
3553 				(asf_mode == ASF_MODE_POST_INIT)) {
3554 
3555 				bge_asf_post_reset_old_mode(bgep,
3556 					BGE_INIT_RESET);
3557 			} else {
3558 				bge_asf_post_reset_old_mode(bgep,
3559 					BGE_SHUTDOWN_RESET);
3560 			}
3561 		}
3562 #endif
3563 	}
3564 #endif
3565 	/*
3566 	 * Steps 16-17: poll for firmware completion
3567 	 */
3568 	mac = bge_poll_firmware(bgep);
3569 
3570 	/*
3571 	 * Step 18: enable external memory -- doesn't apply.
3572 	 *
3573 	 * However we take the opportunity to set the MLCR anyway, as
3574 	 * this register also controls the SEEPROM auto-access method
3575 	 * which we may want to use later ...
3576 	 *
3577 	 * The proper value here depends on the way the chip is wired
3578 	 * into the circuit board, as this register *also* controls which
3579 	 * of the "Miscellaneous I/O" pins are driven as outputs and the
3580 	 * values driven onto those pins!
3581 	 *
3582 	 * See also step 74 in the PRM ...
3583 	 */
3584 	bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG,
3585 	    bgep->chipid.bge_mlcr_default);
3586 	bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
3587 
3588 	/*
3589 	 * Step 20: clear the Ethernet MAC mode register
3590 	 */
3591 	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0);
3592 
3593 	/*
3594 	 * Step 21: restore cache-line-size, latency timer, and
3595 	 * subsystem ID registers to their original values (not
3596 	 * those read into the local structure <chipid>, 'cos
3597 	 * that was after they were cleared by the RESET).
3598 	 *
3599 	 * Note: the Subsystem Vendor/Device ID registers are not
3600 	 * directly writable in config space, so we use the shadow
3601 	 * copy in "Page Zero" of register space to restore them
3602 	 * both in one go ...
3603 	 */
3604 	pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ,
3605 		bgep->chipid.clsize);
3606 	pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER,
3607 		bgep->chipid.latency);
3608 	bge_reg_put32(bgep, PCI_CONF_SUBVENID,
3609 		(bgep->chipid.subdev << 16) | bgep->chipid.subven);
3610 
3611 	/*
3612 	 * The SEND INDEX registers should be reset to zero by the
3613 	 * global chip reset; if they're not, there'll be trouble
3614 	 * later on.
3615 	 */
3616 	sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0));
3617 	if (sx0 != 0) {
3618 		BGE_REPORT((bgep, "SEND INDEX - device didn't RESET"));
3619 		bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE);
3620 		retval = DDI_FAILURE;
3621 	}
3622 
3623 	/* Enable MSI code */
3624 	if (bgep->intr_type == DDI_INTR_TYPE_MSI)
3625 		bge_reg_set32(bgep, MSI_MODE_REG,
3626 		    MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION);
3627 
3628 	/*
3629 	 * On the first time through, save the factory-set MAC address
3630 	 * (if any).  If bge_poll_firmware() above didn't return one
3631 	 * (from a chip register) consider looking in the attached NV
3632 	 * memory device, if any.  Once we have it, we save it in both
3633 	 * register-image (64-bit) and byte-array forms.  All-zero and
3634 	 * all-one addresses are not valid, and we refuse to stash those.
3635 	 */
3636 	if (bgep->bge_chip_state == BGE_CHIP_INITIAL) {
3637 		if (mac == 0ULL)
3638 			mac = bge_get_nvmac(bgep);
3639 		if (mac != 0ULL && mac != ~0ULL) {
3640 			bgep->chipid.hw_mac_addr = mac;
3641 			for (i = ETHERADDRL; i-- != 0; ) {
3642 				bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac;
3643 				mac >>= 8;
3644 			}
3645 			bgep->chipid.vendor_addr.set = B_TRUE;
3646 		}
3647 	}
3648 
3649 #ifdef BGE_IPMI_ASF
3650 	if (bgep->asf_enabled && bgep->asf_newhandshake) {
3651 		if (asf_mode != ASF_MODE_NONE) {
3652 			if ((asf_mode == ASF_MODE_INIT) ||
3653 				(asf_mode == ASF_MODE_POST_INIT)) {
3654 
3655 				bge_asf_post_reset_new_mode(bgep,
3656 					BGE_INIT_RESET);
3657 			} else {
3658 				bge_asf_post_reset_new_mode(bgep,
3659 					BGE_SHUTDOWN_RESET);
3660 			}
3661 		}
3662 	}
3663 #endif
3664 
3665 	/*
3666 	 * Record the new state
3667 	 */
3668 	bgep->chip_resets += 1;
3669 	bgep->bge_chip_state = BGE_CHIP_RESET;
3670 	return (retval);
3671 }
3672 
3673 /*
3674  * bge_chip_start() -- start the chip transmitting and/or receiving,
3675  * including enabling interrupts
3676  */
3677 int bge_chip_start(bge_t *bgep, boolean_t reset_phys);
3678 #pragma	no_inline(bge_chip_start)
3679 
3680 void
3681 bge_chip_coalesce_update(bge_t *bgep)
3682 {
3683 	bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG,
3684 	    bgep->chipid.tx_count_norm);
3685 	bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG,
3686 	    bgep->chipid.tx_ticks_norm);
3687 	bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG,
3688 	    bgep->chipid.rx_count_norm);
3689 	bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG,
3690 	    bgep->chipid.rx_ticks_norm);
3691 }
3692 
3693 int
3694 bge_chip_start(bge_t *bgep, boolean_t reset_phys)
3695 {
3696 	uint32_t coalmode;
3697 	uint32_t ledctl;
3698 	uint32_t mtu;
3699 	uint32_t maxring;
3700 	uint32_t stats_mask;
3701 	uint32_t dma_wrprio;
3702 	uint64_t ring;
3703 	uint32_t regval;
3704 	int retval = DDI_SUCCESS;
3705 
3706 	BGE_TRACE(("bge_chip_start($%p)",
3707 	    (void *)bgep));
3708 
3709 	ASSERT(mutex_owned(bgep->genlock));
3710 	ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET);
3711 
3712 	/*
3713 	 * Taken from Broadcom document 570X-PG102-R, pp 102-116.
3714 	 * The document specifies 95 separate steps to fully
3715 	 * initialise the chip!!!!
3716 	 *
3717 	 * The reset code above has already got us as far as step
3718 	 * 21, so we continue with ...
3719 	 *
3720 	 * Step 22: clear the MAC statistics block
3721 	 * (0x0300-0x0aff in NIC-local memory)
3722 	 */
3723 	if (bgep->chipid.statistic_type == BGE_STAT_BLK)
3724 		bge_nic_zero(bgep, NIC_MEM_STATISTICS,
3725 		    NIC_MEM_STATISTICS_SIZE);
3726 
3727 	/*
3728 	 * Step 23: clear the status block (in host memory)
3729 	 */
3730 	DMA_ZERO(bgep->status_block);
3731 
3732 	/*
3733 	 * Step 24: set DMA read/write control register
3734 	 */
3735 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR,
3736 	    bgep->chipid.bge_dma_rwctrl);
3737 
3738 	/*
3739 	 * Step 25: Configure DMA endianness -- already done (16/17)
3740 	 * Step 26: Configure Host-Based Send Rings
3741 	 * Step 27: Indicate Host Stack Up
3742 	 */
3743 	bge_reg_set32(bgep, MODE_CONTROL_REG,
3744 	    MODE_HOST_SEND_BDS |
3745 	    MODE_HOST_STACK_UP);
3746 
3747 	/*
3748 	 * Step 28: Configure checksum options:
3749 	 *	Solaris supports the hardware default checksum options.
3750 	 *
3751 	 *	Workaround for Incorrect pseudo-header checksum calculation.
3752 	 */
3753 	if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM)
3754 		bge_reg_set32(bgep, MODE_CONTROL_REG,
3755 		    MODE_SEND_NO_PSEUDO_HDR_CSUM);
3756 
3757 	/*
3758 	 * Step 29: configure Timer Prescaler.  The value is always the
3759 	 * same: the Core Clock frequency in MHz (66), minus 1, shifted
3760 	 * into bits 7-1.  Don't set bit 0, 'cos that's the RESET bit
3761 	 * for the whole chip!
3762 	 */
3763 	regval = bge_reg_get32(bgep, MISC_CONFIG_REG);
3764 	regval = (regval & 0xffffff00) | MISC_CONFIG_DEFAULT;
3765 	bge_reg_put32(bgep, MISC_CONFIG_REG, regval);
3766 
3767 	if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
3768 		drv_usecwait(40);
3769 		/* put PHY into ready state */
3770 		bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ);
3771 		(void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */
3772 		drv_usecwait(40);
3773 	}
3774 
3775 	/*
3776 	 * Steps 30-31: Configure MAC local memory pool & DMA pool registers
3777 	 *
3778 	 * If the mbuf_length is specified as 0, we just leave these at
3779 	 * their hardware defaults, rather than explicitly setting them.
3780 	 * As the Broadcom HRM,driver better not change the parameters
3781 	 * when the chipsets is 5705/5788/5721/5751/5714 and 5715.
3782 	 */
3783 	if ((bgep->chipid.mbuf_length != 0) &&
3784 	    (DEVICE_5704_SERIES_CHIPSETS(bgep))) {
3785 			bge_reg_put32(bgep, MBUF_POOL_BASE_REG,
3786 			    bgep->chipid.mbuf_base);
3787 			bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG,
3788 			    bgep->chipid.mbuf_length);
3789 			bge_reg_put32(bgep, DMAD_POOL_BASE_REG,
3790 			    DMAD_POOL_BASE_DEFAULT);
3791 			bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG,
3792 			    DMAD_POOL_LENGTH_DEFAULT);
3793 	}
3794 
3795 	/*
3796 	 * Step 32: configure MAC memory pool watermarks
3797 	 */
3798 	bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG,
3799 	    bgep->chipid.mbuf_lo_water_rdma);
3800 	bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG,
3801 	    bgep->chipid.mbuf_lo_water_rmac);
3802 	bge_reg_put32(bgep, MBUF_HIWAT_REG,
3803 	    bgep->chipid.mbuf_hi_water);
3804 
3805 	/*
3806 	 * Step 33: configure DMA resource watermarks
3807 	 */
3808 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3809 		bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG,
3810 		    bge_dmad_lo_water);
3811 		bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG,
3812 		    bge_dmad_hi_water);
3813 	}
3814 	bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames);
3815 
3816 	/*
3817 	 * Steps 34-36: enable buffer manager & internal h/w queues
3818 	 */
3819 	if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG,
3820 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3821 		retval = DDI_FAILURE;
3822 	if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0))
3823 		retval = DDI_FAILURE;
3824 
3825 	/*
3826 	 * Steps 37-39: initialise Receive Buffer (Producer) RCBs
3827 	 */
3828 	if (DEVICE_5717_SERIES_CHIPSETS(bgep)) {
3829 		buff_ring_t *brp = &bgep->buff[BGE_STD_BUFF_RING];
3830 		bge_reg_put64(bgep, STD_RCV_BD_RING_RCB_REG,
3831 		    brp->desc.cookie.dmac_laddress);
3832 		bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 8,
3833 		    (brp->desc.nslots) << 16 | brp->buf[0].size << 2);
3834 		bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc,
3835 		    NIC_MEM_SHADOW_BUFF_STD_5717);
3836 	} else
3837 		bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG,
3838 		    &bgep->buff[BGE_STD_BUFF_RING].hw_rcb);
3839 
3840 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3841 		bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG,
3842 		    &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb);
3843 		bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG,
3844 		    &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb);
3845 	}
3846 
3847 	/*
3848 	 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds
3849 	 */
3850 	bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std);
3851 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3852 		bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG,
3853 		    bge_replenish_jumbo);
3854 		bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG,
3855 		    bge_replenish_mini);
3856 	}
3857 
3858 	/*
3859 	 * Steps 41-43: clear Send Ring Producer Indices and initialise
3860 	 * Send Producer Rings (0x0100-0x01ff in NIC-local memory)
3861 	 */
3862 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3863 		maxring = BGE_SEND_RINGS_MAX;
3864 	else
3865 		maxring = BGE_SEND_RINGS_MAX_5705;
3866 	for (ring = 0; ring < maxring; ++ring) {
3867 		bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0);
3868 		bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0);
3869 		bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring),
3870 		    &bgep->send[ring].hw_rcb);
3871 	}
3872 
3873 	/*
3874 	 * Steps 44-45: initialise Receive Return Rings
3875 	 * (0x0200-0x02ff in NIC-local memory)
3876 	 */
3877 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3878 		maxring = BGE_RECV_RINGS_MAX;
3879 	else
3880 		maxring = BGE_RECV_RINGS_MAX_5705;
3881 	for (ring = 0; ring < maxring; ++ring)
3882 		bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring),
3883 		    &bgep->recv[ring].hw_rcb);
3884 
3885 	/*
3886 	 * Step 46: initialise Receive Buffer (Producer) Ring indexes
3887 	 */
3888 	bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0);
3889 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3890 		bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0);
3891 		bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0);
3892 	}
3893 	/*
3894 	 * Step 47: configure the MAC unicast address
3895 	 * Step 48: configure the random backoff seed
3896 	 * Step 96: set up multicast filters
3897 	 */
3898 #ifdef BGE_IPMI_ASF
3899 	if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE)
3900 #else
3901 	if (bge_chip_sync(bgep) == DDI_FAILURE)
3902 #endif
3903 		retval = DDI_FAILURE;
3904 
3905 	/*
3906 	 * Step 49: configure the MTU
3907 	 */
3908 	mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ;
3909 	bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu);
3910 
3911 	/*
3912 	 * Step 50: configure the IPG et al
3913 	 */
3914 	bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT);
3915 
3916 	/*
3917 	 * Step 51: configure the default Rx Return Ring
3918 	 */
3919 	bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT);
3920 
3921 	/*
3922 	 * Steps 52-54: configure Receive List Placement,
3923 	 * and enable Receive List Placement Statistics
3924 	 */
3925 	bge_reg_put32(bgep, RCV_LP_CONFIG_REG,
3926 	    RCV_LP_CONFIG(bgep->chipid.rx_rings));
3927 	switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) {
3928 	case MHCR_CHIP_ASIC_REV_5700:
3929 	case MHCR_CHIP_ASIC_REV_5701:
3930 	case MHCR_CHIP_ASIC_REV_5703:
3931 	case MHCR_CHIP_ASIC_REV_5704:
3932 		bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0);
3933 		break;
3934 	case MHCR_CHIP_ASIC_REV_5705:
3935 		break;
3936 	default:
3937 		stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG);
3938 		stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ;
3939 		bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask);
3940 		break;
3941 	}
3942 	bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE);
3943 
3944 	if (bgep->chipid.rx_rings > 1)
3945 		bge_init_recv_rule(bgep);
3946 
3947 	/*
3948 	 * Steps 55-56: enable Send Data Initiator Statistics
3949 	 */
3950 	bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0);
3951 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3952 		bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3953 		    SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER);
3954 	} else {
3955 		bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3956 		    SEND_INIT_STATS_ENABLE);
3957 	}
3958 	/*
3959 	 * Steps 57-58: stop (?) the Host Coalescing Engine
3960 	 */
3961 	if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0))
3962 		retval = DDI_FAILURE;
3963 
3964 	/*
3965 	 * Steps 59-62: initialise Host Coalescing parameters
3966 	 */
3967 	bge_chip_coalesce_update(bgep);
3968 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3969 		bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG,
3970 		    bge_tx_count_intr);
3971 		bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG,
3972 		    bge_tx_ticks_intr);
3973 		bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG,
3974 		    bge_rx_count_intr);
3975 		bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG,
3976 		    bge_rx_ticks_intr);
3977 	}
3978 
3979 	/*
3980 	 * Steps 63-64: initialise status block & statistics
3981 	 * host memory addresses
3982 	 * The statistic block does not exist in some chipsets
3983 	 * Step 65: initialise Statistics Coalescing Tick Counter
3984 	 */
3985 	bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG,
3986 	    bgep->status_block.cookie.dmac_laddress);
3987 
3988 	/*
3989 	 * Steps 66-67: initialise status block & statistics
3990 	 * NIC-local memory addresses
3991 	 */
3992 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3993 		bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG,
3994 		    bgep->statistics.cookie.dmac_laddress);
3995 		bge_reg_put32(bgep, STATISTICS_TICKS_REG,
3996 		    STATISTICS_TICKS_DEFAULT);
3997 		bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG,
3998 		    NIC_MEM_STATUS_BLOCK);
3999 		bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG,
4000 		    NIC_MEM_STATISTICS);
4001 	}
4002 
4003 	/*
4004 	 * Steps 68-71: start the Host Coalescing Engine, the Receive BD
4005 	 * Completion Engine, the Receive List Placement Engine, and the
4006 	 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714
4007 	 * and BCM5715.
4008 	 */
4009 	if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS &&
4010 	    bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS)
4011 		coalmode = COALESCE_64_BYTE_STATUS;
4012 	else
4013 		coalmode = 0;
4014 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
4015 		coalmode = COALESCE_CLR_TICKS_RX;
4016 	if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode))
4017 		retval = DDI_FAILURE;
4018 	if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG,
4019 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4020 		retval = DDI_FAILURE;
4021 	if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0))
4022 		retval = DDI_FAILURE;
4023 
4024 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4025 		if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG,
4026 		    STATE_MACHINE_ATTN_ENABLE_BIT))
4027 			retval = DDI_FAILURE;
4028 
4029 	/*
4030 	 * Step 72: Enable MAC DMA engines
4031 	 * Step 73: Clear & enable MAC statistics
4032 	 */
4033 	bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
4034 	    ETHERNET_MODE_ENABLE_FHDE |
4035 	    ETHERNET_MODE_ENABLE_RDE |
4036 	    ETHERNET_MODE_ENABLE_TDE);
4037 	bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
4038 	    ETHERNET_MODE_ENABLE_TX_STATS |
4039 	    ETHERNET_MODE_ENABLE_RX_STATS |
4040 	    ETHERNET_MODE_CLEAR_TX_STATS |
4041 	    ETHERNET_MODE_CLEAR_RX_STATS);
4042 
4043 	/*
4044 	 * Step 74: configure the MLCR (Miscellaneous Local Control
4045 	 * Register); not required, as we set up the MLCR in step 10
4046 	 * (part of the reset code) above.
4047 	 *
4048 	 * Step 75: clear Interrupt Mailbox 0
4049 	 */
4050 	bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0);
4051 
4052 	/*
4053 	 * Steps 76-87: Gentlemen, start your engines ...
4054 	 *
4055 	 * Enable the DMA Completion Engine, the Write DMA Engine,
4056 	 * the Read DMA Engine, Receive Data Completion Engine,
4057 	 * the MBuf Cluster Free Engine, the Send Data Completion Engine,
4058 	 * the Send BD Completion Engine, the Receive BD Initiator Engine,
4059 	 * the Receive Data Initiator Engine, the Send Data Initiator Engine,
4060 	 * the Send BD Initiator Engine, and the Send BD Selector Engine.
4061 	 *
4062 	 * Beware exhaust fumes?
4063 	 */
4064 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4065 		if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0))
4066 			retval = DDI_FAILURE;
4067 	dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) |
4068 	    ALL_DMA_ATTN_BITS;
4069 	if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4070 	    MHCR_CHIP_ASIC_REV_5755) ||
4071 	    (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4072 	    MHCR_CHIP_ASIC_REV_5723) ||
4073 	    (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4074 	    MHCR_CHIP_ASIC_REV_5906)) {
4075 		dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384;
4076 	}
4077 	if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG,
4078 	    dma_wrprio))
4079 		retval = DDI_FAILURE;
4080 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
4081 	    DEVICE_5717_SERIES_CHIPSETS(bgep))
4082 		bge_dma_rdprio = 0;
4083 	if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG,
4084 	    (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS))
4085 		retval = DDI_FAILURE;
4086 	if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG,
4087 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4088 		retval = DDI_FAILURE;
4089 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4090 		if (!bge_chip_enable_engine(bgep,
4091 		    MBUF_CLUSTER_FREE_MODE_REG, 0))
4092 			retval = DDI_FAILURE;
4093 	if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0))
4094 		retval = DDI_FAILURE;
4095 	if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG,
4096 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4097 		retval = DDI_FAILURE;
4098 	if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG,
4099 	    RCV_BD_DISABLED_RING_ATTN))
4100 		retval = DDI_FAILURE;
4101 	if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG,
4102 	    RCV_DATA_BD_ILL_RING_ATTN))
4103 		retval = DDI_FAILURE;
4104 	if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0))
4105 		retval = DDI_FAILURE;
4106 	if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG,
4107 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4108 		retval = DDI_FAILURE;
4109 	if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG,
4110 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4111 		retval = DDI_FAILURE;
4112 
4113 	/*
4114 	 * Step 88: download firmware -- doesn't apply
4115 	 * Steps 89-90: enable Transmit & Receive MAC Engines
4116 	 */
4117 	if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
4118 		retval = DDI_FAILURE;
4119 #ifdef BGE_IPMI_ASF
4120 	if (!bgep->asf_enabled) {
4121 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
4122 		    RECEIVE_MODE_KEEP_VLAN_TAG))
4123 			retval = DDI_FAILURE;
4124 	} else {
4125 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0))
4126 			retval = DDI_FAILURE;
4127 	}
4128 #else
4129 	if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
4130 	    RECEIVE_MODE_KEEP_VLAN_TAG))
4131 		retval = DDI_FAILURE;
4132 #endif
4133 
4134 	/*
4135 	 * Step 91: disable auto-polling of PHY status
4136 	 */
4137 	bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT);
4138 
4139 	/*
4140 	 * Step 92: configure D0 power state (not required)
4141 	 * Step 93: initialise LED control register ()
4142 	 */
4143 	ledctl = LED_CONTROL_DEFAULT;
4144 	switch (bgep->chipid.device) {
4145 	case DEVICE_ID_5700:
4146 	case DEVICE_ID_5700x:
4147 	case DEVICE_ID_5701:
4148 		/*
4149 		 * Switch to 5700 (MAC) mode on these older chips
4150 		 */
4151 		ledctl &= ~LED_CONTROL_LED_MODE_MASK;
4152 		ledctl |= LED_CONTROL_LED_MODE_5700;
4153 		break;
4154 
4155 	default:
4156 		break;
4157 	}
4158 	bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl);
4159 
4160 	/*
4161 	 * Step 94: activate link
4162 	 */
4163 	bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
4164 
4165 	/*
4166 	 * Step 95: set up physical layer (PHY/SerDes)
4167 	 * restart autoneg (if required)
4168 	 */
4169 	if (reset_phys)
4170 		if (bge_phys_update(bgep) == DDI_FAILURE)
4171 			retval = DDI_FAILURE;
4172 
4173 	/*
4174 	 * Extra step (DSG): hand over all the Receive Buffers to the chip
4175 	 */
4176 	for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring)
4177 		bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg,
4178 		    bgep->buff[ring].rf_next);
4179 
4180 	/*
4181 	 * MSI bits:The least significant MSI 16-bit word.
4182 	 * ISR will be triggered different.
4183 	 */
4184 	if (bgep->intr_type == DDI_INTR_TYPE_MSI)
4185 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70);
4186 
4187 	/*
4188 	 * Extra step (DSG): select which interrupts are enabled
4189 	 *
4190 	 * Program the Ethernet MAC engine to signal attention on
4191 	 * Link Change events, then enable interrupts on MAC, DMA,
4192 	 * and FLOW attention signals.
4193 	 */
4194 	bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG,
4195 	    ETHERNET_EVENT_LINK_INT |
4196 	    ETHERNET_STATUS_PCS_ERROR_INT);
4197 #ifdef BGE_IPMI_ASF
4198 	if (bgep->asf_enabled) {
4199 		bge_reg_set32(bgep, MODE_CONTROL_REG,
4200 		    MODE_INT_ON_FLOW_ATTN |
4201 		    MODE_INT_ON_DMA_ATTN |
4202 		    MODE_HOST_STACK_UP|
4203 		    MODE_INT_ON_MAC_ATTN);
4204 	} else {
4205 #endif
4206 		bge_reg_set32(bgep, MODE_CONTROL_REG,
4207 		    MODE_INT_ON_FLOW_ATTN |
4208 		    MODE_INT_ON_DMA_ATTN |
4209 		    MODE_INT_ON_MAC_ATTN);
4210 #ifdef BGE_IPMI_ASF
4211 	}
4212 #endif
4213 
4214 	/*
4215 	 * Step 97: enable PCI interrupts!!!
4216 	 */
4217 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
4218 		bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR,
4219 		    bgep->chipid.mask_pci_int);
4220 
4221 	/*
4222 	 * All done!
4223 	 */
4224 	bgep->bge_chip_state = BGE_CHIP_RUNNING;
4225 	return (retval);
4226 }
4227 
4228 
4229 /*
4230  * ========== Hardware interrupt handler ==========
4231  */
4232 
4233 #undef	BGE_DBG
4234 #define	BGE_DBG		BGE_DBG_INT	/* debug flag for this code	*/
4235 
4236 /*
4237  * Sync the status block, then atomically clear the specified bits in
4238  * the <flags-and-tag> field of the status block.
4239  * the <flags> word of the status block, returning the value of the
4240  * <tag> and the <flags> before the bits were cleared.
4241  */
4242 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags);
4243 #pragma	inline(bge_status_sync)
4244 
4245 static int
4246 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags)
4247 {
4248 	bge_status_t *bsp;
4249 	int retval;
4250 
4251 	BGE_TRACE(("bge_status_sync($%p, 0x%llx)",
4252 	    (void *)bgep, bits));
4253 
4254 	ASSERT(bgep->bge_guard == BGE_GUARD);
4255 
4256 	DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL);
4257 	retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl);
4258 	if (retval != DDI_FM_OK)
4259 		return (retval);
4260 
4261 	bsp = DMA_VPTR(bgep->status_block);
4262 	*flags = bge_atomic_clr64(&bsp->flags_n_tag, bits);
4263 
4264 	BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx",
4265 	    (void *)bgep, bits, *flags));
4266 
4267 	return (retval);
4268 }
4269 
4270 void bge_wake_factotum(bge_t *bgep);
4271 #pragma	inline(bge_wake_factotum)
4272 
4273 void
4274 bge_wake_factotum(bge_t *bgep)
4275 {
4276 	mutex_enter(bgep->softintrlock);
4277 	if (bgep->factotum_flag == 0) {
4278 		bgep->factotum_flag = 1;
4279 		ddi_trigger_softintr(bgep->factotum_id);
4280 	}
4281 	mutex_exit(bgep->softintrlock);
4282 }
4283 
4284 /*
4285  *	bge_intr() -- handle chip interrupts
4286  */
4287 uint_t bge_intr(caddr_t arg1, caddr_t arg2);
4288 #pragma	no_inline(bge_intr)
4289 
4290 uint_t
4291 bge_intr(caddr_t arg1, caddr_t arg2)
4292 {
4293 	bge_t *bgep = (void *)arg1;		/* private device info	*/
4294 	bge_status_t *bsp;
4295 	uint64_t flags;
4296 	uint32_t regval;
4297 	uint_t result;
4298 	int retval, loop_cnt = 0;
4299 
4300 	BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2));
4301 
4302 	/*
4303 	 * GLD v2 checks that s/w setup is complete before passing
4304 	 * interrupts to this routine, thus eliminating the old
4305 	 * (and well-known) race condition around ddi_add_intr()
4306 	 */
4307 	ASSERT(bgep->progress & PROGRESS_HWINT);
4308 
4309 	result = DDI_INTR_UNCLAIMED;
4310 	mutex_enter(bgep->genlock);
4311 
4312 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
4313 		/*
4314 		 * Check whether chip's says it's asserting #INTA;
4315 		 * if not, don't process or claim the interrupt.
4316 		 *
4317 		 * Note that the PCI signal is active low, so the
4318 		 * bit is *zero* when the interrupt is asserted.
4319 		 */
4320 		regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
4321 		if (!(DEVICE_5717_SERIES_CHIPSETS(bgep)) &&
4322 		    (regval & MLCR_INTA_STATE)) {
4323 			if (bge_check_acc_handle(bgep, bgep->io_handle)
4324 			    != DDI_FM_OK)
4325 				goto chip_stop;
4326 			mutex_exit(bgep->genlock);
4327 			return (result);
4328 		}
4329 
4330 		/*
4331 		 * Block further PCI interrupts ...
4332 		 */
4333 		bge_reg_set32(bgep, PCI_CONF_BGE_MHCR,
4334 		    bgep->chipid.mask_pci_int);
4335 
4336 	} else {
4337 		/*
4338 		 * Check MSI status
4339 		 */
4340 		regval = bge_reg_get32(bgep, MSI_STATUS_REG);
4341 		if (regval & MSI_ERROR_ATTENTION) {
4342 			BGE_REPORT((bgep, "msi error attention,"
4343 			    " status=0x%x", regval));
4344 			bge_reg_put32(bgep, MSI_STATUS_REG, regval);
4345 		}
4346 	}
4347 
4348 	result = DDI_INTR_CLAIMED;
4349 
4350 	BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval));
4351 
4352 	/*
4353 	 * Sync the status block and grab the flags-n-tag from it.
4354 	 * We count the number of interrupts where there doesn't
4355 	 * seem to have been a DMA update of the status block; if
4356 	 * it *has* been updated, the counter will be cleared in
4357 	 * the while() loop below ...
4358 	 */
4359 	bgep->missed_dmas += 1;
4360 	bsp = DMA_VPTR(bgep->status_block);
4361 	for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) {
4362 		if (bgep->bge_chip_state != BGE_CHIP_RUNNING) {
4363 			/*
4364 			 * bge_chip_stop() may have freed dma area etc
4365 			 * while we were in this interrupt handler -
4366 			 * better not call bge_status_sync()
4367 			 */
4368 			(void) bge_check_acc_handle(bgep,
4369 			    bgep->io_handle);
4370 			mutex_exit(bgep->genlock);
4371 			return (DDI_INTR_CLAIMED);
4372 		}
4373 		retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED,
4374 		    &flags);
4375 		if (retval != DDI_FM_OK) {
4376 			bgep->bge_dma_error = B_TRUE;
4377 			goto chip_stop;
4378 		}
4379 
4380 		if (!(flags & STATUS_FLAG_UPDATED))
4381 			break;
4382 
4383 		/*
4384 		 * Tell the chip that we're processing the interrupt
4385 		 */
4386 		bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
4387 		    INTERRUPT_MBOX_DISABLE(flags));
4388 		if (bge_check_acc_handle(bgep, bgep->io_handle) !=
4389 		    DDI_FM_OK)
4390 			goto chip_stop;
4391 
4392 		/*
4393 		 * Drop the mutex while we:
4394 		 * 	Receive any newly-arrived packets
4395 		 *	Recycle any newly-finished send buffers
4396 		 */
4397 		bgep->bge_intr_running = B_TRUE;
4398 		mutex_exit(bgep->genlock);
4399 		bge_receive(bgep, bsp);
4400 		(void) bge_recycle(bgep, bsp);
4401 		mutex_enter(bgep->genlock);
4402 		bgep->bge_intr_running = B_FALSE;
4403 
4404 		/*
4405 		 * Tell the chip we've finished processing, and
4406 		 * give it the tag that we got from the status
4407 		 * block earlier, so that it knows just how far
4408 		 * we've gone.  If it's got more for us to do,
4409 		 * it will now update the status block and try
4410 		 * to assert an interrupt (but we've got the
4411 		 * #INTA blocked at present).  If we see the
4412 		 * update, we'll loop around to do some more.
4413 		 * Eventually we'll get out of here ...
4414 		 */
4415 		bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
4416 		    INTERRUPT_MBOX_ENABLE(flags));
4417 		if (bgep->chipid.pci_type == BGE_PCI_E)
4418 			(void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG);
4419 		bgep->missed_dmas = 0;
4420 	}
4421 
4422 	/*
4423 	 * Check for exceptional conditions that we need to handle
4424 	 *
4425 	 * Link status changed
4426 	 * Status block not updated
4427 	 */
4428 	if (flags & STATUS_FLAG_LINK_CHANGED)
4429 		bge_wake_factotum(bgep);
4430 
4431 	if (bgep->missed_dmas) {
4432 		/*
4433 		 * Probably due to the internal status tag not
4434 		 * being reset.  Force a status block update now;
4435 		 * this should ensure that we get an update and
4436 		 * a new interrupt.  After that, we should be in
4437 		 * sync again ...
4438 		 */
4439 		BGE_REPORT((bgep, "interrupt: flags 0x%llx - "
4440 		    "not updated?", flags));
4441 		bgep->missed_updates++;
4442 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG,
4443 		    COALESCE_NOW);
4444 
4445 		if (bgep->missed_dmas >= bge_dma_miss_limit) {
4446 			/*
4447 			 * If this happens multiple times in a row,
4448 			 * it means DMA is just not working.  Maybe
4449 			 * the chip's failed, or maybe there's a
4450 			 * problem on the PCI bus or in the host-PCI
4451 			 * bridge (Tomatillo).
4452 			 *
4453 			 * At all events, we want to stop further
4454 			 * interrupts and let the recovery code take
4455 			 * over to see whether anything can be done
4456 			 * about it ...
4457 			 */
4458 			bge_fm_ereport(bgep,
4459 			    DDI_FM_DEVICE_BADINT_LIMIT);
4460 			goto chip_stop;
4461 		}
4462 	}
4463 
4464 	/*
4465 	 * Reenable assertion of #INTA, unless there's a DMA fault
4466 	 */
4467 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
4468 		bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR,
4469 		    bgep->chipid.mask_pci_int);
4470 		if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
4471 		    DDI_FM_OK)
4472 			goto chip_stop;
4473 	}
4474 
4475 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4476 		goto chip_stop;
4477 
4478 	mutex_exit(bgep->genlock);
4479 	return (result);
4480 
4481 chip_stop:
4482 #ifdef BGE_IPMI_ASF
4483 	if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) {
4484 		/*
4485 		 * We must stop ASF heart beat before
4486 		 * bge_chip_stop(), otherwise some
4487 		 * computers (ex. IBM HS20 blade
4488 		 * server) may crash.
4489 		 */
4490 		bge_asf_update_status(bgep);
4491 		bge_asf_stop_timer(bgep);
4492 		bgep->asf_status = ASF_STAT_STOP;
4493 
4494 		bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
4495 		(void) bge_check_acc_handle(bgep, bgep->cfg_handle);
4496 	}
4497 #endif
4498 	bge_chip_stop(bgep, B_TRUE);
4499 	(void) bge_check_acc_handle(bgep, bgep->io_handle);
4500 	mutex_exit(bgep->genlock);
4501 	return (result);
4502 }
4503 
4504 /*
4505  * ========== Factotum, implemented as a softint handler ==========
4506  */
4507 
4508 #undef	BGE_DBG
4509 #define	BGE_DBG		BGE_DBG_FACT	/* debug flag for this code	*/
4510 
4511 static void bge_factotum_error_handler(bge_t *bgep);
4512 #pragma	no_inline(bge_factotum_error_handler)
4513 
4514 static void
4515 bge_factotum_error_handler(bge_t *bgep)
4516 {
4517 	uint32_t flow;
4518 	uint32_t rdma;
4519 	uint32_t wdma;
4520 	uint32_t tmac;
4521 	uint32_t rmac;
4522 	uint32_t rxrs;
4523 	uint32_t txrs = 0;
4524 
4525 	ASSERT(mutex_owned(bgep->genlock));
4526 
4527 	/*
4528 	 * Read all the registers that show the possible
4529 	 * reasons for the ERROR bit to be asserted
4530 	 */
4531 	flow = bge_reg_get32(bgep, FLOW_ATTN_REG);
4532 	rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG);
4533 	wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG);
4534 	tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
4535 	rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG);
4536 	rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG);
4537 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4538 		txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG);
4539 
4540 	BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x",
4541 	    (void *)bgep, flow, rdma, wdma));
4542 	BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x",
4543 	    (void *)bgep, tmac, rmac, rxrs, txrs));
4544 
4545 	/*
4546 	 * For now, just clear all the errors ...
4547 	 */
4548 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4549 		bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0);
4550 	bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0);
4551 	bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0);
4552 	bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0);
4553 	bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0);
4554 	bge_reg_put32(bgep, FLOW_ATTN_REG, ~0);
4555 }
4556 
4557 /*
4558  * Handler for hardware link state change.
4559  *
4560  * When this routine is called, the hardware link state has changed
4561  * and the new state is reflected in the param_* variables.  Here
4562  * we must update the softstate and reprogram the MAC to match.
4563  */
4564 static void bge_factotum_link_handler(bge_t *bgep);
4565 #pragma	no_inline(bge_factotum_link_handler)
4566 
4567 static void
4568 bge_factotum_link_handler(bge_t *bgep)
4569 {
4570 	ASSERT(mutex_owned(bgep->genlock));
4571 
4572 	/*
4573 	 * Update the s/w link_state
4574 	 */
4575 	if (bgep->param_link_up)
4576 		bgep->link_state = LINK_STATE_UP;
4577 	else
4578 		bgep->link_state = LINK_STATE_DOWN;
4579 
4580 	/*
4581 	 * Reprogram the MAC modes to match
4582 	 */
4583 	bge_sync_mac_modes(bgep);
4584 }
4585 
4586 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state);
4587 #pragma	no_inline(bge_factotum_link_check)
4588 
4589 static boolean_t
4590 bge_factotum_link_check(bge_t *bgep, int *dma_state)
4591 {
4592 	boolean_t check;
4593 	uint64_t flags;
4594 	uint32_t tmac_status;
4595 
4596 	ASSERT(mutex_owned(bgep->genlock));
4597 
4598 	/*
4599 	 * Get & clear the writable status bits in the Tx status register
4600 	 * (some bits are write-1-to-clear, others are just readonly).
4601 	 */
4602 	tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
4603 	bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status);
4604 
4605 	/*
4606 	 * Get & clear the ERROR and LINK_CHANGED bits from the status block
4607 	 */
4608 	*dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR |
4609 	    STATUS_FLAG_LINK_CHANGED, &flags);
4610 	if (*dma_state != DDI_FM_OK)
4611 		return (B_FALSE);
4612 
4613 	/*
4614 	 * Clear any errors flagged in the status block ...
4615 	 */
4616 	if (flags & STATUS_FLAG_ERROR)
4617 		bge_factotum_error_handler(bgep);
4618 
4619 	/*
4620 	 * We need to check the link status if:
4621 	 *	the status block says there's been a link change
4622 	 *	or there's any discrepancy between the various
4623 	 *	flags indicating the link state (link_state,
4624 	 *	param_link_up, and the LINK STATE bit in the
4625 	 *	Transmit MAC status register).
4626 	 */
4627 	check = (flags & STATUS_FLAG_LINK_CHANGED) != 0;
4628 	switch (bgep->link_state) {
4629 	case LINK_STATE_UP:
4630 		check |= (bgep->param_link_up == B_FALSE);
4631 		check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0);
4632 		break;
4633 
4634 	case LINK_STATE_DOWN:
4635 		check |= (bgep->param_link_up != B_FALSE);
4636 		check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0);
4637 		break;
4638 
4639 	default:
4640 		check = B_TRUE;
4641 		break;
4642 	}
4643 
4644 	/*
4645 	 * If <check> is false, we're sure the link hasn't changed.
4646 	 * If true, however, it's not yet definitive; we have to call
4647 	 * bge_phys_check() to determine whether the link has settled
4648 	 * into a new state yet ... and if it has, then call the link
4649 	 * state change handler.But when the chip is 5700 in Dell 6650
4650 	 * ,even if check is false, the link may have changed.So we
4651 	 * have to call bge_phys_check() to determine the link state.
4652 	 */
4653 	if (check || bgep->chipid.device == DEVICE_ID_5700) {
4654 		check = bge_phys_check(bgep);
4655 		if (check)
4656 			bge_factotum_link_handler(bgep);
4657 	}
4658 
4659 	return (check);
4660 }
4661 
4662 /*
4663  * Factotum routine to check for Tx stall, using the 'watchdog' counter
4664  */
4665 static boolean_t bge_factotum_stall_check(bge_t *bgep);
4666 #pragma	no_inline(bge_factotum_stall_check)
4667 
4668 static boolean_t
4669 bge_factotum_stall_check(bge_t *bgep)
4670 {
4671 	uint32_t dogval;
4672 	bge_status_t *bsp;
4673 	uint64_t now = gethrtime();
4674 
4675 	if ((now - bgep->timestamp) < BGE_CYCLIC_PERIOD)
4676 		return (B_FALSE);
4677 
4678 	bgep->timestamp = now;
4679 
4680 	ASSERT(mutex_owned(bgep->genlock));
4681 
4682 	/*
4683 	 * Specific check for Tx stall ...
4684 	 *
4685 	 * The 'watchdog' counter is incremented whenever a packet
4686 	 * is queued, reset to 1 when some (but not all) buffers
4687 	 * are reclaimed, reset to 0 (disabled) when all buffers
4688 	 * are reclaimed, and shifted left here.  If it exceeds the
4689 	 * threshold value, the chip is assumed to have stalled and
4690 	 * is put into the ERROR state.  The factotum will then reset
4691 	 * it on the next pass.
4692 	 *
4693 	 * All of which should ensure that we don't get into a state
4694 	 * where packets are left pending indefinitely!
4695 	 */
4696 	dogval = bge_atomic_shl32(&bgep->watchdog, 1);
4697 	bsp = DMA_VPTR(bgep->status_block);
4698 	if (dogval < bge_watchdog_count || bge_recycle(bgep, bsp))
4699 		return (B_FALSE);
4700 
4701 #if !defined(BGE_NETCONSOLE)
4702 	BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval));
4703 #endif
4704 	bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL);
4705 	return (B_TRUE);
4706 }
4707 
4708 /*
4709  * The factotum is woken up when there's something to do that we'd rather
4710  * not do from inside a hardware interrupt handler or high-level cyclic.
4711  * Its two main tasks are:
4712  *	reset & restart the chip after an error
4713  *	check the link status whenever necessary
4714  */
4715 uint_t bge_chip_factotum(caddr_t arg);
4716 #pragma	no_inline(bge_chip_factotum)
4717 
4718 uint_t
4719 bge_chip_factotum(caddr_t arg)
4720 {
4721 	bge_t *bgep;
4722 	uint_t result;
4723 	boolean_t error;
4724 	boolean_t linkchg;
4725 	int dma_state;
4726 
4727 	bgep = (void *)arg;
4728 
4729 	BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep));
4730 
4731 	mutex_enter(bgep->softintrlock);
4732 	if (bgep->factotum_flag == 0) {
4733 		mutex_exit(bgep->softintrlock);
4734 		return (DDI_INTR_UNCLAIMED);
4735 	}
4736 	bgep->factotum_flag = 0;
4737 	mutex_exit(bgep->softintrlock);
4738 
4739 	result = DDI_INTR_CLAIMED;
4740 	error = B_FALSE;
4741 	linkchg = B_FALSE;
4742 
4743 	mutex_enter(bgep->genlock);
4744 	switch (bgep->bge_chip_state) {
4745 	default:
4746 		break;
4747 
4748 	case BGE_CHIP_RUNNING:
4749 		linkchg = bge_factotum_link_check(bgep, &dma_state);
4750 		error = bge_factotum_stall_check(bgep);
4751 		if (dma_state != DDI_FM_OK) {
4752 			bgep->bge_dma_error = B_TRUE;
4753 			error = B_TRUE;
4754 		}
4755 		if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4756 			error = B_TRUE;
4757 		if (error)
4758 			bgep->bge_chip_state = BGE_CHIP_ERROR;
4759 		break;
4760 
4761 	case BGE_CHIP_ERROR:
4762 		error = B_TRUE;
4763 		break;
4764 
4765 	case BGE_CHIP_FAULT:
4766 		/*
4767 		 * Fault detected, time to reset ...
4768 		 */
4769 		if (bge_autorecover) {
4770 			if (!(bgep->progress & PROGRESS_BUFS)) {
4771 				/*
4772 				 * if we can't allocate the ring buffers,
4773 				 * try later
4774 				 */
4775 				if (bge_alloc_bufs(bgep) != DDI_SUCCESS) {
4776 					mutex_exit(bgep->genlock);
4777 					return (result);
4778 				}
4779 				bgep->progress |= PROGRESS_BUFS;
4780 			}
4781 			if (!(bgep->progress & PROGRESS_INTR)) {
4782 				bge_init_rings(bgep);
4783 				bge_intr_enable(bgep);
4784 				bgep->progress |= PROGRESS_INTR;
4785 			}
4786 			if (!(bgep->progress & PROGRESS_KSTATS)) {
4787 				bge_init_kstats(bgep,
4788 				    ddi_get_instance(bgep->devinfo));
4789 				bgep->progress |= PROGRESS_KSTATS;
4790 			}
4791 
4792 			BGE_REPORT((bgep, "automatic recovery activated"));
4793 
4794 			if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) {
4795 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4796 				error = B_TRUE;
4797 			}
4798 			if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
4799 			    DDI_FM_OK) {
4800 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4801 				error = B_TRUE;
4802 			}
4803 			if (bge_check_acc_handle(bgep, bgep->io_handle) !=
4804 			    DDI_FM_OK) {
4805 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4806 				error = B_TRUE;
4807 			}
4808 			if (error == B_FALSE) {
4809 #ifdef BGE_IPMI_ASF
4810 				if (bgep->asf_enabled &&
4811 				    bgep->asf_status != ASF_STAT_RUN) {
4812 					bgep->asf_timeout_id = timeout(
4813 					    bge_asf_heartbeat, (void *)bgep,
4814 					    drv_usectohz(
4815 					    BGE_ASF_HEARTBEAT_INTERVAL));
4816 					bgep->asf_status = ASF_STAT_RUN;
4817 				}
4818 #endif
4819 				if (!bgep->manual_reset) {
4820 					ddi_fm_service_impact(bgep->devinfo,
4821 					    DDI_SERVICE_RESTORED);
4822 				}
4823 			}
4824 		}
4825 		break;
4826 	}
4827 
4828 
4829 	/*
4830 	 * If an error is detected, stop the chip now, marking it as
4831 	 * faulty, so that it will be reset next time through ...
4832 	 *
4833 	 * Note that if intr_running is set, then bge_intr() has dropped
4834 	 * genlock to call bge_receive/bge_recycle. Can't stop the chip at
4835 	 * this point so have to wait until the next time the factotum runs.
4836 	 */
4837 	if (error && !bgep->bge_intr_running) {
4838 #ifdef BGE_IPMI_ASF
4839 		if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) {
4840 			/*
4841 			 * We must stop ASF heart beat before bge_chip_stop(),
4842 			 * otherwise some computers (ex. IBM HS20 blade server)
4843 			 * may crash.
4844 			 */
4845 			bge_asf_update_status(bgep);
4846 			bge_asf_stop_timer(bgep);
4847 			bgep->asf_status = ASF_STAT_STOP;
4848 
4849 			bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
4850 			(void) bge_check_acc_handle(bgep, bgep->cfg_handle);
4851 		}
4852 #endif
4853 		bge_chip_stop(bgep, B_TRUE);
4854 		(void) bge_check_acc_handle(bgep, bgep->io_handle);
4855 	}
4856 	mutex_exit(bgep->genlock);
4857 
4858 	/*
4859 	 * If the link state changed, tell the world about it.
4860 	 * Note: can't do this while still holding the mutex.
4861 	 */
4862 	if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT &&
4863 	    bgep->link_state != LINK_STATE_UNKNOWN)
4864 		linkchg = B_TRUE;
4865 	else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT &&
4866 	    bgep->link_state == LINK_STATE_DOWN)
4867 		linkchg = B_FALSE;
4868 
4869 	if (linkchg) {
4870 		mac_link_update(bgep->mh, bgep->link_state);
4871 		bgep->link_update_timer = BGE_LINK_UPDATE_DONE;
4872 	}
4873 	if (bgep->manual_reset) {
4874 		bgep->manual_reset = B_FALSE;
4875 	}
4876 
4877 	return (result);
4878 }
4879 
4880 /*
4881  * High-level cyclic handler
4882  *
4883  * This routine schedules a (low-level) softint callback to the
4884  * factotum, and prods the chip to update the status block (which
4885  * will cause a hardware interrupt when complete).
4886  */
4887 void bge_chip_cyclic(void *arg);
4888 #pragma	no_inline(bge_chip_cyclic)
4889 
4890 void
4891 bge_chip_cyclic(void *arg)
4892 {
4893 	bge_t *bgep;
4894 
4895 	bgep = arg;
4896 
4897 	switch (bgep->bge_chip_state) {
4898 	default:
4899 		return;
4900 
4901 	case BGE_CHIP_RUNNING:
4902 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW);
4903 		if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4904 			ddi_fm_service_impact(bgep->devinfo,
4905 			    DDI_SERVICE_UNAFFECTED);
4906 
4907 		if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT)
4908 			bgep->link_update_timer++;
4909 
4910 		break;
4911 
4912 	case BGE_CHIP_FAULT:
4913 	case BGE_CHIP_ERROR:
4914 		break;
4915 	}
4916 
4917 	bge_wake_factotum(bgep);
4918 }
4919 
4920 
4921 /*
4922  * ========== Ioctl subfunctions ==========
4923  */
4924 
4925 #undef	BGE_DBG
4926 #define	BGE_DBG		BGE_DBG_PPIO	/* debug flag for this code	*/
4927 
4928 #if	BGE_DEBUGGING || BGE_DO_PPIO
4929 
4930 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
4931 #pragma	no_inline(bge_chip_peek_cfg)
4932 
4933 static void
4934 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
4935 {
4936 	uint64_t regval;
4937 	uint64_t regno;
4938 
4939 	BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)",
4940 	    (void *)bgep, (void *)ppd));
4941 
4942 	regno = ppd->pp_acc_offset;
4943 
4944 	switch (ppd->pp_acc_size) {
4945 	case 1:
4946 		regval = pci_config_get8(bgep->cfg_handle, regno);
4947 		break;
4948 
4949 	case 2:
4950 		regval = pci_config_get16(bgep->cfg_handle, regno);
4951 		break;
4952 
4953 	case 4:
4954 		regval = pci_config_get32(bgep->cfg_handle, regno);
4955 		break;
4956 
4957 	case 8:
4958 		regval = pci_config_get64(bgep->cfg_handle, regno);
4959 		break;
4960 	}
4961 
4962 	ppd->pp_acc_data = regval;
4963 }
4964 
4965 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
4966 #pragma	no_inline(bge_chip_poke_cfg)
4967 
4968 static void
4969 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
4970 {
4971 	uint64_t regval;
4972 	uint64_t regno;
4973 
4974 	BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)",
4975 	    (void *)bgep, (void *)ppd));
4976 
4977 	regno = ppd->pp_acc_offset;
4978 	regval = ppd->pp_acc_data;
4979 
4980 	switch (ppd->pp_acc_size) {
4981 	case 1:
4982 		pci_config_put8(bgep->cfg_handle, regno, regval);
4983 		break;
4984 
4985 	case 2:
4986 		pci_config_put16(bgep->cfg_handle, regno, regval);
4987 		break;
4988 
4989 	case 4:
4990 		pci_config_put32(bgep->cfg_handle, regno, regval);
4991 		break;
4992 
4993 	case 8:
4994 		pci_config_put64(bgep->cfg_handle, regno, regval);
4995 		break;
4996 	}
4997 }
4998 
4999 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd);
5000 #pragma	no_inline(bge_chip_peek_reg)
5001 
5002 static void
5003 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd)
5004 {
5005 	uint64_t regval;
5006 	void *regaddr;
5007 
5008 	BGE_TRACE(("bge_chip_peek_reg($%p, $%p)",
5009 	    (void *)bgep, (void *)ppd));
5010 
5011 	regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
5012 
5013 	switch (ppd->pp_acc_size) {
5014 	case 1:
5015 		regval = ddi_get8(bgep->io_handle, regaddr);
5016 		break;
5017 
5018 	case 2:
5019 		regval = ddi_get16(bgep->io_handle, regaddr);
5020 		break;
5021 
5022 	case 4:
5023 		regval = ddi_get32(bgep->io_handle, regaddr);
5024 		break;
5025 
5026 	case 8:
5027 		regval = ddi_get64(bgep->io_handle, regaddr);
5028 		break;
5029 	}
5030 
5031 	ppd->pp_acc_data = regval;
5032 }
5033 
5034 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd);
5035 #pragma	no_inline(bge_chip_peek_reg)
5036 
5037 static void
5038 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd)
5039 {
5040 	uint64_t regval;
5041 	void *regaddr;
5042 
5043 	BGE_TRACE(("bge_chip_poke_reg($%p, $%p)",
5044 	    (void *)bgep, (void *)ppd));
5045 
5046 	regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
5047 	regval = ppd->pp_acc_data;
5048 
5049 	switch (ppd->pp_acc_size) {
5050 	case 1:
5051 		ddi_put8(bgep->io_handle, regaddr, regval);
5052 		break;
5053 
5054 	case 2:
5055 		ddi_put16(bgep->io_handle, regaddr, regval);
5056 		break;
5057 
5058 	case 4:
5059 		ddi_put32(bgep->io_handle, regaddr, regval);
5060 		break;
5061 
5062 	case 8:
5063 		ddi_put64(bgep->io_handle, regaddr, regval);
5064 		break;
5065 	}
5066 	BGE_PCICHK(bgep);
5067 }
5068 
5069 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd);
5070 #pragma	no_inline(bge_chip_peek_nic)
5071 
5072 static void
5073 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd)
5074 {
5075 	uint64_t regoff;
5076 	uint64_t regval;
5077 	void *regaddr;
5078 
5079 	BGE_TRACE(("bge_chip_peek_nic($%p, $%p)",
5080 	    (void *)bgep, (void *)ppd));
5081 
5082 	regoff = ppd->pp_acc_offset;
5083 	bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
5084 	regoff &= MWBAR_GRANULE_MASK;
5085 	regoff += NIC_MEM_WINDOW_OFFSET;
5086 	regaddr = PIO_ADDR(bgep, regoff);
5087 
5088 	switch (ppd->pp_acc_size) {
5089 	case 1:
5090 		regval = ddi_get8(bgep->io_handle, regaddr);
5091 		break;
5092 
5093 	case 2:
5094 		regval = ddi_get16(bgep->io_handle, regaddr);
5095 		break;
5096 
5097 	case 4:
5098 		regval = ddi_get32(bgep->io_handle, regaddr);
5099 		break;
5100 
5101 	case 8:
5102 		regval = ddi_get64(bgep->io_handle, regaddr);
5103 		break;
5104 	}
5105 
5106 	ppd->pp_acc_data = regval;
5107 }
5108 
5109 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd);
5110 #pragma	no_inline(bge_chip_poke_nic)
5111 
5112 static void
5113 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd)
5114 {
5115 	uint64_t regoff;
5116 	uint64_t regval;
5117 	void *regaddr;
5118 
5119 	BGE_TRACE(("bge_chip_poke_nic($%p, $%p)",
5120 	    (void *)bgep, (void *)ppd));
5121 
5122 	regoff = ppd->pp_acc_offset;
5123 	bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
5124 	regoff &= MWBAR_GRANULE_MASK;
5125 	regoff += NIC_MEM_WINDOW_OFFSET;
5126 	regaddr = PIO_ADDR(bgep, regoff);
5127 	regval = ppd->pp_acc_data;
5128 
5129 	switch (ppd->pp_acc_size) {
5130 	case 1:
5131 		ddi_put8(bgep->io_handle, regaddr, regval);
5132 		break;
5133 
5134 	case 2:
5135 		ddi_put16(bgep->io_handle, regaddr, regval);
5136 		break;
5137 
5138 	case 4:
5139 		ddi_put32(bgep->io_handle, regaddr, regval);
5140 		break;
5141 
5142 	case 8:
5143 		ddi_put64(bgep->io_handle, regaddr, regval);
5144 		break;
5145 	}
5146 	BGE_PCICHK(bgep);
5147 }
5148 
5149 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd);
5150 #pragma	no_inline(bge_chip_peek_mii)
5151 
5152 static void
5153 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd)
5154 {
5155 	BGE_TRACE(("bge_chip_peek_mii($%p, $%p)",
5156 	    (void *)bgep, (void *)ppd));
5157 
5158 	ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2);
5159 }
5160 
5161 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd);
5162 #pragma	no_inline(bge_chip_poke_mii)
5163 
5164 static void
5165 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd)
5166 {
5167 	BGE_TRACE(("bge_chip_poke_mii($%p, $%p)",
5168 	    (void *)bgep, (void *)ppd));
5169 
5170 	bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
5171 }
5172 
5173 #if	BGE_SEE_IO32
5174 
5175 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
5176 #pragma	no_inline(bge_chip_peek_seeprom)
5177 
5178 static void
5179 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
5180 {
5181 	uint32_t data;
5182 	int err;
5183 
5184 	BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)",
5185 	    (void *)bgep, (void *)ppd));
5186 
5187 	err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data);
5188 	ppd->pp_acc_data = err ? ~0ull : data;
5189 }
5190 
5191 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
5192 #pragma	no_inline(bge_chip_poke_seeprom)
5193 
5194 static void
5195 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
5196 {
5197 	uint32_t data;
5198 
5199 	BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)",
5200 	    (void *)bgep, (void *)ppd));
5201 
5202 	data = ppd->pp_acc_data;
5203 	(void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data);
5204 }
5205 #endif	/* BGE_SEE_IO32 */
5206 
5207 #if	BGE_FLASH_IO32
5208 
5209 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd);
5210 #pragma	no_inline(bge_chip_peek_flash)
5211 
5212 static void
5213 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd)
5214 {
5215 	uint32_t data;
5216 	int err;
5217 
5218 	BGE_TRACE(("bge_chip_peek_flash($%p, $%p)",
5219 	    (void *)bgep, (void *)ppd));
5220 
5221 	err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data);
5222 	ppd->pp_acc_data = err ? ~0ull : data;
5223 }
5224 
5225 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd);
5226 #pragma	no_inline(bge_chip_poke_flash)
5227 
5228 static void
5229 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd)
5230 {
5231 	uint32_t data;
5232 
5233 	BGE_TRACE(("bge_chip_poke_flash($%p, $%p)",
5234 	    (void *)bgep, (void *)ppd));
5235 
5236 	data = ppd->pp_acc_data;
5237 	(void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE,
5238 	    ppd->pp_acc_offset, &data);
5239 }
5240 #endif	/* BGE_FLASH_IO32 */
5241 
5242 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd);
5243 #pragma	no_inline(bge_chip_peek_mem)
5244 
5245 static void
5246 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd)
5247 {
5248 	uint64_t regval;
5249 	void *vaddr;
5250 
5251 	BGE_TRACE(("bge_chip_peek_bge($%p, $%p)",
5252 	    (void *)bgep, (void *)ppd));
5253 
5254 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
5255 
5256 	switch (ppd->pp_acc_size) {
5257 	case 1:
5258 		regval = *(uint8_t *)vaddr;
5259 		break;
5260 
5261 	case 2:
5262 		regval = *(uint16_t *)vaddr;
5263 		break;
5264 
5265 	case 4:
5266 		regval = *(uint32_t *)vaddr;
5267 		break;
5268 
5269 	case 8:
5270 		regval = *(uint64_t *)vaddr;
5271 		break;
5272 	}
5273 
5274 	BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p",
5275 	    (void *)bgep, (void *)ppd, regval, vaddr));
5276 
5277 	ppd->pp_acc_data = regval;
5278 }
5279 
5280 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd);
5281 #pragma	no_inline(bge_chip_poke_mem)
5282 
5283 static void
5284 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd)
5285 {
5286 	uint64_t regval;
5287 	void *vaddr;
5288 
5289 	BGE_TRACE(("bge_chip_poke_mem($%p, $%p)",
5290 	    (void *)bgep, (void *)ppd));
5291 
5292 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
5293 	regval = ppd->pp_acc_data;
5294 
5295 	BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p",
5296 	    (void *)bgep, (void *)ppd, regval, vaddr));
5297 
5298 	switch (ppd->pp_acc_size) {
5299 	case 1:
5300 		*(uint8_t *)vaddr = (uint8_t)regval;
5301 		break;
5302 
5303 	case 2:
5304 		*(uint16_t *)vaddr = (uint16_t)regval;
5305 		break;
5306 
5307 	case 4:
5308 		*(uint32_t *)vaddr = (uint32_t)regval;
5309 		break;
5310 
5311 	case 8:
5312 		*(uint64_t *)vaddr = (uint64_t)regval;
5313 		break;
5314 	}
5315 }
5316 
5317 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5318 					struct iocblk *iocp);
5319 #pragma	no_inline(bge_pp_ioctl)
5320 
5321 static enum ioc_reply
5322 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5323 {
5324 	void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd);
5325 	bge_peekpoke_t *ppd;
5326 	dma_area_t *areap;
5327 	uint64_t sizemask;
5328 	uint64_t mem_va;
5329 	uint64_t maxoff;
5330 	boolean_t peek;
5331 
5332 	switch (cmd) {
5333 	default:
5334 		/* NOTREACHED */
5335 		bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd);
5336 		return (IOC_INVAL);
5337 
5338 	case BGE_PEEK:
5339 		peek = B_TRUE;
5340 		break;
5341 
5342 	case BGE_POKE:
5343 		peek = B_FALSE;
5344 		break;
5345 	}
5346 
5347 	/*
5348 	 * Validate format of ioctl
5349 	 */
5350 	if (iocp->ioc_count != sizeof (bge_peekpoke_t))
5351 		return (IOC_INVAL);
5352 	if (mp->b_cont == NULL)
5353 		return (IOC_INVAL);
5354 	ppd = (void *)mp->b_cont->b_rptr;
5355 
5356 	/*
5357 	 * Validate request parameters
5358 	 */
5359 	switch (ppd->pp_acc_space) {
5360 	default:
5361 		return (IOC_INVAL);
5362 
5363 	case BGE_PP_SPACE_CFG:
5364 		/*
5365 		 * Config space
5366 		 */
5367 		sizemask = 8|4|2|1;
5368 		mem_va = 0;
5369 		maxoff = PCI_CONF_HDR_SIZE;
5370 		ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg;
5371 		break;
5372 
5373 	case BGE_PP_SPACE_REG:
5374 		/*
5375 		 * Memory-mapped I/O space
5376 		 */
5377 		sizemask = 8|4|2|1;
5378 		mem_va = 0;
5379 		maxoff = RIAAR_REGISTER_MAX;
5380 		ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg;
5381 		break;
5382 
5383 	case BGE_PP_SPACE_NIC:
5384 		/*
5385 		 * NIC on-chip memory
5386 		 */
5387 		sizemask = 8|4|2|1;
5388 		mem_va = 0;
5389 		maxoff = MWBAR_ONCHIP_MAX;
5390 		ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic;
5391 		break;
5392 
5393 	case BGE_PP_SPACE_MII:
5394 		/*
5395 		 * PHY's MII registers
5396 		 * NB: all PHY registers are two bytes, but the
5397 		 * addresses increment in ones (word addressing).
5398 		 * So we scale the address here, then undo the
5399 		 * transformation inside the peek/poke functions.
5400 		 */
5401 		ppd->pp_acc_offset *= 2;
5402 		sizemask = 2;
5403 		mem_va = 0;
5404 		maxoff = (MII_MAXREG+1)*2;
5405 		ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii;
5406 		break;
5407 
5408 #if	BGE_SEE_IO32
5409 	case BGE_PP_SPACE_SEEPROM:
5410 		/*
5411 		 * Attached SEEPROM(s), if any.
5412 		 * NB: we use the high-order bits of the 'address' as
5413 		 * a device select to accommodate multiple SEEPROMS,
5414 		 * If each one is the maximum size (64kbytes), this
5415 		 * makes them appear contiguous.  Otherwise, there may
5416 		 * be holes in the mapping.  ENxS doesn't have any
5417 		 * SEEPROMs anyway ...
5418 		 */
5419 		sizemask = 4;
5420 		mem_va = 0;
5421 		maxoff = SEEPROM_DEV_AND_ADDR_MASK;
5422 		ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom;
5423 		break;
5424 #endif	/* BGE_SEE_IO32 */
5425 
5426 #if	BGE_FLASH_IO32
5427 	case BGE_PP_SPACE_FLASH:
5428 		/*
5429 		 * Attached Flash device (if any); a maximum of one device
5430 		 * is currently supported.  But it can be up to 1MB (unlike
5431 		 * the 64k limit on SEEPROMs) so why would you need more ;-)
5432 		 */
5433 		sizemask = 4;
5434 		mem_va = 0;
5435 		maxoff = NVM_FLASH_ADDR_MASK;
5436 		ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash;
5437 		break;
5438 #endif	/* BGE_FLASH_IO32 */
5439 
5440 	case BGE_PP_SPACE_BGE:
5441 		/*
5442 		 * BGE data structure!
5443 		 */
5444 		sizemask = 8|4|2|1;
5445 		mem_va = (uintptr_t)bgep;
5446 		maxoff = sizeof (*bgep);
5447 		ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
5448 		break;
5449 
5450 	case BGE_PP_SPACE_STATUS:
5451 	case BGE_PP_SPACE_STATISTICS:
5452 	case BGE_PP_SPACE_TXDESC:
5453 	case BGE_PP_SPACE_TXBUFF:
5454 	case BGE_PP_SPACE_RXDESC:
5455 	case BGE_PP_SPACE_RXBUFF:
5456 		/*
5457 		 * Various DMA_AREAs
5458 		 */
5459 		switch (ppd->pp_acc_space) {
5460 		case BGE_PP_SPACE_TXDESC:
5461 			areap = &bgep->tx_desc;
5462 			break;
5463 		case BGE_PP_SPACE_TXBUFF:
5464 			areap = &bgep->tx_buff[0];
5465 			break;
5466 		case BGE_PP_SPACE_RXDESC:
5467 			areap = &bgep->rx_desc[0];
5468 			break;
5469 		case BGE_PP_SPACE_RXBUFF:
5470 			areap = &bgep->rx_buff[0];
5471 			break;
5472 		case BGE_PP_SPACE_STATUS:
5473 			areap = &bgep->status_block;
5474 			break;
5475 		case BGE_PP_SPACE_STATISTICS:
5476 			if (bgep->chipid.statistic_type == BGE_STAT_BLK)
5477 				areap = &bgep->statistics;
5478 			break;
5479 		}
5480 
5481 		sizemask = 8|4|2|1;
5482 		mem_va = (uintptr_t)areap->mem_va;
5483 		maxoff = areap->alength;
5484 		ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
5485 		break;
5486 	}
5487 
5488 	switch (ppd->pp_acc_size) {
5489 	default:
5490 		return (IOC_INVAL);
5491 
5492 	case 8:
5493 	case 4:
5494 	case 2:
5495 	case 1:
5496 		if ((ppd->pp_acc_size & sizemask) == 0)
5497 			return (IOC_INVAL);
5498 		break;
5499 	}
5500 
5501 	if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
5502 		return (IOC_INVAL);
5503 
5504 	if (ppd->pp_acc_offset >= maxoff)
5505 		return (IOC_INVAL);
5506 
5507 	if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff)
5508 		return (IOC_INVAL);
5509 
5510 	/*
5511 	 * All OK - go do it!
5512 	 */
5513 	ppd->pp_acc_offset += mem_va;
5514 	(*ppfn)(bgep, ppd);
5515 	return (peek ? IOC_REPLY : IOC_ACK);
5516 }
5517 
5518 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5519 					struct iocblk *iocp);
5520 #pragma	no_inline(bge_diag_ioctl)
5521 
5522 static enum ioc_reply
5523 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5524 {
5525 	ASSERT(mutex_owned(bgep->genlock));
5526 
5527 	switch (cmd) {
5528 	default:
5529 		/* NOTREACHED */
5530 		bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd);
5531 		return (IOC_INVAL);
5532 
5533 	case BGE_DIAG:
5534 		/*
5535 		 * Currently a no-op
5536 		 */
5537 		return (IOC_ACK);
5538 
5539 	case BGE_PEEK:
5540 	case BGE_POKE:
5541 		return (bge_pp_ioctl(bgep, cmd, mp, iocp));
5542 
5543 	case BGE_PHY_RESET:
5544 		return (IOC_RESTART_ACK);
5545 
5546 	case BGE_SOFT_RESET:
5547 	case BGE_HARD_RESET:
5548 		/*
5549 		 * Reset and reinitialise the 570x hardware
5550 		 */
5551 		bgep->bge_chip_state = BGE_CHIP_FAULT;
5552 		ddi_trigger_softintr(bgep->factotum_id);
5553 		(void) bge_restart(bgep, cmd == BGE_HARD_RESET);
5554 		return (IOC_ACK);
5555 	}
5556 
5557 	/* NOTREACHED */
5558 }
5559 
5560 #endif	/* BGE_DEBUGGING || BGE_DO_PPIO */
5561 
5562 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5563 				    struct iocblk *iocp);
5564 #pragma	no_inline(bge_mii_ioctl)
5565 
5566 static enum ioc_reply
5567 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5568 {
5569 	struct bge_mii_rw *miirwp;
5570 
5571 	/*
5572 	 * Validate format of ioctl
5573 	 */
5574 	if (iocp->ioc_count != sizeof (struct bge_mii_rw))
5575 		return (IOC_INVAL);
5576 	if (mp->b_cont == NULL)
5577 		return (IOC_INVAL);
5578 	miirwp = (void *)mp->b_cont->b_rptr;
5579 
5580 	/*
5581 	 * Validate request parameters ...
5582 	 */
5583 	if (miirwp->mii_reg > MII_MAXREG)
5584 		return (IOC_INVAL);
5585 
5586 	switch (cmd) {
5587 	default:
5588 		/* NOTREACHED */
5589 		bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd);
5590 		return (IOC_INVAL);
5591 
5592 	case BGE_MII_READ:
5593 		miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg);
5594 		return (IOC_REPLY);
5595 
5596 	case BGE_MII_WRITE:
5597 		bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data);
5598 		return (IOC_ACK);
5599 	}
5600 
5601 	/* NOTREACHED */
5602 }
5603 
5604 #if	BGE_SEE_IO32
5605 
5606 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5607 				    struct iocblk *iocp);
5608 #pragma	no_inline(bge_see_ioctl)
5609 
5610 static enum ioc_reply
5611 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5612 {
5613 	struct bge_see_rw *seerwp;
5614 
5615 	/*
5616 	 * Validate format of ioctl
5617 	 */
5618 	if (iocp->ioc_count != sizeof (struct bge_see_rw))
5619 		return (IOC_INVAL);
5620 	if (mp->b_cont == NULL)
5621 		return (IOC_INVAL);
5622 	seerwp = (void *)mp->b_cont->b_rptr;
5623 
5624 	/*
5625 	 * Validate request parameters ...
5626 	 */
5627 	if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK)
5628 		return (IOC_INVAL);
5629 
5630 	switch (cmd) {
5631 	default:
5632 		/* NOTREACHED */
5633 		bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd);
5634 		return (IOC_INVAL);
5635 
5636 	case BGE_SEE_READ:
5637 	case BGE_SEE_WRITE:
5638 		iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5639 		    seerwp->see_addr, &seerwp->see_data);
5640 		return (IOC_REPLY);
5641 	}
5642 
5643 	/* NOTREACHED */
5644 }
5645 
5646 #endif	/* BGE_SEE_IO32 */
5647 
5648 #if	BGE_FLASH_IO32
5649 
5650 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5651 				    struct iocblk *iocp);
5652 #pragma	no_inline(bge_flash_ioctl)
5653 
5654 static enum ioc_reply
5655 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5656 {
5657 	struct bge_flash_rw *flashrwp;
5658 
5659 	/*
5660 	 * Validate format of ioctl
5661 	 */
5662 	if (iocp->ioc_count != sizeof (struct bge_flash_rw))
5663 		return (IOC_INVAL);
5664 	if (mp->b_cont == NULL)
5665 		return (IOC_INVAL);
5666 	flashrwp = (void *)mp->b_cont->b_rptr;
5667 
5668 	/*
5669 	 * Validate request parameters ...
5670 	 */
5671 	if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK)
5672 		return (IOC_INVAL);
5673 
5674 	switch (cmd) {
5675 	default:
5676 		/* NOTREACHED */
5677 		bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd);
5678 		return (IOC_INVAL);
5679 
5680 	case BGE_FLASH_READ:
5681 	case BGE_FLASH_WRITE:
5682 		iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5683 		    flashrwp->flash_addr, &flashrwp->flash_data);
5684 		return (IOC_REPLY);
5685 	}
5686 
5687 	/* NOTREACHED */
5688 }
5689 
5690 #endif	/* BGE_FLASH_IO32 */
5691 
5692 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp,
5693 				struct iocblk *iocp);
5694 #pragma	no_inline(bge_chip_ioctl)
5695 
5696 enum ioc_reply
5697 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
5698 {
5699 	int cmd;
5700 
5701 	BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)",
5702 	    (void *)bgep, (void *)wq, (void *)mp, (void *)iocp));
5703 
5704 	ASSERT(mutex_owned(bgep->genlock));
5705 
5706 	cmd = iocp->ioc_cmd;
5707 	switch (cmd) {
5708 	default:
5709 		/* NOTREACHED */
5710 		bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd);
5711 		return (IOC_INVAL);
5712 
5713 	case BGE_DIAG:
5714 	case BGE_PEEK:
5715 	case BGE_POKE:
5716 	case BGE_PHY_RESET:
5717 	case BGE_SOFT_RESET:
5718 	case BGE_HARD_RESET:
5719 #if	BGE_DEBUGGING || BGE_DO_PPIO
5720 		return (bge_diag_ioctl(bgep, cmd, mp, iocp));
5721 #else
5722 		return (IOC_INVAL);
5723 #endif	/* BGE_DEBUGGING || BGE_DO_PPIO */
5724 
5725 	case BGE_MII_READ:
5726 	case BGE_MII_WRITE:
5727 		return (bge_mii_ioctl(bgep, cmd, mp, iocp));
5728 
5729 #if	BGE_SEE_IO32
5730 	case BGE_SEE_READ:
5731 	case BGE_SEE_WRITE:
5732 		return (bge_see_ioctl(bgep, cmd, mp, iocp));
5733 #endif	/* BGE_SEE_IO32 */
5734 
5735 #if	BGE_FLASH_IO32
5736 	case BGE_FLASH_READ:
5737 	case BGE_FLASH_WRITE:
5738 		return (bge_flash_ioctl(bgep, cmd, mp, iocp));
5739 #endif	/* BGE_FLASH_IO32 */
5740 	}
5741 
5742 	/* NOTREACHED */
5743 }
5744 
5745 /* ARGSUSED */
5746 void
5747 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag)
5748 {
5749 	recv_ring_t *rrp = arg;
5750 	bge_t *bgep = rrp->bgep;
5751 
5752 	mutex_enter(bgep->genlock);
5753 	rrp->poll_flag = flag;
5754 #ifdef NOT_YET
5755 	/*
5756 	 * XXX-Sunay: Since most broadcom cards support only one
5757 	 * interrupt but multiple rx rings, we can't disable the
5758 	 * physical interrupt. This need to be done via capability
5759 	 * negotiation depending on the NIC.
5760 	 */
5761 	bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks);
5762 	bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count);
5763 #endif
5764 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5765 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
5766 	mutex_exit(bgep->genlock);
5767 }
5768 
5769 #ifdef BGE_IPMI_ASF
5770 
5771 uint32_t
5772 bge_nic_read32(bge_t *bgep, bge_regno_t addr)
5773 {
5774 	uint32_t data;
5775 
5776 #ifndef __sparc
5777 	if (!bgep->asf_wordswapped) {
5778 		/* a workaround word swap error */
5779 		if (addr & 4)
5780 			addr = addr - 4;
5781 		else
5782 			addr = addr + 4;
5783 	}
5784 #else
5785 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
5786 		addr = LE_32(addr);
5787 #endif
5788 
5789 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
5790 	data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR);
5791 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
5792 
5793 	data = LE_32(data);
5794 
5795 	BGE_DEBUG(("bge_nic_read32($%p, 0x%x) => 0x%x",
5796 	    (void *)bgep, addr, data));
5797 
5798 	return (data);
5799 }
5800 
5801 void
5802 bge_asf_update_status(bge_t *bgep)
5803 {
5804 	uint32_t event;
5805 
5806 	bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE);
5807 	bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4);
5808 	bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX,   3);
5809 
5810 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5811 	bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
5812 }
5813 
5814 
5815 /*
5816  * The driver is supposed to notify ASF that the OS is still running
5817  * every three seconds, otherwise the management server may attempt
5818  * to reboot the machine.  If it hasn't actually failed, this is
5819  * not a desirable result.  However, this isn't running as a real-time
5820  * thread, and even if it were, it might not be able to generate the
5821  * heartbeat in a timely manner due to system load.  As it isn't a
5822  * significant strain on the machine, we will set the interval to half
5823  * of the required value.
5824  */
5825 void
5826 bge_asf_heartbeat(void *arg)
5827 {
5828 	bge_t *bgep = (bge_t *)arg;
5829 
5830 	mutex_enter(bgep->genlock);
5831 	bge_asf_update_status((bge_t *)bgep);
5832 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5833 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
5834 	if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK)
5835 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
5836 	mutex_exit(bgep->genlock);
5837 	((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep,
5838 	    drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL));
5839 }
5840 
5841 
5842 void
5843 bge_asf_stop_timer(bge_t *bgep)
5844 {
5845 	timeout_id_t tmp_id = 0;
5846 
5847 	while ((bgep->asf_timeout_id != 0) &&
5848 	    (tmp_id != bgep->asf_timeout_id)) {
5849 		tmp_id = bgep->asf_timeout_id;
5850 		(void) untimeout(tmp_id);
5851 	}
5852 	bgep->asf_timeout_id = 0;
5853 }
5854 
5855 
5856 
5857 /*
5858  * This function should be placed at the earliest position of bge_attach().
5859  */
5860 void
5861 bge_asf_get_config(bge_t *bgep)
5862 {
5863 	uint32_t nicsig;
5864 	uint32_t niccfg;
5865 
5866 	bgep->asf_enabled = B_FALSE;
5867 	nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR);
5868 	if (nicsig == BGE_NIC_DATA_SIG) {
5869 		niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR);
5870 		if (niccfg & BGE_NIC_CFG_ENABLE_ASF)
5871 			/*
5872 			 * Here, we don't consider BAXTER, because BGE haven't
5873 			 * supported BAXTER (that is 5752). Also, as I know,
5874 			 * BAXTER doesn't support ASF feature.
5875 			 */
5876 			bgep->asf_enabled = B_TRUE;
5877 		else
5878 			bgep->asf_enabled = B_FALSE;
5879 	} else
5880 		bgep->asf_enabled = B_FALSE;
5881 }
5882 
5883 
5884 void
5885 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode)
5886 {
5887 	uint32_t tries;
5888 	uint32_t event;
5889 
5890 	ASSERT(bgep->asf_enabled);
5891 
5892 	/* Issues "pause firmware" command and wait for ACK */
5893 	bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW);
5894 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5895 	bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
5896 
5897 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5898 	tries = 0;
5899 	while ((event & RRER_ASF_EVENT) && (tries < 100)) {
5900 		drv_usecwait(1);
5901 		tries ++;
5902 		event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5903 	}
5904 
5905 	bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX,
5906 	    BGE_MAGIC_NUM_FIRMWARE_INIT_DONE);
5907 
5908 	if (bgep->asf_newhandshake) {
5909 		switch (mode) {
5910 		case BGE_INIT_RESET:
5911 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5912 			    BGE_DRV_STATE_START);
5913 			break;
5914 		case BGE_SHUTDOWN_RESET:
5915 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5916 			    BGE_DRV_STATE_UNLOAD);
5917 			break;
5918 		case BGE_SUSPEND_RESET:
5919 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5920 			    BGE_DRV_STATE_SUSPEND);
5921 			break;
5922 		default:
5923 			break;
5924 		}
5925 	}
5926 }
5927 
5928 
5929 void
5930 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode)
5931 {
5932 	switch (mode) {
5933 	case BGE_INIT_RESET:
5934 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5935 		    BGE_DRV_STATE_START);
5936 		break;
5937 	case BGE_SHUTDOWN_RESET:
5938 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5939 		    BGE_DRV_STATE_UNLOAD);
5940 		break;
5941 	case BGE_SUSPEND_RESET:
5942 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5943 		    BGE_DRV_STATE_SUSPEND);
5944 		break;
5945 	default:
5946 		break;
5947 	}
5948 }
5949 
5950 
5951 void
5952 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode)
5953 {
5954 	switch (mode) {
5955 	case BGE_INIT_RESET:
5956 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5957 		    BGE_DRV_STATE_START_DONE);
5958 		break;
5959 	case BGE_SHUTDOWN_RESET:
5960 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5961 		    BGE_DRV_STATE_UNLOAD_DONE);
5962 		break;
5963 	default:
5964 		break;
5965 	}
5966 }
5967 
5968 #endif /* BGE_IPMI_ASF */
5969