1 /* 2 * Solaris driver for ethernet cards based on the ADMtek Centaur 3 * 4 * Copyright (c) 2007 by Garrett D'Amore <garrett@damore.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the author nor the names of any co-contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS ``AS IS'' 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AFEIMPL_H 33 #define _AFEIMPL_H 34 35 #pragma ident "%Z%%M% %I% %E% SMI" 36 37 #ifdef _KERNEL 38 39 /* 40 * Compile time tunables. 41 */ 42 #define AFE_RXRING 128 /* number of rcv buffers */ 43 #define AFE_TXRING 128 /* number of xmt buffers */ 44 #define AFE_TXRECLAIM 8 /* when to reclaim tx buffers (txavail) */ 45 #define AFE_TXRESCHED 120 /* when to resched (txavail) */ 46 #define AFE_LINKTIMER 5000 /* how often we check link state (in msec) */ 47 #define AFE_HEADROOM 34 /* headroom in packet (should be 2 modulo 4) */ 48 49 /* 50 * Constants, do not change. 51 */ 52 #define AFE_BUFSZ (1664) /* big enough for a vlan frame */ 53 #define AFE_MCHASH (64) 54 55 typedef struct afe afe_t; 56 typedef struct afe_card afe_card_t; 57 typedef struct afe_nd afe_nd_t; 58 typedef struct afe_rxbuf afe_rxbuf_t; 59 typedef struct afe_txbuf afe_txbuf_t; 60 typedef struct afe_desc afe_desc_t; 61 typedef int (*afe_nd_pf_t)(afe_t *, mblk_t *, afe_nd_t *); 62 63 /* 64 * Card models. 65 */ 66 typedef enum { 67 MODEL_CENTAUR = 1, 68 MODEL_COMET, 69 } afe_model_t; 70 71 struct afe_card { 72 uint16_t card_venid; /* PCI vendor id */ 73 uint16_t card_devid; /* PCI device id */ 74 char *card_cardname; /* Description of the card */ 75 afe_model_t card_model; /* Card specific flags */ 76 }; 77 78 struct afe_nd { 79 afe_nd_t *nd_next; 80 char *nd_name; 81 afe_nd_pf_t nd_get; 82 afe_nd_pf_t nd_set; 83 intptr_t nd_arg1; 84 intptr_t nd_arg2; 85 }; 86 87 /* 88 * Device instance structure, one per PCI card. 89 */ 90 struct afe { 91 dev_info_t *afe_dip; 92 mac_handle_t afe_mh; 93 afe_card_t *afe_cardp; 94 uint16_t afe_cachesize; 95 uint8_t afe_sromwidth; 96 int afe_flags; 97 kmutex_t afe_xmtlock; 98 kmutex_t afe_intrlock; 99 ddi_iblock_cookie_t afe_icookie; 100 101 /* 102 * Register and DMA access. 103 */ 104 uintptr_t afe_regs; 105 ddi_acc_handle_t afe_regshandle; 106 107 /* 108 * Receive descriptors. 109 */ 110 int afe_rxhead; 111 struct afe_desc *afe_rxdescp; 112 ddi_dma_handle_t afe_rxdesc_dmah; 113 ddi_acc_handle_t afe_rxdesc_acch; 114 uint32_t afe_rxdesc_paddr; 115 struct afe_rxbuf **afe_rxbufs; 116 117 /* 118 * Transmit descriptors. 119 */ 120 int afe_txreclaim; 121 int afe_txsend; 122 int afe_txavail; 123 struct afe_desc *afe_txdescp; 124 ddi_dma_handle_t afe_txdesc_dmah; 125 ddi_acc_handle_t afe_txdesc_acch; 126 uint32_t afe_txdesc_paddr; 127 struct afe_txbuf **afe_txbufs; 128 hrtime_t afe_txstall_time; 129 boolean_t afe_wantw; 130 131 /* 132 * Link state. 133 */ 134 int afe_lastifspeed; 135 int afe_lastduplex; 136 int afe_linkup; 137 int afe_duplex; 138 int afe_ifspeed; 139 boolean_t afe_resetting; /* no link warning */ 140 141 /* 142 * NDD related support. 143 */ 144 afe_nd_t *afe_ndp; 145 146 /* 147 * Transceiver stuff. 148 */ 149 int afe_phyaddr; 150 int afe_phyid; 151 int afe_phyinuse; 152 int afe_adv_aneg; 153 int afe_adv_100T4; 154 int afe_adv_100fdx; 155 int afe_adv_100hdx; 156 int afe_adv_10fdx; 157 int afe_adv_10hdx; 158 int afe_forcephy; 159 int afe_forcefiber; 160 161 /* 162 * Address management. 163 */ 164 uchar_t afe_curraddr[ETHERADDRL]; 165 boolean_t afe_promisc; 166 uint16_t afe_mccount[AFE_MCHASH]; 167 uint32_t afe_mctab[AFE_MCHASH / 32]; /* Centaur */ 168 169 /* 170 * Kstats. 171 */ 172 kstat_t *afe_intrstat; 173 uint64_t afe_ipackets; 174 uint64_t afe_opackets; 175 uint64_t afe_rbytes; 176 uint64_t afe_obytes; 177 uint64_t afe_brdcstxmt; 178 uint64_t afe_multixmt; 179 uint64_t afe_brdcstrcv; 180 uint64_t afe_multircv; 181 unsigned afe_norcvbuf; 182 unsigned afe_errrcv; 183 unsigned afe_errxmt; 184 unsigned afe_missed; 185 unsigned afe_underflow; 186 unsigned afe_overflow; 187 unsigned afe_align_errors; 188 unsigned afe_fcs_errors; 189 unsigned afe_carrier_errors; 190 unsigned afe_collisions; 191 unsigned afe_ex_collisions; 192 unsigned afe_tx_late_collisions; 193 unsigned afe_defer_xmts; 194 unsigned afe_first_collisions; 195 unsigned afe_multi_collisions; 196 unsigned afe_sqe_errors; 197 unsigned afe_macxmt_errors; 198 unsigned afe_macrcv_errors; 199 unsigned afe_toolong_errors; 200 unsigned afe_runt; 201 unsigned afe_jabber; 202 }; 203 204 struct afe_rxbuf { 205 caddr_t rxb_buf; 206 ddi_dma_handle_t rxb_dmah; 207 ddi_acc_handle_t rxb_acch; 208 uint32_t rxb_paddr; 209 }; 210 211 struct afe_txbuf { 212 caddr_t txb_buf; 213 uint32_t txb_paddr; 214 ddi_dma_handle_t txb_dmah; 215 ddi_acc_handle_t txb_acch; 216 }; 217 218 /* 219 * Descriptor. We use rings rather than chains. 220 */ 221 struct afe_desc { 222 unsigned desc_status; 223 unsigned desc_control; 224 unsigned desc_buffer1; 225 unsigned desc_buffer2; 226 }; 227 228 #define PUTTXDESC(afep, member, val) \ 229 ddi_put32(afep->afe_txdesc_acch, &member, val) 230 231 #define PUTRXDESC(afep, member, val) \ 232 ddi_put32(afep->afe_rxdesc_acch, &member, val) 233 234 #define GETTXDESC(afep, member) \ 235 ddi_get32(afep->afe_txdesc_acch, &member) 236 237 #define GETRXDESC(afep, member) \ 238 ddi_get32(afep->afe_rxdesc_acch, &member) 239 240 /* 241 * Receive descriptor fields. 242 */ 243 #define RXSTAT_OWN 0x80000000U /* ownership */ 244 #define RXSTAT_RXLEN 0x3FFF0000U /* frame length, incl. crc */ 245 #define RXSTAT_RXERR 0x00008000U /* error summary */ 246 #define RXSTAT_DESCERR 0x00004000U /* descriptor error */ 247 #define RXSTAT_RXTYPE 0x00003000U /* data type */ 248 #define RXSTAT_RUNT 0x00000800U /* runt frame */ 249 #define RXSTAT_GROUP 0x00000400U /* multicast/brdcast frame */ 250 #define RXSTAT_FIRST 0x00000200U /* first descriptor */ 251 #define RXSTAT_LAST 0x00000100U /* last descriptor */ 252 #define RXSTAT_TOOLONG 0x00000080U /* frame too long */ 253 #define RXSTAT_COLLSEEN 0x00000040U /* late collision seen */ 254 #define RXSTAT_FRTYPE 0x00000020U /* frame type */ 255 #define RXSTAT_WATCHDOG 0x00000010U /* receive watchdog */ 256 #define RXSTAT_DRIBBLE 0x00000004U /* dribbling bit */ 257 #define RXSTAT_CRCERR 0x00000002U /* crc error */ 258 #define RXSTAT_OFLOW 0x00000001U /* fifo overflow */ 259 #define RXSTAT_ERRS (RXSTAT_DESCERR | RXSTAT_RUNT | \ 260 RXSTAT_COLLSEEN | RXSTAT_DRIBBLE | \ 261 RXSTAT_CRCERR | RXSTAT_OFLOW) 262 #define RXLENGTH(x) ((x & RXSTAT_RXLEN) >> 16) 263 264 #define RXCTL_ENDRING 0x02000000U /* end of ring */ 265 #define RXCTL_CHAIN 0x01000000U /* chained descriptors */ 266 #define RXCTL_BUFLEN2 0x003FF800U /* buffer 2 length */ 267 #define RXCTL_BUFLEN1 0x000007FFU /* buffer 1 length */ 268 269 /* 270 * Transmit descriptor fields. 271 */ 272 #define TXSTAT_OWN 0x80000000U /* ownership */ 273 #define TXSTAT_URCNT 0x00C00000U /* underrun count */ 274 #define TXSTAT_TXERR 0x00008000U /* error summary */ 275 #define TXSTAT_JABBER 0x00004000U /* jabber timeout */ 276 #define TXSTAT_CARRLOST 0x00000800U /* lost carrier */ 277 #define TXSTAT_NOCARR 0x00000400U /* no carrier */ 278 #define TXSTAT_LATECOL 0x00000200U /* late collision */ 279 #define TXSTAT_EXCOLL 0x00000100U /* excessive collisions */ 280 #define TXSTAT_SQE 0x00000080U /* heartbeat failure */ 281 #define TXSTAT_COLLCNT 0x00000078U /* collision count */ 282 #define TXSTAT_UFLOW 0x00000002U /* underflow */ 283 #define TXSTAT_DEFER 0x00000001U /* deferred */ 284 #define TXCOLLCNT(x) ((x & TXSTAT_COLLCNT) >> 3) 285 #define TXUFLOWCNT(x) ((x & TXSTAT_URCNT) >> 22) 286 287 #define TXCTL_INTCMPLTE 0x80000000U /* interrupt completed */ 288 #define TXCTL_LAST 0x40000000U /* last descriptor */ 289 #define TXCTL_FIRST 0x20000000U /* first descriptor */ 290 #define TXCTL_NOCRC 0x04000000U /* disable crc */ 291 #define TXCTL_ENDRING 0x02000000U /* end of ring */ 292 #define TXCTL_CHAIN 0x01000000U /* chained descriptors */ 293 #define TXCTL_NOPAD 0x00800000U /* disable padding */ 294 #define TXCTL_HASHPERF 0x00400000U /* hash perfect mode */ 295 #define TXCTL_BUFLEN2 0x003FF800U /* buffer length 2 */ 296 #define TXCTL_BUFLEN1 0x000007FFU /* buffer length 1 */ 297 298 299 /* 300 * Interface flags. 301 */ 302 #define AFE_RUNNING 0x1 /* chip is initialized */ 303 #define AFE_SUSPENDED 0x2 /* interface is suspended */ 304 #define AFE_HASFIBER 0x4 /* internal phy supports fiber (AFE_PHY_MCR) */ 305 306 #define AFE_MODEL(afep) ((afep)->afe_cardp->card_model) 307 308 309 /* 310 * Register definitions located in afe.h exported header file. 311 */ 312 313 /* 314 * Macros to simplify hardware access. 315 */ 316 #define GETCSR(afep, reg) \ 317 ddi_get32(afep->afe_regshandle, (uint32_t *)(afep->afe_regs + reg)) 318 319 #define GETCSR16(afep, reg) \ 320 ddi_get16(afep->afe_regshandle, (uint16_t *)(afep->afe_regs + reg)) 321 322 #define PUTCSR(afep, reg, val) \ 323 ddi_put32(afep->afe_regshandle, (uint32_t *)(afep->afe_regs + reg), val) 324 325 #define PUTCSR16(afep, reg, val) \ 326 ddi_put16(afep->afe_regshandle, (uint16_t *)(afep->afe_regs + reg), val) 327 328 #define SETBIT(afep, reg, val) PUTCSR(afep, reg, GETCSR(afep, reg) | (val)) 329 330 #define CLRBIT(afep, reg, val) PUTCSR(afep, reg, GETCSR(afep, reg) & ~(val)) 331 332 #define SYNCTXDESC(afep, index, who) \ 333 (void) ddi_dma_sync(afep->afe_txdesc_dmah, \ 334 (index * sizeof (afe_desc_t)), sizeof (afe_desc_t), who) 335 336 #define SYNCTXBUF(txb, len, who) \ 337 (void) ddi_dma_sync(txb->txb_dmah, 0, len, who) 338 339 #define SYNCRXDESC(afep, index, who) \ 340 (void) ddi_dma_sync(afep->afe_rxdesc_dmah, \ 341 (index * sizeof (afe_desc_t)), sizeof (afe_desc_t), who) 342 343 #define SYNCRXBUF(rxb, len, who) \ 344 (void) ddi_dma_sync(rxb->rxb_dmah, 0, len, who) 345 346 /* 347 * Debugging flags. 348 */ 349 #define DWARN 0x0001 350 #define DINTR 0x0002 351 #define DMACID 0x0008 352 #define DPHY 0x0020 353 #define DPCI 0x0040 354 #define DCHATTY 0x0080 355 #define DDMA 0x0100 356 #define DLINK 0x0200 357 #define DSROM 0x0400 358 #define DRECV 0x0800 359 #define DXMIT 0x1000 360 361 #ifdef DEBUG 362 #define DBG(lvl, ...) afe_dprintf(afep, __func__, lvl, __VA_ARGS__) 363 #else 364 #define DBG(lvl, ...) 365 #endif 366 367 #endif /* _KERNEL */ 368 369 #endif /* _AFEIMPL_H */ 370