1 /* 2 * Solaris driver for ethernet cards based on the ADMtek Centaur 3 * 4 * Copyright (c) 2007 by Garrett D'Amore <garrett@damore.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the author nor the names of any co-contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS ``AS IS'' 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #pragma ident "%Z%%M% %I% %E% SMI" 33 34 #include <sys/varargs.h> 35 #include <sys/types.h> 36 #include <sys/modctl.h> 37 #include <sys/conf.h> 38 #include <sys/devops.h> 39 #include <sys/stream.h> 40 #include <sys/strsun.h> 41 #include <sys/priv.h> 42 #include <sys/policy.h> 43 #include <sys/cred.h> 44 #include <sys/cmn_err.h> 45 #include <sys/dlpi.h> 46 #include <sys/ethernet.h> 47 #include <sys/kmem.h> 48 #include <sys/time.h> 49 #include <sys/crc32.h> 50 #include <sys/miiregs.h> 51 #include <sys/mac.h> 52 #include <sys/mac_ether.h> 53 #include <sys/ddi.h> 54 #include <sys/sunddi.h> 55 56 #include "afe.h" 57 #include "afeimpl.h" 58 59 /* 60 * Driver globals. 61 */ 62 63 /* patchable debug flag ... must not be static! */ 64 #ifdef DEBUG 65 unsigned afe_debug = DWARN; 66 #endif 67 68 /* table of supported devices */ 69 static afe_card_t afe_cards[] = { 70 71 /* 72 * ADMtek Centaur and Comet 73 */ 74 { 0x1317, 0x0981, "ADMtek AL981", MODEL_COMET }, 75 { 0x1317, 0x0985, "ADMtek AN983", MODEL_CENTAUR }, 76 { 0x1317, 0x1985, "ADMtek AN985", MODEL_CENTAUR }, 77 { 0x1317, 0x9511, "ADMtek ADM9511", MODEL_CENTAUR }, 78 { 0x1317, 0x9513, "ADMtek ADM9513", MODEL_CENTAUR }, 79 /* 80 * Accton just relabels other companies' controllers 81 */ 82 { 0x1113, 0x1216, "Accton EN5251", MODEL_CENTAUR }, 83 /* 84 * Models listed here. 85 */ 86 { 0x10b7, 0x9300, "3Com 3CSOHO100B-TX", MODEL_CENTAUR }, 87 { 0x1113, 0xec02, "SMC SMC1244TX", MODEL_CENTAUR }, 88 { 0x10b8, 0x1255, "SMC SMC1255TX", MODEL_CENTAUR }, 89 { 0x111a, 0x1020, "Siemens SpeedStream PCI 10/100", MODEL_CENTAUR }, 90 { 0x1113, 0x1207, "Accton EN1207F", MODEL_CENTAUR }, 91 { 0x1113, 0x2242, "Accton EN2242", MODEL_CENTAUR }, 92 { 0x1113, 0x2220, "Accton EN2220", MODEL_CENTAUR }, 93 { 0x1113, 0x9216, "3M VOL-N100VF+TX", MODEL_CENTAUR }, 94 { 0x1317, 0x0574, "Linksys LNE100TX", MODEL_CENTAUR }, 95 { 0x1317, 0x0570, "Linksys NC100", MODEL_CENTAUR }, 96 { 0x1385, 0x511a, "Netgear FA511", MODEL_CENTAUR }, 97 { 0x13d1, 0xab02, "AboCom FE2500", MODEL_CENTAUR }, 98 { 0x13d1, 0xab03, "AboCom PCM200", MODEL_CENTAUR }, 99 { 0x13d1, 0xab08, "AboCom FE2500MX", MODEL_CENTAUR }, 100 { 0x1414, 0x0001, "Microsoft MN-120", MODEL_CENTAUR }, 101 { 0x16ec, 0x00ed, "U.S. Robotics USR997900", MODEL_CENTAUR }, 102 { 0x1734, 0x100c, "Fujitsu-Siemens D1961", MODEL_CENTAUR }, 103 { 0x1737, 0xab08, "Linksys PCMPC200", MODEL_CENTAUR }, 104 { 0x1737, 0xab09, "Linksys PCM200", MODEL_CENTAUR }, 105 { 0x17b3, 0xab08, "Hawking PN672TX", MODEL_CENTAUR }, 106 }; 107 108 #define ETHERVLANMTU (ETHERMAX + 4) 109 110 /* 111 * Function prototypes 112 */ 113 static int afe_attach(dev_info_t *, ddi_attach_cmd_t); 114 static int afe_detach(dev_info_t *, ddi_detach_cmd_t); 115 static int afe_resume(dev_info_t *); 116 static int afe_m_unicst(void *, const uint8_t *); 117 static int afe_m_multicst(void *, boolean_t, const uint8_t *); 118 static int afe_m_promisc(void *, boolean_t); 119 static mblk_t *afe_m_tx(void *, mblk_t *); 120 static int afe_m_stat(void *, uint_t, uint64_t *); 121 static int afe_m_start(void *); 122 static void afe_m_stop(void *); 123 static void afe_m_ioctl(void *, queue_t *, mblk_t *); 124 static unsigned afe_intr(caddr_t); 125 static void afe_startmac(afe_t *); 126 static void afe_stopmac(afe_t *); 127 static void afe_resetrings(afe_t *); 128 static boolean_t afe_initialize(afe_t *); 129 static void afe_startall(afe_t *); 130 static void afe_stopall(afe_t *); 131 static void afe_resetall(afe_t *); 132 static afe_txbuf_t *afe_alloctxbuf(afe_t *); 133 static void afe_destroytxbuf(afe_txbuf_t *); 134 static afe_rxbuf_t *afe_allocrxbuf(afe_t *); 135 static void afe_destroyrxbuf(afe_rxbuf_t *); 136 static boolean_t afe_send(afe_t *, mblk_t *); 137 static int afe_allocrxring(afe_t *); 138 static void afe_freerxring(afe_t *); 139 static int afe_alloctxring(afe_t *); 140 static void afe_freetxring(afe_t *); 141 static void afe_error(dev_info_t *, char *, ...); 142 static void afe_setrxfilt(afe_t *); 143 static uint8_t afe_sromwidth(afe_t *); 144 static uint16_t afe_readsromword(afe_t *, unsigned); 145 static void afe_readsrom(afe_t *, unsigned, unsigned, char *); 146 static void afe_getfactaddr(afe_t *, uchar_t *); 147 static int afe_miireadbit(afe_t *); 148 static void afe_miiwritebit(afe_t *, int); 149 static void afe_miitristate(afe_t *); 150 static unsigned afe_miiread(afe_t *, int, int); 151 static void afe_miiwrite(afe_t *, int, int, uint16_t); 152 static unsigned afe_miireadgeneral(afe_t *, int, int); 153 static void afe_miiwritegeneral(afe_t *, int, int, uint16_t); 154 static unsigned afe_miireadcomet(afe_t *, int, int); 155 static void afe_miiwritecomet(afe_t *, int, int, uint16_t); 156 static int afe_getmiibit(afe_t *, uint16_t, uint16_t); 157 static void afe_startphy(afe_t *); 158 static void afe_stopphy(afe_t *); 159 static void afe_reportlink(afe_t *); 160 static void afe_checklink(afe_t *); 161 static void afe_checklinkcomet(afe_t *); 162 static void afe_checklinkcentaur(afe_t *); 163 static void afe_checklinkmii(afe_t *); 164 static void afe_disableinterrupts(afe_t *); 165 static void afe_enableinterrupts(afe_t *); 166 static void afe_reclaim(afe_t *); 167 static mblk_t *afe_receive(afe_t *); 168 static int afe_ndaddbytes(mblk_t *, char *, int); 169 static int afe_ndaddstr(mblk_t *, char *, int); 170 static void afe_ndparsestring(mblk_t *, char *, int); 171 static int afe_ndparselen(mblk_t *); 172 static int afe_ndparseint(mblk_t *); 173 static void afe_ndget(afe_t *, queue_t *, mblk_t *); 174 static void afe_ndset(afe_t *, queue_t *, mblk_t *); 175 static void afe_ndfini(afe_t *); 176 static void afe_ndinit(afe_t *); 177 static int afe_ndquestion(afe_t *, mblk_t *, afe_nd_t *); 178 static int afe_ndgetint(afe_t *, mblk_t *, afe_nd_t *); 179 static int afe_ndgetmiibit(afe_t *, mblk_t *, afe_nd_t *); 180 static int afe_ndsetadv(afe_t *, mblk_t *, afe_nd_t *); 181 static afe_nd_t *afe_ndfind(afe_t *, char *); 182 static void afe_ndempty(mblk_t *); 183 static void afe_ndadd(afe_t *, char *, afe_nd_pf_t, afe_nd_pf_t, 184 intptr_t, intptr_t); 185 186 #ifdef DEBUG 187 static void afe_dprintf(afe_t *, const char *, int, char *, ...); 188 #endif 189 190 #define KIOIP KSTAT_INTR_PTR(afep->afe_intrstat) 191 192 static mac_callbacks_t afe_m_callbacks = { 193 MC_IOCTL, 194 afe_m_stat, 195 afe_m_start, 196 afe_m_stop, 197 afe_m_promisc, 198 afe_m_multicst, 199 afe_m_unicst, 200 afe_m_tx, 201 NULL, 202 afe_m_ioctl, 203 NULL, /* m_getcapab */ 204 }; 205 206 207 /* 208 * Stream information 209 */ 210 DDI_DEFINE_STREAM_OPS(afe_devops, nulldev, nulldev, afe_attach, afe_detach, 211 nodev, NULL, D_MP, NULL); 212 213 /* 214 * Module linkage information. 215 */ 216 217 static struct modldrv afe_modldrv = { 218 &mod_driverops, /* drv_modops */ 219 "ADMtek Fast Ethernet", /* drv_linkinfo */ 220 &afe_devops /* drv_dev_ops */ 221 }; 222 223 static struct modlinkage afe_modlinkage = { 224 MODREV_1, /* ml_rev */ 225 { &afe_modldrv, NULL } /* ml_linkage */ 226 }; 227 228 /* 229 * Device attributes. 230 */ 231 static ddi_device_acc_attr_t afe_devattr = { 232 DDI_DEVICE_ATTR_V0, 233 DDI_STRUCTURE_LE_ACC, 234 DDI_STRICTORDER_ACC 235 }; 236 237 static ddi_device_acc_attr_t afe_bufattr = { 238 DDI_DEVICE_ATTR_V0, 239 DDI_NEVERSWAP_ACC, 240 DDI_STRICTORDER_ACC 241 }; 242 243 static ddi_dma_attr_t afe_dma_attr = { 244 DMA_ATTR_V0, /* dma_attr_version */ 245 0, /* dma_attr_addr_lo */ 246 0xFFFFFFFFU, /* dma_attr_addr_hi */ 247 0x7FFFFFFFU, /* dma_attr_count_max */ 248 4, /* dma_attr_align */ 249 0x3F, /* dma_attr_burstsizes */ 250 1, /* dma_attr_minxfer */ 251 0xFFFFFFFFU, /* dma_attr_maxxfer */ 252 0xFFFFFFFFU, /* dma_attr_seg */ 253 1, /* dma_attr_sgllen */ 254 1, /* dma_attr_granular */ 255 0 /* dma_attr_flags */ 256 }; 257 258 /* 259 * Tx buffers can be arbitrarily aligned. Additionally, they can 260 * cross a page boundary, so we use the two buffer addresses of the 261 * chip to provide a two-entry scatter-gather list. 262 */ 263 static ddi_dma_attr_t afe_dma_txattr = { 264 DMA_ATTR_V0, /* dma_attr_version */ 265 0, /* dma_attr_addr_lo */ 266 0xFFFFFFFFU, /* dma_attr_addr_hi */ 267 0x7FFFFFFFU, /* dma_attr_count_max */ 268 1, /* dma_attr_align */ 269 0x3F, /* dma_attr_burstsizes */ 270 1, /* dma_attr_minxfer */ 271 0xFFFFFFFFU, /* dma_attr_maxxfer */ 272 0xFFFFFFFFU, /* dma_attr_seg */ 273 2, /* dma_attr_sgllen */ 274 1, /* dma_attr_granular */ 275 0 /* dma_attr_flags */ 276 }; 277 278 /* 279 * Ethernet addresses. 280 */ 281 static uchar_t afe_broadcast[ETHERADDRL] = { 282 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 283 }; 284 285 /* 286 * DDI entry points. 287 */ 288 int 289 _init(void) 290 { 291 int rv; 292 mac_init_ops(&afe_devops, "afe"); 293 if ((rv = mod_install(&afe_modlinkage)) != DDI_SUCCESS) { 294 mac_fini_ops(&afe_devops); 295 } 296 return (rv); 297 } 298 299 int 300 _fini(void) 301 { 302 int rv; 303 if ((rv = mod_remove(&afe_modlinkage)) == DDI_SUCCESS) { 304 mac_fini_ops(&afe_devops); 305 } 306 return (rv); 307 } 308 309 int 310 _info(struct modinfo *modinfop) 311 { 312 return (mod_info(&afe_modlinkage, modinfop)); 313 } 314 315 int 316 afe_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 317 { 318 afe_t *afep; 319 mac_register_t *macp; 320 int inst = ddi_get_instance(dip); 321 ddi_acc_handle_t pci; 322 uint16_t venid; 323 uint16_t devid; 324 uint16_t svid; 325 uint16_t ssid; 326 uint16_t cachesize; 327 afe_card_t *cardp; 328 int i; 329 330 switch (cmd) { 331 case DDI_RESUME: 332 return (afe_resume(dip)); 333 334 case DDI_ATTACH: 335 break; 336 337 default: 338 return (DDI_FAILURE); 339 } 340 341 /* this card is a bus master, reject any slave-only slot */ 342 if (ddi_slaveonly(dip) == DDI_SUCCESS) { 343 afe_error(dip, "slot does not support PCI bus-master"); 344 return (DDI_FAILURE); 345 } 346 /* PCI devices shouldn't generate hilevel interrupts */ 347 if (ddi_intr_hilevel(dip, 0) != 0) { 348 afe_error(dip, "hilevel interrupts not supported"); 349 return (DDI_FAILURE); 350 } 351 if (pci_config_setup(dip, &pci) != DDI_SUCCESS) { 352 afe_error(dip, "unable to setup PCI config handle"); 353 return (DDI_FAILURE); 354 } 355 356 venid = pci_config_get16(pci, PCI_VID); 357 devid = pci_config_get16(pci, PCI_DID); 358 svid = pci_config_get16(pci, PCI_SVID); 359 ssid = pci_config_get16(pci, PCI_SSID); 360 361 /* 362 * Note: ADMtek boards seem to misprogram themselves with bogus 363 * timings, which do not seem to work properly on SPARC. We 364 * reprogram them zero (but only if they appear to be broken), 365 * which seems to at least work. Its unclear that this is a 366 * legal or wise practice to me, but it certainly works better 367 * than the original values. (I would love to hear 368 * suggestions for better values, or a better strategy.) 369 */ 370 if ((pci_config_get8(pci, PCI_MINGNT) == 0xff) && 371 (pci_config_get8(pci, PCI_MAXLAT) == 0xff)) { 372 pci_config_put8(pci, PCI_MINGNT, 0); 373 pci_config_put8(pci, PCI_MAXLAT, 0); 374 } 375 376 /* 377 * the last entry in the card table matches every possible 378 * card, so the for-loop always terminates properly. 379 */ 380 cardp = NULL; 381 for (i = 0; i < (sizeof (afe_cards) / sizeof (afe_card_t)); i++) { 382 if ((venid == afe_cards[i].card_venid) && 383 (devid == afe_cards[i].card_devid)) { 384 cardp = &afe_cards[i]; 385 } 386 if ((svid == afe_cards[i].card_venid) && 387 (ssid == afe_cards[i].card_devid)) { 388 cardp = &afe_cards[i]; 389 break; 390 } 391 } 392 393 if (cardp == NULL) { 394 pci_config_teardown(&pci); 395 afe_error(dip, "Unable to identify PCI card"); 396 return (DDI_FAILURE); 397 } 398 399 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 400 cardp->card_cardname) != DDI_PROP_SUCCESS) { 401 pci_config_teardown(&pci); 402 afe_error(dip, "Unable to create model property"); 403 return (DDI_FAILURE); 404 } 405 406 /* 407 * Grab the PCI cachesize -- we use this to program the 408 * cache-optimization bus access bits. 409 */ 410 cachesize = pci_config_get8(pci, PCI_CLS); 411 412 /* this cannot fail */ 413 afep = kmem_zalloc(sizeof (afe_t), KM_SLEEP); 414 ddi_set_driver_private(dip, afep); 415 416 /* get the interrupt block cookie */ 417 if (ddi_get_iblock_cookie(dip, 0, &afep->afe_icookie) != DDI_SUCCESS) { 418 afe_error(dip, "ddi_get_iblock_cookie failed"); 419 pci_config_teardown(&pci); 420 kmem_free(afep, sizeof (afe_t)); 421 return (DDI_FAILURE); 422 } 423 424 afep->afe_dip = dip; 425 afep->afe_cardp = cardp; 426 afep->afe_phyaddr = -1; 427 afep->afe_cachesize = cachesize; 428 429 /* default properties */ 430 afep->afe_adv_aneg = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 431 "adv_autoneg_cap", 1); 432 afep->afe_adv_100T4 = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 433 "adv_100T4_cap", 1); 434 afep->afe_adv_100fdx = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 435 "adv_100fdx_cap", 1); 436 afep->afe_adv_100hdx = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 437 "adv_100hdx_cap", 1); 438 afep->afe_adv_10fdx = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 439 "adv_10fdx_cap", 1); 440 afep->afe_adv_10hdx = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 441 "adv_10hdx_cap", 1); 442 443 afep->afe_forcefiber = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 444 "fiber", 0); 445 446 DBG(DPCI, "PCI vendor id = %x", venid); 447 DBG(DPCI, "PCI device id = %x", devid); 448 DBG(DPCI, "PCI cachesize = %d", cachesize); 449 DBG(DPCI, "PCI COMM = %x", pci_config_get8(pci, PCI_CMD)); 450 DBG(DPCI, "PCI STAT = %x", pci_config_get8(pci, PCI_STAT)); 451 452 mutex_init(&afep->afe_xmtlock, NULL, MUTEX_DRIVER, afep->afe_icookie); 453 mutex_init(&afep->afe_intrlock, NULL, MUTEX_DRIVER, afep->afe_icookie); 454 455 afe_ndinit(afep); 456 457 /* 458 * Enable bus master, IO space, and memory space accesses. 459 */ 460 pci_config_put16(pci, PCI_CMD, 461 pci_config_get16(pci, PCI_CMD) | PCI_CMD_BME | PCI_CMD_MAE); 462 463 /* we're done with this now, drop it */ 464 pci_config_teardown(&pci); 465 466 /* 467 * Initialize interrupt kstat. This should not normally fail, since 468 * we don't use a persistent stat. We do it this way to avoid having 469 * to test for it at run time on the hot path. 470 */ 471 afep->afe_intrstat = kstat_create("afe", inst, "intr", "controller", 472 KSTAT_TYPE_INTR, 1, 0); 473 if (afep->afe_intrstat == NULL) { 474 afe_error(dip, "kstat_create failed"); 475 goto failed; 476 } 477 kstat_install(afep->afe_intrstat); 478 479 /* 480 * Map in the device registers. 481 */ 482 if (ddi_regs_map_setup(dip, 1, (caddr_t *)&afep->afe_regs, 483 0, 0, &afe_devattr, &afep->afe_regshandle)) { 484 afe_error(dip, "ddi_regs_map_setup failed"); 485 goto failed; 486 } 487 488 /* 489 * Allocate DMA resources (descriptor rings and buffers). 490 */ 491 if ((afe_allocrxring(afep) != DDI_SUCCESS) || 492 (afe_alloctxring(afep) != DDI_SUCCESS)) { 493 afe_error(dip, "unable to allocate DMA resources"); 494 goto failed; 495 } 496 497 /* Initialize the chip. */ 498 mutex_enter(&afep->afe_intrlock); 499 mutex_enter(&afep->afe_xmtlock); 500 if (!afe_initialize(afep)) { 501 mutex_exit(&afep->afe_xmtlock); 502 mutex_exit(&afep->afe_intrlock); 503 goto failed; 504 } 505 mutex_exit(&afep->afe_xmtlock); 506 mutex_exit(&afep->afe_intrlock); 507 508 /* Determine the number of address bits to our EEPROM. */ 509 afep->afe_sromwidth = afe_sromwidth(afep); 510 511 /* 512 * Get the factory ethernet address. This becomes the current 513 * ethernet address (it can be overridden later via ifconfig). 514 */ 515 afe_getfactaddr(afep, afep->afe_curraddr); 516 afep->afe_promisc = B_FALSE; 517 518 /* make sure we add configure the initial filter */ 519 (void) afe_m_unicst(afep, afep->afe_curraddr); 520 (void) afe_m_multicst(afep, B_TRUE, afe_broadcast); 521 522 /* 523 * Establish interrupt handler. 524 */ 525 if (ddi_add_intr(dip, 0, NULL, NULL, afe_intr, (caddr_t)afep) != 526 DDI_SUCCESS) { 527 afe_error(dip, "unable to add interrupt"); 528 goto failed; 529 } 530 531 /* TODO: do the power management stuff */ 532 533 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 534 afe_error(dip, "mac_alloc failed"); 535 goto failed; 536 } 537 538 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 539 macp->m_driver = afep; 540 macp->m_dip = dip; 541 macp->m_src_addr = afep->afe_curraddr; 542 macp->m_callbacks = &afe_m_callbacks; 543 macp->m_min_sdu = 0; 544 macp->m_max_sdu = ETHERMTU; 545 546 if (mac_register(macp, &afep->afe_mh) == DDI_SUCCESS) { 547 mac_free(macp); 548 return (DDI_SUCCESS); 549 } 550 551 /* failed to register with MAC */ 552 mac_free(macp); 553 failed: 554 if (afep->afe_icookie != NULL) { 555 ddi_remove_intr(dip, 0, afep->afe_icookie); 556 } 557 if (afep->afe_intrstat) { 558 kstat_delete(afep->afe_intrstat); 559 } 560 afe_ndfini(afep); 561 mutex_destroy(&afep->afe_intrlock); 562 mutex_destroy(&afep->afe_xmtlock); 563 564 afe_freerxring(afep); 565 afe_freetxring(afep); 566 567 if (afep->afe_regshandle != NULL) { 568 ddi_regs_map_free(&afep->afe_regshandle); 569 } 570 kmem_free(afep, sizeof (afe_t)); 571 return (DDI_FAILURE); 572 } 573 574 int 575 afe_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 576 { 577 afe_t *afep; 578 579 afep = ddi_get_driver_private(dip); 580 if (afep == NULL) { 581 afe_error(dip, "no soft state in detach!"); 582 return (DDI_FAILURE); 583 } 584 585 switch (cmd) { 586 case DDI_DETACH: 587 588 if (mac_unregister(afep->afe_mh) != 0) { 589 return (DDI_FAILURE); 590 } 591 592 /* make sure hardware is quiesced */ 593 mutex_enter(&afep->afe_intrlock); 594 mutex_enter(&afep->afe_xmtlock); 595 afep->afe_flags &= ~AFE_RUNNING; 596 afe_stopall(afep); 597 mutex_exit(&afep->afe_xmtlock); 598 mutex_exit(&afep->afe_intrlock); 599 600 /* clean up and shut down device */ 601 ddi_remove_intr(dip, 0, afep->afe_icookie); 602 603 /* clean up kstats */ 604 kstat_delete(afep->afe_intrstat); 605 606 ddi_prop_remove_all(dip); 607 608 /* free up any left over buffers or DMA resources */ 609 afe_freerxring(afep); 610 afe_freetxring(afep); 611 612 afe_ndfini(afep); 613 ddi_regs_map_free(&afep->afe_regshandle); 614 mutex_destroy(&afep->afe_intrlock); 615 mutex_destroy(&afep->afe_xmtlock); 616 617 kmem_free(afep, sizeof (afe_t)); 618 return (DDI_SUCCESS); 619 620 case DDI_SUSPEND: 621 /* quiesce the hardware */ 622 mutex_enter(&afep->afe_intrlock); 623 mutex_enter(&afep->afe_xmtlock); 624 afep->afe_flags |= AFE_SUSPENDED; 625 afe_stopall(afep); 626 mutex_exit(&afep->afe_xmtlock); 627 mutex_exit(&afep->afe_intrlock); 628 return (DDI_SUCCESS); 629 default: 630 return (DDI_FAILURE); 631 } 632 } 633 634 int 635 afe_resume(dev_info_t *dip) 636 { 637 afe_t *afep; 638 639 if ((afep = ddi_get_driver_private(dip)) == NULL) { 640 return (DDI_FAILURE); 641 } 642 643 mutex_enter(&afep->afe_intrlock); 644 mutex_enter(&afep->afe_xmtlock); 645 646 afep->afe_flags &= ~AFE_SUSPENDED; 647 648 /* re-initialize chip */ 649 if (!afe_initialize(afep)) { 650 afe_error(afep->afe_dip, "unable to resume chip!"); 651 afep->afe_flags |= AFE_SUSPENDED; 652 mutex_exit(&afep->afe_intrlock); 653 mutex_exit(&afep->afe_xmtlock); 654 return (DDI_SUCCESS); 655 } 656 657 /* start the chip */ 658 if (afep->afe_flags & AFE_RUNNING) { 659 afe_startall(afep); 660 } 661 662 /* drop locks */ 663 mutex_exit(&afep->afe_xmtlock); 664 mutex_exit(&afep->afe_intrlock); 665 666 return (DDI_SUCCESS); 667 } 668 669 void 670 afe_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 671 { 672 afe_t *afep = arg; 673 674 switch (*(int *)(void *)(mp->b_rptr)) { 675 676 case NDIOC_GET: 677 afe_ndget(afep, wq, mp); 678 break; 679 680 case NDIOC_SET: 681 afe_ndset(afep, wq, mp); 682 break; 683 684 default: 685 miocnak(wq, mp, 0, EINVAL); 686 break; 687 } 688 } 689 690 void 691 afe_setrxfilt(afe_t *afep) 692 { 693 unsigned rxen, pa0, pa1; 694 695 if (afep->afe_flags & AFE_SUSPENDED) { 696 /* don't touch a suspended interface */ 697 return; 698 } 699 700 rxen = GETCSR(afep, CSR_NAR) & NAR_RX_ENABLE; 701 702 /* stop receiver */ 703 if (rxen) { 704 afe_stopmac(afep); 705 } 706 707 /* program promiscuous mode */ 708 if (afep->afe_promisc) 709 SETBIT(afep, CSR_NAR, NAR_RX_PROMISC); 710 else 711 CLRBIT(afep, CSR_NAR, NAR_RX_PROMISC); 712 713 /* program mac address */ 714 pa0 = (afep->afe_curraddr[3] << 24) | (afep->afe_curraddr[2] << 16) | 715 (afep->afe_curraddr[1] << 8) | afep->afe_curraddr[0]; 716 pa1 = (afep->afe_curraddr[5] << 8) | afep->afe_curraddr[4]; 717 718 DBG(DMACID, "programming PAR0 with %x", pa0); 719 DBG(DMACID, "programming PAR1 with %x", pa1); 720 PUTCSR(afep, CSR_PAR0, pa0); 721 PUTCSR(afep, CSR_PAR1, pa1); 722 if (rxen) { 723 SETBIT(afep, CSR_NAR, rxen); 724 } 725 726 DBG(DMACID, "programming MAR0 = %x", afep->afe_mctab[0]); 727 DBG(DMACID, "programming MAR1 = %x", afep->afe_mctab[1]); 728 729 /* program multicast filter */ 730 if (AFE_MODEL(afep) == MODEL_COMET) { 731 if (afep->afe_mctab[0] || afep->afe_mctab[1]) { 732 SETBIT(afep, CSR_NAR, NAR_RX_MULTI); 733 } else { 734 CLRBIT(afep, CSR_NAR, NAR_RX_MULTI); 735 } 736 } else { 737 CLRBIT(afep, CSR_NAR, NAR_RX_MULTI); 738 PUTCSR(afep, CSR_MAR0, afep->afe_mctab[0]); 739 PUTCSR(afep, CSR_MAR1, afep->afe_mctab[1]); 740 } 741 742 /* restart receiver */ 743 if (rxen) { 744 afe_startmac(afep); 745 } 746 } 747 748 int 749 afe_m_multicst(void *arg, boolean_t add, const uint8_t *macaddr) 750 { 751 afe_t *afep = arg; 752 int index; 753 uint32_t crc; 754 uint32_t bit; 755 uint32_t newval, oldval; 756 757 CRC32(crc, macaddr, ETHERADDRL, -1U, crc32_table); 758 crc %= AFE_MCHASH; 759 760 /* bit within a 32-bit word */ 761 index = crc / 32; 762 bit = (1 << (crc % 32)); 763 764 mutex_enter(&afep->afe_intrlock); 765 mutex_enter(&afep->afe_xmtlock); 766 newval = oldval = afep->afe_mctab[index]; 767 768 if (add) { 769 afep->afe_mccount[crc]++; 770 if (afep->afe_mccount[crc] == 1) 771 newval |= bit; 772 } else { 773 afep->afe_mccount[crc]--; 774 if (afep->afe_mccount[crc] == 0) 775 newval &= ~bit; 776 } 777 if (newval != oldval) { 778 afep->afe_mctab[index] = newval; 779 afe_setrxfilt(afep); 780 } 781 782 mutex_exit(&afep->afe_xmtlock); 783 mutex_exit(&afep->afe_intrlock); 784 785 return (0); 786 } 787 788 int 789 afe_m_promisc(void *arg, boolean_t on) 790 { 791 afe_t *afep = arg; 792 793 /* exclusive access to the card while we reprogram it */ 794 mutex_enter(&afep->afe_intrlock); 795 mutex_enter(&afep->afe_xmtlock); 796 /* save current promiscuous mode state for replay in resume */ 797 afep->afe_promisc = on; 798 799 afe_setrxfilt(afep); 800 mutex_exit(&afep->afe_xmtlock); 801 mutex_exit(&afep->afe_intrlock); 802 803 return (0); 804 } 805 806 int 807 afe_m_unicst(void *arg, const uint8_t *macaddr) 808 { 809 afe_t *afep = arg; 810 811 /* exclusive access to the card while we reprogram it */ 812 mutex_enter(&afep->afe_intrlock); 813 mutex_enter(&afep->afe_xmtlock); 814 815 bcopy(macaddr, afep->afe_curraddr, ETHERADDRL); 816 afe_setrxfilt(afep); 817 818 mutex_exit(&afep->afe_xmtlock); 819 mutex_exit(&afep->afe_intrlock); 820 821 return (0); 822 } 823 824 mblk_t * 825 afe_m_tx(void *arg, mblk_t *mp) 826 { 827 afe_t *afep = arg; 828 mblk_t *nmp; 829 830 mutex_enter(&afep->afe_xmtlock); 831 832 if (afep->afe_flags & AFE_SUSPENDED) { 833 while ((nmp = mp) != NULL) { 834 afep->afe_carrier_errors++; 835 mp = mp->b_next; 836 freemsg(nmp); 837 } 838 mutex_exit(&afep->afe_xmtlock); 839 return (NULL); 840 } 841 842 while (mp != NULL) { 843 nmp = mp->b_next; 844 mp->b_next = NULL; 845 846 if (!afe_send(afep, mp)) { 847 mp->b_next = nmp; 848 break; 849 } 850 mp = nmp; 851 } 852 mutex_exit(&afep->afe_xmtlock); 853 854 return (mp); 855 } 856 857 /* 858 * Hardware management. 859 */ 860 static boolean_t 861 afe_initialize(afe_t *afep) 862 { 863 int i; 864 unsigned val; 865 uint32_t par, nar; 866 867 ASSERT(mutex_owned(&afep->afe_intrlock)); 868 ASSERT(mutex_owned(&afep->afe_xmtlock)); 869 870 DBG(DCHATTY, "resetting!"); 871 SETBIT(afep, CSR_PAR, PAR_RESET); 872 for (i = 1; i < 10; i++) { 873 drv_usecwait(5); 874 val = GETCSR(afep, CSR_PAR); 875 if (!(val & PAR_RESET)) { 876 break; 877 } 878 } 879 if (i == 10) { 880 afe_error(afep->afe_dip, "timed out waiting for reset!"); 881 return (B_FALSE); 882 } 883 884 /* 885 * Updated Centaur data sheets show that the Comet and Centaur are 886 * alike here (contrary to earlier versions of the data sheet). 887 */ 888 /* XXX:? chip problems */ 889 /* par = PAR_MRLE | PAR_MRME | PAR_MWIE; */ 890 par = 0; 891 switch (afep->afe_cachesize) { 892 case 8: 893 par |= PAR_CALIGN_8 | PAR_BURST_8; 894 break; 895 case 16: 896 par |= PAR_CALIGN_16 | PAR_BURST_16; 897 break; 898 case 32: 899 par |= PAR_CALIGN_32 | PAR_BURST_32; 900 break; 901 default: 902 par |= PAR_BURST_32; 903 par &= ~(PAR_MWIE | PAR_MRLE | PAR_MRME); 904 break; 905 906 } 907 908 PUTCSR(afep, CSR_PAR, par); 909 910 /* enable transmit underrun auto-recovery */ 911 SETBIT(afep, CSR_CR, CR_TXURAUTOR); 912 913 afe_resetrings(afep); 914 915 /* clear the lost packet counter (cleared on read) */ 916 (void) GETCSR(afep, CSR_LPC); 917 918 nar = GETCSR(afep, CSR_NAR); 919 nar &= ~NAR_TR; /* clear tx threshold */ 920 nar |= NAR_SF; /* store-and-forward */ 921 nar |= NAR_HBD; /* disable SQE test */ 922 PUTCSR(afep, CSR_NAR, nar); 923 924 afe_setrxfilt(afep); 925 926 return (B_TRUE); 927 } 928 929 /* 930 * Serial EEPROM access - inspired by the FreeBSD implementation. 931 */ 932 933 uint8_t 934 afe_sromwidth(afe_t *afep) 935 { 936 int i; 937 uint32_t eeread; 938 uint8_t addrlen = 8; 939 940 eeread = SPR_SROM_READ | SPR_SROM_SEL | SPR_SROM_CHIP; 941 942 PUTCSR(afep, CSR_SPR, eeread & ~SPR_SROM_CHIP); 943 drv_usecwait(1); 944 PUTCSR(afep, CSR_SPR, eeread); 945 946 /* command bits first */ 947 for (i = 4; i != 0; i >>= 1) { 948 unsigned val = (SROM_READCMD & i) ? SPR_SROM_DIN : 0; 949 950 PUTCSR(afep, CSR_SPR, eeread | val); 951 drv_usecwait(1); 952 PUTCSR(afep, CSR_SPR, eeread | val | SPR_SROM_CLOCK); 953 drv_usecwait(1); 954 } 955 956 PUTCSR(afep, CSR_SPR, eeread); 957 958 for (addrlen = 1; addrlen <= 12; addrlen++) { 959 PUTCSR(afep, CSR_SPR, eeread | SPR_SROM_CLOCK); 960 drv_usecwait(1); 961 if (!(GETCSR(afep, CSR_SPR) & SPR_SROM_DOUT)) { 962 PUTCSR(afep, CSR_SPR, eeread); 963 drv_usecwait(1); 964 break; 965 } 966 PUTCSR(afep, CSR_SPR, eeread); 967 drv_usecwait(1); 968 } 969 970 /* turn off accesses to the EEPROM */ 971 PUTCSR(afep, CSR_SPR, eeread &~ SPR_SROM_CHIP); 972 973 DBG(DSROM, "detected srom width = %d bits", addrlen); 974 975 return ((addrlen < 4 || addrlen > 12) ? 6 : addrlen); 976 } 977 978 /* 979 * The words in EEPROM are stored in little endian order. We 980 * shift bits out in big endian order, though. This requires 981 * a byte swap on some platforms. 982 */ 983 uint16_t 984 afe_readsromword(afe_t *afep, unsigned romaddr) 985 { 986 int i; 987 uint16_t word = 0; 988 uint16_t retval; 989 int eeread; 990 uint8_t addrlen; 991 int readcmd; 992 uchar_t *ptr; 993 994 eeread = SPR_SROM_READ | SPR_SROM_SEL | SPR_SROM_CHIP; 995 addrlen = afep->afe_sromwidth; 996 readcmd = (SROM_READCMD << addrlen) | romaddr; 997 998 if (romaddr >= (1 << addrlen)) { 999 /* too big to fit! */ 1000 return (0); 1001 } 1002 1003 PUTCSR(afep, CSR_SPR, eeread & ~SPR_SROM_CHIP); 1004 PUTCSR(afep, CSR_SPR, eeread); 1005 1006 /* command and address bits */ 1007 for (i = 4 + addrlen; i >= 0; i--) { 1008 short val = (readcmd & (1 << i)) ? SPR_SROM_DIN : 0; 1009 1010 PUTCSR(afep, CSR_SPR, eeread | val); 1011 drv_usecwait(1); 1012 PUTCSR(afep, CSR_SPR, eeread | val | SPR_SROM_CLOCK); 1013 drv_usecwait(1); 1014 } 1015 1016 PUTCSR(afep, CSR_SPR, eeread); 1017 1018 for (i = 0; i < 16; i++) { 1019 PUTCSR(afep, CSR_SPR, eeread | SPR_SROM_CLOCK); 1020 drv_usecwait(1); 1021 word <<= 1; 1022 if (GETCSR(afep, CSR_SPR) & SPR_SROM_DOUT) { 1023 word |= 1; 1024 } 1025 PUTCSR(afep, CSR_SPR, eeread); 1026 drv_usecwait(1); 1027 } 1028 1029 /* turn off accesses to the EEPROM */ 1030 PUTCSR(afep, CSR_SPR, eeread &~ SPR_SROM_CHIP); 1031 1032 /* 1033 * Fix up the endianness thing. Note that the values 1034 * are stored in little endian format on the SROM. 1035 */ 1036 ptr = (uchar_t *)&word; 1037 retval = (ptr[1] << 8) | ptr[0]; 1038 return (retval); 1039 } 1040 1041 void 1042 afe_readsrom(afe_t *afep, unsigned romaddr, unsigned len, char *dest) 1043 { 1044 int i; 1045 uint16_t word; 1046 uint16_t *ptr = (uint16_t *)((void *)dest); 1047 for (i = 0; i < len; i++) { 1048 word = afe_readsromword(afep, romaddr + i); 1049 *ptr = word; 1050 ptr++; 1051 } 1052 } 1053 1054 void 1055 afe_getfactaddr(afe_t *afep, uchar_t *eaddr) 1056 { 1057 afe_readsrom(afep, SROM_ENADDR, ETHERADDRL / 2, (char *)eaddr); 1058 1059 DBG(DMACID, 1060 "factory ethernet address = %02x:%02x:%02x:%02x:%02x:%02x", 1061 eaddr[0], eaddr[1], eaddr[2], eaddr[3], eaddr[4], eaddr[5]); 1062 } 1063 1064 /* 1065 * MII management. 1066 */ 1067 void 1068 afe_startphy(afe_t *afep) 1069 { 1070 unsigned phyaddr; 1071 unsigned bmcr; 1072 unsigned bmsr; 1073 unsigned anar; 1074 unsigned phyidr1; 1075 unsigned phyidr2; 1076 unsigned nosqe = 0; 1077 int retries; 1078 int force; 1079 int fiber; 1080 int cnt; 1081 1082 /* ADMtek devices just use the PHY at address 1 */ 1083 afep->afe_phyaddr = phyaddr = 1; 1084 1085 phyidr1 = afe_miiread(afep, phyaddr, MII_PHYIDH); 1086 phyidr2 = afe_miiread(afep, phyaddr, MII_PHYIDL); 1087 if ((phyidr1 == 0x0022) && 1088 ((phyidr2 & 0xfff0) == 0x5410)) { 1089 nosqe = 1; 1090 /* only 983B has fiber support */ 1091 afep->afe_flags |= AFE_HASFIBER; 1092 } 1093 afep->afe_phyid = (phyidr1 << 16) | phyidr2; 1094 1095 DBG(DPHY, "phy at %d: %x,%x", phyaddr, phyidr1, phyidr2); 1096 DBG(DPHY, "bmsr = %x", afe_miiread(afep, 1097 afep->afe_phyaddr, MII_STATUS)); 1098 DBG(DPHY, "anar = %x", afe_miiread(afep, 1099 afep->afe_phyaddr, MII_AN_ADVERT)); 1100 DBG(DPHY, "anlpar = %x", afe_miiread(afep, 1101 afep->afe_phyaddr, MII_AN_LPABLE)); 1102 DBG(DPHY, "aner = %x", afe_miiread(afep, 1103 afep->afe_phyaddr, MII_AN_EXPANSION)); 1104 1105 DBG(DPHY, "resetting phy"); 1106 1107 /* we reset the phy block */ 1108 afe_miiwrite(afep, phyaddr, MII_CONTROL, MII_CONTROL_RESET); 1109 /* 1110 * wait for it to complete -- 500usec is still to short to 1111 * bother getting the system clock involved. 1112 */ 1113 drv_usecwait(500); 1114 for (retries = 0; retries < 10; retries++) { 1115 if (afe_miiread(afep, phyaddr, MII_CONTROL) & 1116 MII_CONTROL_RESET) { 1117 drv_usecwait(500); 1118 continue; 1119 } 1120 break; 1121 } 1122 if (retries == 100) { 1123 afe_error(afep->afe_dip, "timeout waiting on phy to reset"); 1124 return; 1125 } 1126 1127 DBG(DPHY, "phy reset complete"); 1128 1129 bmsr = afe_miiread(afep, phyaddr, MII_STATUS); 1130 anar = afe_miiread(afep, phyaddr, MII_AN_ADVERT); 1131 1132 anar &= ~(MII_ABILITY_100BASE_T4 | 1133 MII_ABILITY_100BASE_TX_FD | MII_ABILITY_100BASE_TX | 1134 MII_ABILITY_10BASE_T_FD | MII_ABILITY_10BASE_T); 1135 1136 force = 0; 1137 fiber = 0; 1138 1139 /* if fiber is being forced, and device supports fiber... */ 1140 if (afep->afe_flags & AFE_HASFIBER) { 1141 1142 uint16_t mcr; 1143 1144 DBG(DPHY, "device supports 100BaseFX"); 1145 mcr = afe_miiread(afep, phyaddr, PHY_MCR); 1146 switch (afep->afe_forcefiber) { 1147 case 0: 1148 /* UTP Port */ 1149 DBG(DPHY, "forcing twpair"); 1150 mcr &= ~MCR_FIBER; 1151 fiber = 0; 1152 break; 1153 case 1: 1154 /* Fiber Port */ 1155 force = 1; 1156 DBG(DPHY, "forcing 100BaseFX"); 1157 mcr |= MCR_FIBER; 1158 bmcr = (MII_CONTROL_100MB | MII_CONTROL_FDUPLEX); 1159 fiber = 1; 1160 break; 1161 default: 1162 DBG(DPHY, "checking for 100BaseFX link"); 1163 /* fiber is 100 Mb FDX */ 1164 afe_miiwrite(afep, phyaddr, MII_CONTROL, 1165 MII_CONTROL_100MB | MII_CONTROL_FDUPLEX); 1166 drv_usecwait(50); 1167 1168 mcr = afe_miiread(afep, phyaddr, PHY_MCR); 1169 mcr |= MCR_FIBER; 1170 afe_miiwrite(afep, phyaddr, PHY_MCR, mcr); 1171 drv_usecwait(500); 1172 1173 /* if fiber is active, use it */ 1174 if ((afe_miiread(afep, phyaddr, MII_STATUS) & 1175 MII_STATUS_LINKUP)) { 1176 bmcr = MII_CONTROL_100MB | MII_CONTROL_FDUPLEX; 1177 fiber = 1; 1178 } else { 1179 mcr &= ~MCR_FIBER; 1180 fiber = 0; 1181 } 1182 break; 1183 } 1184 afe_miiwrite(afep, phyaddr, PHY_MCR, mcr); 1185 drv_usecwait(500); 1186 } 1187 1188 if (fiber) { 1189 /* fiber only supports 100FDX(?) */ 1190 bmsr &= ~(MII_STATUS_100_BASE_T4 | 1191 MII_STATUS_100_BASEX | MII_STATUS_10_FD | MII_STATUS_10); 1192 bmsr |= MII_STATUS_100_BASEX_FD; 1193 } 1194 1195 /* disable modes not supported in hardware */ 1196 if (!(bmsr & MII_STATUS_100_BASEX_FD)) { 1197 afep->afe_adv_100fdx = 0; 1198 } 1199 if (!(bmsr & MII_STATUS_100_BASE_T4)) { 1200 afep->afe_adv_100T4 = 0; 1201 } 1202 if (!(bmsr & MII_STATUS_100_BASEX)) { 1203 afep->afe_adv_100hdx = 0; 1204 } 1205 if (!(bmsr & MII_STATUS_10_FD)) { 1206 afep->afe_adv_10fdx = 0; 1207 } 1208 if (!(bmsr & MII_STATUS_10)) { 1209 afep->afe_adv_10hdx = 0; 1210 } 1211 if (!(bmsr & MII_STATUS_CANAUTONEG)) { 1212 afep->afe_adv_aneg = 0; 1213 force = 1; 1214 } 1215 1216 cnt = 0; 1217 if (afep->afe_adv_100fdx) { 1218 anar |= MII_ABILITY_100BASE_TX_FD; 1219 cnt++; 1220 } 1221 if (afep->afe_adv_100T4) { 1222 anar |= MII_ABILITY_100BASE_T4; 1223 cnt++; 1224 } 1225 if (afep->afe_adv_100hdx) { 1226 anar |= MII_ABILITY_100BASE_TX; 1227 cnt++; 1228 } 1229 if (afep->afe_adv_10fdx) { 1230 anar |= MII_ABILITY_10BASE_T_FD; 1231 cnt++; 1232 } 1233 if (afep->afe_adv_10hdx) { 1234 anar |= MII_ABILITY_10BASE_T; 1235 cnt++; 1236 } 1237 1238 /* 1239 * Make certain at least one valid link mode is selected. 1240 */ 1241 if (!cnt) { 1242 afe_error(afep->afe_dip, "No valid link mode selected."); 1243 afe_error(afep->afe_dip, "Powering down PHY."); 1244 afe_stopphy(afep); 1245 afep->afe_linkup = LINK_STATE_DOWN; 1246 if (afep->afe_flags & AFE_RUNNING) 1247 afe_reportlink(afep); 1248 return; 1249 } 1250 1251 if (fiber) { 1252 bmcr = MII_CONTROL_100MB | MII_CONTROL_FDUPLEX; 1253 } else if ((afep->afe_adv_aneg) && (bmsr & MII_STATUS_CANAUTONEG)) { 1254 DBG(DPHY, "using autoneg mode"); 1255 bmcr = (MII_CONTROL_ANE | MII_CONTROL_RSAN); 1256 } else { 1257 DBG(DPHY, "using forced mode"); 1258 force = 1; 1259 if (afep->afe_adv_100fdx) { 1260 bmcr = (MII_CONTROL_100MB | MII_CONTROL_FDUPLEX); 1261 } else if (afep->afe_adv_100hdx) { 1262 bmcr = MII_CONTROL_100MB; 1263 } else if (afep->afe_adv_10fdx) { 1264 bmcr = MII_CONTROL_FDUPLEX; 1265 } else { 1266 /* 10HDX */ 1267 bmcr = 0; 1268 } 1269 } 1270 1271 afep->afe_forcephy = force; 1272 1273 DBG(DPHY, "programming anar to 0x%x", anar); 1274 afe_miiwrite(afep, phyaddr, MII_AN_ADVERT, anar); 1275 DBG(DPHY, "programming bmcr to 0x%x", bmcr); 1276 afe_miiwrite(afep, phyaddr, MII_CONTROL, bmcr); 1277 1278 if (nosqe) { 1279 uint16_t pilr; 1280 /* 1281 * work around for errata 983B_0416 -- duplex light flashes 1282 * in 10 HDX. we just disable SQE testing on the device. 1283 */ 1284 pilr = afe_miiread(afep, phyaddr, PHY_PILR); 1285 pilr |= PILR_NOSQE; 1286 afe_miiwrite(afep, phyaddr, PHY_PILR, pilr); 1287 } 1288 1289 /* 1290 * schedule a query of the link status 1291 */ 1292 PUTCSR(afep, CSR_TIMER, TIMER_LOOP | 1293 (AFE_LINKTIMER * 1000 / TIMER_USEC)); 1294 } 1295 1296 void 1297 afe_stopphy(afe_t *afep) 1298 { 1299 /* stop the phy timer */ 1300 PUTCSR(afep, CSR_TIMER, 0); 1301 1302 /* 1303 * phy in isolate & powerdown mode... 1304 */ 1305 afe_miiwrite(afep, afep->afe_phyaddr, MII_CONTROL, 1306 MII_CONTROL_PWRDN | MII_CONTROL_ISOLATE); 1307 1308 /* 1309 * mark the link state unknown 1310 */ 1311 if (!afep->afe_resetting) { 1312 afep->afe_linkup = LINK_STATE_UNKNOWN; 1313 afep->afe_ifspeed = 0; 1314 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1315 if (afep->afe_flags & AFE_RUNNING) 1316 afe_reportlink(afep); 1317 } 1318 } 1319 1320 void 1321 afe_reportlink(afe_t *afep) 1322 { 1323 int changed = 0; 1324 1325 if (afep->afe_ifspeed != afep->afe_lastifspeed) { 1326 afep->afe_lastifspeed = afep->afe_ifspeed; 1327 changed++; 1328 } 1329 if (afep->afe_duplex != afep->afe_lastduplex) { 1330 afep->afe_lastduplex = afep->afe_duplex; 1331 changed++; 1332 } 1333 if (changed) 1334 mac_link_update(afep->afe_mh, afep->afe_linkup); 1335 } 1336 1337 void 1338 afe_checklink(afe_t *afep) 1339 { 1340 if ((afep->afe_flags & AFE_RUNNING) == 0) 1341 return; 1342 1343 if ((afep->afe_txstall_time != 0) && 1344 (gethrtime() > afep->afe_txstall_time) && 1345 (afep->afe_txavail != AFE_TXRING)) { 1346 afep->afe_txstall_time = 0; 1347 afe_error(afep->afe_dip, "TX stall detected!"); 1348 afe_resetall(afep); 1349 return; 1350 } 1351 1352 switch (AFE_MODEL(afep)) { 1353 case MODEL_COMET: 1354 afe_checklinkcomet(afep); 1355 break; 1356 case MODEL_CENTAUR: 1357 afe_checklinkcentaur(afep); 1358 break; 1359 } 1360 } 1361 1362 void 1363 afe_checklinkcomet(afe_t *afep) 1364 { 1365 uint16_t xciis; 1366 int reinit = 0; 1367 1368 xciis = GETCSR16(afep, CSR_XCIIS); 1369 if (xciis & XCIIS_PDF) { 1370 afe_error(afep->afe_dip, "Parallel detection fault detected!"); 1371 } 1372 if (xciis & XCIIS_RF) { 1373 afe_error(afep->afe_dip, "Remote fault detected."); 1374 } 1375 if (xciis & XCIIS_LFAIL) { 1376 if (afep->afe_linkup == LINK_STATE_UP) { 1377 reinit++; 1378 } 1379 afep->afe_ifspeed = 0; 1380 afep->afe_linkup = LINK_STATE_DOWN; 1381 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1382 afe_reportlink(afep); 1383 if (reinit) { 1384 afe_startphy(afep); 1385 } 1386 return; 1387 } 1388 1389 afep->afe_linkup = LINK_STATE_UP; 1390 afep->afe_ifspeed = (xciis & XCIIS_SPEED) ? 100000000 : 10000000; 1391 if (xciis & XCIIS_DUPLEX) { 1392 afep->afe_duplex = LINK_DUPLEX_FULL; 1393 } else { 1394 afep->afe_duplex = LINK_DUPLEX_HALF; 1395 } 1396 1397 afe_reportlink(afep); 1398 } 1399 1400 void 1401 afe_checklinkcentaur(afe_t *afep) 1402 { 1403 unsigned opmode; 1404 int reinit = 0; 1405 1406 opmode = GETCSR(afep, CSR_OPM); 1407 if ((opmode & OPM_MODE) == OPM_MACONLY) { 1408 DBG(DPHY, "Centaur running in MAC-only mode"); 1409 afe_checklinkmii(afep); 1410 return; 1411 } 1412 DBG(DPHY, "Centaur running in single chip mode"); 1413 if ((opmode & OPM_LINK) == 0) { 1414 if (afep->afe_linkup == LINK_STATE_UP) { 1415 reinit++; 1416 } 1417 afep->afe_ifspeed = 0; 1418 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1419 afep->afe_linkup = LINK_STATE_DOWN; 1420 afe_reportlink(afep); 1421 if (reinit) { 1422 afe_startphy(afep); 1423 } 1424 return; 1425 } 1426 1427 afep->afe_linkup = LINK_STATE_UP; 1428 afep->afe_ifspeed = (opmode & OPM_SPEED) ? 100000000 : 10000000; 1429 if (opmode & OPM_DUPLEX) { 1430 afep->afe_duplex = LINK_DUPLEX_FULL; 1431 } else { 1432 afep->afe_duplex = LINK_DUPLEX_HALF; 1433 } 1434 afe_reportlink(afep); 1435 } 1436 1437 void 1438 afe_checklinkmii(afe_t *afep) 1439 { 1440 /* read MII state registers */ 1441 uint16_t bmsr; 1442 uint16_t bmcr; 1443 uint16_t anar; 1444 uint16_t anlpar; 1445 int reinit = 0; 1446 1447 /* read this twice, to clear latched link state */ 1448 bmsr = afe_miiread(afep, afep->afe_phyaddr, MII_STATUS); 1449 bmsr = afe_miiread(afep, afep->afe_phyaddr, MII_STATUS); 1450 bmcr = afe_miiread(afep, afep->afe_phyaddr, MII_CONTROL); 1451 anar = afe_miiread(afep, afep->afe_phyaddr, MII_AN_ADVERT); 1452 anlpar = afe_miiread(afep, afep->afe_phyaddr, MII_AN_LPABLE); 1453 1454 if (bmsr & MII_STATUS_REMFAULT) { 1455 afe_error(afep->afe_dip, "Remote fault detected."); 1456 } 1457 if (bmsr & MII_STATUS_JABBERING) { 1458 afe_error(afep->afe_dip, "Jabber condition detected."); 1459 } 1460 if ((bmsr & MII_STATUS_LINKUP) == 0) { 1461 /* no link */ 1462 if (afep->afe_linkup) { 1463 reinit = 1; 1464 } 1465 afep->afe_ifspeed = 0; 1466 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1467 afep->afe_linkup = LINK_STATE_DOWN; 1468 afe_reportlink(afep); 1469 if (reinit) { 1470 afe_startphy(afep); 1471 } 1472 return; 1473 } 1474 1475 DBG(DCHATTY, "link up!"); 1476 afep->afe_linkup = LINK_STATE_UP; 1477 1478 if (!(bmcr & MII_CONTROL_ANE)) { 1479 /* forced mode */ 1480 if (bmcr & MII_CONTROL_100MB) { 1481 afep->afe_ifspeed = 100000000; 1482 } else { 1483 afep->afe_ifspeed = 10000000; 1484 } 1485 if (bmcr & MII_CONTROL_FDUPLEX) { 1486 afep->afe_duplex = LINK_DUPLEX_FULL; 1487 } else { 1488 afep->afe_duplex = LINK_DUPLEX_HALF; 1489 } 1490 } else if ((!(bmsr & MII_STATUS_CANAUTONEG)) || 1491 (!(bmsr & MII_STATUS_ANDONE))) { 1492 afep->afe_ifspeed = 0; 1493 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1494 } else if (anar & anlpar & MII_ABILITY_100BASE_TX_FD) { 1495 afep->afe_ifspeed = 100000000; 1496 afep->afe_duplex = LINK_DUPLEX_FULL; 1497 } else if (anar & anlpar & MII_ABILITY_100BASE_T4) { 1498 afep->afe_ifspeed = 100000000; 1499 afep->afe_duplex = LINK_DUPLEX_HALF; 1500 } else if (anar & anlpar & MII_ABILITY_100BASE_TX) { 1501 afep->afe_ifspeed = 100000000; 1502 afep->afe_duplex = LINK_DUPLEX_HALF; 1503 } else if (anar & anlpar & MII_ABILITY_10BASE_T_FD) { 1504 afep->afe_ifspeed = 10000000; 1505 afep->afe_duplex = LINK_DUPLEX_FULL; 1506 } else if (anar & anlpar & MII_ABILITY_10BASE_T) { 1507 afep->afe_ifspeed = 10000000; 1508 afep->afe_duplex = LINK_DUPLEX_HALF; 1509 } else { 1510 afep->afe_ifspeed = 0; 1511 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1512 } 1513 1514 afe_reportlink(afep); 1515 } 1516 1517 void 1518 afe_miitristate(afe_t *afep) 1519 { 1520 unsigned val = SPR_SROM_WRITE | SPR_MII_CTRL; 1521 PUTCSR(afep, CSR_SPR, val); 1522 drv_usecwait(1); 1523 PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK); 1524 drv_usecwait(1); 1525 } 1526 1527 void 1528 afe_miiwritebit(afe_t *afep, int bit) 1529 { 1530 unsigned val = bit ? SPR_MII_DOUT : 0; 1531 PUTCSR(afep, CSR_SPR, val); 1532 drv_usecwait(1); 1533 PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK); 1534 drv_usecwait(1); 1535 } 1536 1537 int 1538 afe_miireadbit(afe_t *afep) 1539 { 1540 unsigned val = SPR_MII_CTRL | SPR_SROM_READ; 1541 int bit; 1542 PUTCSR(afep, CSR_SPR, val); 1543 drv_usecwait(1); 1544 bit = (GETCSR(afep, CSR_SPR) & SPR_MII_DIN) ? 1 : 0; 1545 PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK); 1546 drv_usecwait(1); 1547 return (bit); 1548 } 1549 1550 unsigned 1551 afe_miiread(afe_t *afep, int phy, int reg) 1552 { 1553 /* 1554 * ADMtek bugs ignore address decode bits -- they only 1555 * support PHY at 1. 1556 */ 1557 if (phy != 1) { 1558 return (0xffff); 1559 } 1560 switch (AFE_MODEL(afep)) { 1561 case MODEL_COMET: 1562 return (afe_miireadcomet(afep, phy, reg)); 1563 case MODEL_CENTAUR: 1564 return (afe_miireadgeneral(afep, phy, reg)); 1565 } 1566 return (0xffff); 1567 } 1568 1569 unsigned 1570 afe_miireadgeneral(afe_t *afep, int phy, int reg) 1571 { 1572 unsigned value = 0; 1573 int i; 1574 1575 /* send the 32 bit preamble */ 1576 for (i = 0; i < 32; i++) { 1577 afe_miiwritebit(afep, 1); 1578 } 1579 1580 /* send the start code - 01b */ 1581 afe_miiwritebit(afep, 0); 1582 afe_miiwritebit(afep, 1); 1583 1584 /* send the opcode for read, - 10b */ 1585 afe_miiwritebit(afep, 1); 1586 afe_miiwritebit(afep, 0); 1587 1588 /* next we send the 5 bit phy address */ 1589 for (i = 0x10; i > 0; i >>= 1) { 1590 afe_miiwritebit(afep, (phy & i) ? 1 : 0); 1591 } 1592 1593 /* the 5 bit register address goes next */ 1594 for (i = 0x10; i > 0; i >>= 1) { 1595 afe_miiwritebit(afep, (reg & i) ? 1 : 0); 1596 } 1597 1598 /* turnaround - tristate followed by logic 0 */ 1599 afe_miitristate(afep); 1600 afe_miiwritebit(afep, 0); 1601 1602 /* read the 16 bit register value */ 1603 for (i = 0x8000; i > 0; i >>= 1) { 1604 value <<= 1; 1605 value |= afe_miireadbit(afep); 1606 } 1607 afe_miitristate(afep); 1608 return (value); 1609 } 1610 1611 unsigned 1612 afe_miireadcomet(afe_t *afep, int phy, int reg) 1613 { 1614 if (phy != 1) { 1615 return (0xffff); 1616 } 1617 switch (reg) { 1618 case MII_CONTROL: 1619 reg = CSR_BMCR; 1620 break; 1621 case MII_STATUS: 1622 reg = CSR_BMSR; 1623 break; 1624 case MII_PHYIDH: 1625 reg = CSR_PHYIDR1; 1626 break; 1627 case MII_PHYIDL: 1628 reg = CSR_PHYIDR2; 1629 break; 1630 case MII_AN_ADVERT: 1631 reg = CSR_ANAR; 1632 break; 1633 case MII_AN_LPABLE: 1634 reg = CSR_ANLPAR; 1635 break; 1636 case MII_AN_EXPANSION: 1637 reg = CSR_ANER; 1638 break; 1639 default: 1640 return (0); 1641 } 1642 return (GETCSR16(afep, reg) & 0xFFFF); 1643 } 1644 1645 void 1646 afe_miiwrite(afe_t *afep, int phy, int reg, uint16_t val) 1647 { 1648 /* 1649 * ADMtek bugs ignore address decode bits -- they only 1650 * support PHY at 1. 1651 */ 1652 if (phy != 1) { 1653 return; 1654 } 1655 switch (AFE_MODEL(afep)) { 1656 case MODEL_COMET: 1657 afe_miiwritecomet(afep, phy, reg, val); 1658 break; 1659 case MODEL_CENTAUR: 1660 afe_miiwritegeneral(afep, phy, reg, val); 1661 break; 1662 } 1663 } 1664 1665 void 1666 afe_miiwritegeneral(afe_t *afep, int phy, int reg, uint16_t val) 1667 { 1668 int i; 1669 1670 /* send the 32 bit preamble */ 1671 for (i = 0; i < 32; i++) { 1672 afe_miiwritebit(afep, 1); 1673 } 1674 1675 /* send the start code - 01b */ 1676 afe_miiwritebit(afep, 0); 1677 afe_miiwritebit(afep, 1); 1678 1679 /* send the opcode for write, - 01b */ 1680 afe_miiwritebit(afep, 0); 1681 afe_miiwritebit(afep, 1); 1682 1683 /* next we send the 5 bit phy address */ 1684 for (i = 0x10; i > 0; i >>= 1) { 1685 afe_miiwritebit(afep, (phy & i) ? 1 : 0); 1686 } 1687 1688 /* the 5 bit register address goes next */ 1689 for (i = 0x10; i > 0; i >>= 1) { 1690 afe_miiwritebit(afep, (reg & i) ? 1 : 0); 1691 } 1692 1693 /* turnaround - tristate followed by logic 0 */ 1694 afe_miitristate(afep); 1695 afe_miiwritebit(afep, 0); 1696 1697 /* now write out our data (16 bits) */ 1698 for (i = 0x8000; i > 0; i >>= 1) { 1699 afe_miiwritebit(afep, (val & i) ? 1 : 0); 1700 } 1701 1702 /* idle mode */ 1703 afe_miitristate(afep); 1704 } 1705 1706 void 1707 afe_miiwritecomet(afe_t *afep, int phy, int reg, uint16_t val) 1708 { 1709 if (phy != 1) { 1710 return; 1711 } 1712 switch (reg) { 1713 case MII_CONTROL: 1714 reg = CSR_BMCR; 1715 break; 1716 case MII_STATUS: 1717 reg = CSR_BMSR; 1718 break; 1719 case MII_PHYIDH: 1720 reg = CSR_PHYIDR1; 1721 break; 1722 case MII_PHYIDL: 1723 reg = CSR_PHYIDR2; 1724 break; 1725 case MII_AN_ADVERT: 1726 reg = CSR_ANAR; 1727 break; 1728 case MII_AN_LPABLE: 1729 reg = CSR_ANLPAR; 1730 break; 1731 case MII_AN_EXPANSION: 1732 reg = CSR_ANER; 1733 break; 1734 default: 1735 return; 1736 } 1737 PUTCSR16(afep, reg, val); 1738 } 1739 1740 int 1741 afe_m_start(void *arg) 1742 { 1743 afe_t *afep = arg; 1744 1745 /* grab exclusive access to the card */ 1746 mutex_enter(&afep->afe_intrlock); 1747 mutex_enter(&afep->afe_xmtlock); 1748 1749 afe_startall(afep); 1750 afep->afe_flags |= AFE_RUNNING; 1751 1752 mutex_exit(&afep->afe_xmtlock); 1753 mutex_exit(&afep->afe_intrlock); 1754 return (0); 1755 } 1756 1757 void 1758 afe_m_stop(void *arg) 1759 { 1760 afe_t *afep = arg; 1761 1762 /* exclusive access to the hardware! */ 1763 mutex_enter(&afep->afe_intrlock); 1764 mutex_enter(&afep->afe_xmtlock); 1765 1766 afe_stopall(afep); 1767 afep->afe_flags &= ~AFE_RUNNING; 1768 1769 mutex_exit(&afep->afe_xmtlock); 1770 mutex_exit(&afep->afe_intrlock); 1771 } 1772 1773 void 1774 afe_startmac(afe_t *afep) 1775 { 1776 /* verify exclusive access to the card */ 1777 ASSERT(mutex_owned(&afep->afe_intrlock)); 1778 ASSERT(mutex_owned(&afep->afe_xmtlock)); 1779 1780 /* start the card */ 1781 SETBIT(afep, CSR_NAR, NAR_TX_ENABLE | NAR_RX_ENABLE); 1782 1783 if (afep->afe_txavail != AFE_TXRING) 1784 PUTCSR(afep, CSR_TDR, 0); 1785 1786 /* tell the mac that we are ready to go! */ 1787 if (afep->afe_flags & AFE_RUNNING) 1788 mac_tx_update(afep->afe_mh); 1789 } 1790 1791 void 1792 afe_stopmac(afe_t *afep) 1793 { 1794 int i; 1795 1796 /* exclusive access to the hardware! */ 1797 ASSERT(mutex_owned(&afep->afe_intrlock)); 1798 ASSERT(mutex_owned(&afep->afe_xmtlock)); 1799 1800 CLRBIT(afep, CSR_NAR, NAR_TX_ENABLE | NAR_RX_ENABLE); 1801 1802 /* 1803 * A 1518 byte frame at 10Mbps takes about 1.2 msec to drain. 1804 * We just add up to the nearest msec (2), which should be 1805 * plenty to complete. 1806 * 1807 * Note that some chips never seem to indicate the transition to 1808 * the stopped state properly. Experience shows that we can safely 1809 * proceed anyway, after waiting the requisite timeout. 1810 */ 1811 for (i = 2000; i != 0; i -= 10) { 1812 if ((GETCSR(afep, CSR_SR) & (SR_TX_STATE | SR_RX_STATE)) == 0) 1813 break; 1814 drv_usecwait(10); 1815 } 1816 1817 /* prevent an interrupt */ 1818 PUTCSR(afep, CSR_SR2, INT_RXSTOPPED | INT_TXSTOPPED); 1819 } 1820 1821 void 1822 afe_resetrings(afe_t *afep) 1823 { 1824 int i; 1825 1826 /* now we need to reset the pointers... */ 1827 PUTCSR(afep, CSR_RDB, 0); 1828 PUTCSR(afep, CSR_TDB, 0); 1829 1830 /* reset the descriptor ring pointers */ 1831 afep->afe_rxhead = 0; 1832 afep->afe_txreclaim = 0; 1833 afep->afe_txsend = 0; 1834 afep->afe_txavail = AFE_TXRING; 1835 1836 /* set up transmit descriptor ring */ 1837 for (i = 0; i < AFE_TXRING; i++) { 1838 afe_desc_t *tmdp = &afep->afe_txdescp[i]; 1839 unsigned control = 0; 1840 if (i == (AFE_TXRING - 1)) { 1841 control |= TXCTL_ENDRING; 1842 } 1843 PUTTXDESC(afep, tmdp->desc_status, 0); 1844 PUTTXDESC(afep, tmdp->desc_control, control); 1845 PUTTXDESC(afep, tmdp->desc_buffer1, 0); 1846 PUTTXDESC(afep, tmdp->desc_buffer2, 0); 1847 SYNCTXDESC(afep, i, DDI_DMA_SYNC_FORDEV); 1848 } 1849 PUTCSR(afep, CSR_TDB, afep->afe_txdesc_paddr); 1850 1851 /* make the receive buffers available */ 1852 for (i = 0; i < AFE_RXRING; i++) { 1853 afe_rxbuf_t *rxb = afep->afe_rxbufs[i]; 1854 afe_desc_t *rmdp = &afep->afe_rxdescp[i]; 1855 unsigned control; 1856 1857 control = AFE_BUFSZ & RXCTL_BUFLEN1; 1858 if (i == (AFE_RXRING - 1)) { 1859 control |= RXCTL_ENDRING; 1860 } 1861 PUTRXDESC(afep, rmdp->desc_buffer1, rxb->rxb_paddr); 1862 PUTRXDESC(afep, rmdp->desc_buffer2, 0); 1863 PUTRXDESC(afep, rmdp->desc_control, control); 1864 PUTRXDESC(afep, rmdp->desc_status, RXSTAT_OWN); 1865 SYNCRXDESC(afep, i, DDI_DMA_SYNC_FORDEV); 1866 } 1867 PUTCSR(afep, CSR_RDB, afep->afe_rxdesc_paddr); 1868 } 1869 1870 void 1871 afe_stopall(afe_t *afep) 1872 { 1873 afe_disableinterrupts(afep); 1874 1875 afe_stopmac(afep); 1876 1877 /* stop the phy */ 1878 afe_stopphy(afep); 1879 } 1880 1881 void 1882 afe_startall(afe_t *afep) 1883 { 1884 ASSERT(mutex_owned(&afep->afe_intrlock)); 1885 ASSERT(mutex_owned(&afep->afe_xmtlock)); 1886 1887 /* make sure interrupts are disabled to begin */ 1888 afe_disableinterrupts(afep); 1889 1890 /* initialize the chip */ 1891 (void) afe_initialize(afep); 1892 1893 /* now we can enable interrupts */ 1894 afe_enableinterrupts(afep); 1895 1896 /* start up the phy */ 1897 afe_startphy(afep); 1898 1899 /* start up the mac */ 1900 afe_startmac(afep); 1901 } 1902 1903 void 1904 afe_resetall(afe_t *afep) 1905 { 1906 afep->afe_resetting = B_TRUE; 1907 afe_stopall(afep); 1908 afep->afe_resetting = B_FALSE; 1909 afe_startall(afep); 1910 } 1911 1912 afe_txbuf_t * 1913 afe_alloctxbuf(afe_t *afep) 1914 { 1915 ddi_dma_cookie_t dmac; 1916 unsigned ncookies; 1917 afe_txbuf_t *txb; 1918 size_t len; 1919 1920 txb = kmem_zalloc(sizeof (*txb), KM_SLEEP); 1921 1922 if (ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_txattr, 1923 DDI_DMA_SLEEP, NULL, &txb->txb_dmah) != DDI_SUCCESS) { 1924 return (NULL); 1925 } 1926 1927 if (ddi_dma_mem_alloc(txb->txb_dmah, AFE_BUFSZ, &afe_bufattr, 1928 DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, &txb->txb_buf, &len, 1929 &txb->txb_acch) != DDI_SUCCESS) { 1930 return (NULL); 1931 } 1932 if (ddi_dma_addr_bind_handle(txb->txb_dmah, NULL, txb->txb_buf, 1933 len, DDI_DMA_WRITE | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, 1934 &dmac, &ncookies) != DDI_DMA_MAPPED) { 1935 return (NULL); 1936 } 1937 txb->txb_paddr = dmac.dmac_address; 1938 1939 return (txb); 1940 } 1941 1942 void 1943 afe_destroytxbuf(afe_txbuf_t *txb) 1944 { 1945 if (txb != NULL) { 1946 if (txb->txb_paddr) 1947 (void) ddi_dma_unbind_handle(txb->txb_dmah); 1948 if (txb->txb_acch) 1949 ddi_dma_mem_free(&txb->txb_acch); 1950 if (txb->txb_dmah) 1951 ddi_dma_free_handle(&txb->txb_dmah); 1952 kmem_free(txb, sizeof (*txb)); 1953 } 1954 } 1955 1956 afe_rxbuf_t * 1957 afe_allocrxbuf(afe_t *afep) 1958 { 1959 afe_rxbuf_t *rxb; 1960 size_t len; 1961 unsigned ccnt; 1962 ddi_dma_cookie_t dmac; 1963 1964 rxb = kmem_zalloc(sizeof (*rxb), KM_SLEEP); 1965 1966 if (ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_attr, 1967 DDI_DMA_SLEEP, NULL, &rxb->rxb_dmah) != DDI_SUCCESS) { 1968 kmem_free(rxb, sizeof (*rxb)); 1969 return (NULL); 1970 } 1971 if (ddi_dma_mem_alloc(rxb->rxb_dmah, AFE_BUFSZ, &afe_bufattr, 1972 DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, &rxb->rxb_buf, &len, 1973 &rxb->rxb_acch) != DDI_SUCCESS) { 1974 ddi_dma_free_handle(&rxb->rxb_dmah); 1975 kmem_free(rxb, sizeof (*rxb)); 1976 return (NULL); 1977 } 1978 if (ddi_dma_addr_bind_handle(rxb->rxb_dmah, NULL, rxb->rxb_buf, len, 1979 DDI_DMA_READ | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, &dmac, 1980 &ccnt) != DDI_DMA_MAPPED) { 1981 ddi_dma_mem_free(&rxb->rxb_acch); 1982 ddi_dma_free_handle(&rxb->rxb_dmah); 1983 kmem_free(rxb, sizeof (*rxb)); 1984 return (NULL); 1985 } 1986 rxb->rxb_paddr = dmac.dmac_address; 1987 1988 return (rxb); 1989 } 1990 1991 void 1992 afe_destroyrxbuf(afe_rxbuf_t *rxb) 1993 { 1994 if (rxb) { 1995 (void) ddi_dma_unbind_handle(rxb->rxb_dmah); 1996 ddi_dma_mem_free(&rxb->rxb_acch); 1997 ddi_dma_free_handle(&rxb->rxb_dmah); 1998 kmem_free(rxb, sizeof (*rxb)); 1999 } 2000 } 2001 2002 /* 2003 * Allocate receive resources. 2004 */ 2005 int 2006 afe_allocrxring(afe_t *afep) 2007 { 2008 int rval; 2009 int i; 2010 size_t size; 2011 size_t len; 2012 ddi_dma_cookie_t dmac; 2013 unsigned ncookies; 2014 caddr_t kaddr; 2015 2016 size = AFE_RXRING * sizeof (afe_desc_t); 2017 2018 rval = ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_attr, 2019 DDI_DMA_SLEEP, NULL, &afep->afe_rxdesc_dmah); 2020 if (rval != DDI_SUCCESS) { 2021 afe_error(afep->afe_dip, 2022 "unable to allocate DMA handle for rx descriptors"); 2023 return (DDI_FAILURE); 2024 } 2025 2026 rval = ddi_dma_mem_alloc(afep->afe_rxdesc_dmah, size, &afe_devattr, 2027 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &kaddr, &len, 2028 &afep->afe_rxdesc_acch); 2029 if (rval != DDI_SUCCESS) { 2030 afe_error(afep->afe_dip, 2031 "unable to allocate DMA memory for rx descriptors"); 2032 return (DDI_FAILURE); 2033 } 2034 2035 rval = ddi_dma_addr_bind_handle(afep->afe_rxdesc_dmah, NULL, kaddr, 2036 size, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2037 &dmac, &ncookies); 2038 if (rval != DDI_DMA_MAPPED) { 2039 afe_error(afep->afe_dip, 2040 "unable to bind DMA for rx descriptors"); 2041 return (DDI_FAILURE); 2042 } 2043 2044 /* because of afe_dma_attr */ 2045 ASSERT(ncookies == 1); 2046 2047 /* we take the 32-bit physical address out of the cookie */ 2048 afep->afe_rxdesc_paddr = dmac.dmac_address; 2049 afep->afe_rxdescp = (void *)kaddr; 2050 2051 /* allocate buffer pointers (not the buffers themselves, yet) */ 2052 afep->afe_rxbufs = kmem_zalloc(AFE_RXRING * sizeof (afe_rxbuf_t *), 2053 KM_SLEEP); 2054 2055 /* now allocate rx buffers */ 2056 for (i = 0; i < AFE_RXRING; i++) { 2057 afe_rxbuf_t *rxb = afe_allocrxbuf(afep); 2058 if (rxb == NULL) 2059 return (DDI_FAILURE); 2060 afep->afe_rxbufs[i] = rxb; 2061 } 2062 2063 return (DDI_SUCCESS); 2064 } 2065 2066 /* 2067 * Allocate transmit resources. 2068 */ 2069 int 2070 afe_alloctxring(afe_t *afep) 2071 { 2072 int rval; 2073 int i; 2074 size_t size; 2075 size_t len; 2076 ddi_dma_cookie_t dmac; 2077 unsigned ncookies; 2078 caddr_t kaddr; 2079 2080 size = AFE_TXRING * sizeof (afe_desc_t); 2081 2082 rval = ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_attr, 2083 DDI_DMA_SLEEP, NULL, &afep->afe_txdesc_dmah); 2084 if (rval != DDI_SUCCESS) { 2085 afe_error(afep->afe_dip, 2086 "unable to allocate DMA handle for tx descriptors"); 2087 return (DDI_FAILURE); 2088 } 2089 2090 rval = ddi_dma_mem_alloc(afep->afe_txdesc_dmah, size, &afe_devattr, 2091 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &kaddr, &len, 2092 &afep->afe_txdesc_acch); 2093 if (rval != DDI_SUCCESS) { 2094 afe_error(afep->afe_dip, 2095 "unable to allocate DMA memory for tx descriptors"); 2096 return (DDI_FAILURE); 2097 } 2098 2099 rval = ddi_dma_addr_bind_handle(afep->afe_txdesc_dmah, NULL, kaddr, 2100 size, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2101 &dmac, &ncookies); 2102 if (rval != DDI_DMA_MAPPED) { 2103 afe_error(afep->afe_dip, 2104 "unable to bind DMA for tx descriptors"); 2105 return (DDI_FAILURE); 2106 } 2107 2108 /* because of afe_dma_attr */ 2109 ASSERT(ncookies == 1); 2110 2111 /* we take the 32-bit physical address out of the cookie */ 2112 afep->afe_txdesc_paddr = dmac.dmac_address; 2113 afep->afe_txdescp = (void *)kaddr; 2114 2115 /* allocate buffer pointers (not the buffers themselves, yet) */ 2116 afep->afe_txbufs = kmem_zalloc(AFE_TXRING * sizeof (afe_txbuf_t *), 2117 KM_SLEEP); 2118 2119 /* now allocate tx buffers */ 2120 for (i = 0; i < AFE_TXRING; i++) { 2121 afe_txbuf_t *txb = afe_alloctxbuf(afep); 2122 if (txb == NULL) 2123 return (DDI_FAILURE); 2124 afep->afe_txbufs[i] = txb; 2125 } 2126 2127 return (DDI_SUCCESS); 2128 } 2129 2130 void 2131 afe_freerxring(afe_t *afep) 2132 { 2133 int i; 2134 2135 for (i = 0; i < AFE_RXRING; i++) { 2136 afe_destroyrxbuf(afep->afe_rxbufs[i]); 2137 } 2138 2139 if (afep->afe_rxbufs) { 2140 kmem_free(afep->afe_rxbufs, 2141 AFE_RXRING * sizeof (afe_rxbuf_t *)); 2142 } 2143 2144 if (afep->afe_rxdesc_paddr) 2145 (void) ddi_dma_unbind_handle(afep->afe_rxdesc_dmah); 2146 if (afep->afe_rxdesc_acch) 2147 ddi_dma_mem_free(&afep->afe_rxdesc_acch); 2148 if (afep->afe_rxdesc_dmah) 2149 ddi_dma_free_handle(&afep->afe_rxdesc_dmah); 2150 } 2151 2152 void 2153 afe_freetxring(afe_t *afep) 2154 { 2155 int i; 2156 2157 for (i = 0; i < AFE_TXRING; i++) { 2158 afe_destroytxbuf(afep->afe_txbufs[i]); 2159 } 2160 2161 if (afep->afe_txbufs) { 2162 kmem_free(afep->afe_txbufs, 2163 AFE_TXRING * sizeof (afe_txbuf_t *)); 2164 } 2165 if (afep->afe_txdesc_paddr) 2166 (void) ddi_dma_unbind_handle(afep->afe_txdesc_dmah); 2167 if (afep->afe_txdesc_acch) 2168 ddi_dma_mem_free(&afep->afe_txdesc_acch); 2169 if (afep->afe_txdesc_dmah) 2170 ddi_dma_free_handle(&afep->afe_txdesc_dmah); 2171 } 2172 2173 /* 2174 * Interrupt service routine. 2175 */ 2176 unsigned 2177 afe_intr(caddr_t arg) 2178 { 2179 afe_t *afep = (void *)arg; 2180 uint32_t status; 2181 mblk_t *mp = NULL; 2182 2183 mutex_enter(&afep->afe_intrlock); 2184 2185 if (afep->afe_flags & AFE_SUSPENDED) { 2186 /* we cannot receive interrupts! */ 2187 mutex_exit(&afep->afe_intrlock); 2188 return (DDI_INTR_UNCLAIMED); 2189 } 2190 2191 /* check interrupt status bits, did we interrupt? */ 2192 status = GETCSR(afep, CSR_SR2) & INT_ALL; 2193 2194 if (status == 0) { 2195 KIOIP->intrs[KSTAT_INTR_SPURIOUS]++; 2196 mutex_exit(&afep->afe_intrlock); 2197 return (DDI_INTR_UNCLAIMED); 2198 } 2199 /* ack the interrupt */ 2200 PUTCSR(afep, CSR_SR2, status); 2201 KIOIP->intrs[KSTAT_INTR_HARD]++; 2202 2203 if (!(afep->afe_flags & AFE_RUNNING)) { 2204 /* not running, don't touch anything */ 2205 mutex_exit(&afep->afe_intrlock); 2206 return (DDI_INTR_CLAIMED); 2207 } 2208 2209 if (status & (INT_RXOK|INT_RXNOBUF)) { 2210 /* receive packets */ 2211 mp = afe_receive(afep); 2212 if (status & INT_RXNOBUF) 2213 PUTCSR(afep, CSR_RDR, 0); /* wake up chip */ 2214 } 2215 2216 if (status & INT_TXOK) { 2217 /* transmit completed */ 2218 mutex_enter(&afep->afe_xmtlock); 2219 afe_reclaim(afep); 2220 mutex_exit(&afep->afe_xmtlock); 2221 } 2222 2223 if (status & (INT_LINKCHG|INT_TIMER)) { 2224 mutex_enter(&afep->afe_xmtlock); 2225 afe_checklink(afep); 2226 mutex_exit(&afep->afe_xmtlock); 2227 } 2228 2229 if (status & (INT_RXSTOPPED|INT_TXSTOPPED| 2230 INT_RXJABBER|INT_TXJABBER|INT_TXUNDERFLOW)) { 2231 2232 if (status & (INT_RXJABBER | INT_TXJABBER)) { 2233 afep->afe_jabber++; 2234 } 2235 DBG(DWARN, "resetting mac, status %x", status); 2236 mutex_enter(&afep->afe_xmtlock); 2237 afe_resetall(afep); 2238 mutex_exit(&afep->afe_xmtlock); 2239 } 2240 2241 if (status & INT_BUSERR) { 2242 switch (GETCSR(afep, CSR_SR) & SR_BERR_TYPE) { 2243 case SR_BERR_PARITY: 2244 afe_error(afep->afe_dip, "PCI parity error"); 2245 break; 2246 case SR_BERR_TARGET_ABORT: 2247 afe_error(afep->afe_dip, "PCI target abort"); 2248 break; 2249 case SR_BERR_MASTER_ABORT: 2250 afe_error(afep->afe_dip, "PCI master abort"); 2251 break; 2252 default: 2253 afe_error(afep->afe_dip, "Unknown PCI error"); 2254 break; 2255 } 2256 2257 /* reset the chip in an attempt to fix things */ 2258 mutex_enter(&afep->afe_xmtlock); 2259 afe_resetall(afep); 2260 mutex_exit(&afep->afe_xmtlock); 2261 } 2262 2263 mutex_exit(&afep->afe_intrlock); 2264 2265 /* 2266 * Send up packets. We do this outside of the intrlock. 2267 */ 2268 if (mp) { 2269 mac_rx(afep->afe_mh, NULL, mp); 2270 } 2271 2272 return (DDI_INTR_CLAIMED); 2273 } 2274 2275 void 2276 afe_enableinterrupts(afe_t *afep) 2277 { 2278 unsigned mask = INT_WANTED; 2279 2280 if (afep->afe_wantw) 2281 mask |= INT_TXOK; 2282 2283 PUTCSR(afep, CSR_IER2, mask); 2284 2285 if (AFE_MODEL(afep) == MODEL_COMET) { 2286 /* 2287 * On the Comet, this is the internal transceiver 2288 * interrupt. We program the Comet's built-in PHY to 2289 * enable certain interrupts. 2290 */ 2291 PUTCSR16(afep, CSR_XIE, XIE_LDE | XIE_ANCE); 2292 } 2293 } 2294 2295 void 2296 afe_disableinterrupts(afe_t *afep) 2297 { 2298 /* disable further interrupts */ 2299 PUTCSR(afep, CSR_IER2, INT_NONE); 2300 2301 /* clear any pending interrupts */ 2302 PUTCSR(afep, CSR_SR2, INT_ALL); 2303 } 2304 2305 boolean_t 2306 afe_send(afe_t *afep, mblk_t *mp) 2307 { 2308 size_t len; 2309 afe_txbuf_t *txb; 2310 afe_desc_t *tmd; 2311 uint32_t control; 2312 int txsend; 2313 2314 ASSERT(mutex_owned(&afep->afe_xmtlock)); 2315 ASSERT(mp != NULL); 2316 2317 len = msgsize(mp); 2318 if (len > ETHERVLANMTU) { 2319 DBG(DXMIT, "frame too long: %d", len); 2320 afep->afe_macxmt_errors++; 2321 freemsg(mp); 2322 return (B_TRUE); 2323 } 2324 2325 if (afep->afe_txavail < AFE_TXRECLAIM) 2326 afe_reclaim(afep); 2327 2328 if (afep->afe_txavail == 0) { 2329 /* no more tmds */ 2330 afep->afe_wantw = B_TRUE; 2331 /* enable TX interrupt */ 2332 afe_enableinterrupts(afep); 2333 return (B_FALSE); 2334 } 2335 2336 txsend = afep->afe_txsend; 2337 2338 /* 2339 * For simplicity, we just do a copy into a preallocated 2340 * DMA buffer. 2341 */ 2342 2343 txb = afep->afe_txbufs[txsend]; 2344 mcopymsg(mp, txb->txb_buf); /* frees mp! */ 2345 2346 /* 2347 * Statistics. 2348 */ 2349 afep->afe_opackets++; 2350 afep->afe_obytes += len; 2351 if (txb->txb_buf[0] & 0x1) { 2352 if (bcmp(txb->txb_buf, afe_broadcast, ETHERADDRL) != 0) 2353 afep->afe_multixmt++; 2354 else 2355 afep->afe_brdcstxmt++; 2356 } 2357 2358 /* note len is already known to be a small unsigned */ 2359 control = len | TXCTL_FIRST | TXCTL_LAST | TXCTL_INTCMPLTE; 2360 2361 if (txsend == (AFE_TXRING - 1)) 2362 control |= TXCTL_ENDRING; 2363 2364 tmd = &afep->afe_txdescp[txsend]; 2365 2366 SYNCTXBUF(txb, len, DDI_DMA_SYNC_FORDEV); 2367 PUTTXDESC(afep, tmd->desc_control, control); 2368 PUTTXDESC(afep, tmd->desc_buffer1, txb->txb_paddr); 2369 PUTTXDESC(afep, tmd->desc_buffer2, 0); 2370 PUTTXDESC(afep, tmd->desc_status, TXSTAT_OWN); 2371 /* sync the descriptor out to the device */ 2372 SYNCTXDESC(afep, txsend, DDI_DMA_SYNC_FORDEV); 2373 2374 /* 2375 * Note the new values of txavail and txsend. 2376 */ 2377 afep->afe_txavail--; 2378 afep->afe_txsend = (txsend + 1) % AFE_TXRING; 2379 2380 /* 2381 * It should never, ever take more than 5 seconds to drain 2382 * the ring. If it happens, then we are stuck! 2383 */ 2384 afep->afe_txstall_time = gethrtime() + (5 * 1000000000ULL); 2385 2386 /* 2387 * wake up the chip ... inside the lock to protect against DR suspend, 2388 * etc. 2389 */ 2390 PUTCSR(afep, CSR_TDR, 0); 2391 2392 return (B_TRUE); 2393 } 2394 2395 /* 2396 * Reclaim buffers that have completed transmission. 2397 */ 2398 void 2399 afe_reclaim(afe_t *afep) 2400 { 2401 afe_desc_t *tmdp; 2402 2403 while (afep->afe_txavail != AFE_TXRING) { 2404 uint32_t status; 2405 uint32_t control; 2406 int index = afep->afe_txreclaim; 2407 2408 tmdp = &afep->afe_txdescp[index]; 2409 2410 /* sync it before we read it */ 2411 SYNCTXDESC(afep, index, DDI_DMA_SYNC_FORKERNEL); 2412 2413 control = GETTXDESC(afep, tmdp->desc_control); 2414 status = GETTXDESC(afep, tmdp->desc_status); 2415 2416 if (status & TXSTAT_OWN) { 2417 /* chip is still working on it, we're done */ 2418 break; 2419 } 2420 2421 afep->afe_txavail++; 2422 afep->afe_txreclaim = (index + 1) % AFE_TXRING; 2423 2424 /* in the most common successful case, all bits are clear */ 2425 if (status == 0) 2426 continue; 2427 2428 if ((control & TXCTL_LAST) == 0) 2429 continue; 2430 2431 if (status & TXSTAT_TXERR) { 2432 afep->afe_errxmt++; 2433 2434 if (status & TXSTAT_JABBER) { 2435 /* transmit jabber timeout */ 2436 afep->afe_macxmt_errors++; 2437 } 2438 if (status & 2439 (TXSTAT_CARRLOST | TXSTAT_NOCARR)) { 2440 afep->afe_carrier_errors++; 2441 } 2442 if (status & TXSTAT_UFLOW) { 2443 afep->afe_underflow++; 2444 } 2445 if (status & TXSTAT_LATECOL) { 2446 afep->afe_tx_late_collisions++; 2447 } 2448 if (status & TXSTAT_EXCOLL) { 2449 afep->afe_ex_collisions++; 2450 afep->afe_collisions += 16; 2451 } 2452 } 2453 2454 if (status & TXSTAT_DEFER) { 2455 afep->afe_defer_xmts++; 2456 } 2457 2458 /* collision counting */ 2459 if (TXCOLLCNT(status) == 1) { 2460 afep->afe_collisions++; 2461 afep->afe_first_collisions++; 2462 } else if (TXCOLLCNT(status)) { 2463 afep->afe_collisions += TXCOLLCNT(status); 2464 afep->afe_multi_collisions += TXCOLLCNT(status); 2465 } 2466 } 2467 2468 if (afep->afe_txavail >= AFE_TXRESCHED) { 2469 if (afep->afe_wantw) { 2470 /* 2471 * we were able to reclaim some packets, so 2472 * disable tx interrupts 2473 */ 2474 afep->afe_wantw = B_FALSE; 2475 afe_enableinterrupts(afep); 2476 mac_tx_update(afep->afe_mh); 2477 } 2478 } 2479 } 2480 2481 mblk_t * 2482 afe_receive(afe_t *afep) 2483 { 2484 unsigned len; 2485 afe_rxbuf_t *rxb; 2486 afe_desc_t *rmd; 2487 uint32_t status; 2488 mblk_t *mpchain, **mpp, *mp; 2489 int head, cnt; 2490 2491 mpchain = NULL; 2492 mpp = &mpchain; 2493 head = afep->afe_rxhead; 2494 2495 /* limit the number of packets we process to a half ring size */ 2496 for (cnt = 0; cnt < AFE_RXRING / 2; cnt++) { 2497 2498 DBG(DRECV, "receive at index %d", head); 2499 2500 rmd = &afep->afe_rxdescp[head]; 2501 rxb = afep->afe_rxbufs[head]; 2502 2503 SYNCRXDESC(afep, head, DDI_DMA_SYNC_FORKERNEL); 2504 status = GETRXDESC(afep, rmd->desc_status); 2505 if (status & RXSTAT_OWN) { 2506 /* chip is still chewing on it */ 2507 break; 2508 } 2509 2510 /* discard the ethernet frame checksum */ 2511 len = RXLENGTH(status) - ETHERFCSL; 2512 2513 DBG(DRECV, "recv length %d, status %x", len, status); 2514 2515 if ((status & (RXSTAT_ERRS | RXSTAT_FIRST | RXSTAT_LAST)) != 2516 (RXSTAT_FIRST | RXSTAT_LAST)) { 2517 2518 afep->afe_errrcv++; 2519 2520 /* 2521 * Abnormal status bits detected, analyze further. 2522 */ 2523 if ((status & (RXSTAT_LAST|RXSTAT_FIRST)) != 2524 (RXSTAT_LAST|RXSTAT_FIRST)) { 2525 DBG(DRECV, "rx packet overspill"); 2526 if (status & RXSTAT_FIRST) { 2527 afep->afe_toolong_errors++; 2528 } 2529 } else if (status & RXSTAT_DESCERR) { 2530 afep->afe_macrcv_errors++; 2531 2532 } else if (status & RXSTAT_RUNT) { 2533 afep->afe_runt++; 2534 2535 } else if (status & RXSTAT_COLLSEEN) { 2536 /* this should really be rx_late_collisions */ 2537 afep->afe_macrcv_errors++; 2538 2539 } else if (status & RXSTAT_DRIBBLE) { 2540 afep->afe_align_errors++; 2541 2542 } else if (status & RXSTAT_CRCERR) { 2543 afep->afe_fcs_errors++; 2544 2545 } else if (status & RXSTAT_OFLOW) { 2546 afep->afe_overflow++; 2547 } 2548 } 2549 2550 else if (len > ETHERVLANMTU) { 2551 afep->afe_errrcv++; 2552 afep->afe_toolong_errors++; 2553 } 2554 2555 /* 2556 * At this point, the chip thinks the packet is OK. 2557 */ 2558 else { 2559 mp = allocb(len + AFE_HEADROOM, 0); 2560 if (mp == NULL) { 2561 afep->afe_errrcv++; 2562 afep->afe_norcvbuf++; 2563 goto skip; 2564 } 2565 2566 /* sync the buffer before we look at it */ 2567 SYNCRXBUF(rxb, len, DDI_DMA_SYNC_FORKERNEL); 2568 mp->b_rptr += AFE_HEADROOM; 2569 mp->b_wptr = mp->b_rptr + len; 2570 bcopy((char *)rxb->rxb_buf, mp->b_rptr, len); 2571 2572 afep->afe_ipackets++; 2573 afep->afe_rbytes += len; 2574 if (status & RXSTAT_GROUP) { 2575 if (bcmp(mp->b_rptr, afe_broadcast, 2576 ETHERADDRL) == 0) 2577 afep->afe_brdcstrcv++; 2578 else 2579 afep->afe_multircv++; 2580 } 2581 *mpp = mp; 2582 mpp = &mp->b_next; 2583 } 2584 2585 skip: 2586 /* return ring entry to the hardware */ 2587 PUTRXDESC(afep, rmd->desc_status, RXSTAT_OWN); 2588 SYNCRXDESC(afep, head, DDI_DMA_SYNC_FORDEV); 2589 2590 /* advance to next RMD */ 2591 head = (head + 1) % AFE_RXRING; 2592 } 2593 2594 afep->afe_rxhead = head; 2595 2596 return (mpchain); 2597 } 2598 2599 int 2600 afe_getmiibit(afe_t *afep, uint16_t reg, uint16_t bit) 2601 { 2602 unsigned val; 2603 2604 mutex_enter(&afep->afe_xmtlock); 2605 if (afep->afe_flags & AFE_SUSPENDED) { 2606 mutex_exit(&afep->afe_xmtlock); 2607 /* device is suspended */ 2608 return (0); 2609 } 2610 val = afe_miiread(afep, afep->afe_phyaddr, reg); 2611 mutex_exit(&afep->afe_xmtlock); 2612 2613 return (val & bit ? 1 : 0); 2614 } 2615 #define GETMIIBIT(reg, bit) afe_getmiibit(afep, reg, bit) 2616 2617 int 2618 afe_m_stat(void *arg, uint_t stat, uint64_t *val) 2619 { 2620 afe_t *afep = arg; 2621 2622 mutex_enter(&afep->afe_xmtlock); 2623 if ((afep->afe_flags & (AFE_RUNNING|AFE_SUSPENDED)) == AFE_RUNNING) 2624 afe_reclaim(afep); 2625 mutex_exit(&afep->afe_xmtlock); 2626 2627 switch (stat) { 2628 case MAC_STAT_IFSPEED: 2629 *val = afep->afe_ifspeed; 2630 break; 2631 2632 case MAC_STAT_MULTIRCV: 2633 *val = afep->afe_multircv; 2634 break; 2635 2636 case MAC_STAT_BRDCSTRCV: 2637 *val = afep->afe_brdcstrcv; 2638 break; 2639 2640 case MAC_STAT_MULTIXMT: 2641 *val = afep->afe_multixmt; 2642 break; 2643 2644 case MAC_STAT_BRDCSTXMT: 2645 *val = afep->afe_brdcstxmt; 2646 break; 2647 2648 case MAC_STAT_IPACKETS: 2649 *val = afep->afe_ipackets; 2650 break; 2651 2652 case MAC_STAT_RBYTES: 2653 *val = afep->afe_rbytes; 2654 break; 2655 2656 case MAC_STAT_OPACKETS: 2657 *val = afep->afe_opackets; 2658 break; 2659 2660 case MAC_STAT_OBYTES: 2661 *val = afep->afe_obytes; 2662 break; 2663 2664 case MAC_STAT_NORCVBUF: 2665 *val = afep->afe_norcvbuf; 2666 break; 2667 2668 case MAC_STAT_NOXMTBUF: 2669 *val = 0; 2670 break; 2671 2672 case MAC_STAT_COLLISIONS: 2673 *val = afep->afe_collisions; 2674 break; 2675 2676 case MAC_STAT_IERRORS: 2677 *val = afep->afe_errrcv; 2678 break; 2679 2680 case MAC_STAT_OERRORS: 2681 *val = afep->afe_errxmt; 2682 break; 2683 2684 case ETHER_STAT_LINK_DUPLEX: 2685 *val = afep->afe_duplex; 2686 break; 2687 2688 case ETHER_STAT_ALIGN_ERRORS: 2689 *val = afep->afe_align_errors; 2690 break; 2691 2692 case ETHER_STAT_FCS_ERRORS: 2693 *val = afep->afe_fcs_errors; 2694 break; 2695 2696 case ETHER_STAT_SQE_ERRORS: 2697 *val = afep->afe_sqe_errors; 2698 break; 2699 2700 case ETHER_STAT_DEFER_XMTS: 2701 *val = afep->afe_defer_xmts; 2702 break; 2703 2704 case ETHER_STAT_FIRST_COLLISIONS: 2705 *val = afep->afe_first_collisions; 2706 break; 2707 2708 case ETHER_STAT_MULTI_COLLISIONS: 2709 *val = afep->afe_multi_collisions; 2710 break; 2711 2712 case ETHER_STAT_TX_LATE_COLLISIONS: 2713 *val = afep->afe_tx_late_collisions; 2714 break; 2715 2716 case ETHER_STAT_EX_COLLISIONS: 2717 *val = afep->afe_ex_collisions; 2718 break; 2719 2720 case ETHER_STAT_MACXMT_ERRORS: 2721 *val = afep->afe_macxmt_errors; 2722 break; 2723 2724 case ETHER_STAT_CARRIER_ERRORS: 2725 *val = afep->afe_carrier_errors; 2726 break; 2727 2728 case ETHER_STAT_TOOLONG_ERRORS: 2729 *val = afep->afe_toolong_errors; 2730 break; 2731 2732 case ETHER_STAT_MACRCV_ERRORS: 2733 *val = afep->afe_macrcv_errors; 2734 break; 2735 2736 case MAC_STAT_OVERFLOWS: 2737 *val = afep->afe_overflow; 2738 break; 2739 2740 case MAC_STAT_UNDERFLOWS: 2741 *val = afep->afe_underflow; 2742 break; 2743 2744 case ETHER_STAT_TOOSHORT_ERRORS: 2745 *val = afep->afe_runt; 2746 break; 2747 2748 case ETHER_STAT_JABBER_ERRORS: 2749 *val = afep->afe_jabber; 2750 break; 2751 2752 case ETHER_STAT_CAP_100T4: 2753 *val = GETMIIBIT(MII_STATUS, MII_STATUS_100_BASE_T4); 2754 break; 2755 2756 case ETHER_STAT_CAP_100FDX: 2757 *val = GETMIIBIT(MII_STATUS, MII_STATUS_100_BASEX_FD); 2758 break; 2759 2760 case ETHER_STAT_CAP_100HDX: 2761 *val = GETMIIBIT(MII_STATUS, MII_STATUS_100_BASEX); 2762 break; 2763 2764 case ETHER_STAT_CAP_10FDX: 2765 *val = GETMIIBIT(MII_STATUS, MII_STATUS_10_FD); 2766 break; 2767 2768 case ETHER_STAT_CAP_10HDX: 2769 *val = GETMIIBIT(MII_STATUS, MII_STATUS_10); 2770 break; 2771 2772 case ETHER_STAT_CAP_AUTONEG: 2773 *val = GETMIIBIT(MII_STATUS, MII_STATUS_CANAUTONEG); 2774 break; 2775 2776 case ETHER_STAT_LINK_AUTONEG: 2777 *val = ((afep->afe_adv_aneg != 0) && 2778 (GETMIIBIT(MII_AN_LPABLE, MII_AN_EXP_LPCANAN) != 0)); 2779 break; 2780 2781 case ETHER_STAT_ADV_CAP_100T4: 2782 *val = afep->afe_adv_100T4; 2783 break; 2784 2785 case ETHER_STAT_ADV_CAP_100FDX: 2786 *val = afep->afe_adv_100fdx; 2787 break; 2788 2789 case ETHER_STAT_ADV_CAP_100HDX: 2790 *val = afep->afe_adv_100hdx; 2791 break; 2792 2793 case ETHER_STAT_ADV_CAP_10FDX: 2794 *val = afep->afe_adv_10fdx; 2795 break; 2796 2797 case ETHER_STAT_ADV_CAP_10HDX: 2798 *val = afep->afe_adv_10hdx; 2799 break; 2800 2801 case ETHER_STAT_ADV_CAP_AUTONEG: 2802 *val = afep->afe_adv_aneg; 2803 break; 2804 2805 case ETHER_STAT_LP_CAP_100T4: 2806 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_100BASE_T4); 2807 break; 2808 2809 case ETHER_STAT_LP_CAP_100FDX: 2810 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_100BASE_TX_FD); 2811 break; 2812 2813 case ETHER_STAT_LP_CAP_100HDX: 2814 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_100BASE_TX); 2815 break; 2816 2817 case ETHER_STAT_LP_CAP_10FDX: 2818 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_10BASE_T_FD); 2819 break; 2820 2821 case ETHER_STAT_LP_CAP_10HDX: 2822 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_10BASE_T); 2823 break; 2824 2825 case ETHER_STAT_LP_CAP_AUTONEG: 2826 *val = GETMIIBIT(MII_AN_EXPANSION, MII_AN_EXP_LPCANAN); 2827 break; 2828 2829 case ETHER_STAT_XCVR_ADDR: 2830 *val = afep->afe_phyaddr; 2831 break; 2832 2833 case ETHER_STAT_XCVR_ID: 2834 *val = afep->afe_phyid; 2835 break; 2836 2837 default: 2838 return (ENOTSUP); 2839 } 2840 return (0); 2841 } 2842 2843 /* 2844 * NDD support. 2845 */ 2846 afe_nd_t * 2847 afe_ndfind(afe_t *afep, char *name) 2848 { 2849 afe_nd_t *ndp; 2850 2851 for (ndp = afep->afe_ndp; ndp != NULL; ndp = ndp->nd_next) { 2852 if (strcmp(name, ndp->nd_name) == 0) { 2853 break; 2854 } 2855 } 2856 return (ndp); 2857 } 2858 2859 void 2860 afe_ndadd(afe_t *afep, char *name, afe_nd_pf_t get, afe_nd_pf_t set, 2861 intptr_t arg1, intptr_t arg2) 2862 { 2863 afe_nd_t *newndp; 2864 afe_nd_t **ndpp; 2865 2866 newndp = (afe_nd_t *)kmem_alloc(sizeof (afe_nd_t), KM_SLEEP); 2867 newndp->nd_next = NULL; 2868 newndp->nd_name = name; 2869 newndp->nd_get = get; 2870 newndp->nd_set = set; 2871 newndp->nd_arg1 = arg1; 2872 newndp->nd_arg2 = arg2; 2873 2874 /* seek to the end of the list */ 2875 for (ndpp = &afep->afe_ndp; *ndpp; ndpp = &(*ndpp)->nd_next) { 2876 } 2877 2878 *ndpp = newndp; 2879 } 2880 2881 void 2882 afe_ndempty(mblk_t *mp) 2883 { 2884 while (mp != NULL) { 2885 mp->b_rptr = mp->b_datap->db_base; 2886 mp->b_wptr = mp->b_rptr; 2887 mp = mp->b_cont; 2888 } 2889 } 2890 2891 void 2892 afe_ndget(afe_t *afep, queue_t *wq, mblk_t *mp) 2893 { 2894 mblk_t *nmp = mp->b_cont; 2895 afe_nd_t *ndp; 2896 int rv; 2897 char name[128]; 2898 2899 /* assumption, name will fit in first mblk of chain */ 2900 if ((nmp == NULL) || (nmp->b_wptr <= nmp->b_rptr)) { 2901 miocnak(wq, mp, 0, EINVAL); 2902 return; 2903 } 2904 2905 if (afe_ndparselen(nmp) >= sizeof (name)) { 2906 miocnak(wq, mp, 0, EINVAL); 2907 return; 2908 } 2909 afe_ndparsestring(nmp, name, sizeof (name)); 2910 2911 /* locate variable */ 2912 if ((ndp = afe_ndfind(afep, name)) == NULL) { 2913 miocnak(wq, mp, 0, EINVAL); 2914 return; 2915 } 2916 2917 /* locate get callback */ 2918 if (ndp->nd_get == NULL) { 2919 miocnak(wq, mp, 0, EACCES); 2920 return; 2921 } 2922 2923 /* clear the result buffer */ 2924 afe_ndempty(nmp); 2925 2926 rv = (*ndp->nd_get)(afep, nmp, ndp); 2927 if (rv == 0) { 2928 /* add final null bytes */ 2929 rv = afe_ndaddbytes(nmp, "\0", 1); 2930 } 2931 2932 if (rv == 0) { 2933 miocack(wq, mp, msgsize(nmp), 0); 2934 } else { 2935 miocnak(wq, mp, 0, rv); 2936 } 2937 } 2938 2939 void 2940 afe_ndset(afe_t *afep, queue_t *wq, mblk_t *mp) 2941 { 2942 struct iocblk *iocp = (void *)mp->b_rptr; 2943 mblk_t *nmp = mp->b_cont; 2944 afe_nd_t *ndp; 2945 int rv; 2946 char name[128]; 2947 2948 /* enforce policy */ 2949 if ((rv = priv_getbyname(PRIV_SYS_NET_CONFIG, 0)) < 0) { 2950 /* priv_getbyname returns a negative errno */ 2951 miocnak(wq, mp, 0, -rv); 2952 return; 2953 } 2954 if ((rv = priv_policy(iocp->ioc_cr, rv, B_FALSE, EPERM, NULL)) != 0) { 2955 miocnak(wq, mp, 0, rv); 2956 return; 2957 } 2958 2959 /* assumption, name will fit in first mblk of chain */ 2960 if ((nmp == NULL) || (nmp->b_wptr <= nmp->b_rptr)) { 2961 miocnak(wq, mp, 0, EINVAL); 2962 return; 2963 } 2964 2965 if (afe_ndparselen(nmp) >= sizeof (name)) { 2966 miocnak(wq, mp, 0, EINVAL); 2967 return; 2968 } 2969 afe_ndparsestring(nmp, name, sizeof (name)); 2970 2971 /* locate variable */ 2972 if ((ndp = afe_ndfind(afep, name)) == NULL) { 2973 miocnak(wq, mp, 0, EINVAL); 2974 return; 2975 } 2976 2977 /* locate set callback */ 2978 if (ndp->nd_set == NULL) { 2979 miocnak(wq, mp, 0, EACCES); 2980 return; 2981 } 2982 2983 rv = (*ndp->nd_set)(afep, nmp, ndp); 2984 2985 if (rv == 0) { 2986 miocack(wq, mp, 0, 0); 2987 } else { 2988 miocnak(wq, mp, 0, rv); 2989 } 2990 } 2991 2992 int 2993 afe_ndaddbytes(mblk_t *mp, char *bytes, int cnt) 2994 { 2995 int index; 2996 2997 for (index = 0; index < cnt; index++) { 2998 while (mp && (mp->b_wptr >= DB_LIM(mp))) { 2999 mp = mp->b_cont; 3000 } 3001 if (mp == NULL) { 3002 return (ENOSPC); 3003 } 3004 *(mp->b_wptr) = *bytes; 3005 mp->b_wptr++; 3006 bytes++; 3007 } 3008 return (0); 3009 } 3010 3011 int 3012 afe_ndaddstr(mblk_t *mp, char *str, int addnull) 3013 { 3014 /* store the string, plus the terminating null */ 3015 return (afe_ndaddbytes(mp, str, strlen(str) + (addnull ? 1 : 0))); 3016 } 3017 3018 int 3019 afe_ndparselen(mblk_t *mp) 3020 { 3021 int len = 0; 3022 int done = 0; 3023 uchar_t *ptr; 3024 3025 while (mp && !done) { 3026 for (ptr = mp->b_rptr; ptr < mp->b_wptr; ptr++) { 3027 if (!(*ptr)) { 3028 done = 1; 3029 break; 3030 } 3031 len++; 3032 } 3033 mp = mp->b_cont; 3034 } 3035 return (len); 3036 } 3037 3038 int 3039 afe_ndparseint(mblk_t *mp) 3040 { 3041 int done = 0; 3042 int val = 0; 3043 while (mp && !done) { 3044 while (mp->b_rptr < mp->b_wptr) { 3045 uchar_t ch = *(mp->b_rptr); 3046 mp->b_rptr++; 3047 if ((ch >= '0') && (ch <= '9')) { 3048 val *= 10; 3049 val += ch - '0'; 3050 } else if (ch == 0) { 3051 return (val); 3052 } else { 3053 /* parse error, put back rptr */ 3054 mp->b_rptr--; 3055 return (val); 3056 } 3057 } 3058 mp = mp->b_cont; 3059 } 3060 return (val); 3061 } 3062 3063 void 3064 afe_ndparsestring(mblk_t *mp, char *buf, int maxlen) 3065 { 3066 int done = 0; 3067 int len = 0; 3068 3069 /* ensure null termination */ 3070 buf[maxlen - 1] = 0; 3071 while (mp && !done) { 3072 while (mp->b_rptr < mp->b_wptr) { 3073 char ch = *((char *)mp->b_rptr); 3074 mp->b_rptr++; 3075 buf[len++] = ch; 3076 if ((ch == 0) || (len == maxlen)) { 3077 return; 3078 } 3079 } 3080 mp = mp->b_cont; 3081 } 3082 } 3083 3084 int 3085 afe_ndquestion(afe_t *afep, mblk_t *mp, afe_nd_t *ndp) 3086 { 3087 for (ndp = afep->afe_ndp; ndp; ndp = ndp->nd_next) { 3088 int rv; 3089 char *s; 3090 if ((rv = afe_ndaddstr(mp, ndp->nd_name, 0)) != 0) { 3091 return (rv); 3092 } 3093 if (ndp->nd_get && ndp->nd_set) { 3094 s = " (read and write)"; 3095 } else if (ndp->nd_get) { 3096 s = " (read only)"; 3097 } else if (ndp->nd_set) { 3098 s = " (write only)"; 3099 } else { 3100 s = " (no read or write)"; 3101 } 3102 if ((rv = afe_ndaddstr(mp, s, 1)) != 0) { 3103 return (rv); 3104 } 3105 } 3106 return (0); 3107 } 3108 3109 /*ARGSUSED*/ 3110 int 3111 afe_ndgetint(afe_t *afep, mblk_t *mp, afe_nd_t *ndp) 3112 { 3113 int val; 3114 char buf[16]; 3115 3116 val = *(int *)ndp->nd_arg1; 3117 3118 (void) snprintf(buf, sizeof (buf), "%d", val); 3119 return (afe_ndaddstr(mp, buf, 1)); 3120 } 3121 3122 int 3123 afe_ndgetmiibit(afe_t *afep, mblk_t *mp, afe_nd_t *ndp) 3124 { 3125 unsigned val; 3126 unsigned mask; 3127 int reg; 3128 3129 reg = (int)ndp->nd_arg1; 3130 mask = (unsigned)ndp->nd_arg2; 3131 3132 mutex_enter(&afep->afe_xmtlock); 3133 if (afep->afe_flags & AFE_SUSPENDED) { 3134 mutex_exit(&afep->afe_xmtlock); 3135 /* device is suspended */ 3136 return (EIO); 3137 } 3138 val = afe_miiread(afep, afep->afe_phyaddr, reg); 3139 mutex_exit(&afep->afe_xmtlock); 3140 3141 return (afe_ndaddstr(mp, val & mask ? "1" : "0", 1)); 3142 } 3143 3144 int 3145 afe_ndsetadv(afe_t *afep, mblk_t *mp, afe_nd_t *ndp) 3146 { 3147 unsigned *ptr = (unsigned *)ndp->nd_arg1; 3148 unsigned oldval, newval; 3149 3150 newval = afe_ndparseint(mp) ? 1 : 0; 3151 3152 mutex_enter(&afep->afe_intrlock); 3153 mutex_enter(&afep->afe_xmtlock); 3154 3155 oldval = *ptr; 3156 if (oldval != newval) { 3157 *ptr = newval; 3158 if ((afep->afe_flags & (AFE_RUNNING|AFE_SUSPENDED)) == 3159 AFE_RUNNING) { 3160 /* 3161 * This re-initializes the phy, but it also 3162 * restarts transmit and receive rings. 3163 * Needless to say, changing the link 3164 * parameters is destructive to traffic in 3165 * progress. 3166 */ 3167 afe_resetall(afep); 3168 } 3169 } 3170 mutex_exit(&afep->afe_xmtlock); 3171 mutex_exit(&afep->afe_intrlock); 3172 3173 return (0); 3174 } 3175 3176 void 3177 afe_ndfini(afe_t *afep) 3178 { 3179 afe_nd_t *ndp; 3180 3181 while ((ndp = afep->afe_ndp) != NULL) { 3182 afep->afe_ndp = ndp->nd_next; 3183 kmem_free(ndp, sizeof (afe_nd_t)); 3184 } 3185 } 3186 3187 void 3188 afe_ndinit(afe_t *afep) 3189 { 3190 afe_ndadd(afep, "?", afe_ndquestion, NULL, 0, 0); 3191 afe_ndadd(afep, "link_status", afe_ndgetint, NULL, 3192 (intptr_t)&afep->afe_linkup, 0); 3193 afe_ndadd(afep, "link_speed", afe_ndgetint, NULL, 3194 (intptr_t)&afep->afe_ifspeed, 0); 3195 afe_ndadd(afep, "link_duplex", afe_ndgetint, NULL, 3196 (intptr_t)&afep->afe_duplex, 0); 3197 afe_ndadd(afep, "adv_autoneg_cap", afe_ndgetint, afe_ndsetadv, 3198 (intptr_t)&afep->afe_adv_aneg, 0); 3199 afe_ndadd(afep, "adv_100T4_cap", afe_ndgetint, afe_ndsetadv, 3200 (intptr_t)&afep->afe_adv_100T4, 0); 3201 afe_ndadd(afep, "adv_100fdx_cap", afe_ndgetint, afe_ndsetadv, 3202 (intptr_t)&afep->afe_adv_100fdx, 0); 3203 afe_ndadd(afep, "adv_100hdx_cap", afe_ndgetint, afe_ndsetadv, 3204 (intptr_t)&afep->afe_adv_100hdx, 0); 3205 afe_ndadd(afep, "adv_10fdx_cap", afe_ndgetint, afe_ndsetadv, 3206 (intptr_t)&afep->afe_adv_10fdx, 0); 3207 afe_ndadd(afep, "adv_10hdx_cap", afe_ndgetint, afe_ndsetadv, 3208 (intptr_t)&afep->afe_adv_10hdx, 0); 3209 afe_ndadd(afep, "autoneg_cap", afe_ndgetmiibit, NULL, 3210 MII_STATUS, MII_STATUS_CANAUTONEG); 3211 afe_ndadd(afep, "100T4_cap", afe_ndgetmiibit, NULL, 3212 MII_STATUS, MII_STATUS_100_BASE_T4); 3213 afe_ndadd(afep, "100fdx_cap", afe_ndgetmiibit, NULL, 3214 MII_STATUS, MII_STATUS_100_BASEX_FD); 3215 afe_ndadd(afep, "100hdx_cap", afe_ndgetmiibit, NULL, 3216 MII_STATUS, MII_STATUS_100_BASEX); 3217 afe_ndadd(afep, "10fdx_cap", afe_ndgetmiibit, NULL, 3218 MII_STATUS, MII_STATUS_10_FD); 3219 afe_ndadd(afep, "10hdx_cap", afe_ndgetmiibit, NULL, 3220 MII_STATUS, MII_STATUS_10); 3221 afe_ndadd(afep, "lp_autoneg_cap", afe_ndgetmiibit, NULL, 3222 MII_AN_EXPANSION, MII_AN_EXP_LPCANAN); 3223 afe_ndadd(afep, "lp_100T4_cap", afe_ndgetmiibit, NULL, 3224 MII_AN_LPABLE, MII_ABILITY_100BASE_T4); 3225 afe_ndadd(afep, "lp_100fdx_cap", afe_ndgetmiibit, NULL, 3226 MII_AN_LPABLE, MII_ABILITY_100BASE_TX_FD); 3227 afe_ndadd(afep, "lp_100hdx_cap", afe_ndgetmiibit, NULL, 3228 MII_AN_LPABLE, MII_ABILITY_100BASE_TX); 3229 afe_ndadd(afep, "lp_10fdx_cap", afe_ndgetmiibit, NULL, 3230 MII_AN_LPABLE, MII_ABILITY_10BASE_T_FD); 3231 afe_ndadd(afep, "lp_10hdx_cap", afe_ndgetmiibit, NULL, 3232 MII_AN_LPABLE, MII_ABILITY_10BASE_T); 3233 } 3234 3235 /* 3236 * Debugging and error reporting. 3237 */ 3238 void 3239 afe_error(dev_info_t *dip, char *fmt, ...) 3240 { 3241 va_list ap; 3242 char buf[256]; 3243 3244 va_start(ap, fmt); 3245 (void) vsnprintf(buf, sizeof (buf), fmt, ap); 3246 va_end(ap); 3247 3248 if (dip) { 3249 cmn_err(CE_WARN, "%s%d: %s", 3250 ddi_driver_name(dip), ddi_get_instance(dip), buf); 3251 } else { 3252 cmn_err(CE_WARN, "afe: %s", buf); 3253 } 3254 } 3255 3256 #ifdef DEBUG 3257 3258 void 3259 afe_dprintf(afe_t *afep, const char *func, int level, char *fmt, ...) 3260 { 3261 va_list ap; 3262 3263 va_start(ap, fmt); 3264 if (afe_debug & level) { 3265 char tag[64]; 3266 char buf[256]; 3267 3268 if (afep && afep->afe_dip) { 3269 (void) snprintf(tag, sizeof (tag), "%s%d", 3270 ddi_driver_name(afep->afe_dip), 3271 ddi_get_instance(afep->afe_dip)); 3272 } else { 3273 (void) snprintf(tag, sizeof (tag), "afe"); 3274 } 3275 3276 (void) snprintf(buf, sizeof (buf), "%s: %s: %s\n", 3277 tag, func, fmt); 3278 3279 vcmn_err(CE_CONT, buf, ap); 3280 } 3281 va_end(ap); 3282 } 3283 3284 #endif 3285