1 /* rhine.c:Fast Ethernet driver for Linux. */ 2 /* 3 Adapted 09-jan-2000 by Paolo Marini (paolom@prisma-eng.it) 4 5 originally written by Donald Becker. 6 7 This software may be used and distributed according to the terms 8 of the GNU Public License (GPL), incorporated herein by reference. 9 Drivers derived from this code also fall under the GPL and must retain 10 this authorship and copyright notice. 11 12 Under no circumstances are the authors responsible for 13 the proper functioning of this software, nor do the authors assume any 14 responsibility for damages incurred with its use. 15 16 This driver is designed for the VIA VT86C100A Rhine-II PCI Fast Ethernet 17 controller. 18 19 */ 20 21 static const char *version = "rhine.c v1.0.1 2003-02-06\n"; 22 23 /* A few user-configurable values. */ 24 25 /* Size of the in-memory receive ring. */ 26 #define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K */ 27 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX) 28 29 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */ 30 #define TX_BUF_SIZE 1536 31 #define RX_BUF_SIZE 1536 32 33 /* PCI Tuning Parameters 34 Threshold is bytes transferred to chip before transmission starts. */ 35 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ 36 37 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024. */ 38 #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */ 39 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */ 40 #define TX_DMA_BURST 4 41 42 /* Operational parameters that usually are not changed. */ 43 /* Time in jiffies before concluding the transmitter is hung. */ 44 #define TX_TIMEOUT ((2000*HZ)/1000) 45 46 #include "etherboot.h" 47 #include "nic.h" 48 #include "pci.h" 49 50 /* define all ioaddr */ 51 52 #define byPAR0 ioaddr 53 #define byRCR ioaddr + 6 54 #define byTCR ioaddr + 7 55 #define byCR0 ioaddr + 8 56 #define byCR1 ioaddr + 9 57 #define byISR0 ioaddr + 0x0c 58 #define byISR1 ioaddr + 0x0d 59 #define byIMR0 ioaddr + 0x0e 60 #define byIMR1 ioaddr + 0x0f 61 #define byMAR0 ioaddr + 0x10 62 #define byMAR1 ioaddr + 0x11 63 #define byMAR2 ioaddr + 0x12 64 #define byMAR3 ioaddr + 0x13 65 #define byMAR4 ioaddr + 0x14 66 #define byMAR5 ioaddr + 0x15 67 #define byMAR6 ioaddr + 0x16 68 #define byMAR7 ioaddr + 0x17 69 #define dwCurrentRxDescAddr ioaddr + 0x18 70 #define dwCurrentTxDescAddr ioaddr + 0x1c 71 #define dwCurrentRDSE0 ioaddr + 0x20 72 #define dwCurrentRDSE1 ioaddr + 0x24 73 #define dwCurrentRDSE2 ioaddr + 0x28 74 #define dwCurrentRDSE3 ioaddr + 0x2c 75 #define dwNextRDSE0 ioaddr + 0x30 76 #define dwNextRDSE1 ioaddr + 0x34 77 #define dwNextRDSE2 ioaddr + 0x38 78 #define dwNextRDSE3 ioaddr + 0x3c 79 #define dwCurrentTDSE0 ioaddr + 0x40 80 #define dwCurrentTDSE1 ioaddr + 0x44 81 #define dwCurrentTDSE2 ioaddr + 0x48 82 #define dwCurrentTDSE3 ioaddr + 0x4c 83 #define dwNextTDSE0 ioaddr + 0x50 84 #define dwNextTDSE1 ioaddr + 0x54 85 #define dwNextTDSE2 ioaddr + 0x58 86 #define dwNextTDSE3 ioaddr + 0x5c 87 #define dwCurrRxDMAPtr ioaddr + 0x60 88 #define dwCurrTxDMAPtr ioaddr + 0x64 89 #define byMPHY ioaddr + 0x6c 90 #define byMIISR ioaddr + 0x6d 91 #define byBCR0 ioaddr + 0x6e 92 #define byBCR1 ioaddr + 0x6f 93 #define byMIICR ioaddr + 0x70 94 #define byMIIAD ioaddr + 0x71 95 #define wMIIDATA ioaddr + 0x72 96 #define byEECSR ioaddr + 0x74 97 #define byTEST ioaddr + 0x75 98 #define byGPIO ioaddr + 0x76 99 #define byCFGA ioaddr + 0x78 100 #define byCFGB ioaddr + 0x79 101 #define byCFGC ioaddr + 0x7a 102 #define byCFGD ioaddr + 0x7b 103 #define wTallyCntMPA ioaddr + 0x7c 104 #define wTallyCntCRC ioaddr + 0x7d 105 #define bySTICKHW ioaddr + 0x83 106 #define byWOLcrClr ioaddr + 0xA4 107 #define byWOLcgClr ioaddr + 0xA7 108 #define byPwrcsrClr ioaddr + 0xAC 109 110 /*--------------------- Exioaddr Definitions -------------------------*/ 111 112 /* 113 * Bits in the RCR register 114 */ 115 116 #define RCR_RRFT2 0x80 117 #define RCR_RRFT1 0x40 118 #define RCR_RRFT0 0x20 119 #define RCR_PROM 0x10 120 #define RCR_AB 0x08 121 #define RCR_AM 0x04 122 #define RCR_AR 0x02 123 #define RCR_SEP 0x01 124 125 /* 126 * Bits in the TCR register 127 */ 128 129 #define TCR_RTSF 0x80 130 #define TCR_RTFT1 0x40 131 #define TCR_RTFT0 0x20 132 #define TCR_OFSET 0x08 133 #define TCR_LB1 0x04 /* loopback[1] */ 134 #define TCR_LB0 0x02 /* loopback[0] */ 135 136 /* 137 * Bits in the CR0 register 138 */ 139 140 #define CR0_RDMD 0x40 /* rx descriptor polling demand */ 141 #define CR0_TDMD 0x20 /* tx descriptor polling demand */ 142 #define CR0_TXON 0x10 143 #define CR0_RXON 0x08 144 #define CR0_STOP 0x04 /* stop NIC, default = 1 */ 145 #define CR0_STRT 0x02 /* start NIC */ 146 #define CR0_INIT 0x01 /* start init process */ 147 148 149 /* 150 * Bits in the CR1 register 151 */ 152 153 #define CR1_SFRST 0x80 /* software reset */ 154 #define CR1_RDMD1 0x40 /* RDMD1 */ 155 #define CR1_TDMD1 0x20 /* TDMD1 */ 156 #define CR1_KEYPAG 0x10 /* turn on par/key */ 157 #define CR1_DPOLL 0x08 /* disable rx/tx auto polling */ 158 #define CR1_FDX 0x04 /* full duplex mode */ 159 #define CR1_ETEN 0x02 /* early tx mode */ 160 #define CR1_EREN 0x01 /* early rx mode */ 161 162 /* 163 * Bits in the CR register 164 */ 165 166 #define CR_RDMD 0x0040 /* rx descriptor polling demand */ 167 #define CR_TDMD 0x0020 /* tx descriptor polling demand */ 168 #define CR_TXON 0x0010 169 #define CR_RXON 0x0008 170 #define CR_STOP 0x0004 /* stop NIC, default = 1 */ 171 #define CR_STRT 0x0002 /* start NIC */ 172 #define CR_INIT 0x0001 /* start init process */ 173 #define CR_SFRST 0x8000 /* software reset */ 174 #define CR_RDMD1 0x4000 /* RDMD1 */ 175 #define CR_TDMD1 0x2000 /* TDMD1 */ 176 #define CR_KEYPAG 0x1000 /* turn on par/key */ 177 #define CR_DPOLL 0x0800 /* disable rx/tx auto polling */ 178 #define CR_FDX 0x0400 /* full duplex mode */ 179 #define CR_ETEN 0x0200 /* early tx mode */ 180 #define CR_EREN 0x0100 /* early rx mode */ 181 182 /* 183 * Bits in the IMR0 register 184 */ 185 186 #define IMR0_CNTM 0x80 187 #define IMR0_BEM 0x40 188 #define IMR0_RUM 0x20 189 #define IMR0_TUM 0x10 190 #define IMR0_TXEM 0x08 191 #define IMR0_RXEM 0x04 192 #define IMR0_PTXM 0x02 193 #define IMR0_PRXM 0x01 194 195 /* define imrshadow */ 196 197 #define IMRShadow 0x5AFF 198 199 /* 200 * Bits in the IMR1 register 201 */ 202 203 #define IMR1_INITM 0x80 204 #define IMR1_SRCM 0x40 205 #define IMR1_NBFM 0x10 206 #define IMR1_PRAIM 0x08 207 #define IMR1_RES0M 0x04 208 #define IMR1_ETM 0x02 209 #define IMR1_ERM 0x01 210 211 /* 212 * Bits in the ISR register 213 */ 214 215 #define ISR_INITI 0x8000 216 #define ISR_SRCI 0x4000 217 #define ISR_ABTI 0x2000 218 #define ISR_NORBF 0x1000 219 #define ISR_PKTRA 0x0800 220 #define ISR_RES0 0x0400 221 #define ISR_ETI 0x0200 222 #define ISR_ERI 0x0100 223 #define ISR_CNT 0x0080 224 #define ISR_BE 0x0040 225 #define ISR_RU 0x0020 226 #define ISR_TU 0x0010 227 #define ISR_TXE 0x0008 228 #define ISR_RXE 0x0004 229 #define ISR_PTX 0x0002 230 #define ISR_PRX 0x0001 231 232 /* 233 * Bits in the ISR0 register 234 */ 235 236 #define ISR0_CNT 0x80 237 #define ISR0_BE 0x40 238 #define ISR0_RU 0x20 239 #define ISR0_TU 0x10 240 #define ISR0_TXE 0x08 241 #define ISR0_RXE 0x04 242 #define ISR0_PTX 0x02 243 #define ISR0_PRX 0x01 244 245 /* 246 * Bits in the ISR1 register 247 */ 248 249 #define ISR1_INITI 0x80 250 #define ISR1_SRCI 0x40 251 #define ISR1_NORBF 0x10 252 #define ISR1_PKTRA 0x08 253 #define ISR1_ETI 0x02 254 #define ISR1_ERI 0x01 255 256 /* ISR ABNORMAL CONDITION */ 257 258 #define ISR_ABNORMAL ISR_BE+ISR_RU+ISR_TU+ISR_CNT+ISR_NORBF+ISR_PKTRA 259 260 /* 261 * Bits in the MIISR register 262 */ 263 264 #define MIISR_MIIERR 0x08 265 #define MIISR_MRERR 0x04 266 #define MIISR_LNKFL 0x02 267 #define MIISR_SPEED 0x01 268 269 /* 270 * Bits in the MIICR register 271 */ 272 273 #define MIICR_MAUTO 0x80 274 #define MIICR_RCMD 0x40 275 #define MIICR_WCMD 0x20 276 #define MIICR_MDPM 0x10 277 #define MIICR_MOUT 0x08 278 #define MIICR_MDO 0x04 279 #define MIICR_MDI 0x02 280 #define MIICR_MDC 0x01 281 282 /* 283 * Bits in the EECSR register 284 */ 285 286 #define EECSR_EEPR 0x80 /* eeprom programed status, 73h means programed */ 287 #define EECSR_EMBP 0x40 /* eeprom embeded programming */ 288 #define EECSR_AUTOLD 0x20 /* eeprom content reload */ 289 #define EECSR_DPM 0x10 /* eeprom direct programming */ 290 #define EECSR_CS 0x08 /* eeprom CS pin */ 291 #define EECSR_SK 0x04 /* eeprom SK pin */ 292 #define EECSR_DI 0x02 /* eeprom DI pin */ 293 #define EECSR_DO 0x01 /* eeprom DO pin */ 294 295 /* 296 * Bits in the BCR0 register 297 */ 298 299 #define BCR0_CRFT2 0x20 300 #define BCR0_CRFT1 0x10 301 #define BCR0_CRFT0 0x08 302 #define BCR0_DMAL2 0x04 303 #define BCR0_DMAL1 0x02 304 #define BCR0_DMAL0 0x01 305 306 /* 307 * Bits in the BCR1 register 308 */ 309 310 #define BCR1_CTSF 0x20 311 #define BCR1_CTFT1 0x10 312 #define BCR1_CTFT0 0x08 313 #define BCR1_POT2 0x04 314 #define BCR1_POT1 0x02 315 #define BCR1_POT0 0x01 316 317 /* 318 * Bits in the CFGA register 319 */ 320 321 #define CFGA_EELOAD 0x80 /* enable eeprom embeded and direct programming */ 322 #define CFGA_JUMPER 0x40 323 #define CFGA_MTGPIO 0x08 324 #define CFGA_T10EN 0x02 325 #define CFGA_AUTO 0x01 326 327 /* 328 * Bits in the CFGB register 329 */ 330 331 #define CFGB_PD 0x80 332 #define CFGB_POLEN 0x02 333 #define CFGB_LNKEN 0x01 334 335 /* 336 * Bits in the CFGC register 337 */ 338 339 #define CFGC_M10TIO 0x80 340 #define CFGC_M10POL 0x40 341 #define CFGC_PHY1 0x20 342 #define CFGC_PHY0 0x10 343 #define CFGC_BTSEL 0x08 344 #define CFGC_BPS2 0x04 /* bootrom select[2] */ 345 #define CFGC_BPS1 0x02 /* bootrom select[1] */ 346 #define CFGC_BPS0 0x01 /* bootrom select[0] */ 347 348 /* 349 * Bits in the CFGD register 350 */ 351 352 #define CFGD_GPIOEN 0x80 353 #define CFGD_DIAG 0x40 354 #define CFGD_MAGIC 0x10 355 #define CFGD_CFDX 0x04 356 #define CFGD_CEREN 0x02 357 #define CFGD_CETEN 0x01 358 359 /* Bits in RSR */ 360 #define RSR_RERR 0x00000001 361 #define RSR_CRC 0x00000002 362 #define RSR_FAE 0x00000004 363 #define RSR_FOV 0x00000008 364 #define RSR_LONG 0x00000010 365 #define RSR_RUNT 0x00000020 366 #define RSR_SERR 0x00000040 367 #define RSR_BUFF 0x00000080 368 #define RSR_EDP 0x00000100 369 #define RSR_STP 0x00000200 370 #define RSR_CHN 0x00000400 371 #define RSR_PHY 0x00000800 372 #define RSR_BAR 0x00001000 373 #define RSR_MAR 0x00002000 374 #define RSR_RXOK 0x00008000 375 #define RSR_ABNORMAL RSR_RERR+RSR_LONG+RSR_RUNT 376 377 /* Bits in TSR */ 378 #define TSR_NCR0 0x00000001 379 #define TSR_NCR1 0x00000002 380 #define TSR_NCR2 0x00000004 381 #define TSR_NCR3 0x00000008 382 #define TSR_COLS 0x00000010 383 #define TSR_CDH 0x00000080 384 #define TSR_ABT 0x00000100 385 #define TSR_OWC 0x00000200 386 #define TSR_CRS 0x00000400 387 #define TSR_UDF 0x00000800 388 #define TSR_TBUFF 0x00001000 389 #define TSR_SERR 0x00002000 390 #define TSR_JAB 0x00004000 391 #define TSR_TERR 0x00008000 392 #define TSR_ABNORMAL TSR_TERR+TSR_OWC+TSR_ABT+TSR_JAB+TSR_CRS 393 #define TSR_OWN_BIT 0x80000000 394 395 #define CB_DELAY_LOOP_WAIT 10 /* 10ms */ 396 /* enabled mask value of irq */ 397 398 #define W_IMR_MASK_VALUE 0x1BFF /* initial value of IMR */ 399 400 /* Ethernet address filter type */ 401 #define PKT_TYPE_DIRECTED 0x0001 /* obsolete, directed address is always accepted */ 402 #define PKT_TYPE_MULTICAST 0x0002 403 #define PKT_TYPE_ALL_MULTICAST 0x0004 404 #define PKT_TYPE_BROADCAST 0x0008 405 #define PKT_TYPE_PROMISCUOUS 0x0020 406 #define PKT_TYPE_LONG 0x2000 407 #define PKT_TYPE_RUNT 0x4000 408 #define PKT_TYPE_ERROR 0x8000 /* accept error packets, e.g. CRC error */ 409 410 /* Loopback mode */ 411 412 #define NIC_LB_NONE 0x00 413 #define NIC_LB_INTERNAL 0x01 414 #define NIC_LB_PHY 0x02 /* MII or Internal-10BaseT loopback */ 415 416 #define TX_RING_SIZE 2 417 #define RX_RING_SIZE 2 418 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */ 419 420 /* Transmit and receive descriptors definition */ 421 422 struct rhine_tx_desc 423 { 424 union VTC_tx_status_tag 425 { 426 struct 427 { 428 unsigned long ncro:1; 429 unsigned long ncr1:1; 430 unsigned long ncr2:1; 431 unsigned long ncr3:1; 432 unsigned long cols:1; 433 unsigned long reserve_1:2; 434 unsigned long cdh:1; 435 unsigned long abt:1; 436 unsigned long owc:1; 437 unsigned long crs:1; 438 unsigned long udf:1; 439 unsigned long tbuff:1; 440 unsigned long serr:1; 441 unsigned long jab:1; 442 unsigned long terr:1; 443 unsigned long reserve_2:15; 444 unsigned long own_bit:1; 445 } 446 bits; 447 unsigned long lw; 448 } 449 tx_status; 450 451 union VTC_tx_ctrl_tag 452 { 453 struct 454 { 455 unsigned long tx_buf_size:11; 456 unsigned long extend_tx_buf_size:4; 457 unsigned long chn:1; 458 unsigned long crc:1; 459 unsigned long reserve_1:4; 460 unsigned long stp:1; 461 unsigned long edp:1; 462 unsigned long ic:1; 463 unsigned long reserve_2:8; 464 } 465 bits; 466 unsigned long lw; 467 } 468 tx_ctrl; 469 470 unsigned long buf_addr_1:32; 471 unsigned long buf_addr_2:32; 472 473 }; 474 475 struct rhine_rx_desc 476 { 477 union VTC_rx_status_tag 478 { 479 struct 480 { 481 unsigned long rerr:1; 482 unsigned long crc_error:1; 483 unsigned long fae:1; 484 unsigned long fov:1; 485 unsigned long toolong:1; 486 unsigned long runt:1; 487 unsigned long serr:1; 488 unsigned long buff:1; 489 unsigned long edp:1; 490 unsigned long stp:1; 491 unsigned long chn:1; 492 unsigned long phy:1; 493 unsigned long bar:1; 494 unsigned long mar:1; 495 unsigned long reserve_1:1; 496 unsigned long rxok:1; 497 unsigned long frame_length:11; 498 unsigned long reverve_2:4; 499 unsigned long own_bit:1; 500 } 501 bits; 502 unsigned long lw; 503 } 504 rx_status; 505 506 union VTC_rx_ctrl_tag 507 { 508 struct 509 { 510 unsigned long rx_buf_size:11; 511 unsigned long extend_rx_buf_size:4; 512 unsigned long reserved_1:17; 513 } 514 bits; 515 unsigned long lw; 516 } 517 rx_ctrl; 518 519 unsigned long buf_addr_1:32; 520 unsigned long buf_addr_2:32; 521 522 }; 523 524 525 /* The I/O extent. */ 526 #define rhine_TOTAL_SIZE 0x80 527 528 #ifdef HAVE_DEVLIST 529 struct netdev_entry rhine_drv = 530 { "rhine", rhine_probe, rhine_TOTAL_SIZE, NULL }; 531 #endif 532 533 static int rhine_debug = 1; 534 535 /* 536 Theory of Operation 537 538 I. Board Compatibility 539 540 This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet 541 controller. 542 543 II. Board-specific settings 544 545 Boards with this chip are functional only in a bus-master PCI slot. 546 547 Many operational settings are loaded from the EEPROM to the Config word at 548 offset 0x78. This driver assumes that they are correct. 549 If this driver is compiled to use PCI memory space operations the EEPROM 550 must be configured to enable memory ops. 551 552 III. Driver operation 553 554 IIIa. Ring buffers 555 556 This driver uses two statically allocated fixed-size descriptor lists 557 formed into rings by a branch from the final descriptor to the beginning of 558 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE. 559 560 IIIb/c. Transmit/Receive Structure 561 562 This driver attempts to use a zero-copy receive and transmit scheme. 563 564 Alas, all data buffers are required to start on a 32 bit boundary, so 565 the driver must often copy transmit packets into bounce buffers. 566 567 The driver allocates full frame size skbuffs for the Rx ring buffers at 568 open() time and passes the skb->data field to the chip as receive data 569 buffers. When an incoming frame is less than RX_COPYBREAK bytes long, 570 a fresh skbuff is allocated and the frame is copied to the new skbuff. 571 When the incoming frame is larger, the skbuff is passed directly up the 572 protocol stack. Buffers consumed this way are replaced by newly allocated 573 skbuffs in the last phase of netdev_rx(). 574 575 The RX_COPYBREAK value is chosen to trade-off the memory wasted by 576 using a full-sized skbuff for small frames vs. the copying costs of larger 577 frames. New boards are typically used in generously configured machines 578 and the underfilled buffers have negligible impact compared to the benefit of 579 a single allocation size, so the default value of zero results in never 580 copying packets. When copying is done, the cost is usually mitigated by using 581 a combined copy/checksum routine. Copying also preloads the cache, which is 582 most useful with small frames. 583 584 Since the VIA chips are only able to transfer data to buffers on 32 bit 585 boundaries, the the IP header at offset 14 in an ethernet frame isn't 586 longword aligned for further processing. Copying these unaligned buffers 587 has the beneficial effect of 16-byte aligning the IP header. 588 589 IIId. Synchronization 590 591 The driver runs as two independent, single-threaded flows of control. One 592 is the send-packet routine, which enforces single-threaded use by the 593 dev->tbusy flag. The other thread is the interrupt handler, which is single 594 threaded by the hardware and interrupt handling software. 595 596 The send packet thread has partial control over the Tx ring and 'dev->tbusy' 597 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next 598 queue slot is empty, it clears the tbusy flag when finished otherwise it sets 599 the 'lp->tx_full' flag. 600 601 The interrupt handler has exclusive control over the Rx ring and records stats 602 from the Tx ring. After reaping the stats, it marks the Tx queue entry as 603 empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it 604 clears both the tx_full and tbusy flags. 605 606 IV. Notes 607 608 IVb. References 609 610 Preliminary VT86C100A manual from http://www.via.com.tw/ 611 http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html 612 http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html 613 614 IVc. Errata 615 616 The VT86C100A manual is not reliable information. 617 The chip does not handle unaligned transmit or receive buffers, resulting 618 in significant performance degradation for bounce buffer copies on transmit 619 and unaligned IP headers on receive. 620 The chip does not pad to minimum transmit length. 621 622 */ 623 624 /* The rest of these values should never change. */ 625 #define NUM_TX_DESC 2 /* Number of Tx descriptor registers. */ 626 627 static struct rhine_private 628 { 629 char devname[8]; /* Used only for kernel debugging. */ 630 const char *product_name; 631 struct rhine_rx_desc *rx_ring; 632 struct rhine_tx_desc *tx_ring; 633 char *rx_buffs[RX_RING_SIZE]; 634 char *tx_buffs[TX_RING_SIZE]; 635 636 /* temporary Rx buffers. */ 637 638 int chip_id; 639 int chip_revision; 640 unsigned short ioaddr; 641 unsigned int cur_rx, cur_tx; /* The next free and used entries */ 642 unsigned int dirty_rx, dirty_tx; 643 /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 644 struct sk_buff *tx_skbuff[TX_RING_SIZE]; 645 unsigned char mc_filter[8]; /* Current multicast filter. */ 646 char phys[4]; /* MII device addresses. */ 647 unsigned int tx_full:1; /* The Tx queue is full. */ 648 unsigned int full_duplex:1; /* Full-duplex operation requested. */ 649 unsigned int default_port:4; /* Last dev->if_port value. */ 650 unsigned int media2:4; /* Secondary monitored media port. */ 651 unsigned int medialock:1; /* Don't sense media type. */ 652 unsigned int mediasense:1; /* Media sensing in progress. */ 653 } 654 rhine; 655 656 static void rhine_probe1 (struct nic *nic, int ioaddr, 657 int chip_id, int options); 658 static int QueryAuto (int); 659 static int ReadMII (int byMIIIndex, int); 660 static void WriteMII (char, char, char, int); 661 static void MIIDelay (void); 662 static void rhine_init_ring (struct nic *dev); 663 static void rhine_disable (struct dev *dev); 664 static void rhine_reset (struct nic *nic); 665 static int rhine_poll (struct nic *nic, int retreive); 666 static void rhine_transmit (struct nic *nic, const char *d, unsigned int t, 667 unsigned int s, const char *p); 668 669 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 670 static void 671 rhine_init_ring (struct nic *nic) 672 { 673 struct rhine_private *tp = (struct rhine_private *) nic->priv_data; 674 int i; 675 676 tp->tx_full = 0; 677 tp->cur_rx = tp->cur_tx = 0; 678 tp->dirty_rx = tp->dirty_tx = 0; 679 680 for (i = 0; i < RX_RING_SIZE; i++) 681 { 682 683 tp->rx_ring[i].rx_status.bits.own_bit = 1; 684 tp->rx_ring[i].rx_ctrl.bits.rx_buf_size = 1536; 685 686 tp->rx_ring[i].buf_addr_1 = virt_to_bus (tp->rx_buffs[i]); 687 tp->rx_ring[i].buf_addr_2 = virt_to_bus (&tp->rx_ring[i + 1]); 688 /* printf("[%d]buf1=%hX,buf2=%hX",i,tp->rx_ring[i].buf_addr_1,tp->rx_ring[i].buf_addr_2); */ 689 } 690 /* Mark the last entry as wrapping the ring. */ 691 /* tp->rx_ring[i-1].rx_ctrl.bits.rx_buf_size =1518; */ 692 tp->rx_ring[i - 1].buf_addr_2 = virt_to_bus (&tp->rx_ring[0]); 693 /*printf("[%d]buf1=%hX,buf2=%hX",i-1,tp->rx_ring[i-1].buf_addr_1,tp->rx_ring[i-1].buf_addr_2); */ 694 695 /* The Tx buffer descriptor is filled in as needed, but we 696 do need to clear the ownership bit. */ 697 698 for (i = 0; i < TX_RING_SIZE; i++) 699 { 700 701 tp->tx_ring[i].tx_status.lw = 0; 702 tp->tx_ring[i].tx_ctrl.lw = 0x00e08000; 703 tp->tx_ring[i].buf_addr_1 = virt_to_bus (tp->tx_buffs[i]); 704 tp->tx_ring[i].buf_addr_2 = virt_to_bus (&tp->tx_ring[i + 1]); 705 /* printf("[%d]buf1=%hX,buf2=%hX",i,tp->tx_ring[i].buf_addr_1,tp->tx_ring[i].buf_addr_2); */ 706 } 707 708 tp->tx_ring[i - 1].buf_addr_2 = virt_to_bus (&tp->tx_ring[0]); 709 /* printf("[%d]buf1=%hX,buf2=%hX",i,tp->tx_ring[i-1].buf_addr_1,tp->tx_ring[i-1].buf_addr_2); */ 710 } 711 712 int 713 QueryAuto (int ioaddr) 714 { 715 int byMIIIndex; 716 int MIIReturn; 717 718 int advertising,mii_reg5; 719 int negociated; 720 721 byMIIIndex = 0x04; 722 MIIReturn = ReadMII (byMIIIndex, ioaddr); 723 advertising=MIIReturn; 724 725 byMIIIndex = 0x05; 726 MIIReturn = ReadMII (byMIIIndex, ioaddr); 727 mii_reg5=MIIReturn; 728 729 negociated=mii_reg5 & advertising; 730 731 if ( (negociated & 0x100) || (negociated & 0x1C0) == 0x40 ) 732 return 1; 733 else 734 return 0; 735 736 } 737 738 int 739 ReadMII (int byMIIIndex, int ioaddr) 740 { 741 int ReturnMII; 742 char byMIIAdrbak; 743 char byMIICRbak; 744 char byMIItemp; 745 746 byMIIAdrbak = inb (byMIIAD); 747 byMIICRbak = inb (byMIICR); 748 outb (byMIICRbak & 0x7f, byMIICR); 749 MIIDelay (); 750 751 outb (byMIIIndex, byMIIAD); 752 MIIDelay (); 753 754 outb (inb (byMIICR) | 0x40, byMIICR); 755 756 byMIItemp = inb (byMIICR); 757 byMIItemp = byMIItemp & 0x40; 758 759 while (byMIItemp != 0) 760 { 761 byMIItemp = inb (byMIICR); 762 byMIItemp = byMIItemp & 0x40; 763 } 764 MIIDelay (); 765 766 ReturnMII = inw (wMIIDATA); 767 768 outb (byMIIAdrbak, byMIIAD); 769 outb (byMIICRbak, byMIICR); 770 MIIDelay (); 771 772 return (ReturnMII); 773 774 } 775 776 void 777 WriteMII (char byMIISetByte, char byMIISetBit, char byMIIOP, int ioaddr) 778 { 779 int ReadMIItmp; 780 int MIIMask; 781 char byMIIAdrbak; 782 char byMIICRbak; 783 char byMIItemp; 784 785 786 byMIIAdrbak = inb (byMIIAD); 787 788 byMIICRbak = inb (byMIICR); 789 outb (byMIICRbak & 0x7f, byMIICR); 790 MIIDelay (); 791 outb (byMIISetByte, byMIIAD); 792 MIIDelay (); 793 794 outb (inb (byMIICR) | 0x40, byMIICR); 795 796 byMIItemp = inb (byMIICR); 797 byMIItemp = byMIItemp & 0x40; 798 799 while (byMIItemp != 0) 800 { 801 byMIItemp = inb (byMIICR); 802 byMIItemp = byMIItemp & 0x40; 803 } 804 MIIDelay (); 805 806 ReadMIItmp = inw (wMIIDATA); 807 MIIMask = 0x0001; 808 MIIMask = MIIMask << byMIISetBit; 809 810 811 if (byMIIOP == 0) 812 { 813 MIIMask = ~MIIMask; 814 ReadMIItmp = ReadMIItmp & MIIMask; 815 } 816 else 817 { 818 ReadMIItmp = ReadMIItmp | MIIMask; 819 820 } 821 outw (ReadMIItmp, wMIIDATA); 822 MIIDelay (); 823 824 outb (inb (byMIICR) | 0x20, byMIICR); 825 byMIItemp = inb (byMIICR); 826 byMIItemp = byMIItemp & 0x20; 827 828 while (byMIItemp != 0) 829 { 830 byMIItemp = inb (byMIICR); 831 byMIItemp = byMIItemp & 0x20; 832 } 833 MIIDelay (); 834 835 outb (byMIIAdrbak & 0x7f, byMIIAD); 836 outb (byMIICRbak, byMIICR); 837 MIIDelay (); 838 839 } 840 841 void 842 MIIDelay (void) 843 { 844 int i; 845 for (i = 0; i < 0x7fff; i++) 846 { 847 inb (0x61); 848 inb (0x61); 849 inb (0x61); 850 inb (0x61); 851 } 852 } 853 854 /* Offsets to the device registers. */ 855 enum register_offsets { 856 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08, 857 IntrStatus=0x0C, IntrEnable=0x0E, 858 MulticastFilter0=0x10, MulticastFilter1=0x14, 859 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54, 860 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, 861 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74, 862 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B, 863 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81, 864 StickyHW=0x83, IntrStatus2=0x84, WOLcrClr=0xA4, WOLcgClr=0xA7, 865 PwrcsrClr=0xAC, 866 }; 867 868 /* Bits in the interrupt status/mask registers. */ 869 enum intr_status_bits { 870 IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020, 871 IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210, 872 IntrPCIErr=0x0040, 873 IntrStatsMax=0x0080, IntrRxEarly=0x0100, 874 IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000, 875 IntrTxAborted=0x2000, IntrLinkChange=0x4000, 876 IntrRxWakeUp=0x8000, 877 IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260, 878 IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */ 879 IntrTxErrSummary=0x082218, 880 }; 881 #define DEFAULT_INTR (IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow | \ 882 IntrRxDropped | IntrRxNoBuf) 883 884 /*************************************************************************** 885 IRQ - PXE IRQ Handler 886 ***************************************************************************/ 887 void rhine_irq ( struct nic *nic, irq_action_t action ) { 888 struct rhine_private *tp = (struct rhine_private *) nic->priv_data; 889 /* Enable interrupts by setting the interrupt mask. */ 890 unsigned int intr_status; 891 892 switch ( action ) { 893 case DISABLE : 894 case ENABLE : 895 intr_status = inw(nic->ioaddr + IntrStatus); 896 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */ 897 if (tp->chip_id == 0x3065) 898 intr_status |= inb(nic->ioaddr + IntrStatus2) << 16; 899 intr_status = (intr_status & ~DEFAULT_INTR); 900 if ( action == ENABLE ) 901 intr_status = intr_status | DEFAULT_INTR; 902 outw(intr_status, nic->ioaddr + IntrEnable); 903 break; 904 case FORCE : 905 outw(0x0010, nic->ioaddr + 0x84); 906 break; 907 } 908 } 909 910 static int 911 rhine_probe (struct dev *dev, struct pci_device *pci) 912 { 913 struct nic *nic = (struct nic *)dev; 914 struct rhine_private *tp = &rhine; 915 if (!pci->ioaddr) 916 return 0; 917 rhine_probe1 (nic, pci->ioaddr, pci->dev_id, -1); 918 919 adjust_pci_device(pci); 920 rhine_reset (nic); 921 922 dev->disable = rhine_disable; 923 nic->poll = rhine_poll; 924 nic->transmit = rhine_transmit; 925 nic->irqno = pci->irq; 926 nic->irq = rhine_irq; 927 nic->ioaddr = tp->ioaddr; 928 929 930 return 1; 931 } 932 933 static void set_rx_mode(struct nic *nic __unused) { 934 struct rhine_private *tp = (struct rhine_private *) nic->priv_data; 935 unsigned char rx_mode; 936 int ioaddr = tp->ioaddr; 937 938 /* ! IFF_PROMISC */ 939 outl(0xffffffff, byMAR0); 940 outl(0xffffffff, byMAR4); 941 rx_mode = 0x0C; 942 943 outb(0x60 /* thresh */ | rx_mode, byRCR ); 944 } 945 946 static void 947 rhine_probe1 (struct nic *nic, int ioaddr, int chip_id, int options) 948 { 949 struct rhine_private *tp; 950 static int did_version = 0; /* Already printed version info. */ 951 int i; 952 unsigned int timeout; 953 int FDXFlag; 954 int byMIIvalue, LineSpeed, MIICRbak; 955 956 if (rhine_debug > 0 && did_version++ == 0) 957 printf (version); 958 959 /* D-Link provided reset code (with comment additions) */ 960 if((chip_id != 0x3043) && (chip_id != 0x6100)) { 961 unsigned char byOrgValue; 962 963 if(rhine_debug > 0) 964 printf("Enabling Sticky Bit Workaround for Chip_id: 0x%hX\n" 965 , chip_id); 966 /* clear sticky bit before reset & read ethernet address */ 967 byOrgValue = inb(bySTICKHW); 968 byOrgValue = byOrgValue & 0xFC; 969 outb(byOrgValue, bySTICKHW); 970 971 /* (bits written are cleared?) */ 972 /* disable force PME-enable */ 973 outb(0x80, byWOLcgClr); 974 /* disable power-event config bit */ 975 outb(0xFF, byWOLcrClr); 976 /* clear power status (undocumented in vt6102 docs?) */ 977 outb(0xFF, byPwrcsrClr); 978 979 } 980 981 /* Perhaps this should be read from the EEPROM? */ 982 for (i = 0; i < ETH_ALEN; i++) 983 nic->node_addr[i] = inb (byPAR0 + i); 984 printf ("IO address %hX Ethernet Address: %!\n", ioaddr, nic->node_addr); 985 986 /* restart MII auto-negotiation */ 987 WriteMII (0, 9, 1, ioaddr); 988 printf ("Analyzing Media type,this will take several seconds........"); 989 for (i = 0; i < 5; i++) 990 { 991 /* need to wait 1 millisecond - we will round it up to 50-100ms */ 992 timeout = currticks() + 2; 993 for (timeout = currticks() + 2; currticks() < timeout;) 994 /* nothing */; 995 if (ReadMII (1, ioaddr) & 0x0020) 996 break; 997 } 998 printf ("OK\n"); 999 1000 #if 0 1001 /* JJM : for Debug */ 1002 printf("MII : Address %hhX ",inb(ioaddr+0x6c)); 1003 { 1004 unsigned char st1,st2,adv1,adv2,l1,l2; 1005 1006 st1=ReadMII(1,ioaddr)>>8; 1007 st2=ReadMII(1,ioaddr)&0xFF; 1008 adv1=ReadMII(4,ioaddr)>>8; 1009 adv2=ReadMII(4,ioaddr)&0xFF; 1010 l1=ReadMII(5,ioaddr)>>8; 1011 l2=ReadMII(5,ioaddr)&0xFF; 1012 printf(" status 0x%hhX%hhX, advertising 0x%hhX%hhX, link 0x%hhX%hhX\n", st1,st2,adv1,adv2,l1,l2); 1013 } 1014 #endif 1015 1016 1017 /* query MII to know LineSpeed,duplex mode */ 1018 byMIIvalue = inb (ioaddr + 0x6d); 1019 LineSpeed = byMIIvalue & MIISR_SPEED; 1020 if (LineSpeed != 0) //JJM 1021 { 1022 printf ("Linespeed=10Mbs"); 1023 } 1024 else 1025 { 1026 printf ("Linespeed=100Mbs"); 1027 } 1028 1029 FDXFlag = QueryAuto (ioaddr); 1030 if (FDXFlag == 1) 1031 { 1032 printf (" Fullduplex\n"); 1033 outw (CR_FDX, byCR0); 1034 } 1035 else 1036 { 1037 printf (" Halfduplex\n"); 1038 } 1039 1040 1041 /* set MII 10 FULL ON */ 1042 WriteMII (17, 1, 1, ioaddr); 1043 1044 /* turn on MII link change */ 1045 MIICRbak = inb (byMIICR); 1046 outb (MIICRbak & 0x7F, byMIICR); 1047 MIIDelay (); 1048 outb (0x41, byMIIAD); 1049 MIIDelay (); 1050 1051 /* while((inb(byMIIAD)&0x20)==0) ; */ 1052 outb (MIICRbak | 0x80, byMIICR); 1053 1054 nic->priv_data = &rhine; 1055 tp = &rhine; 1056 tp->chip_id = chip_id; 1057 tp->ioaddr = ioaddr; 1058 tp->phys[0] = -1; 1059 1060 /* The lower four bits are the media type. */ 1061 if (options > 0) 1062 { 1063 tp->full_duplex = (options & 16) ? 1 : 0; 1064 tp->default_port = options & 15; 1065 if (tp->default_port) 1066 tp->medialock = 1; 1067 } 1068 return; 1069 } 1070 1071 static void 1072 rhine_disable (struct dev *dev) 1073 { 1074 struct nic *nic = (struct nic *)dev; 1075 struct rhine_private *tp = (struct rhine_private *) nic->priv_data; 1076 int ioaddr = tp->ioaddr; 1077 1078 /* merge reset and disable */ 1079 rhine_reset(nic); 1080 1081 printf ("rhine disable\n"); 1082 /* Switch to loopback mode to avoid hardware races. */ 1083 writeb(0x60 | 0x01, byTCR); 1084 /* Stop the chip's Tx and Rx processes. */ 1085 writew(CR_STOP, byCR0); 1086 } 1087 1088 /************************************************************************** 1089 ETH_RESET - Reset adapter 1090 ***************************************************************************/ 1091 static void 1092 rhine_reset (struct nic *nic) 1093 { 1094 struct rhine_private *tp = (struct rhine_private *) nic->priv_data; 1095 int ioaddr = tp->ioaddr; 1096 int i, j; 1097 int FDXFlag, CRbak; 1098 int rx_ring_tmp, rx_ring_tmp1; 1099 int tx_ring_tmp, tx_ring_tmp1; 1100 int rx_bufs_tmp, rx_bufs_tmp1; 1101 int tx_bufs_tmp, tx_bufs_tmp1; 1102 1103 static char buf1[RX_RING_SIZE * PKT_BUF_SZ + 32]; 1104 static char buf2[RX_RING_SIZE * PKT_BUF_SZ + 32]; 1105 static char desc1[TX_RING_SIZE * sizeof (struct rhine_tx_desc) + 32]; 1106 static char desc2[TX_RING_SIZE * sizeof (struct rhine_tx_desc) + 32]; 1107 1108 /* printf ("rhine_reset\n"); */ 1109 /* Soft reset the chip. */ 1110 /*outb(CmdReset, ioaddr + ChipCmd); */ 1111 1112 tx_bufs_tmp = (int) buf1; 1113 tx_ring_tmp = (int) desc1; 1114 rx_bufs_tmp = (int) buf2; 1115 rx_ring_tmp = (int) desc2; 1116 1117 /* tune RD TD 32 byte alignment */ 1118 rx_ring_tmp1 = (int) virt_to_bus ((char *) rx_ring_tmp); 1119 j = (rx_ring_tmp1 + 32) & (~0x1f); 1120 /* printf ("txring[%d]", j); */ 1121 tp->rx_ring = (struct rhine_rx_desc *) bus_to_virt (j); 1122 1123 tx_ring_tmp1 = (int) virt_to_bus ((char *) tx_ring_tmp); 1124 j = (tx_ring_tmp1 + 32) & (~0x1f); 1125 tp->tx_ring = (struct rhine_tx_desc *) bus_to_virt (j); 1126 /* printf ("rxring[%X]", j); */ 1127 1128 1129 tx_bufs_tmp1 = (int) virt_to_bus ((char *) tx_bufs_tmp); 1130 j = (int) (tx_bufs_tmp1 + 32) & (~0x1f); 1131 tx_bufs_tmp = (int) bus_to_virt (j); 1132 /* printf ("txb[%X]", j); */ 1133 1134 rx_bufs_tmp1 = (int) virt_to_bus ((char *) rx_bufs_tmp); 1135 j = (int) (rx_bufs_tmp1 + 32) & (~0x1f); 1136 rx_bufs_tmp = (int) bus_to_virt (j); 1137 /* printf ("rxb[%X][%X]", rx_bufs_tmp1, j); */ 1138 1139 for (i = 0; i < RX_RING_SIZE; i++) 1140 { 1141 tp->rx_buffs[i] = (char *) rx_bufs_tmp; 1142 /* printf("r[%X]",tp->rx_buffs[i]); */ 1143 rx_bufs_tmp += 1536; 1144 } 1145 1146 for (i = 0; i < TX_RING_SIZE; i++) 1147 { 1148 tp->tx_buffs[i] = (char *) tx_bufs_tmp; 1149 /* printf("t[%X]",tp->tx_buffs[i]); */ 1150 tx_bufs_tmp += 1536; 1151 } 1152 1153 /* software reset */ 1154 outb (CR1_SFRST, byCR1); 1155 MIIDelay (); 1156 1157 /* printf ("init ring"); */ 1158 rhine_init_ring (nic); 1159 /*write TD RD Descriptor to MAC */ 1160 outl (virt_to_bus (tp->rx_ring), dwCurrentRxDescAddr); 1161 outl (virt_to_bus (tp->tx_ring), dwCurrentTxDescAddr); 1162 1163 /* Setup Multicast */ 1164 set_rx_mode(nic); 1165 1166 /* close IMR */ 1167 outw (0x0000, byIMR0); 1168 1169 /* set TCR RCR threshold */ 1170 outb (0x06, byBCR0); 1171 outb (0x00, byBCR1); 1172 outb (0x2c, byRCR); 1173 outb (0x60, byTCR); 1174 /* Set Fulldupex */ 1175 FDXFlag = QueryAuto (ioaddr); 1176 if (FDXFlag == 1) 1177 { 1178 outb (CFGD_CFDX, byCFGD); 1179 outw (CR_FDX, byCR0); 1180 } 1181 1182 /* KICK NIC to WORK */ 1183 CRbak = inw (byCR0); 1184 CRbak = CRbak & 0xFFFB; /* not CR_STOP */ 1185 outw ((CRbak | CR_STRT | CR_TXON | CR_RXON | CR_DPOLL), byCR0); 1186 1187 /*set IMR to work */ 1188 outw (IMRShadow, byIMR0); 1189 } 1190 /* Beware of PCI posted writes */ 1191 #define IOSYNC do { readb(nic->ioaddr + StationAddr); } while (0) 1192 1193 static int 1194 rhine_poll (struct nic *nic, int retreive) 1195 { 1196 struct rhine_private *tp = (struct rhine_private *) nic->priv_data; 1197 int rxstatus, good = 0;; 1198 1199 if (tp->rx_ring[tp->cur_rx].rx_status.bits.own_bit == 0) 1200 { 1201 unsigned int intr_status; 1202 /* There is a packet ready */ 1203 if(!retreive) 1204 return 1; 1205 1206 intr_status = inw(nic->ioaddr + IntrStatus); 1207 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */ 1208 #if 0 1209 if (tp->chip_id == 0x3065) 1210 intr_status |= inb(nic->ioaddr + IntrStatus2) << 16; 1211 #endif 1212 /* Acknowledge all of the current interrupt sources ASAP. */ 1213 if (intr_status & IntrTxDescRace) 1214 outb(0x08, nic->ioaddr + IntrStatus2); 1215 outw(intr_status & 0xffff, nic->ioaddr + IntrStatus); 1216 IOSYNC; 1217 1218 rxstatus = tp->rx_ring[tp->cur_rx].rx_status.lw; 1219 if ((rxstatus & 0x0300) != 0x0300) 1220 { 1221 printf("rhine_poll: bad status\n"); 1222 } 1223 else if (rxstatus & (RSR_ABNORMAL)) 1224 { 1225 printf ("rxerr[%X]\n", rxstatus); 1226 } 1227 else 1228 good = 1; 1229 1230 if (good) 1231 { 1232 nic->packetlen = tp->rx_ring[tp->cur_rx].rx_status.bits.frame_length; 1233 memcpy (nic->packet, tp->rx_buffs[tp->cur_rx], nic->packetlen); 1234 /* printf ("Packet RXed\n"); */ 1235 } 1236 tp->rx_ring[tp->cur_rx].rx_status.bits.own_bit = 1; 1237 tp->cur_rx++; 1238 tp->cur_rx = tp->cur_rx % RX_RING_SIZE; 1239 } 1240 /* Acknowledge all of the current interrupt sources ASAP. */ 1241 outw(DEFAULT_INTR & ~IntrRxDone, nic->ioaddr + IntrStatus); 1242 1243 IOSYNC; 1244 1245 return good; 1246 } 1247 1248 static void 1249 rhine_transmit (struct nic *nic, 1250 const char *d, unsigned int t, unsigned int s, const char *p) 1251 { 1252 struct rhine_private *tp = (struct rhine_private *) nic->priv_data; 1253 int ioaddr = tp->ioaddr; 1254 int entry; 1255 unsigned char CR1bak; 1256 1257 /*printf ("rhine_transmit\n"); */ 1258 /* setup ethernet header */ 1259 1260 1261 /* Calculate the next Tx descriptor entry. */ 1262 entry = tp->cur_tx % TX_RING_SIZE; 1263 1264 memcpy (tp->tx_buffs[entry], d, ETH_ALEN); /* dst */ 1265 memcpy (tp->tx_buffs[entry] + ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */ 1266 *((char *) tp->tx_buffs[entry] + 12) = t >> 8; /* type */ 1267 *((char *) tp->tx_buffs[entry] + 13) = t; 1268 memcpy (tp->tx_buffs[entry] + ETH_HLEN, p, s); 1269 s += ETH_HLEN; 1270 while (s < ETH_ZLEN) 1271 *((char *) tp->tx_buffs[entry] + ETH_HLEN + (s++)) = 0; 1272 1273 tp->tx_ring[entry].tx_ctrl.bits.tx_buf_size = s; 1274 1275 tp->tx_ring[entry].tx_status.bits.own_bit = 1; 1276 1277 1278 CR1bak = inb (byCR1); 1279 1280 CR1bak = CR1bak | CR1_TDMD1; 1281 /*printf("tdsw=[%X]",tp->tx_ring[entry].tx_status.lw); */ 1282 /*printf("tdcw=[%X]",tp->tx_ring[entry].tx_ctrl.lw); */ 1283 /*printf("tdbuf1=[%X]",tp->tx_ring[entry].buf_addr_1); */ 1284 /*printf("tdbuf2=[%X]",tp->tx_ring[entry].buf_addr_2); */ 1285 /*printf("td1=[%X]",inl(dwCurrentTDSE0)); */ 1286 /*printf("td2=[%X]",inl(dwCurrentTDSE1)); */ 1287 /*printf("td3=[%X]",inl(dwCurrentTDSE2)); */ 1288 /*printf("td4=[%X]",inl(dwCurrentTDSE3)); */ 1289 1290 outb (CR1bak, byCR1); 1291 /* Wait until transmit is finished */ 1292 while (tp->tx_ring[entry].tx_status.bits.own_bit != 0) 1293 ; 1294 tp->cur_tx++; 1295 1296 /*outw(IMRShadow,byIMR0); */ 1297 /*dev_kfree_skb(tp->tx_skbuff[entry], FREE_WRITE); */ 1298 /*tp->tx_skbuff[entry] = 0; */ 1299 } 1300 1301 static struct pci_id rhine_nics[] = { 1302 PCI_ROM(0x1106, 0x3065, "dlink-530tx", "VIA 6102"), 1303 PCI_ROM(0x1106, 0x3106, "via-rhine-6105", "VIA 6105"), 1304 PCI_ROM(0x1106, 0x3043, "dlink-530tx-old", "VIA 3043"), /* Rhine-I 86c100a */ 1305 PCI_ROM(0x1106, 0x3053, "via6105m", "VIA 6105M"), 1306 PCI_ROM(0x1106, 0x6100, "via-rhine-old", "VIA 86C100A"), /* Rhine-II */ 1307 }; 1308 1309 struct pci_driver rhine_driver = { 1310 .type = NIC_DRIVER, 1311 .name = "VIA 86C100", 1312 .probe = rhine_probe, 1313 .ids = rhine_nics, 1314 .id_count = sizeof(rhine_nics)/sizeof(rhine_nics[0]), 1315 .class = 0, 1316 }; 1317 1318 /* EOF via-rhine.c */ 1319