xref: /titanic_51/usr/src/cmd/fm/dicts/SUN4V.dict (revision 88447a05f537aabe9a1bc3d5313f22581ec992a7)
1#
2# Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
3# Use is subject to license terms.
4#
5# CDDL HEADER START
6#
7# The contents of this file are subject to the terms of the
8# Common Development and Distribution License (the "License").
9# You may not use this file except in compliance with the License.
10#
11# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
12# or http://www.opensolaris.org/os/licensing.
13# See the License for the specific language governing permissions
14# and limitations under the License.
15#
16# When distributing Covered Code, include this CDDL HEADER in each
17# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
18# If applicable, add the following below this CDDL HEADER, with the
19# fields enclosed by brackets "[]" replaced with your own identifying
20# information: Portions Copyright [yyyy] [name of copyright owner]
21#
22# CDDL HEADER END
23#
24# DO NOT EDIT -- this file is generated by the Event Registry.
25#
26
27FMDICT: name=SUN4V version=1 maxkey=3 dictid=0x3456
28
29fault.cpu.ultraSPARC-T1.ireg=1
30fault.cpu.ultraSPARC-T1.freg=2
31fault.cpu.ultraSPARC-T1.itlb=3
32fault.cpu.ultraSPARC-T1.dtlb=4
33fault.cpu.ultraSPARC-T1.icache=5
34fault.cpu.ultraSPARC-T1.dcache=6
35fault.cpu.ultraSPARC-T1.mau=7
36fault.cpu.ultraSPARC-T1.l2cachedata=8
37fault.cpu.ultraSPARC-T1.l2cachetag=9
38fault.cpu.ultraSPARC-T1.l2cachectl=10
39fault.memory.page=11
40fault.memory.dimm=12
41fault.memory.bank=13
42fault.memory.link-c=14
43fault.cpu.ultraSPARC-T2.ireg=15
44fault.cpu.ultraSPARC-T2.freg=16
45fault.cpu.ultraSPARC-T2.misc_reg=17
46fault.cpu.ultraSPARC-T2.itlb=18
47fault.cpu.ultraSPARC-T2.dtlb=19
48fault.cpu.ultraSPARC-T2.icache=20
49fault.cpu.ultraSPARC-T2.dcache=21
50fault.cpu.ultraSPARC-T2.mau=22
51fault.cpu.ultraSPARC-T2.l2data-c=23
52fault.cpu.ultraSPARC-T2.l2cachetag=24
53fault.cpu.ultraSPARC-T2.l2cachectl=25
54fault.memory.link-u=26
55fault.cpu.ultraSPARC-T2.l2data-u=27
56fault.cpu.ultraSPARC-T1.l2data-c=28
57fault.cpu.ultraSPARC-T1.l2data-u=29
58fault.memory.datapath=30
59fault.io.n2.ncu=31
60fault.io.n2.dmu=32
61fault.io.n2.niu=33
62fault.io.n2.siu=34
63fault.io.n2.soc=35
64fault.io.n2.crossbar=36
65fault.io.fire.fw-epkt fault.io.fire.sw-epkt fault.io.fire.sw-fw-mismatch=37
66fault.io.vf.ncx=38
67fault.memory.link-f=39
68fault.cpu.ultraSPARC-T2plus.ireg=40
69fault.cpu.ultraSPARC-T2plus.freg=41
70fault.cpu.ultraSPARC-T2plus.misc_reg=42
71fault.cpu.ultraSPARC-T2plus.itlb=43
72fault.cpu.ultraSPARC-T2plus.dtlb=44
73fault.cpu.ultraSPARC-T2plus.icache=45
74fault.cpu.ultraSPARC-T2plus.dcache=46
75fault.cpu.ultraSPARC-T2plus.mau=47
76fault.cpu.ultraSPARC-T2plus.l2data-c=48
77fault.cpu.ultraSPARC-T2plus.l2cachetag=49
78fault.cpu.ultraSPARC-T2plus.l2cachectl=50
79fault.cpu.ultraSPARC-T2plus.l2data-u=51
80fault.cpu.ultraSPARC-T2plus.lfu-f=52
81fault.cpu.ultraSPARC-T2plus.lfu-p=53
82fault.cpu.ultraSPARC-T2plus.lfu-u=54
83fault.asic.ultraSPARC-T2plus.interconnect.opu-u=55
84fault.asic.ultraSPARC-T2plus.interconnect.opu-c=56
85fault.cpu.ultraSPARC-T2plus.chip=57
86fault.asic.ultraSPARC-T2plus.interconnect.lfu-c fault.cpu.ultraSPARC-T2plus.chip=58
87fault.asic.ultraSPARC-T2plus.interconnect.lfu-f fault.cpu.ultraSPARC-T2plus.chip=59
88fault.asic.ultraSPARC-T2plus.interconnect.lfu-u fault.cpu.ultraSPARC-T2plus.chip=60
89fault.asic.ultraSPARC-T2plus.interconnect.lfu-u=61
90fault.asic.ultraSPARC-T2plus.interconnect.gpd-u fault.cpu.ultraSPARC-T2plus.chip=62
91fault.asic.ultraSPARC-T2plus.interconnect.gpd-c fault.cpu.ultraSPARC-T2plus.chip=63
92fault.asic.ultraSPARC-T2plus.interconnect.gpd-c=64
93fault.asic.fpga fault.asic.ultraSPARC-T2plus.interconnect.gpd-c=65
94fault.asic.ultraSPARC-T2plus.interconnect.asu=66
95fault.memory.dimm-page-retires-excessive=67
96fault.memory.dimm-ue-imminent=68
97fault.memory.dram-ue-imminent=69
98fault.cpu.generic-sparc.strand=70
99fault.cpu.generic-sparc.strand-nr=71
100fault.cpu.generic-sparc.strand-uc=72
101fault.cpu.generic-sparc.strand-uc-nr=73
102fault.cpu.generic-sparc.core=74
103fault.cpu.generic-sparc.core-nr=75
104fault.cpu.generic-sparc.core-uc=76
105fault.cpu.generic-sparc.core-uc-nr=77
106fault.cpu.generic-sparc.chip=78
107fault.cpu.generic-sparc.chip-nr=79
108fault.cpu.generic-sparc.chip-uc=80
109fault.cpu.generic-sparc.chip-uc-nr=81
110fault.cpu.generic-sparc.c2c=82
111fault.cpu.generic-sparc.c2c-failover=83
112fault.cpu.generic-sparc.c2c-uc=84
113fault.memory.memlink=85
114fault.memory.memlink-failover=86
115fault.memory.memlink-uc=87
116defect.fw.generic-sparc.addr-oob=88
117defect.fw.generic-sparc.erpt-gen=89
118fault.cpu.generic-sparc.bootbus=90
119