1# 2# Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3# Use is subject to license terms. 4# 5# CDDL HEADER START 6# 7# The contents of this file are subject to the terms of the 8# Common Development and Distribution License (the "License"). 9# You may not use this file except in compliance with the License. 10# 11# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 12# or http://www.opensolaris.org/os/licensing. 13# See the License for the specific language governing permissions 14# and limitations under the License. 15# 16# When distributing Covered Code, include this CDDL HEADER in each 17# file and include the License file at usr/src/OPENSOLARIS.LICENSE. 18# If applicable, add the following below this CDDL HEADER, with the 19# fields enclosed by brackets "[]" replaced with your own identifying 20# information: Portions Copyright [yyyy] [name of copyright owner] 21# 22# CDDL HEADER END 23# 24# 25# DO NOT EDIT -- this file is generated by the Event Registry. 26# 27 28FMDICT: name=SUN4V version=1 maxkey=3 dictid=0x3456 29 30fault.cpu.ultraSPARC-T1.ireg=1 31fault.cpu.ultraSPARC-T1.freg=2 32fault.cpu.ultraSPARC-T1.itlb=3 33fault.cpu.ultraSPARC-T1.dtlb=4 34fault.cpu.ultraSPARC-T1.icache=5 35fault.cpu.ultraSPARC-T1.dcache=6 36fault.cpu.ultraSPARC-T1.mau=7 37fault.cpu.ultraSPARC-T1.l2cachedata=8 38fault.cpu.ultraSPARC-T1.l2cachetag=9 39fault.cpu.ultraSPARC-T1.l2cachectl=10 40fault.memory.page=11 41fault.memory.dimm=12 42fault.memory.bank=13 43fault.memory.link-c=14 44fault.cpu.ultraSPARC-T2.ireg=15 45fault.cpu.ultraSPARC-T2.freg=16 46fault.cpu.ultraSPARC-T2.misc_reg=17 47fault.cpu.ultraSPARC-T2.itlb=18 48fault.cpu.ultraSPARC-T2.dtlb=19 49fault.cpu.ultraSPARC-T2.icache=20 50fault.cpu.ultraSPARC-T2.dcache=21 51fault.cpu.ultraSPARC-T2.mau=22 52fault.cpu.ultraSPARC-T2.l2data-c=23 53fault.cpu.ultraSPARC-T2.l2cachetag=24 54fault.cpu.ultraSPARC-T2.l2cachectl=25 55fault.memory.link-u=26 56fault.cpu.ultraSPARC-T2.l2data-u=27 57fault.cpu.ultraSPARC-T1.l2data-c=28 58fault.cpu.ultraSPARC-T1.l2data-u=29 59fault.memory.datapath=30 60fault.io.n2.ncu=31 61fault.io.n2.dmu=32 62fault.io.n2.niu=33 63fault.io.n2.siu=34 64fault.io.n2.soc=35 65fault.io.n2.crossbar=36 66fault.io.fire.fw-epkt fault.io.fire.sw-epkt fault.io.fire.sw-fw-mismatch=37 67fault.io.vf.ncx=38 68fault.memory.link-f=39 69fault.cpu.ultraSPARC-T2plus.ireg=40 70fault.cpu.ultraSPARC-T2plus.freg=41 71fault.cpu.ultraSPARC-T2plus.misc_reg=42 72fault.cpu.ultraSPARC-T2plus.itlb=43 73fault.cpu.ultraSPARC-T2plus.dtlb=44 74fault.cpu.ultraSPARC-T2plus.icache=45 75fault.cpu.ultraSPARC-T2plus.dcache=46 76fault.cpu.ultraSPARC-T2plus.mau=47 77fault.cpu.ultraSPARC-T2plus.l2data-c=48 78fault.cpu.ultraSPARC-T2plus.l2cachetag=49 79fault.cpu.ultraSPARC-T2plus.l2cachectl=50 80fault.cpu.ultraSPARC-T2plus.l2data-u=51 81fault.cpu.ultraSPARC-T2plus.lfu-f=52 82fault.cpu.ultraSPARC-T2plus.lfu-p=53 83fault.cpu.ultraSPARC-T2plus.lfu-u=54 84fault.asic.ultraSPARC-T2plus.interconnect.opu-u=55 85fault.asic.ultraSPARC-T2plus.interconnect.opu-c=56 86fault.cpu.ultraSPARC-T2plus.chip=57 87fault.asic.ultraSPARC-T2plus.interconnect.lfu-c fault.cpu.ultraSPARC-T2plus.chip=58 88fault.asic.ultraSPARC-T2plus.interconnect.lfu-f fault.cpu.ultraSPARC-T2plus.chip=59 89fault.asic.ultraSPARC-T2plus.interconnect.lfu-u fault.cpu.ultraSPARC-T2plus.chip=60 90fault.asic.ultraSPARC-T2plus.interconnect.lfu-u=61 91fault.asic.ultraSPARC-T2plus.interconnect.gpd-u fault.cpu.ultraSPARC-T2plus.chip=62 92fault.asic.ultraSPARC-T2plus.interconnect.gpd-c fault.cpu.ultraSPARC-T2plus.chip=63 93fault.asic.ultraSPARC-T2plus.interconnect.gpd-c=64 94fault.asic.fpga fault.asic.ultraSPARC-T2plus.interconnect.gpd-c=65 95fault.asic.ultraSPARC-T2plus.interconnect.asu=66 96fault.memory.dimm-page-retires-excessive=67 97fault.memory.dimm-ue-imminent=68 98fault.memory.dram-ue-imminent=69 99