1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/sysmacros.h> 30 #include <sys/ddi.h> 31 #include <sys/async.h> 32 #include <sys/sunddi.h> 33 #include <sys/ddifm.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/vmem.h> 36 #include <sys/intr.h> 37 #include <sys/ivintr.h> 38 #include <sys/errno.h> 39 #include <sys/hypervisor_api.h> 40 #include <sys/hsvc.h> 41 #include <px_obj.h> 42 #include <sys/machsystm.h> 43 #include <sys/hotplug/pci/pcihp.h> 44 #include "px_lib4v.h" 45 #include "px_err.h" 46 47 /* mask for the ranges property in calculating the real PFN range */ 48 uint_t px_ranges_phi_mask = ((1 << 28) -1); 49 50 /* 51 * Hypervisor VPCI services information for the px nexus driver. 52 */ 53 static uint64_t px_vpci_min_ver; /* Negotiated VPCI API minor version */ 54 static uint_t px_vpci_users = 0; /* VPCI API users */ 55 56 static hsvc_info_t px_hsvc = { 57 HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER, 58 PX_VPCI_MINOR_VER, "PX" 59 }; 60 61 int 62 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 63 { 64 px_nexus_regspec_t *rp; 65 uint_t reglen; 66 int ret; 67 68 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 69 70 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 71 "reg", (uchar_t **)&rp, ®len); 72 if (ret != DDI_PROP_SUCCESS) { 73 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 74 return (DDI_FAILURE); 75 } 76 77 /* 78 * Initilize device handle. The device handle uniquely identifies 79 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 80 * of the first entry of the SUN4V device's "reg" property as 81 * defined by the SUN4V Bus Binding to Open Firmware. 82 */ 83 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 84 ddi_prop_free(rp); 85 86 /* 87 * hotplug implementation requires this property to be associated with 88 * any indirect PCI config access services 89 */ 90 (void) ddi_prop_update_int(makedevice(ddi_driver_major(dip), 91 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 92 PCI_BUS_CONF_MAP_PROP, 1); 93 94 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 95 96 /* 97 * Negotiate the API version for VPCI hypervisor services. 98 */ 99 if (px_vpci_users++) 100 return (DDI_SUCCESS); 101 102 if ((ret = hsvc_register(&px_hsvc, &px_vpci_min_ver)) != 0) { 103 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 104 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 105 px_hsvc.hsvc_modname, px_hsvc.hsvc_group, 106 px_hsvc.hsvc_major, px_hsvc.hsvc_minor, ret); 107 108 return (DDI_FAILURE); 109 } 110 111 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " 112 "major 0x%lx minor 0x%lx\n", px_hsvc.hsvc_major, px_vpci_min_ver); 113 114 return (DDI_SUCCESS); 115 } 116 117 /*ARGSUSED*/ 118 int 119 px_lib_dev_fini(dev_info_t *dip) 120 { 121 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 122 123 (void) ddi_prop_remove(makedevice(ddi_driver_major(dip), 124 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 125 PCI_BUS_CONF_MAP_PROP); 126 127 if (--px_vpci_users == 0) 128 (void) hsvc_unregister(&px_hsvc); 129 130 return (DDI_SUCCESS); 131 } 132 133 /*ARGSUSED*/ 134 int 135 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 136 sysino_t *sysino) 137 { 138 uint64_t ret; 139 140 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 141 "devino 0x%x\n", dip, devino); 142 143 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 144 devino, sysino)) != H_EOK) { 145 DBG(DBG_LIB_INT, dip, 146 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 147 return (DDI_FAILURE); 148 } 149 150 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 151 *sysino); 152 153 return (DDI_SUCCESS); 154 } 155 156 /*ARGSUSED*/ 157 int 158 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 159 intr_valid_state_t *intr_valid_state) 160 { 161 uint64_t ret; 162 163 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 164 dip, sysino); 165 166 if ((ret = hvio_intr_getvalid(sysino, 167 (int *)intr_valid_state)) != H_EOK) { 168 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 169 ret); 170 return (DDI_FAILURE); 171 } 172 173 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 174 *intr_valid_state); 175 176 return (DDI_SUCCESS); 177 } 178 179 /*ARGSUSED*/ 180 int 181 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 182 intr_valid_state_t intr_valid_state) 183 { 184 uint64_t ret; 185 186 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 187 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 188 189 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 190 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 191 ret); 192 return (DDI_FAILURE); 193 } 194 195 return (DDI_SUCCESS); 196 } 197 198 /*ARGSUSED*/ 199 int 200 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 201 intr_state_t *intr_state) 202 { 203 uint64_t ret; 204 205 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 206 dip, sysino); 207 208 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 209 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 210 ret); 211 return (DDI_FAILURE); 212 } 213 214 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 215 *intr_state); 216 217 return (DDI_SUCCESS); 218 } 219 220 /*ARGSUSED*/ 221 int 222 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 223 intr_state_t intr_state) 224 { 225 uint64_t ret; 226 227 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 228 "intr_state 0x%x\n", dip, sysino, intr_state); 229 230 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 231 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 232 ret); 233 return (DDI_FAILURE); 234 } 235 236 return (DDI_SUCCESS); 237 } 238 239 /*ARGSUSED*/ 240 int 241 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 242 { 243 uint64_t ret; 244 245 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 246 dip, sysino); 247 248 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 249 DBG(DBG_LIB_INT, dip, 250 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 251 return (DDI_FAILURE); 252 } 253 254 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 255 256 return (DDI_SUCCESS); 257 } 258 259 /*ARGSUSED*/ 260 int 261 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 262 { 263 uint64_t ret; 264 265 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 266 "cpuid 0x%x\n", dip, sysino, cpuid); 267 268 if ((ret = hvio_intr_settarget(sysino, cpuid)) != H_EOK) { 269 DBG(DBG_LIB_INT, dip, 270 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 271 return (DDI_FAILURE); 272 } 273 274 return (DDI_SUCCESS); 275 } 276 277 /*ARGSUSED*/ 278 int 279 px_lib_intr_reset(dev_info_t *dip) 280 { 281 px_t *px_p = DIP_TO_STATE(dip); 282 px_ib_t *ib_p = px_p->px_ib_p; 283 px_ino_t *ino_p; 284 285 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 286 287 mutex_enter(&ib_p->ib_ino_lst_mutex); 288 289 /* Reset all Interrupts */ 290 for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next_p) { 291 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 292 INTR_IDLE_STATE) != DDI_SUCCESS) 293 return (BF_FATAL); 294 } 295 296 mutex_exit(&ib_p->ib_ino_lst_mutex); 297 298 return (BF_NONE); 299 } 300 301 /*ARGSUSED*/ 302 int 303 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 304 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 305 { 306 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 307 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 308 io_page_list_t *pfns, *pfn_p; 309 pages_t ttes_mapped = 0; 310 int i, err = DDI_SUCCESS; 311 312 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 313 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 314 dip, tsbid, pages, attr, addr, pfn_index, flags); 315 316 if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), 317 KM_NOSLEEP)) == NULL) { 318 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 319 return (DDI_FAILURE); 320 } 321 322 for (i = 0; i < pages; i++) 323 pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i)); 324 325 /* 326 * If HV VPCI version is 1.1 and higher, pass BDF, phantom function, 327 * and relaxed ordering attributes. Otherwise, pass only read or write 328 * attribute. 329 */ 330 if (px_vpci_min_ver == PX_VPCI_MINOR_VER_0) 331 attr = attr & (PCI_MAP_ATTR_READ | PCI_MAP_ATTR_WRITE); 332 333 while ((ttes_mapped = pfn_p - pfns) < pages) { 334 uintptr_t ra = va_to_pa(pfn_p); 335 pages_t ttes2map; 336 uint64_t ret; 337 338 ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3; 339 ra = MMU_PTOB(MMU_BTOP(ra)); 340 341 for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map; 342 ttes2map -= ttes_mapped, pfn_p += ttes_mapped) { 343 344 ttes_mapped = 0; 345 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 346 PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), 347 ttes2map, attr, (io_page_list_t *)(ra | 348 ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), 349 &ttes_mapped)) != H_EOK) { 350 DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " 351 "ret 0x%lx\n", ret); 352 353 ttes_mapped = pfn_p - pfns; 354 err = DDI_FAILURE; 355 goto cleanup; 356 } 357 358 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " 359 "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%x " 360 "ra 0x%p ttes_mapped 0x%x\n", tsb_num, 361 tsb_index + (pfn_p - pfns), ttes2map, attr, 362 ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), 363 ttes_mapped); 364 } 365 } 366 367 cleanup: 368 if ((err == DDI_FAILURE) && ttes_mapped) 369 (void) px_lib_iommu_demap(dip, tsbid, ttes_mapped); 370 371 kmem_free(pfns, pages * sizeof (io_page_list_t)); 372 return (err); 373 } 374 375 /*ARGSUSED*/ 376 int 377 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 378 { 379 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 380 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 381 pages_t ttes2demap, ttes_demapped = 0; 382 uint64_t ret; 383 384 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 385 "pages 0x%x\n", dip, tsbid, pages); 386 387 for (ttes2demap = pages; ttes2demap; 388 ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) { 389 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 390 PCI_TSBID(tsb_num, tsb_index), ttes2demap, 391 &ttes_demapped)) != H_EOK) { 392 DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, " 393 "ret 0x%lx\n", ret); 394 395 return (DDI_FAILURE); 396 } 397 398 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x " 399 "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n", 400 tsb_num, tsb_index, ttes2demap, ttes_demapped); 401 } 402 403 return (DDI_SUCCESS); 404 } 405 406 /*ARGSUSED*/ 407 int 408 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 409 r_addr_t *r_addr_p) 410 { 411 uint64_t ret; 412 413 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 414 dip, tsbid); 415 416 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 417 attr_p, r_addr_p)) != H_EOK) { 418 DBG(DBG_LIB_DMA, dip, 419 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 420 421 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 422 } 423 424 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 425 *attr_p, *r_addr_p); 426 427 return (DDI_SUCCESS); 428 } 429 430 /*ARGSUSED*/ 431 uint64_t 432 px_get_rng_parent_hi_mask(px_t *px_p) 433 { 434 return (PX_RANGE_PROP_MASK); 435 } 436 437 /* 438 * Checks dma attributes against system bypass ranges 439 * A sun4v device must be capable of generating the entire 64-bit 440 * address in order to perform bypass DMA. 441 */ 442 /*ARGSUSED*/ 443 int 444 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 445 uint64_t *lo_p, uint64_t *hi_p) 446 { 447 if ((attr_p->dma_attr_addr_lo != 0ull) || 448 (attr_p->dma_attr_addr_hi != UINT64_MAX)) { 449 450 return (DDI_DMA_BADATTR); 451 } 452 453 *lo_p = 0ull; 454 *hi_p = UINT64_MAX; 455 456 return (DDI_SUCCESS); 457 } 458 459 460 /*ARGSUSED*/ 461 int 462 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 463 io_addr_t *io_addr_p) 464 { 465 uint64_t ret; 466 467 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 468 "attr 0x%x\n", dip, ra, attr); 469 470 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 471 attr, io_addr_p)) != H_EOK) { 472 DBG(DBG_LIB_DMA, dip, 473 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 474 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 475 } 476 477 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 478 *io_addr_p); 479 480 return (DDI_SUCCESS); 481 } 482 483 /*ARGSUSED*/ 484 int 485 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 486 off_t off, size_t len, uint_t cache_flags) 487 { 488 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 489 uint64_t sync_dir; 490 size_t bytes_synced; 491 int end, idx; 492 off_t pg_off; 493 devhandle_t hdl = DIP_TO_HANDLE(dip); /* need to cache hdl */ 494 495 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 496 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 497 dip, rdip, handle, off, len, cache_flags); 498 499 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 500 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 501 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 502 return (DDI_FAILURE); 503 } 504 505 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 506 return (DDI_SUCCESS); 507 508 if (!len) 509 len = mp->dmai_size; 510 511 if (mp->dmai_rflags & DDI_DMA_READ) 512 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 513 else 514 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 515 516 off += mp->dmai_offset; 517 pg_off = off & MMU_PAGEOFFSET; 518 519 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: page offset %x size %x\n", 520 pg_off, len); 521 522 /* sync on page basis */ 523 end = MMU_BTOPR(off + len - 1); 524 for (idx = MMU_BTOP(off); idx < end; idx++, 525 len -= bytes_synced, pg_off = 0) { 526 size_t bytes_to_sync = bytes_to_sync = 527 MIN(len, MMU_PAGESIZE - pg_off); 528 529 if (hvio_dma_sync(hdl, MMU_PTOB(PX_GET_MP_PFN(mp, idx)) + 530 pg_off, bytes_to_sync, sync_dir, &bytes_synced) != H_EOK) 531 break; 532 533 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: Called hvio_dma_sync " 534 "ra = %p bytes to sync = %x bytes synced %x\n", 535 MMU_PTOB(PX_GET_MP_PFN(mp, idx)) + pg_off, bytes_to_sync, 536 bytes_synced); 537 538 if (bytes_to_sync != bytes_synced) 539 break; 540 } 541 542 return (len ? DDI_FAILURE : DDI_SUCCESS); 543 } 544 545 546 /* 547 * MSIQ Functions: 548 */ 549 550 /*ARGSUSED*/ 551 int 552 px_lib_msiq_init(dev_info_t *dip) 553 { 554 px_t *px_p = DIP_TO_STATE(dip); 555 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 556 r_addr_t ra; 557 size_t msiq_size; 558 uint_t rec_cnt; 559 int i, err = DDI_SUCCESS; 560 uint64_t ret; 561 562 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 563 564 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 565 566 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 567 ra = (r_addr_t)va_to_pa((caddr_t)msiq_state_p->msiq_buf_p + 568 (i * msiq_size)); 569 570 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 571 (i + msiq_state_p->msiq_1st_msiq_id), 572 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 573 DBG(DBG_LIB_MSIQ, dip, 574 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 575 err = DDI_FAILURE; 576 break; 577 } 578 579 if ((err = px_lib_msiq_info(dip, 580 (i + msiq_state_p->msiq_1st_msiq_id), 581 &ra, &rec_cnt)) != DDI_SUCCESS) { 582 DBG(DBG_LIB_MSIQ, dip, 583 "px_lib_msiq_info failed, ret 0x%x\n", err); 584 err = DDI_FAILURE; 585 break; 586 } 587 588 DBG(DBG_LIB_MSIQ, dip, 589 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 590 } 591 592 return (err); 593 } 594 595 /*ARGSUSED*/ 596 int 597 px_lib_msiq_fini(dev_info_t *dip) 598 { 599 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 600 601 return (DDI_SUCCESS); 602 } 603 604 /*ARGSUSED*/ 605 int 606 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 607 uint_t *msiq_rec_cnt_p) 608 { 609 uint64_t ret; 610 611 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 612 dip, msiq_id); 613 614 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 615 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 616 DBG(DBG_LIB_MSIQ, dip, 617 "hvio_msiq_info failed, ret 0x%lx\n", ret); 618 return (DDI_FAILURE); 619 } 620 621 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 622 ra_p, *msiq_rec_cnt_p); 623 624 return (DDI_SUCCESS); 625 } 626 627 /*ARGSUSED*/ 628 int 629 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 630 pci_msiq_valid_state_t *msiq_valid_state) 631 { 632 uint64_t ret; 633 634 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 635 dip, msiq_id); 636 637 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 638 msiq_id, msiq_valid_state)) != H_EOK) { 639 DBG(DBG_LIB_MSIQ, dip, 640 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 641 return (DDI_FAILURE); 642 } 643 644 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 645 *msiq_valid_state); 646 647 return (DDI_SUCCESS); 648 } 649 650 /*ARGSUSED*/ 651 int 652 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 653 pci_msiq_valid_state_t msiq_valid_state) 654 { 655 uint64_t ret; 656 657 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 658 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 659 660 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 661 msiq_id, msiq_valid_state)) != H_EOK) { 662 DBG(DBG_LIB_MSIQ, dip, 663 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 664 return (DDI_FAILURE); 665 } 666 667 return (DDI_SUCCESS); 668 } 669 670 /*ARGSUSED*/ 671 int 672 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 673 pci_msiq_state_t *msiq_state) 674 { 675 uint64_t ret; 676 677 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 678 dip, msiq_id); 679 680 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 681 msiq_id, msiq_state)) != H_EOK) { 682 DBG(DBG_LIB_MSIQ, dip, 683 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 684 return (DDI_FAILURE); 685 } 686 687 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 688 *msiq_state); 689 690 return (DDI_SUCCESS); 691 } 692 693 /*ARGSUSED*/ 694 int 695 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 696 pci_msiq_state_t msiq_state) 697 { 698 uint64_t ret; 699 700 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 701 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 702 703 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 704 msiq_id, msiq_state)) != H_EOK) { 705 DBG(DBG_LIB_MSIQ, dip, 706 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 707 return (DDI_FAILURE); 708 } 709 710 return (DDI_SUCCESS); 711 } 712 713 /*ARGSUSED*/ 714 int 715 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 716 msiqhead_t *msiq_head_p) 717 { 718 uint64_t ret; 719 720 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 721 dip, msiq_id); 722 723 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 724 msiq_id, msiq_head_p)) != H_EOK) { 725 DBG(DBG_LIB_MSIQ, dip, 726 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 727 return (DDI_FAILURE); 728 } 729 730 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 731 732 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 733 *msiq_head_p); 734 735 return (DDI_SUCCESS); 736 } 737 738 /*ARGSUSED*/ 739 int 740 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 741 msiqhead_t msiq_head) 742 { 743 uint64_t ret; 744 745 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 746 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 747 748 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 749 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 750 DBG(DBG_LIB_MSIQ, dip, 751 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 752 return (DDI_FAILURE); 753 } 754 755 return (DDI_SUCCESS); 756 } 757 758 /*ARGSUSED*/ 759 int 760 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 761 msiqtail_t *msiq_tail_p) 762 { 763 uint64_t ret; 764 765 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 766 dip, msiq_id); 767 768 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 769 msiq_id, msiq_tail_p)) != H_EOK) { 770 DBG(DBG_LIB_MSIQ, dip, 771 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 772 return (DDI_FAILURE); 773 } 774 775 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 776 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 777 *msiq_tail_p); 778 779 return (DDI_SUCCESS); 780 } 781 782 /*ARGSUSED*/ 783 void 784 px_lib_get_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p, 785 msiq_rec_t *msiq_rec_p) 786 { 787 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 788 789 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 790 791 if (!curr_msiq_rec_p->msiq_rec_type) { 792 /* Set msiq_rec_type to zero */ 793 msiq_rec_p->msiq_rec_type = 0; 794 795 return; 796 } 797 798 *msiq_rec_p = *curr_msiq_rec_p; 799 } 800 801 /*ARGSUSED*/ 802 void 803 px_lib_clr_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p) 804 { 805 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 806 807 DBG(DBG_LIB_MSIQ, dip, "px_lib_clr_msiq_rec: dip 0x%p\n", dip); 808 809 /* Zero out msiq_rec_type field */ 810 curr_msiq_rec_p->msiq_rec_type = 0; 811 } 812 813 /* 814 * MSI Functions: 815 */ 816 817 /*ARGSUSED*/ 818 int 819 px_lib_msi_init(dev_info_t *dip) 820 { 821 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 822 823 /* Noop */ 824 return (DDI_SUCCESS); 825 } 826 827 /*ARGSUSED*/ 828 int 829 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 830 msiqid_t *msiq_id) 831 { 832 uint64_t ret; 833 834 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 835 dip, msi_num); 836 837 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 838 msi_num, msiq_id)) != H_EOK) { 839 DBG(DBG_LIB_MSI, dip, 840 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 841 return (DDI_FAILURE); 842 } 843 844 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 845 *msiq_id); 846 847 return (DDI_SUCCESS); 848 } 849 850 /*ARGSUSED*/ 851 int 852 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 853 msiqid_t msiq_id, msi_type_t msitype) 854 { 855 uint64_t ret; 856 857 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 858 "msq_id 0x%x\n", dip, msi_num, msiq_id); 859 860 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 861 msi_num, msiq_id, msitype)) != H_EOK) { 862 DBG(DBG_LIB_MSI, dip, 863 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 864 return (DDI_FAILURE); 865 } 866 867 return (DDI_SUCCESS); 868 } 869 870 /*ARGSUSED*/ 871 int 872 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 873 pci_msi_valid_state_t *msi_valid_state) 874 { 875 uint64_t ret; 876 877 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 878 dip, msi_num); 879 880 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 881 msi_num, msi_valid_state)) != H_EOK) { 882 DBG(DBG_LIB_MSI, dip, 883 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 884 return (DDI_FAILURE); 885 } 886 887 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 888 *msi_valid_state); 889 890 return (DDI_SUCCESS); 891 } 892 893 /*ARGSUSED*/ 894 int 895 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 896 pci_msi_valid_state_t msi_valid_state) 897 { 898 uint64_t ret; 899 900 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 901 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 902 903 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 904 msi_num, msi_valid_state)) != H_EOK) { 905 DBG(DBG_LIB_MSI, dip, 906 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 907 return (DDI_FAILURE); 908 } 909 910 return (DDI_SUCCESS); 911 } 912 913 /*ARGSUSED*/ 914 int 915 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 916 pci_msi_state_t *msi_state) 917 { 918 uint64_t ret; 919 920 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 921 dip, msi_num); 922 923 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 924 msi_num, msi_state)) != H_EOK) { 925 DBG(DBG_LIB_MSI, dip, 926 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 927 return (DDI_FAILURE); 928 } 929 930 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 931 *msi_state); 932 933 return (DDI_SUCCESS); 934 } 935 936 /*ARGSUSED*/ 937 int 938 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 939 pci_msi_state_t msi_state) 940 { 941 uint64_t ret; 942 943 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 944 "msi_state 0x%x\n", dip, msi_num, msi_state); 945 946 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 947 msi_num, msi_state)) != H_EOK) { 948 DBG(DBG_LIB_MSI, dip, 949 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 950 return (DDI_FAILURE); 951 } 952 953 return (DDI_SUCCESS); 954 } 955 956 /* 957 * MSG Functions: 958 */ 959 960 /*ARGSUSED*/ 961 int 962 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 963 msiqid_t *msiq_id) 964 { 965 uint64_t ret; 966 967 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 968 dip, msg_type); 969 970 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 971 msg_type, msiq_id)) != H_EOK) { 972 DBG(DBG_LIB_MSG, dip, 973 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 974 return (DDI_FAILURE); 975 } 976 977 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 978 *msiq_id); 979 980 return (DDI_SUCCESS); 981 } 982 983 /*ARGSUSED*/ 984 int 985 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 986 msiqid_t msiq_id) 987 { 988 uint64_t ret; 989 990 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 991 "msq_id 0x%x\n", dip, msg_type, msiq_id); 992 993 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 994 msg_type, msiq_id)) != H_EOK) { 995 DBG(DBG_LIB_MSG, dip, 996 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 997 return (DDI_FAILURE); 998 } 999 1000 return (DDI_SUCCESS); 1001 } 1002 1003 /*ARGSUSED*/ 1004 int 1005 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1006 pcie_msg_valid_state_t *msg_valid_state) 1007 { 1008 uint64_t ret; 1009 1010 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 1011 dip, msg_type); 1012 1013 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 1014 msg_valid_state)) != H_EOK) { 1015 DBG(DBG_LIB_MSG, dip, 1016 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 1017 return (DDI_FAILURE); 1018 } 1019 1020 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1021 *msg_valid_state); 1022 1023 return (DDI_SUCCESS); 1024 } 1025 1026 /*ARGSUSED*/ 1027 int 1028 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1029 pcie_msg_valid_state_t msg_valid_state) 1030 { 1031 uint64_t ret; 1032 1033 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1034 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1035 1036 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1037 msg_valid_state)) != H_EOK) { 1038 DBG(DBG_LIB_MSG, dip, 1039 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1040 return (DDI_FAILURE); 1041 } 1042 1043 return (DDI_SUCCESS); 1044 } 1045 1046 /* 1047 * Suspend/Resume Functions: 1048 * Currently unsupported by hypervisor and all functions are noops. 1049 */ 1050 /*ARGSUSED*/ 1051 int 1052 px_lib_suspend(dev_info_t *dip) 1053 { 1054 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 1055 1056 /* Not supported */ 1057 return (DDI_FAILURE); 1058 } 1059 1060 /*ARGSUSED*/ 1061 void 1062 px_lib_resume(dev_info_t *dip) 1063 { 1064 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 1065 1066 /* Noop */ 1067 } 1068 1069 /* 1070 * Misc Functions: 1071 * Currently unsupported by hypervisor and all functions are noops. 1072 */ 1073 /*ARGSUSED*/ 1074 static int 1075 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1076 uint8_t size, pci_cfg_data_t *data_p) 1077 { 1078 uint64_t ret; 1079 1080 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1081 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1082 1083 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1084 size, data_p)) != H_EOK) { 1085 DBG(DBG_LIB_CFG, dip, 1086 "hvio_config_get failed, ret 0x%lx\n", ret); 1087 return (DDI_FAILURE); 1088 } 1089 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1090 1091 return (DDI_SUCCESS); 1092 } 1093 1094 /*ARGSUSED*/ 1095 static int 1096 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1097 uint8_t size, pci_cfg_data_t data) 1098 { 1099 uint64_t ret; 1100 1101 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1102 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1103 1104 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1105 size, data)) != H_EOK) { 1106 DBG(DBG_LIB_CFG, dip, 1107 "hvio_config_put failed, ret 0x%lx\n", ret); 1108 return (DDI_FAILURE); 1109 } 1110 1111 return (DDI_SUCCESS); 1112 } 1113 1114 static uint32_t 1115 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1116 { 1117 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1118 handle->ahi_common.ah_bus_private; 1119 uint32_t pci_dev_addr = px_pvt->raddr; 1120 uint32_t vaddr = px_pvt->vaddr; 1121 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1122 uint32_t rdata = 0; 1123 1124 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1125 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1126 /* XXX update error kstats */ 1127 return (0xffffffff); 1128 return (rdata); 1129 } 1130 1131 static void 1132 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1133 int size, pci_cfg_data_t wdata) 1134 { 1135 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1136 handle->ahi_common.ah_bus_private; 1137 uint32_t pci_dev_addr = px_pvt->raddr; 1138 uint32_t vaddr = px_pvt->vaddr; 1139 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1140 1141 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1142 size, wdata) != DDI_SUCCESS) { 1143 /*EMPTY*/ 1144 /* XXX update error kstats */ 1145 } 1146 } 1147 1148 static uint8_t 1149 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1150 { 1151 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1152 } 1153 1154 static uint16_t 1155 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1156 { 1157 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1158 } 1159 1160 static uint32_t 1161 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1162 { 1163 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1164 } 1165 1166 static uint64_t 1167 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1168 { 1169 uint32_t rdatah, rdatal; 1170 1171 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1172 rdatah = (uint32_t)px_pci_config_get(handle, 1173 (uint32_t *)((char *)addr+4), 4); 1174 return (((uint64_t)rdatah << 32) | rdatal); 1175 } 1176 1177 static void 1178 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1179 { 1180 pci_cfg_data_t wdata = { 0 }; 1181 1182 wdata.qw = (uint8_t)data; 1183 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1184 } 1185 1186 static void 1187 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1188 { 1189 pci_cfg_data_t wdata = { 0 }; 1190 1191 wdata.qw = (uint16_t)data; 1192 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1193 } 1194 1195 static void 1196 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1197 { 1198 pci_cfg_data_t wdata = { 0 }; 1199 1200 wdata.qw = (uint32_t)data; 1201 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1202 } 1203 1204 static void 1205 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1206 { 1207 pci_cfg_data_t wdata = { 0 }; 1208 1209 wdata.qw = (uint32_t)(data & 0xffffffff); 1210 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1211 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1212 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1213 } 1214 1215 static void 1216 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1217 uint8_t *dev_addr, size_t repcount, uint_t flags) 1218 { 1219 if (flags == DDI_DEV_AUTOINCR) 1220 for (; repcount; repcount--) 1221 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1222 else 1223 for (; repcount; repcount--) 1224 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1225 } 1226 1227 /* 1228 * Function to rep read 16 bit data off the PCI configuration space behind 1229 * the 21554's host interface. 1230 */ 1231 static void 1232 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1233 uint16_t *dev_addr, size_t repcount, uint_t flags) 1234 { 1235 if (flags == DDI_DEV_AUTOINCR) 1236 for (; repcount; repcount--) 1237 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1238 else 1239 for (; repcount; repcount--) 1240 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1241 } 1242 1243 /* 1244 * Function to rep read 32 bit data off the PCI configuration space behind 1245 * the 21554's host interface. 1246 */ 1247 static void 1248 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1249 uint32_t *dev_addr, size_t repcount, uint_t flags) 1250 { 1251 if (flags == DDI_DEV_AUTOINCR) 1252 for (; repcount; repcount--) 1253 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1254 else 1255 for (; repcount; repcount--) 1256 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1257 } 1258 1259 /* 1260 * Function to rep read 64 bit data off the PCI configuration space behind 1261 * the 21554's host interface. 1262 */ 1263 static void 1264 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1265 uint64_t *dev_addr, size_t repcount, uint_t flags) 1266 { 1267 if (flags == DDI_DEV_AUTOINCR) 1268 for (; repcount; repcount--) 1269 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1270 else 1271 for (; repcount; repcount--) 1272 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1273 } 1274 1275 /* 1276 * Function to rep write 8 bit data into the PCI configuration space behind 1277 * the 21554's host interface. 1278 */ 1279 static void 1280 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1281 uint8_t *dev_addr, size_t repcount, uint_t flags) 1282 { 1283 if (flags == DDI_DEV_AUTOINCR) 1284 for (; repcount; repcount--) 1285 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1286 else 1287 for (; repcount; repcount--) 1288 px_pci_config_put8(handle, dev_addr, *host_addr++); 1289 } 1290 1291 /* 1292 * Function to rep write 16 bit data into the PCI configuration space behind 1293 * the 21554's host interface. 1294 */ 1295 static void 1296 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1297 uint16_t *dev_addr, size_t repcount, uint_t flags) 1298 { 1299 if (flags == DDI_DEV_AUTOINCR) 1300 for (; repcount; repcount--) 1301 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1302 else 1303 for (; repcount; repcount--) 1304 px_pci_config_put16(handle, dev_addr, *host_addr++); 1305 } 1306 1307 /* 1308 * Function to rep write 32 bit data into the PCI configuration space behind 1309 * the 21554's host interface. 1310 */ 1311 static void 1312 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1313 uint32_t *dev_addr, size_t repcount, uint_t flags) 1314 { 1315 if (flags == DDI_DEV_AUTOINCR) 1316 for (; repcount; repcount--) 1317 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1318 else 1319 for (; repcount; repcount--) 1320 px_pci_config_put32(handle, dev_addr, *host_addr++); 1321 } 1322 1323 /* 1324 * Function to rep write 64 bit data into the PCI configuration space behind 1325 * the 21554's host interface. 1326 */ 1327 static void 1328 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1329 uint64_t *dev_addr, size_t repcount, uint_t flags) 1330 { 1331 if (flags == DDI_DEV_AUTOINCR) 1332 for (; repcount; repcount--) 1333 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1334 else 1335 for (; repcount; repcount--) 1336 px_pci_config_put64(handle, dev_addr, *host_addr++); 1337 } 1338 1339 /* 1340 * Provide a private access handle to route config access calls to Hypervisor. 1341 * Beware: Do all error checking for config space accesses before calling 1342 * this function. ie. do error checking from the calling function. 1343 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1344 * DDI_SUCCESS from here makes the code organization readable/easier from 1345 * the generic code. 1346 */ 1347 /*ARGSUSED*/ 1348 int 1349 px_lib_map_vconfig(dev_info_t *dip, 1350 ddi_map_req_t *mp, pci_config_offset_t off, 1351 pci_regspec_t *rp, caddr_t *addrp) 1352 { 1353 ddi_acc_hdl_t *hp; 1354 ddi_acc_impl_t *ap; 1355 uchar_t busnum; /* bus number */ 1356 uchar_t devnum; /* device number */ 1357 uchar_t funcnum; /* function number */ 1358 px_config_acc_pvt_t *px_pvt; 1359 1360 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1361 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1362 1363 /* Check for mapping teardown operation */ 1364 if ((mp->map_op == DDI_MO_UNMAP) || 1365 (mp->map_op == DDI_MO_UNLOCK)) { 1366 /* free up memory allocated for the private access handle. */ 1367 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1368 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1369 1370 /* unmap operation of PCI IO/config space. */ 1371 return (DDI_SUCCESS); 1372 } 1373 1374 ap->ahi_get8 = px_pci_config_get8; 1375 ap->ahi_get16 = px_pci_config_get16; 1376 ap->ahi_get32 = px_pci_config_get32; 1377 ap->ahi_get64 = px_pci_config_get64; 1378 ap->ahi_put8 = px_pci_config_put8; 1379 ap->ahi_put16 = px_pci_config_put16; 1380 ap->ahi_put32 = px_pci_config_put32; 1381 ap->ahi_put64 = px_pci_config_put64; 1382 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1383 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1384 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1385 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1386 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1387 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1388 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1389 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1390 1391 /* Initialize to default check/notify functions */ 1392 ap->ahi_fault = 0; 1393 ap->ahi_fault_check = i_ddi_acc_fault_check; 1394 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1395 1396 /* allocate memory for our private handle */ 1397 px_pvt = (px_config_acc_pvt_t *) 1398 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1399 hp->ah_bus_private = (void *)px_pvt; 1400 1401 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1402 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1403 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1404 1405 /* set up private data for use during IO routines */ 1406 1407 /* addr needed by the HV APIs */ 1408 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1409 /* 1410 * Address that specifies the actual offset into the 256MB 1411 * memory mapped configuration space, 4K per device. 1412 * First 12bits form the offset into 4K config space. 1413 * This address is only used during the IO routines to calculate 1414 * the offset at which the transaction must be performed. 1415 * Drivers bypassing DDI functions to access PCI config space will 1416 * panic the system since the following is a bogus virtual address. 1417 */ 1418 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1419 px_pvt->dip = dip; 1420 1421 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1422 px_pvt->raddr, px_pvt->vaddr); 1423 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1424 return (DDI_SUCCESS); 1425 } 1426 1427 /*ARGSUSED*/ 1428 void 1429 px_lib_map_attr_check(ddi_map_req_t *mp) 1430 { 1431 } 1432 1433 /* 1434 * px_lib_log_safeacc_err: 1435 * Imitate a cpu/mem trap call when a peek/poke fails. 1436 * This will initiate something similar to px_fm_callback. 1437 */ 1438 static void 1439 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag, 1440 r_addr_t addr) 1441 { 1442 uint32_t addr_high, addr_low; 1443 pcie_req_id_t bdf; 1444 px_ranges_t *ranges_p; 1445 int range_len, i; 1446 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1447 ddi_fm_error_t derr; 1448 1449 derr.fme_status = DDI_FM_NONFATAL; 1450 derr.fme_version = DDI_FME_VERSION; 1451 derr.fme_flag = fme_flag; 1452 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1453 derr.fme_acc_handle = handle; 1454 if (hp) 1455 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1456 1457 addr_high = (uint32_t)(addr >> 32); 1458 addr_low = (uint32_t)addr; 1459 1460 /* 1461 * Make sure this failed load came from this PCIe port. Check by 1462 * matching the upper 32 bits of the address with the ranges property. 1463 */ 1464 range_len = px_p->px_ranges_length / sizeof (px_ranges_t); 1465 i = 0; 1466 for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) { 1467 if (ranges_p->parent_high == addr_high) { 1468 switch (ranges_p->child_high & PCI_ADDR_MASK) { 1469 case PCI_ADDR_CONFIG: 1470 bdf = (pcie_req_id_t)(addr_low >> 12); 1471 break; 1472 default: 1473 bdf = NULL; 1474 break; 1475 } 1476 break; 1477 } 1478 } 1479 1480 mutex_enter(&px_p->px_fm_mutex); 1481 1482 if (!px_lib_is_in_drain_state(px_p)) { 1483 /* 1484 * This is to ensure that device corresponding to the addr of 1485 * the failed PIO/CFG load gets scanned. 1486 */ 1487 px_rp_en_q(px_p, bdf, addr, 1488 (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)); 1489 (void) pf_scan_fabric(px_p->px_dip, &derr, 1490 px_p->px_dq_p, &px_p->px_dq_tail); 1491 } 1492 1493 mutex_exit(&px_p->px_fm_mutex); 1494 } 1495 1496 1497 #ifdef DEBUG 1498 int px_peekfault_cnt = 0; 1499 int px_pokefault_cnt = 0; 1500 #endif /* DEBUG */ 1501 1502 /* 1503 * Do a safe write to a device. 1504 * 1505 * When this function is given a handle (cautious access), all errors are 1506 * suppressed. 1507 * 1508 * When this function is not given a handle (poke), only Unsupported Request 1509 * and Completer Abort errors are suppressed. 1510 * 1511 * In all cases, all errors are returned in the function return status. 1512 */ 1513 1514 int 1515 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1516 peekpoke_ctlops_t *in_args) 1517 { 1518 px_t *px_p = DIP_TO_STATE(dip); 1519 px_pec_t *pec_p = px_p->px_pec_p; 1520 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1521 1522 size_t repcount = in_args->repcount; 1523 size_t size = in_args->size; 1524 uintptr_t dev_addr = in_args->dev_addr; 1525 uintptr_t host_addr = in_args->host_addr; 1526 1527 int err = DDI_SUCCESS; 1528 uint64_t hvio_poke_status; 1529 uint32_t wrt_stat; 1530 1531 r_addr_t ra; 1532 uint64_t pokeval; 1533 pcie_req_id_t bdf; 1534 1535 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1536 for (; repcount; repcount--) { 1537 1538 switch (size) { 1539 case sizeof (uint8_t): 1540 pokeval = *(uint8_t *)host_addr; 1541 break; 1542 case sizeof (uint16_t): 1543 pokeval = *(uint16_t *)host_addr; 1544 break; 1545 case sizeof (uint32_t): 1546 pokeval = *(uint32_t *)host_addr; 1547 break; 1548 case sizeof (uint64_t): 1549 pokeval = *(uint64_t *)host_addr; 1550 break; 1551 default: 1552 DBG(DBG_MAP, px_p->px_dip, 1553 "poke: invalid size %d passed\n", size); 1554 err = DDI_FAILURE; 1555 goto done; 1556 } 1557 1558 /* 1559 * Grab pokefault mutex since hypervisor does not guarantee 1560 * poke serialization. 1561 */ 1562 if (hp) { 1563 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1564 (ddi_acc_handle_t)hp); 1565 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1566 } else { 1567 mutex_enter(&pec_p->pec_pokefault_mutex); 1568 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1569 } 1570 1571 if (pcie_get_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1572 err = DDI_FAILURE; 1573 goto done; 1574 } 1575 1576 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1577 pokeval, bdf << 8, &wrt_stat); 1578 1579 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1580 err = DDI_FAILURE; 1581 #ifdef DEBUG 1582 px_pokefault_cnt++; 1583 #endif 1584 /* 1585 * For CAUTIOUS and POKE access, notify FMA to 1586 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1587 */ 1588 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1589 (hp ? DDI_FM_ERR_EXPECTED : 1590 DDI_FM_ERR_POKE), ra); 1591 1592 pec_p->pec_ontrap_data = NULL; 1593 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1594 if (hp) { 1595 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1596 (ddi_acc_handle_t)hp); 1597 } else { 1598 mutex_exit(&pec_p->pec_pokefault_mutex); 1599 } 1600 goto done; 1601 } 1602 1603 pec_p->pec_ontrap_data = NULL; 1604 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1605 if (hp) { 1606 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1607 (ddi_acc_handle_t)hp); 1608 } else { 1609 mutex_exit(&pec_p->pec_pokefault_mutex); 1610 } 1611 1612 host_addr += size; 1613 1614 if (in_args->flags == DDI_DEV_AUTOINCR) { 1615 dev_addr += size; 1616 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1617 } 1618 } 1619 1620 done: 1621 return (err); 1622 } 1623 1624 1625 /*ARGSUSED*/ 1626 int 1627 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1628 peekpoke_ctlops_t *in_args, void *result) 1629 { 1630 px_t *px_p = DIP_TO_STATE(dip); 1631 px_pec_t *pec_p = px_p->px_pec_p; 1632 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1633 1634 size_t repcount = in_args->repcount; 1635 uintptr_t dev_addr = in_args->dev_addr; 1636 uintptr_t host_addr = in_args->host_addr; 1637 1638 r_addr_t ra; 1639 uint32_t read_status; 1640 uint64_t hvio_peek_status; 1641 uint64_t peekval; 1642 int err = DDI_SUCCESS; 1643 1644 result = (void *)in_args->host_addr; 1645 1646 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1647 for (; repcount; repcount--) { 1648 1649 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1650 if (hp) { 1651 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1652 (ddi_acc_handle_t)hp); 1653 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1654 } else { 1655 mutex_enter(&pec_p->pec_pokefault_mutex); 1656 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1657 } 1658 1659 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1660 in_args->size, &read_status, &peekval); 1661 1662 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1663 err = DDI_FAILURE; 1664 1665 /* 1666 * For CAUTIOUS and PEEK access, notify FMA to 1667 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1668 */ 1669 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1670 (hp ? DDI_FM_ERR_EXPECTED : 1671 DDI_FM_ERR_PEEK), ra); 1672 1673 /* Stuff FFs in host addr if peek. */ 1674 if (hp == NULL) { 1675 int i; 1676 uint8_t *ff_addr = (uint8_t *)host_addr; 1677 for (i = 0; i < in_args->size; i++) 1678 *ff_addr++ = 0xff; 1679 } 1680 #ifdef DEBUG 1681 px_peekfault_cnt++; 1682 #endif 1683 pec_p->pec_ontrap_data = NULL; 1684 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1685 if (hp) { 1686 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1687 (ddi_acc_handle_t)hp); 1688 } else { 1689 mutex_exit(&pec_p->pec_pokefault_mutex); 1690 } 1691 goto done; 1692 1693 } 1694 pec_p->pec_ontrap_data = NULL; 1695 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1696 if (hp) { 1697 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1698 (ddi_acc_handle_t)hp); 1699 } else { 1700 mutex_exit(&pec_p->pec_pokefault_mutex); 1701 } 1702 1703 switch (in_args->size) { 1704 case sizeof (uint8_t): 1705 *(uint8_t *)host_addr = (uint8_t)peekval; 1706 break; 1707 case sizeof (uint16_t): 1708 *(uint16_t *)host_addr = (uint16_t)peekval; 1709 break; 1710 case sizeof (uint32_t): 1711 *(uint32_t *)host_addr = (uint32_t)peekval; 1712 break; 1713 case sizeof (uint64_t): 1714 *(uint64_t *)host_addr = (uint64_t)peekval; 1715 break; 1716 default: 1717 DBG(DBG_MAP, px_p->px_dip, 1718 "peek: invalid size %d passed\n", 1719 in_args->size); 1720 err = DDI_FAILURE; 1721 goto done; 1722 } 1723 1724 host_addr += in_args->size; 1725 1726 if (in_args->flags == DDI_DEV_AUTOINCR) { 1727 dev_addr += in_args->size; 1728 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1729 } 1730 } 1731 done: 1732 return (err); 1733 } 1734 1735 1736 /* add interrupt vector */ 1737 int 1738 px_err_add_intr(px_fault_t *px_fault_p) 1739 { 1740 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1741 1742 DBG(DBG_LIB_INT, px_p->px_dip, 1743 "px_err_add_intr: calling add_ivintr"); 1744 1745 VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1746 (intrfunc)px_fault_p->px_err_func, (caddr_t)px_fault_p, NULL, 1747 (caddr_t)&px_fault_p->px_intr_payload[0]) == 0); 1748 1749 DBG(DBG_LIB_INT, px_p->px_dip, 1750 "px_err_add_intr: ib_intr_enable "); 1751 1752 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1753 1754 return (DDI_SUCCESS); 1755 } 1756 1757 /* remove interrupt vector */ 1758 void 1759 px_err_rem_intr(px_fault_t *px_fault_p) 1760 { 1761 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1762 1763 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1764 IB_INTR_WAIT); 1765 1766 VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0); 1767 } 1768 1769 void 1770 px_cb_intr_redist(void *arg) 1771 { 1772 px_t *px_p = (px_t *)arg; 1773 px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(), 1774 px_p->px_inos[PX_INTR_XBC], B_FALSE); 1775 } 1776 1777 int 1778 px_cb_add_intr(px_fault_t *f_p) 1779 { 1780 px_t *px_p = DIP_TO_STATE(f_p->px_fh_dip); 1781 1782 DBG(DBG_LIB_INT, px_p->px_dip, 1783 "px_err_add_intr: calling add_ivintr"); 1784 1785 VERIFY(add_ivintr(f_p->px_fh_sysino, PX_ERR_PIL, 1786 (intrfunc)f_p->px_err_func, (caddr_t)f_p, NULL, 1787 (caddr_t)&f_p->px_intr_payload[0]) == 0); 1788 1789 intr_dist_add(px_cb_intr_redist, px_p); 1790 1791 DBG(DBG_LIB_INT, px_p->px_dip, 1792 "px_err_add_intr: ib_intr_enable "); 1793 1794 px_ib_intr_enable(px_p, intr_dist_cpuid(), f_p->px_intr_ino); 1795 1796 return (DDI_SUCCESS); 1797 } 1798 1799 void 1800 px_cb_rem_intr(px_fault_t *f_p) 1801 { 1802 intr_dist_rem(px_cb_intr_redist, DIP_TO_STATE(f_p->px_fh_dip)); 1803 px_err_rem_intr(f_p); 1804 } 1805 1806 #ifdef FMA 1807 void 1808 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1809 { 1810 px_pec_err_t *err_pkt; 1811 1812 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1813 1814 /* initialise all the structure members */ 1815 rc_status->status_valid = 0; 1816 1817 if (err_pkt->pec_descr.P) { 1818 /* PCI Status Register */ 1819 rc_status->pci_err_status = err_pkt->pci_err_status; 1820 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1821 } 1822 1823 if (err_pkt->pec_descr.E) { 1824 /* PCIe Status Register */ 1825 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1826 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1827 } 1828 1829 if (err_pkt->pec_descr.U) { 1830 rc_status->ue_status = err_pkt->ue_reg_status; 1831 rc_status->status_valid |= UE_STATUS_VALID; 1832 } 1833 1834 if (err_pkt->pec_descr.H) { 1835 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1836 rc_status->status_valid |= UE_HDR1_VALID; 1837 } 1838 1839 if (err_pkt->pec_descr.I) { 1840 rc_status->ue_hdr2 = err_pkt->hdr[1]; 1841 rc_status->status_valid |= UE_HDR2_VALID; 1842 } 1843 1844 /* ue_fst_err_ptr - not available for sun4v?? */ 1845 1846 1847 if (err_pkt->pec_descr.S) { 1848 rc_status->source_id = err_pkt->err_src_reg; 1849 rc_status->status_valid |= SOURCE_ID_VALID; 1850 } 1851 1852 if (err_pkt->pec_descr.R) { 1853 rc_status->root_err_status = err_pkt->root_err_status; 1854 rc_status->status_valid |= CE_STATUS_VALID; 1855 } 1856 } 1857 #endif 1858 1859 /*ARGSUSED*/ 1860 int 1861 px_lib_pmctl(int cmd, px_t *px_p) 1862 { 1863 return (DDI_FAILURE); 1864 } 1865 1866 /*ARGSUSED*/ 1867 uint_t 1868 px_pmeq_intr(caddr_t arg) 1869 { 1870 return (DDI_INTR_CLAIMED); 1871 } 1872 1873 /* 1874 * Unprotected raw reads/writes of fabric device's config space. 1875 * Only used for temporary PCI-E Fabric Error Handling. 1876 */ 1877 uint32_t 1878 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) { 1879 uint32_t data = 0; 1880 1881 (void) hvio_config_get(px_p->px_dev_hdl, 1882 (bdf << PX_RA_BDF_SHIFT), offset, 4, 1883 (pci_cfg_data_t *)&data); 1884 1885 return (data); 1886 } 1887 1888 void 1889 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 1890 uint32_t val) { 1891 pci_cfg_data_t wdata = { 0 }; 1892 1893 wdata.qw = (uint32_t)val; 1894 (void) hvio_config_put(px_p->px_dev_hdl, 1895 (bdf << PX_RA_BDF_SHIFT), offset, 4, wdata); 1896 } 1897 1898 /*ARGSUSED*/ 1899 int 1900 px_lib_hotplug_init(dev_info_t *dip, void *arg) 1901 { 1902 return (DDI_ENOTSUP); 1903 } 1904 1905 /*ARGSUSED*/ 1906 void 1907 px_lib_hotplug_uninit(dev_info_t *dip) 1908 { 1909 } 1910 1911 /*ARGSUSED*/ 1912 void 1913 px_hp_intr_redist(px_t *px_p) 1914 { 1915 } 1916 1917 /* Dummy cpr add callback */ 1918 /*ARGSUSED*/ 1919 void 1920 px_cpr_add_callb(px_t *px_p) 1921 { 1922 } 1923 1924 /* Dummy cpr rem callback */ 1925 /*ARGSUSED*/ 1926 void 1927 px_cpr_rem_callb(px_t *px_p) 1928 { 1929 } 1930 1931 /*ARGSUSED*/ 1932 boolean_t 1933 px_lib_is_in_drain_state(px_t *px_p) 1934 { 1935 return (B_FALSE); 1936 } 1937 1938 /* 1939 * There is no IOAPI to get the BDF of the pcie root port nexus at this moment. 1940 * Assume it is 0x0000, until otherwise noted. For now, all sun4v platforms 1941 * have programmed the BDF to be 0x0000. 1942 */ 1943 /*ARGSUSED*/ 1944 pcie_req_id_t 1945 px_lib_get_bdf(px_t *px_p) 1946 { 1947 return (0x0000); 1948 } 1949