1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/systm.h> 30 #include <sys/archsystm.h> 31 #include <sys/machparam.h> 32 #include <sys/machsystm.h> 33 #include <sys/cpu.h> 34 #include <sys/elf_SPARC.h> 35 #include <vm/hat_sfmmu.h> 36 #include <vm/page.h> 37 #include <sys/cpuvar.h> 38 #include <sys/async.h> 39 #include <sys/cmn_err.h> 40 #include <sys/debug.h> 41 #include <sys/dditypes.h> 42 #include <sys/sunddi.h> 43 #include <sys/cpu_module.h> 44 #include <sys/prom_debug.h> 45 #include <sys/vmsystm.h> 46 #include <sys/prom_plat.h> 47 #include <sys/sysmacros.h> 48 #include <sys/intreg.h> 49 #include <sys/machtrap.h> 50 #include <sys/ontrap.h> 51 #include <sys/ivintr.h> 52 #include <sys/atomic.h> 53 #include <sys/panic.h> 54 #include <sys/dtrace.h> 55 #include <sys/simulate.h> 56 #include <sys/fault.h> 57 #include <sys/niagararegs.h> 58 #include <sys/trapstat.h> 59 #include <sys/hsvc.h> 60 61 #define S_VAC_SIZE MMU_PAGESIZE /* XXXQ? */ 62 63 /* 64 * Maximum number of contexts 65 */ 66 #define MAX_NCTXS (1 << 13) 67 68 uint_t root_phys_addr_lo_mask = 0xffffffffU; 69 static niagara_mmustat_t *cpu_tstat_va; /* VA of mmustat buffer */ 70 static uint64_t cpu_tstat_pa; /* PA of mmustat buffer */ 71 char cpu_module_name[] = "SUNW,UltraSPARC-T1"; 72 73 /* 74 * Hypervisor services information for the NIAGARA CPU module 75 */ 76 static boolean_t niagara_hsvc_available = B_TRUE; 77 static uint64_t niagara_sup_minor; /* Supported minor number */ 78 static hsvc_info_t niagara_hsvc = { 79 HSVC_REV_1, NULL, HSVC_GROUP_NIAGARA_CPU, 1, 0, cpu_module_name 80 }; 81 82 void 83 cpu_setup(void) 84 { 85 extern int at_flags; 86 extern int disable_delay_tlb_flush, delay_tlb_flush; 87 extern int mmu_exported_pagesize_mask; 88 extern int get_cpu_pagesizes(void); 89 extern int cpc_has_overflow_intr; 90 int status; 91 92 /* 93 * Negotiate the API version for Niagara specific hypervisor 94 * services. 95 */ 96 status = hsvc_register(&niagara_hsvc, &niagara_sup_minor); 97 if (status != 0) { 98 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 99 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 100 niagara_hsvc.hsvc_modname, niagara_hsvc.hsvc_group, 101 niagara_hsvc.hsvc_major, niagara_hsvc.hsvc_minor, status); 102 niagara_hsvc_available = B_FALSE; 103 } 104 105 cache |= (CACHE_PTAG | CACHE_IOCOHERENT); 106 at_flags = EF_SPARC_SUN_US3 | EF_SPARC_32PLUS | EF_SPARC_SUN_US1; 107 108 /* 109 * Use the maximum number of contexts available for Spitfire unless 110 * it has been tuned for debugging. 111 * We are checking against 0 here since this value can be patched 112 * while booting. It can not be patched via /etc/system since it 113 * will be patched too late and thus cause the system to panic. 114 */ 115 if (nctxs == 0) 116 nctxs = MAX_NCTXS; 117 118 if (use_page_coloring) { 119 do_pg_coloring = 1; 120 if (use_virtual_coloring) 121 do_virtual_coloring = 1; 122 } 123 /* 124 * Initalize supported page sizes information before the PD. 125 * If no information is available, then initialize the 126 * mmu_exported_pagesize_mask to a reasonable value for that processor. 127 */ 128 mmu_exported_pagesize_mask = get_cpu_pagesizes(); 129 if (mmu_exported_pagesize_mask <= 0) { 130 mmu_exported_pagesize_mask = (1 << TTE8K) | (1 << TTE64K) | 131 (1 << TTE4M) | (1 << TTE256M); 132 } 133 134 /* 135 * Tune pp_slots to use up to 1/8th of the tlb entries. 136 */ 137 pp_slots = MIN(8, MAXPP_SLOTS); 138 139 /* 140 * Block stores invalidate all pages of the d$ so pagecopy 141 * et. al. do not need virtual translations with virtual 142 * coloring taken into consideration. 143 */ 144 pp_consistent_coloring = 0; 145 isa_list = 146 "sparcv9 sparcv8plus sparcv8 sparcv8-fsmuld sparcv7 " 147 "sparc sparcv9+vis sparcv9+vis2 sparcv8plus+vis sparcv8plus+vis2"; 148 149 cpu_hwcap_flags |= AV_SPARC_ASI_BLK_INIT; 150 151 /* 152 * Niagara supports a 48-bit subset of the full 64-bit virtual 153 * address space. Virtual addresses between 0x0000800000000000 154 * and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole" 155 * and must never be mapped. In addition, software must not use 156 * pages within 4GB of the VA hole as instruction pages to 157 * avoid problems with prefetching into the VA hole. 158 * 159 * VA hole information should be obtained from the machine 160 * description. 161 */ 162 hole_start = (caddr_t)(0x800000000000ul - (1ul << 32)); 163 hole_end = (caddr_t)(0xffff800000000000ul + (1ul << 32)); 164 165 /* 166 * The kpm mapping window. 167 * kpm_size: 168 * The size of a single kpm range. 169 * The overall size will be: kpm_size * vac_colors. 170 * kpm_vbase: 171 * The virtual start address of the kpm range within the kernel 172 * virtual address space. kpm_vbase has to be kpm_size aligned. 173 */ 174 kpm_size = (size_t)(2ull * 1024 * 1024 * 1024 * 1024); /* 2TB */ 175 kpm_size_shift = 41; 176 kpm_vbase = (caddr_t)0xfffffa0000000000ull; /* 16EB - 6TB */ 177 178 /* 179 * The traptrace code uses either %tick or %stick for 180 * timestamping. We have %stick so we can use it. 181 */ 182 traptrace_use_stick = 1; 183 184 /* 185 * sun4v provides demap_all 186 */ 187 if (!disable_delay_tlb_flush) 188 delay_tlb_flush = 1; 189 /* 190 * Niagara has a performance counter overflow interrupt 191 */ 192 cpc_has_overflow_intr = 1; 193 } 194 195 #define MB * 1024 * 1024 196 /* 197 * Set the magic constants of the implementation. 198 */ 199 void 200 cpu_fiximp(struct cpu_node *cpunode) 201 { 202 extern int vac_size, vac_shift; 203 extern uint_t vac_mask; 204 int i, a; 205 206 /* 207 * The assumption here is that fillsysinfo will eventually 208 * have code to fill this info in from the PD. 209 * We hard code this for niagara now. 210 * Once the PD access library is done this code 211 * might need to be changed to get the info from the PD 212 */ 213 if (cpunode->ecache_size == 0) 214 cpunode->ecache_size = 3 MB; 215 if (cpunode->ecache_linesize == 0) 216 cpunode->ecache_linesize = 64; 217 if (cpunode->ecache_associativity == 0) 218 cpunode->ecache_associativity = 12; 219 220 cpunode->ecache_setsize = 221 cpunode->ecache_size / cpunode->ecache_associativity; 222 223 if (ecache_setsize == 0) 224 ecache_setsize = cpunode->ecache_setsize; 225 if (ecache_alignsize == 0) 226 ecache_alignsize = cpunode->ecache_linesize; 227 228 vac_size = S_VAC_SIZE; 229 vac_mask = MMU_PAGEMASK & (vac_size - 1); 230 i = 0; a = vac_size; 231 while (a >>= 1) 232 ++i; 233 vac_shift = i; 234 shm_alignment = vac_size; 235 vac = 0; 236 } 237 238 static int niagara_cpucnt; 239 240 void 241 cpu_init_private(struct cpu *cp) 242 { 243 extern int niagara_kstat_init(void); 244 245 /* 246 * This code change assumes that the virtual cpu ids are identical 247 * to the physical cpu ids which is true for ontario but not for 248 * niagara in general. 249 * This is a temporary fix which will later be modified to obtain 250 * the execution unit sharing information from MD table. 251 */ 252 cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id / 4); 253 254 ASSERT(MUTEX_HELD(&cpu_lock)); 255 if (niagara_cpucnt++ == 0 && niagara_hsvc_available == B_TRUE) { 256 (void) niagara_kstat_init(); 257 } 258 } 259 260 void 261 cpu_uninit_private(struct cpu *cp) 262 { 263 extern int niagara_kstat_fini(void); 264 265 ASSERT(MUTEX_HELD(&cpu_lock)); 266 if (--niagara_cpucnt == 0 && niagara_hsvc_available == B_TRUE) { 267 (void) niagara_kstat_fini(); 268 } 269 } 270 271 /* 272 * On Niagara, any flush will cause all preceding stores to be 273 * synchronized wrt the i$, regardless of address or ASI. In fact, 274 * the address is ignored, so we always flush address 0. 275 */ 276 void 277 dtrace_flush_sec(uintptr_t addr) 278 { 279 doflush(0); 280 } 281 282 #define IS_FLOAT(i) (((i) & 0x1000000) != 0) 283 #define IS_IBIT_SET(x) (x & 0x2000) 284 #define IS_VIS1(op, op3)(op == 2 && op3 == 0x36) 285 #define IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(op, op3, asi) \ 286 (op == 3 && (op3 == IOP_V8_LDDFA || \ 287 op3 == IOP_V8_STDFA) && asi > ASI_SNFL) 288 int 289 vis1_partial_support(struct regs *rp, k_siginfo_t *siginfo, uint_t *fault) 290 { 291 char *badaddr; 292 int instr; 293 uint_t optype, op3, asi; 294 uint_t rd, ignor; 295 296 if (!USERMODE(rp->r_tstate)) 297 return (-1); 298 299 instr = fetch_user_instr((caddr_t)rp->r_pc); 300 301 rd = (instr >> 25) & 0x1f; 302 optype = (instr >> 30) & 0x3; 303 op3 = (instr >> 19) & 0x3f; 304 ignor = (instr >> 5) & 0xff; 305 if (IS_IBIT_SET(instr)) { 306 asi = (uint32_t)((rp->r_tstate >> TSTATE_ASI_SHIFT) & 307 TSTATE_ASI_MASK); 308 } else { 309 asi = ignor; 310 } 311 312 if (!IS_VIS1(optype, op3) && 313 !IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(optype, op3, asi)) { 314 return (-1); 315 } 316 switch (simulate_unimp(rp, &badaddr)) { 317 case SIMU_RETRY: 318 break; /* regs are already set up */ 319 /*NOTREACHED*/ 320 321 case SIMU_SUCCESS: 322 /* 323 * skip the successfully 324 * simulated instruction 325 */ 326 rp->r_pc = rp->r_npc; 327 rp->r_npc += 4; 328 break; 329 /*NOTREACHED*/ 330 331 case SIMU_FAULT: 332 siginfo->si_signo = SIGSEGV; 333 siginfo->si_code = SEGV_MAPERR; 334 siginfo->si_addr = badaddr; 335 *fault = FLTBOUNDS; 336 break; 337 338 case SIMU_DZERO: 339 siginfo->si_signo = SIGFPE; 340 siginfo->si_code = FPE_INTDIV; 341 siginfo->si_addr = (caddr_t)rp->r_pc; 342 *fault = FLTIZDIV; 343 break; 344 345 case SIMU_UNALIGN: 346 siginfo->si_signo = SIGBUS; 347 siginfo->si_code = BUS_ADRALN; 348 siginfo->si_addr = badaddr; 349 *fault = FLTACCESS; 350 break; 351 352 case SIMU_ILLEGAL: 353 default: 354 siginfo->si_signo = SIGILL; 355 op3 = (instr >> 19) & 0x3F; 356 if ((IS_FLOAT(instr) && (op3 == IOP_V8_STQFA) || 357 (op3 == IOP_V8_STDFA))) 358 siginfo->si_code = ILL_ILLADR; 359 else 360 siginfo->si_code = ILL_ILLOPC; 361 siginfo->si_addr = (caddr_t)rp->r_pc; 362 *fault = FLTILL; 363 break; 364 } 365 return (0); 366 } 367 368 /* 369 * Trapstat support for Niagara processor 370 */ 371 int 372 cpu_trapstat_conf(int cmd) 373 { 374 size_t len; 375 uint64_t mmustat_pa, hvret; 376 int status = 0; 377 378 if (niagara_hsvc_available == B_FALSE) 379 return (ENOTSUP); 380 381 switch (cmd) { 382 case CPU_TSTATCONF_INIT: 383 ASSERT(cpu_tstat_va == NULL); 384 len = (NCPU+1) * sizeof (niagara_mmustat_t); 385 cpu_tstat_va = contig_mem_alloc_align(len, 386 sizeof (niagara_mmustat_t)); 387 if (cpu_tstat_va == NULL) 388 status = EAGAIN; 389 else { 390 bzero(cpu_tstat_va, len); 391 cpu_tstat_pa = va_to_pa(cpu_tstat_va); 392 } 393 break; 394 395 case CPU_TSTATCONF_FINI: 396 if (cpu_tstat_va) { 397 len = (NCPU+1) * sizeof (niagara_mmustat_t); 398 contig_mem_free(cpu_tstat_va, len); 399 cpu_tstat_va = NULL; 400 cpu_tstat_pa = 0; 401 } 402 break; 403 404 case CPU_TSTATCONF_ENABLE: 405 hvret = hv_niagara_mmustat_conf((cpu_tstat_pa + 406 (CPU->cpu_id+1) * sizeof (niagara_mmustat_t)), 407 (uint64_t *)&mmustat_pa); 408 if (hvret != H_EOK) 409 status = EINVAL; 410 break; 411 412 case CPU_TSTATCONF_DISABLE: 413 hvret = hv_niagara_mmustat_conf(0, (uint64_t *)&mmustat_pa); 414 if (hvret != H_EOK) 415 status = EINVAL; 416 break; 417 418 default: 419 status = EINVAL; 420 break; 421 } 422 return (status); 423 } 424 425 void 426 cpu_trapstat_data(void *buf, uint_t tstat_pgszs) 427 { 428 niagara_mmustat_t *mmustatp; 429 tstat_pgszdata_t *tstatp = (tstat_pgszdata_t *)buf; 430 int i, pgcnt; 431 432 if (cpu_tstat_va == NULL) 433 return; 434 435 mmustatp = &((niagara_mmustat_t *)cpu_tstat_va)[CPU->cpu_id+1]; 436 if (tstat_pgszs > NIAGARA_MMUSTAT_PGSZS) 437 tstat_pgszs = NIAGARA_MMUSTAT_PGSZS; 438 439 for (i = 0; i < tstat_pgszs; i++, tstatp++) { 440 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_count = 441 mmustatp->kitsb[i].tsbhit_count; 442 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_time = 443 mmustatp->kitsb[i].tsbhit_time; 444 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_count = 445 mmustatp->uitsb[i].tsbhit_count; 446 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_time = 447 mmustatp->uitsb[i].tsbhit_time; 448 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_count = 449 mmustatp->kdtsb[i].tsbhit_count; 450 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_time = 451 mmustatp->kdtsb[i].tsbhit_time; 452 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_count = 453 mmustatp->udtsb[i].tsbhit_count; 454 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_time = 455 mmustatp->udtsb[i].tsbhit_time; 456 } 457 } 458