1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_OPL_OLYMPUS_REGS_H 27 #define _SYS_OPL_OLYMPUS_REGS_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/machasi.h> 32 #include <sys/cpu_impl.h> 33 34 /* 35 * This file is cpu dependent. 36 */ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #ifdef _ASM 43 /* 44 * assembler doesn't understand the 'ull' suffix for C constants so 45 * use the inttypes.h macros and undefine them here for assembly code 46 */ 47 #undef INT64_C 48 #define INT64_C(x) (x) 49 #undef UINT64_C 50 #define UINT64_C(x) (x) 51 #endif /* _ASM */ 52 53 /* 54 * Synchronous Fault Physical Address Register 55 */ 56 #define OPL_MMU_SFPAR 0x78 57 58 /* 59 * ASI_MCNTL: MEMORY CONTROL Register layout (ASI 0x45, VA 8) 60 * 61 * +-------------------------+---------+--------+--------+-----+---------+ 62 * | reserved [63:17] | NC_Cache|fw_fITLB|fw_fDTLB|00000|JPS1_TSBP| 63 * +-------------------------+---------+--------+--------+-----+---------+ 64 * 16 15 14 13-9 8 65 * +---------+---------+------+ 66 * |mpg_sITLB|mpg_sDTLB|000000| 67 * +---------+---------+------+ 68 * 7 6 5-0 69 */ 70 #define ASI_MCNTL 0x45 71 #define LSU_MCNTL 0x8 /* vaddr offset of ASI_MCNTL */ 72 #define MCNTL_FW_FDTLB INT64_C(0x0000000000004000) 73 #define MCNTL_FW_FITLB INT64_C(0x0000000000008000) 74 #define MCNTL_JPS1_TSBP INT64_C(0x0000000000000100) 75 #define MCNTL_MPG_SITLB INT64_C(0x0000000000000080) 76 #define MCNTL_MPG_SDTLB INT64_C(0x0000000000000040) 77 #define MCNTL_SPECULATIVE_SHIFT 41 /* bit 41 is speculative mode bit */ 78 79 /* 80 * ASI_UGESR: URGENT ERROR STATES layout (ASI 0x4C, VA 0x8) 81 * 82 * +--------+---+----+----+---+---+--+--+---+---+-+----+----+----+ 83 * |0[63:23]|CRE|TSBX|TSBP|PST|TST| F| R|SDC|WDT|0|DTLB|ITLB|CORE| 84 * +--------+---+----+----+---+---+--+--+---+---+-+----+----+----+ 85 * 22 21 20 19 18 17 16 15 14 10 9 8 86 * +-------+----+---+---+---+ 87 * |INSTEND|PRIV|DAE|IAE|UGE| 88 * +-------+----+---+---+---+ 89 * 5 4 3 2 1 0 90 * 91 */ 92 #define ASI_UGERSR 0x8 93 #define UGESR_IAUG_CRE INT64_C(0x0000000000400000) 94 #define UGESR_IAUG_TSBCTXT INT64_C(0x0000000000200000) 95 #define UGESR_IUG_TSBP INT64_C(0x0000000000100000) 96 #define UGESR_IUG_PSTATE INT64_C(0x0000000000080000) 97 #define UGESR_IUG_TSTATE INT64_C(0x0000000000040000) 98 #define UGESR_IUG_F INT64_C(0x0000000000020000) 99 #define UGESR_IUG_R INT64_C(0x0000000000010000) 100 #define UGESR_AUG_SDC INT64_C(0x0000000000008000) 101 #define UGESR_IUG_WDT INT64_C(0x0000000000004000) 102 #define UGESR_IUG_DTLB INT64_C(0x0000000000000400) 103 #define UGESR_IUG_ITLB INT64_C(0x0000000000000200) 104 #define UGESR_IUG_COREERR INT64_C(0x0000000000000100) 105 #define UGESR_PRIV INT64_C(0x0000000000000008) 106 #define UGESR_MULTI_DAE INT64_C(0x0000000000000004) 107 #define UGESR_MULTI_IAE INT64_C(0x0000000000000002) 108 #define UGESR_MULTI_UGE INT64_C(0x0000000000000001) 109 110 #define UGESR_CAN_RECOVER (UGESR_IUG_DTLB | \ 111 UGESR_IUG_ITLB | \ 112 UGESR_IUG_COREERR) 113 114 #define UGESR_MULTI (UGESR_MULTI_DAE | \ 115 UGESR_MULTI_IAE | \ 116 UGESR_MULTI_UGE) 117 118 #define UGESR_NOSYNC_PANIC (UGESR_IAUG_CRE | \ 119 UGESR_AUG_SDC | \ 120 UGESR_MULTI_DAE | \ 121 UGESR_MULTI_IAE | \ 122 UGESR_MULTI_UGE) 123 /* 124 * The value means 10000 Mz per 10ms. 125 */ 126 #define OPL_UGER_STICK_DIFF 10000 127 128 129 /* 130 * ASI_ECR: Control of Error Action layout (ASI 0x4C, VA 0x10) 131 * 132 * +-------------------------+------+--------+-----+-------+-----------+ 133 * | reserved [63:10] |RTE_UE|RTE_CEDG|0...0|WEAK_ED|UGE_HANDLER| 134 * +-------------------------+------+--------+-----+-------+-----------+ 135 * 9 8 7 - 2 1 0 136 * 137 */ 138 #define ASI_ECR ASI_AFSR 139 #define AFSR_ECR 0x10 140 #define ASI_ECR_RTE_UE INT64_C(0x0000000000000200) 141 #define ASI_ECR_RTE_CEDG INT64_C(0x0000000000000100) 142 #define ASI_ECR_WEAK_ED INT64_C(0x0000000000000002) 143 #define ASI_ECR_UGE_HANDLER INT64_C(0x0000000000000001) 144 145 146 /* 147 * ASI_L2_CTRL: Level-2 Cache Control Register (ASI 0x6A, VA 0x10) 148 * 149 * +---------------------+--------+-----+---------+----+--------+ 150 * | reserved[63:25] |UGE_TRAP|0...0|NUMINSWAY|0..0|U2_FLUSH| 151 * +---------------------+--------+-----+---------+----+--------+ 152 * 24 23 19 18 16 15 1 0 153 * 154 */ 155 #define ASI_L2_CTRL 0x6A /* L2$ Control Register */ 156 #define ASI_L2_CTRL_RW_ADDR 0x10 157 #define ASI_L2_CTRL_UGE_TRAP INT64_C(0x0000000001000000) 158 #define ASI_L2_CTRL_NUMINSWAY_MASK INT64_C(0x0000000000070000) 159 #define ASI_L2_CTRL_U2_FLUSH INT64_C(0x0000000000000001) 160 161 162 /* 163 * Synchronous Fault Status Register Layout (ASI 0x50/0x58, VA 0x18) 164 * 165 * IMMU and DMMU maintain their own SFSR Register 166 * 167 * +----+----+-----+----+--+-----+--+---+-+----+--+--+-----+--+-+ 168 * |TLB#|0..0|index|0..0|MK| EID |UE|UPA|0|mTLB|NC|NF| ASI |TM|0| 169 * +----+----+-----+----+--+-----+--+---+-+----+--+--+-----+--+-+ 170 * 63 62 61 58 48 46 45 32 31 30 28 27 25 24 23 16 15 14 171 * +----+-+---+--+-+--+--+ 172 * | FT |E| CT|PR|W|OW|FV| 173 * +----+-+---+--+-+--+--+ 174 * 13 7 6 5 4 3 2 1 0 175 * 176 */ 177 #define SFSR_MK_UE INT64_C(0x0000400000000000) 178 #define SFSR_EID_MOD INT64_C(0x0000300000000000) 179 #define SFSR_EID_SID INT64_C(0x00000FFF00000000) 180 #define SFSR_UE INT64_C(0x0000000080000000) 181 #define SFSR_BERR INT64_C(0x0000000040000000) 182 #define SFSR_TO INT64_C(0x0000000020000000) 183 #define SFSR_TLB_MUL INT64_C(0x0000000008000000) 184 #define SFSR_TLB_PRT INT64_C(0x0000000004000000) 185 186 #define SFSR_EID_MOD_SHIFT 44 187 #define SFSR_EID_SID_SHIFT 32 188 189 /* 190 * Error Mark ID: Module Type 191 */ 192 #define OPL_ERRID_MEM 0 193 #define OPL_ERRID_CHANNEL 1 194 #define OPL_ERRID_CPU 2 195 #define OPL_ERRID_PATH 3 196 197 198 #define SFSR_ERRS (SFSR_UE | SFSR_BERR | \ 199 SFSR_TO | SFSR_TLB_MUL | \ 200 SFSR_TLB_PRT) 201 202 #define SFSR_MEMORY (SFSR_UE | \ 203 SFSR_BERR | \ 204 SFSR_TO) 205 206 /* 207 * Miscellaneous ASI definitions 208 */ 209 #define ASI_IIU_INST_TRAP 0x60 /* Instruction breakpoint */ 210 #define ASI_ALL_FLUSH_L1I 0x67 /* Flush Level-1 Inst. cache */ 211 #define ASI_L2_TAG_READ 0x6B /* L2 Diagnostics Tag Read */ 212 #define ASI_L2_TAG_READ_REG 0x6C /* L2 Diagnostics Tag Read Register */ 213 #define ASI_EIDR 0x6E /* Urgent errors */ 214 #define ASI_CACHE_INV 0x74 /* Cache invalidation */ 215 #define ASI_ERR_INJCT 0x76 /* Error injection */ 216 /* 217 * Address of ASI scratch register. ASI 0x4F 218 */ 219 #define OPL_SCRATCHPAD_SAVE_AG1 0x00 /* used for saving global registers */ 220 #define OPL_SCRATCHPAD_SAVE_AG2 0x08 /* used for saving global registers */ 221 #define OPL_SCRATCHPAD_SAVE_AG3 0x10 /* used for saving global registers */ 222 #define OPL_SCRATCHPAD_ERRLOG 0x18 /* keeps EIDR, log's PA & err counter */ 223 #define OPL_SCRATCHPAD_UTSBREG4 0x20 224 #define OPL_SCRATCHPAD_UTSBREG5 0x28 225 #define OPL_SCRATCHPAD_UTSBREG6 0x30 226 #define OPL_SCRATCHPAD_UNUSED7 0x38 227 228 /* 229 * Error log scratchpad register format. 230 * 231 * +--------+-------------------+----------+ 232 * |ASI_EIDR| PA to logging buf | # of err | 233 * +--------+-------------------+----------+ 234 * 63 50 49 6 5 0 235 * 236 */ 237 238 #define ERRLOG_REG_LOGPA_MASK INT64_C(0x0003ffffffffffc0) /* PA to log */ 239 #define ERRLOG_REG_NUMERR_MASK INT64_C(0x000000000000003f) /* Counter */ 240 #define ERRLOG_REG_EIDR_MASK INT64_C(0x0000000000003fff) /* EIDR */ 241 242 #define ERRLOG_REG_EIDR_SHIFT 50 243 #define ERRLOG_REG_ERR_SHIFT 6 244 #define ERRLOG_REG_EIDR(reg) ((reg >> ERRLOG_REG_EIDR_SHIFT) & \ 245 ERRLOG_REG_EIDR_MASK) 246 #define ERRLOG_REG_LOGPA(reg) (reg & ERRLOG_REG_LOGPA_MASK) 247 #define ERRLOG_REG_NUMERR(reg) (reg & ERRLOG_REG_NUMERR_MASK) 248 249 #define ERRLOG_BUFSZ 0x2000 250 #define ERRLOG_SZ (1 << ERRLOG_REG_ERR_SHIFT) 251 #define ERRLOG_ALLOC_SZ (ERRLOG_BUFSZ * 512) 252 253 /* 254 * Olympus-C default cache parameters. 255 */ 256 #define OPL_DCACHE_SIZE 0x20000 257 #define OPL_DCACHE_LSIZE 0x40 258 #define OPL_ICACHE_SIZE 0x20000 259 #define OPL_ICACHE_LSIZE 0x40 260 #define OPL_ECACHE_SIZE 0x600000 261 #define OPL_ECACHE_LSIZE 0x100 262 #define OPL_ECACHE_NWAY 12 263 #define OPL_ECACHE_SETSIZE 0x80000 264 265 /* 266 * The minimum size needed to ensure consistency on a virtually address 267 * cache. Computed by taking the largest virtually indexed cache and dividing 268 * by its associativity. 269 */ 270 #define OPL_VAC_SIZE 0x4000 271 272 /* these are field offsets for opl_errlog structure */ 273 #define LOG_STICK_OFF 0x0 274 #define LOG_TL_OFF 0x8 275 #define LOG_ASI3_OFF 0x10 276 #define LOG_SFSR_OFF 0x18 277 #define LOG_SFAR_OFF 0x20 278 279 #define LOG_UGER_OFF 0x18 280 #define LOG_TSTATE_OFF 0x20 281 #define LOG_TPC_OFF 0x28 282 283 #ifndef _ASM 284 typedef struct opl_errlog { 285 uint64_t stick; 286 uint32_t tl; 287 uint32_t tt; 288 uint64_t asi3; 289 union { 290 struct { 291 uint64_t sfsr; 292 union { 293 uint64_t sfar; 294 uint64_t sfpar; 295 } sync_addr; 296 } sync; 297 struct { 298 uint64_t ugesr; 299 uint64_t tstate; 300 } ugesr; 301 } reg; 302 uint64_t tpc; 303 } opl_errlog_t; 304 #endif /* _ASM */ 305 306 #ifdef __cplusplus 307 } 308 #endif 309 310 #endif /* _SYS_OPL_OLYMPUS_REGS_H */ 311