1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_MACHSYSTM_H 27 #define _SYS_MACHSYSTM_H 28 29 /* 30 * Numerous platform-dependent interfaces that don't seem to belong 31 * in any other header file. 32 * 33 * This file should not be included by code that purports to be 34 * platform-independent. 35 */ 36 37 #ifndef _ASM 38 #include <sys/types.h> 39 #include <sys/scb.h> 40 #include <sys/varargs.h> 41 #include <sys/machparam.h> 42 #include <sys/thread.h> 43 #include <vm/seg_enum.h> 44 #include <sys/processor.h> 45 #include <sys/sunddi.h> 46 #include <sys/memlist.h> 47 #include <sys/async.h> 48 #include <sys/errorq.h> 49 #endif /* _ASM */ 50 51 #ifdef __cplusplus 52 extern "C" { 53 #endif 54 55 #ifdef _KERNEL 56 57 #ifndef _ASM 58 /* 59 * The following enum types determine how interrupts are distributed 60 * on a sun4u system. 61 */ 62 enum intr_policies { 63 /* 64 * Target interrupt at the CPU running the add_intrspec 65 * thread. Also used to target all interrupts at the panicing 66 * CPU. 67 */ 68 INTR_CURRENT_CPU = 0, 69 70 /* 71 * Target all interrupts at the boot cpu 72 */ 73 INTR_BOOT_CPU, 74 75 /* 76 * Flat distribution of all interrupts 77 */ 78 INTR_FLAT_DIST, 79 80 /* 81 * Weighted distribution of all interrupts 82 */ 83 INTR_WEIGHTED_DIST 84 }; 85 86 87 /* 88 * Structure that defines the interrupt distribution list. It contains 89 * enough info about the interrupt so that it can callback the parent 90 * nexus driver and retarget the interrupt to a different CPU. 91 */ 92 struct intr_dist { 93 struct intr_dist *next; /* link to next in list */ 94 void (*func)(void *); /* Callback function */ 95 void *arg; /* Nexus parent callback arg 1 */ 96 }; 97 98 /* 99 * Miscellaneous cpu_state changes 100 */ 101 extern void power_down(const char *); 102 extern void do_shutdown(void); 103 104 /* 105 * Number of seconds until power is shut off 106 */ 107 extern int thermal_powerdown_delay; 108 109 110 /* 111 * prom-related 112 */ 113 extern int obpdebug; 114 extern int forthdebug_supported; 115 extern uint_t tba_taken_over; 116 extern void forthdebug_init(void); 117 extern void init_vx_handler(void); 118 extern void kern_preprom(void); 119 extern void kern_postprom(void); 120 121 /* 122 * externally (debugger or prom) initiated panic 123 */ 124 extern struct regs sync_reg_buf; 125 extern uint64_t sync_tt; 126 extern void sync_handler(void); 127 128 /* 129 * Trap-related 130 */ 131 struct regs; 132 extern void trap(struct regs *rp, caddr_t addr, uint32_t type, 133 uint32_t mmu_fsr); 134 extern void *get_tba(void); 135 extern void *set_tba(void *); 136 extern caddr_t set_trap_table(void); 137 extern struct scb trap_table; 138 139 struct panic_trap_info { 140 struct regs *trap_regs; 141 uint_t trap_type; 142 caddr_t trap_addr; 143 uint_t trap_mmu_fsr; 144 }; 145 146 /* 147 * misc. primitives 148 */ 149 extern void debug_flush_windows(void); 150 extern void flush_windows(void); 151 extern int getprocessorid(void); 152 extern void reestablish_curthread(void); 153 154 extern void stphys(uint64_t physaddr, int value); 155 extern int ldphys(uint64_t physaddr); 156 extern void stdphys(uint64_t physaddr, uint64_t value); 157 extern uint64_t lddphys(uint64_t physaddr); 158 159 extern void stphysio(u_longlong_t physaddr, uint_t value); 160 extern uint_t ldphysio(u_longlong_t physaddr); 161 extern void sthphysio(u_longlong_t physaddr, ushort_t value); 162 extern ushort_t ldhphysio(u_longlong_t physaddr); 163 extern void stbphysio(u_longlong_t physaddr, uchar_t value); 164 extern uchar_t ldbphysio(u_longlong_t physaddr); 165 extern void stdphysio(u_longlong_t physaddr, u_longlong_t value); 166 extern u_longlong_t lddphysio(u_longlong_t physaddr); 167 168 extern int pf_is_dmacapable(pfn_t); 169 170 extern int dip_to_cpu_id(dev_info_t *dip, processorid_t *cpu_id); 171 172 extern void set_cmp_error_steering(void); 173 174 /* 175 * SPARCv9 %ver register and field definitions 176 */ 177 178 #define ULTRA_VER_MANUF(x) ((x) >> 48) 179 #define ULTRA_VER_IMPL(x) (((x) >> 32) & 0xFFFF) 180 #define ULTRA_VER_MASK(x) (((x) >> 24) & 0xFF) 181 182 extern uint64_t ultra_getver(void); 183 184 /* 185 * bootup-time 186 */ 187 extern int ncpunode; 188 extern int niobus; 189 190 extern void segnf_init(void); 191 extern void kern_setup1(void); 192 extern void startup(void); 193 extern void post_startup(void); 194 extern void install_va_to_tte(void); 195 extern void setwstate(uint_t); 196 extern void create_va_to_tte(void); 197 extern int memscrub_init(void); 198 199 extern void kcpc_hw_init(void); 200 extern void kcpc_hw_startup_cpu(ushort_t); 201 extern int kcpc_hw_load_pcbe(void); 202 203 /* 204 * Interrupts 205 */ 206 struct cpu; 207 extern struct cpu cpu0; 208 extern struct scb *set_tbr(struct scb *); 209 210 extern uint_t disable_vec_intr(void); 211 extern void enable_vec_intr(uint_t); 212 extern void setintrenable(int); 213 214 extern void intr_dist_add(void (*f)(void *), void *); 215 extern void intr_dist_rem(void (*f)(void *), void *); 216 extern void intr_dist_add_weighted(void (*f)(void *, int32_t, int32_t), void *); 217 extern void intr_dist_rem_weighted(void (*f)(void *, int32_t, int32_t), void *); 218 219 extern uint32_t intr_dist_cpuid(void); 220 221 void intr_dist_cpuid_add_device_weight(uint32_t cpuid, dev_info_t *dip, 222 int32_t weight); 223 void intr_dist_cpuid_rem_device_weight(uint32_t cpuid, dev_info_t *dip); 224 225 extern void intr_redist_all_cpus(void); 226 extern void intr_redist_all_cpus_shutdown(void); 227 228 extern void send_dirint(int, int); 229 extern void setsoftint(uint64_t); 230 extern void setsoftint_tl1(uint64_t, uint64_t); 231 extern void siron(void); 232 extern void sir_on(int); 233 extern uint64_t getidsr(void); 234 extern void intr_enqueue_req(uint_t pil, uint64_t inum); 235 extern void intr_dequeue_req(uint_t pil, uint64_t inum); 236 extern void wr_clr_softint(uint_t); 237 238 /* 239 * Time- and %tick-related 240 */ 241 extern hrtime_t rdtick(void); 242 extern void tick_write_delta(uint64_t); 243 extern void tickcmpr_set(uint64_t); 244 extern void tickcmpr_reset(void); 245 extern void tickcmpr_disable(void); 246 extern int tickcmpr_disabled(void); 247 extern uint64_t cbe_level14_inum; 248 249 /* 250 * Caches 251 */ 252 extern int vac; 253 extern int cache; 254 extern int use_mp; 255 extern uint_t vac_mask; 256 extern uint64_t ecache_flushaddr; 257 extern int dcache_size; /* Maximum dcache size */ 258 extern int dcache_linesize; /* Minimum dcache linesize */ 259 extern int icache_size; /* Maximum icache size */ 260 extern int icache_linesize; /* Minimum icache linesize */ 261 extern int ecache_alignsize; /* Maximum ecache linesize for struct align */ 262 extern int ecache_size; /* Maximum ecache size */ 263 extern int ecache_associativity; /* ecache associativity */ 264 extern int ecache_setsize; /* Maximum ecache setsize possible */ 265 extern int cpu_setsize; /* Maximum ecache setsize of configured cpus */ 266 267 /* 268 * VM 269 */ 270 extern int do_pg_coloring; 271 extern int use_page_coloring; 272 extern uint_t vac_colors_mask; 273 274 extern int ndata_alloc_page_freelists(struct memlist *, int); 275 extern int ndata_alloc_dmv(struct memlist *); 276 extern int ndata_alloc_tsbs(struct memlist *, pgcnt_t); 277 extern int ndata_alloc_hat(struct memlist *, pgcnt_t); 278 extern int ndata_alloc_kpm(struct memlist *, pgcnt_t); 279 extern int ndata_alloc_page_mutexs(struct memlist *ndata); 280 281 extern size_t calc_pp_sz(pgcnt_t); 282 extern size_t calc_kpmpp_sz(pgcnt_t); 283 extern size_t calc_hmehash_sz(pgcnt_t); 284 extern size_t calc_pagehash_sz(pgcnt_t); 285 extern size_t calc_free_pagelist_sz(void); 286 287 extern caddr_t alloc_hmehash(caddr_t); 288 extern caddr_t alloc_page_freelists(caddr_t); 289 290 extern size_t page_ctrs_sz(void); 291 extern caddr_t page_ctrs_alloc(caddr_t); 292 extern void page_freelist_coalesce_all(int); 293 extern void ppmapinit(void); 294 extern void hwblkpagecopy(const void *, void *); 295 extern void hw_pa_bcopy32(uint64_t, uint64_t); 296 297 extern int pp_slots; 298 extern int pp_consistent_coloring; 299 300 /* 301 * ppcopy/hwblkpagecopy interaction. See ppage.c. 302 */ 303 #define PPAGE_STORE_VCOLORING 0x1 /* use vcolors to maintain consistency */ 304 #define PPAGE_LOAD_VCOLORING 0x2 /* use vcolors to maintain consistency */ 305 #define PPAGE_STORES_POLLUTE 0x4 /* stores pollute VAC */ 306 #define PPAGE_LOADS_POLLUTE 0x8 /* loads pollute VAC */ 307 308 /* 309 * VIS-accelerated copy/zero 310 */ 311 extern int use_hw_bcopy; 312 extern uint_t hw_copy_limit_1; 313 extern uint_t hw_copy_limit_2; 314 extern uint_t hw_copy_limit_4; 315 extern uint_t hw_copy_limit_8; 316 extern int use_hw_bzero; 317 318 #ifdef CHEETAH 319 #define VIS_COPY_THRESHOLD 256 320 #else 321 #define VIS_COPY_THRESHOLD 900 322 #endif 323 324 /* 325 * MP 326 */ 327 extern void idle_other_cpus(void); 328 extern void resume_other_cpus(void); 329 extern void stop_other_cpus(void); 330 extern void idle_stop_xcall(void); 331 extern void set_idle_cpu(int); 332 extern void unset_idle_cpu(int); 333 extern void mp_cpu_quiesce(struct cpu *); 334 335 /* 336 * Error handling 337 */ 338 extern void set_error_enable(uint64_t neer); 339 extern void set_error_enable_tl1(uint64_t neer, uint64_t action); 340 extern uint64_t get_error_enable(void); 341 extern void get_asyncflt(uint64_t *afsr); 342 extern void set_asyncflt(uint64_t afsr); 343 extern void get_asyncaddr(uint64_t *afar); 344 extern void scrubphys(uint64_t paddr, int ecache_size); 345 extern void clearphys(uint64_t paddr, int ecache_size, int ecache_linesize); 346 extern void flushecacheline(uint64_t paddr, int ecache_size); 347 extern int ce_scrub_xdiag_recirc(struct async_flt *, errorq_t *, 348 errorq_elem_t *, size_t); 349 extern char *flt_to_error_type(struct async_flt *); 350 351 /* 352 * Panic at TL > 0 353 */ 354 extern uint64_t cpu_pa[]; 355 extern void ptl1_init_cpu(struct cpu *); 356 357 /* 358 * Constants which define the "hole" in the 64-bit sfmmu address space. 359 * These are set to specific values by the CPU module code. 360 */ 361 extern caddr_t hole_start, hole_end; 362 363 /* kpm mapping window */ 364 extern size_t kpm_size; 365 extern uchar_t kpm_size_shift; 366 extern caddr_t kpm_vbase; 367 368 #define INVALID_VADDR(a) (((a) >= hole_start && (a) < hole_end)) 369 370 extern void adjust_hw_copy_limits(int); 371 372 #endif /* _ASM */ 373 374 /* 375 * Actions for set_error_enable_tl1 376 */ 377 #define EER_SET_ABSOLUTE 0x0 378 #define EER_SET_SETBITS 0x1 379 #define EER_SET_CLRBITS 0x2 380 381 #endif /* _KERNEL */ 382 383 #ifdef __cplusplus 384 } 385 #endif 386 387 #endif /* _SYS_MACHSYSTM_H */ 388