1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/sunddi.h> 31 #include <sys/esunddi.h> 32 #include <sys/sunndi.h> 33 #include <sys/ddi.h> 34 #include <sys/modctl.h> 35 #include <sys/sysmacros.h> 36 #include <sys/note.h> 37 38 #include <sys/platform_module.h> 39 #include <sys/errno.h> 40 #include <sys/i2c/clients/i2c_client.h> 41 #include <sys/cherrystone.h> 42 #include <sys/machsystm.h> 43 #include <sys/promif.h> 44 #include <vm/page.h> 45 #include <sys/memnode.h> 46 #include <vm/vm_dep.h> 47 48 /* Cherrystone Keyswitch Information */ 49 #define CHERRY_KEY_POLL_PORT 3 50 #define CHERRY_KEY_POLL_BIT 2 51 #define CHERRY_KEY_POLL_INTVL 10 52 53 #define SHARED_PCF8584_PATH "/pci@9,700000/ebus@1/i2c@1,2e/nvram@4,a4" 54 static dev_info_t *shared_pcf8584_dip; 55 static kmutex_t cherry_pcf8584_mutex; 56 57 static boolean_t key_locked_bit; 58 static clock_t keypoll_timeout_hz; 59 60 /* 61 * Table that maps memory slices to a specific memnode. 62 */ 63 int slice_to_memnode[CHERRYSTONE_MAX_SLICE]; 64 65 /* 66 * For software memory interleaving support. 67 */ 68 static void update_mem_bounds(int, int, int, uint64_t, uint64_t); 69 70 static uint64_t 71 slice_table[CHERRYSTONE_SBD_SLOTS][CHERRYSTONE_CPUS_PER_BOARD] 72 [CHERRYSTONE_BANKS_PER_MC][2]; 73 74 #define SLICE_PA 0 75 #define SLICE_SPAN 1 76 77 /* Function prototypes */ 78 int (*p2get_mem_unum)(int, uint64_t, char *, int, int *); 79 80 int (*cherry_ssc050_get_port_bit) (dev_info_t *, int, int, uint8_t *, int); 81 extern void (*abort_seq_handler)(); 82 83 static int cherry_dev_search(dev_info_t *, void *); 84 static void keyswitch_poll(void *); 85 static void cherry_abort_seq_handler(char *msg); 86 87 /* Function definitions from this point forward. */ 88 89 int 90 set_platform_tsb_spares() 91 { 92 return (0); 93 } 94 95 void 96 startup_platform(void) 97 { 98 /* 99 * Disable an active h/w watchdog timer 100 * upon exit to OBP. 101 */ 102 extern int disable_watchdog_on_exit; 103 disable_watchdog_on_exit = 1; 104 105 mutex_init(&cherry_pcf8584_mutex, NULL, NULL, NULL); 106 } 107 108 #pragma weak mmu_init_large_pages 109 110 void 111 set_platform_defaults(void) 112 { 113 extern void mmu_init_large_pages(size_t); 114 115 if ((mmu_page_sizes == max_mmu_page_sizes) && 116 (mmu_ism_pagesize != DEFAULT_ISM_PAGESIZE)) { 117 if (&mmu_init_large_pages) 118 mmu_init_large_pages(mmu_ism_pagesize); 119 } 120 } 121 122 void 123 load_platform_modules(void) 124 { 125 if (modload("drv", "pmc") < 0) { 126 cmn_err(CE_NOTE, "pmc driver failed to load"); 127 } 128 } 129 130 void 131 load_platform_drivers(void) 132 { 133 char **drv; 134 dev_info_t *i2cnexus_dip; 135 dev_info_t *keysw_dip = NULL; 136 137 static char *boot_time_drivers[] = { 138 "todds1287", 139 "mc-us3", 140 "ssc050", 141 NULL 142 }; 143 144 for (drv = boot_time_drivers; *drv; drv++) { 145 if (i_ddi_attach_hw_nodes(*drv) != DDI_SUCCESS) 146 cmn_err(CE_WARN, "Failed to install \"%s\" driver.", 147 *drv); 148 } 149 150 /* 151 * mc-us3 and ssc050 must stay loaded for plat_get_mem_unum() 152 * and keyswitch_poll() 153 */ 154 (void) ddi_hold_driver(ddi_name_to_major("mc-us3")); 155 (void) ddi_hold_driver(ddi_name_to_major("ssc050")); 156 157 /* Gain access into the ssc050_get_port function */ 158 cherry_ssc050_get_port_bit = (int (*) (dev_info_t *, int, int, 159 uint8_t *, int)) modgetsymvalue("ssc050_get_port_bit", 0); 160 if (cherry_ssc050_get_port_bit == NULL) { 161 cmn_err(CE_WARN, "cannot find ssc050_get_port_bit"); 162 return; 163 } 164 165 e_ddi_walk_driver("i2c-ssc050", cherry_dev_search, (void *)&keysw_dip); 166 ASSERT(keysw_dip != NULL); 167 168 keypoll_timeout_hz = drv_usectohz(10 * MICROSEC); 169 keyswitch_poll(keysw_dip); 170 abort_seq_handler = cherry_abort_seq_handler; 171 172 /* 173 * Figure out which pcf8584_dip is shared with OBP for the nvram 174 * device, so the lock can be acquired. 175 */ 176 177 i2cnexus_dip = e_ddi_hold_devi_by_path(SHARED_PCF8584_PATH, 0); 178 179 ASSERT(i2cnexus_dip != NULL); 180 shared_pcf8584_dip = ddi_get_parent(i2cnexus_dip); 181 182 ndi_hold_devi(shared_pcf8584_dip); 183 ndi_rele_devi(i2cnexus_dip); 184 } 185 186 static int 187 cherry_dev_search(dev_info_t *dip, void *arg) 188 { 189 int *dev_regs; /* Info about where the device is. */ 190 uint_t len; 191 int err; 192 193 if (strcmp(ddi_binding_name(dip), "i2c-ssc050") != 0) 194 return (DDI_WALK_CONTINUE); 195 196 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 197 DDI_PROP_DONTPASS, "reg", &dev_regs, &len); 198 if (err != DDI_PROP_SUCCESS) { 199 return (DDI_WALK_CONTINUE); 200 } 201 /* 202 * regs[0] contains the bus number and regs[1] 203 * contains the device address of the i2c device. 204 * 0x82 is the device address of the i2c device 205 * from which the key switch position is read. 206 */ 207 if (dev_regs[0] == 0 && dev_regs[1] == 0x82) { 208 *((dev_info_t **)arg) = dip; 209 ddi_prop_free(dev_regs); 210 return (DDI_WALK_TERMINATE); 211 } 212 ddi_prop_free(dev_regs); 213 return (DDI_WALK_CONTINUE); 214 } 215 216 static void 217 keyswitch_poll(void *arg) 218 { 219 dev_info_t *dip = arg; 220 uchar_t port_byte; 221 int port = CHERRY_KEY_POLL_PORT; 222 int bit = CHERRY_KEY_POLL_BIT; 223 int err; 224 225 err = cherry_ssc050_get_port_bit(dip, port, bit, 226 &port_byte, I2C_NOSLEEP); 227 if (err != 0) { 228 return; 229 } 230 231 key_locked_bit = (boolean_t)((port_byte & 0x1)); 232 timeout(keyswitch_poll, (caddr_t)dip, keypoll_timeout_hz); 233 } 234 235 static void 236 cherry_abort_seq_handler(char *msg) 237 { 238 if (key_locked_bit == 0) 239 cmn_err(CE_CONT, "KEY in LOCKED position, " 240 "ignoring debug enter sequence"); 241 else { 242 debug_enter(msg); 243 } 244 } 245 246 247 /*ARGSUSED*/ 248 int 249 plat_cpu_poweron(struct cpu *cp) 250 { 251 return (ENOTSUP); /* not supported on this platform */ 252 } 253 254 /*ARGSUSED*/ 255 int 256 plat_cpu_poweroff(struct cpu *cp) 257 { 258 return (ENOTSUP); /* not supported on this platform */ 259 } 260 261 /* 262 * Given a pfn, return the board and beginning/end of the page's 263 * memory controller's address range. 264 */ 265 static int 266 plat_discover_slice(pfn_t pfn, pfn_t *first, pfn_t *last) 267 { 268 int bd, cpu, bank; 269 270 for (bd = 0; bd < CHERRYSTONE_SBD_SLOTS; bd++) { 271 for (cpu = 0; cpu < CHERRYSTONE_CPUS_PER_BOARD; cpu++) { 272 for (bank = 0; bank < CHERRYSTONE_BANKS_PER_MC; 273 bank++) { 274 uint64_t *slice = slice_table[bd][cpu][bank]; 275 uint64_t base = btop(slice[SLICE_PA]); 276 uint64_t len = btop(slice[SLICE_SPAN]); 277 if (len && pfn >= base && pfn < (base + len)) { 278 *first = base; 279 *last = base + len - 1; 280 return (bd); 281 } 282 } 283 } 284 } 285 panic("plat_discover_slice: no slice for pfn 0x%lx\n", pfn); 286 /* NOTREACHED */ 287 } 288 289 /*ARGSUSED*/ 290 void 291 plat_freelist_process(int mnode) 292 {} 293 294 /* 295 * Called for each board/cpu/PA range detected in plat_fill_mc(). 296 */ 297 static void 298 update_mem_bounds(int boardid, int cpuid, int bankid, 299 uint64_t base, uint64_t size) 300 { 301 uint64_t end; 302 int mnode; 303 304 slice_table[boardid][cpuid][bankid][SLICE_PA] = base; 305 slice_table[boardid][cpuid][bankid][SLICE_SPAN] = size; 306 307 end = base + size - 1; 308 309 /* 310 * First see if this board already has a memnode associated 311 * with it. If not, see if this slice has a memnode. This 312 * covers the cases where a single slice covers multiple 313 * boards (cross-board interleaving) and where a single 314 * board has multiple slices (1+GB DIMMs). 315 */ 316 if ((mnode = plat_lgrphand_to_mem_node(boardid)) == -1) { 317 if ((mnode = slice_to_memnode[PA_2_SLICE(base)]) == -1) 318 mnode = mem_node_alloc(); 319 320 ASSERT(mnode >= 0); 321 ASSERT(mnode < MAX_MEM_NODES); 322 plat_assign_lgrphand_to_mem_node(boardid, mnode); 323 } 324 325 base = P2ALIGN(base, (1ul << PA_SLICE_SHIFT)); 326 327 while (base < end) { 328 slice_to_memnode[PA_2_SLICE(base)] = mnode; 329 base += (1ul << PA_SLICE_SHIFT); 330 } 331 } 332 333 /* 334 * Dynamically detect memory slices in the system by decoding 335 * the cpu memory decoder registers at boot time. 336 */ 337 void 338 plat_fill_mc(pnode_t nodeid) 339 { 340 uint64_t mc_addr, saf_addr; 341 uint64_t mc_decode[CHERRYSTONE_BANKS_PER_MC]; 342 uint64_t base, size; 343 uint64_t saf_mask; 344 uint64_t offset; 345 uint32_t regs[4]; 346 int len; 347 int local_mc; 348 int portid; 349 int boardid; 350 int cpuid; 351 int i; 352 353 if ((prom_getprop(nodeid, "portid", (caddr_t)&portid) < 0) || 354 (portid == -1)) 355 return; 356 357 /* 358 * Decode the board number from the MC portid. Assumes 359 * portid == safari agentid. 360 */ 361 boardid = CHERRYSTONE_GETSLOT(portid); 362 cpuid = CHERRYSTONE_GETSID(portid); 363 364 /* 365 * The "reg" property returns 4 32-bit values. The first two are 366 * combined to form a 64-bit address. The second two are for a 367 * 64-bit size, but we don't actually need to look at that value. 368 */ 369 len = prom_getproplen(nodeid, "reg"); 370 if (len != (sizeof (uint32_t) * 4)) { 371 prom_printf("Warning: malformed 'reg' property\n"); 372 return; 373 } 374 if (prom_getprop(nodeid, "reg", (caddr_t)regs) < 0) 375 return; 376 mc_addr = ((uint64_t)regs[0]) << 32; 377 mc_addr |= (uint64_t)regs[1]; 378 379 /* 380 * Figure out whether the memory controller we are examining 381 * belongs to this CPU or a different one. 382 */ 383 saf_addr = lddsafaddr(8); 384 saf_mask = (uint64_t)SAF_MASK; 385 if ((mc_addr & saf_mask) == saf_addr) 386 local_mc = 1; 387 else 388 local_mc = 0; 389 390 for (i = 0; i < CHERRYSTONE_BANKS_PER_MC; i++) { 391 /* 392 * Memory decode masks are at offsets 0x10 - 0x28. 393 */ 394 offset = 0x10 + (i << 3); 395 396 /* 397 * If the memory controller is local to this CPU, we use 398 * the special ASI to read the decode registers. 399 * Otherwise, we load the values from a magic address in 400 * I/O space. 401 */ 402 if (local_mc) 403 mc_decode[i] = lddmcdecode(offset); 404 else 405 mc_decode[i] = lddphysio(mc_addr | offset); 406 407 /* 408 * If the upper bit is set, we have a valid mask 409 */ 410 if ((int64_t)mc_decode[i] < 0) { 411 /* 412 * The memory decode register is a bitmask field, 413 * so we can decode that into both a base and 414 * a span. 415 */ 416 base = MC_BASE(mc_decode[i]) << PHYS2UM_SHIFT; 417 size = MC_UK2SPAN(mc_decode[i]); 418 update_mem_bounds(boardid, cpuid, i, base, size); 419 } 420 } 421 } 422 423 /* 424 * This routine is run midway through the boot process. By the time we get 425 * here, we know about all the active CPU boards in the system, and we have 426 * extracted information about each board's memory from the memory 427 * controllers. We have also figured out which ranges of memory will be 428 * assigned to which memnodes, so we walk the slice table to build the table 429 * of memnodes. 430 */ 431 /* ARGSUSED */ 432 void 433 plat_build_mem_nodes(u_longlong_t *list, size_t nelems) 434 { 435 int slice; 436 pfn_t basepfn; 437 pgcnt_t npgs; 438 439 mem_node_pfn_shift = PFN_SLICE_SHIFT; 440 mem_node_physalign = (1ull << PA_SLICE_SHIFT); 441 npgs = 1ull << PFN_SLICE_SHIFT; 442 443 for (slice = 0; slice < CHERRYSTONE_MAX_SLICE; slice++) { 444 if (slice_to_memnode[slice] == -1) 445 continue; 446 basepfn = (uint64_t)slice << PFN_SLICE_SHIFT; 447 mem_node_add_slice(basepfn, basepfn + npgs - 1); 448 } 449 } 450 451 452 453 /* 454 * Cherrystone support for lgroups. 455 * 456 * On Cherrystone, an lgroup platform handle == slot number. 457 * 458 * Mappings between lgroup handles and memnodes are managed 459 * in addition to mappings between memory slices and memnodes 460 * to support cross-board interleaving as well as multiple 461 * slices per board (e.g. >1GB DIMMs). The initial mapping 462 * of memnodes to lgroup handles is determined at boot time. 463 */ 464 465 int 466 plat_pfn_to_mem_node(pfn_t pfn) 467 { 468 return (slice_to_memnode[PFN_2_SLICE(pfn)]); 469 } 470 471 /* 472 * Return the platform handle for the lgroup containing the given CPU 473 * 474 * For Cherrystone, lgroup platform handle == slot/board number 475 */ 476 lgrp_handle_t 477 plat_lgrp_cpu_to_hand(processorid_t id) 478 { 479 return (CHERRYSTONE_GETSLOT(id)); 480 } 481 482 /* 483 * Platform specific lgroup initialization 484 */ 485 void 486 plat_lgrp_init(void) 487 { 488 int i; 489 490 /* 491 * Initialize lookup tables to invalid values so we catch 492 * any illegal use of them. 493 */ 494 for (i = 0; i < CHERRYSTONE_MAX_SLICE; i++) { 495 slice_to_memnode[i] = -1; 496 } 497 } 498 499 /* 500 * Return latency between "from" and "to" lgroups 501 * 502 * This latency number can only be used for relative comparison 503 * between lgroups on the running system, cannot be used across platforms, 504 * and may not reflect the actual latency. It is platform and implementation 505 * specific, so platform gets to decide its value. It would be nice if the 506 * number was at least proportional to make comparisons more meaningful though. 507 * NOTE: The numbers below are supposed to be load latencies for uncached 508 * memory divided by 10. 509 */ 510 int 511 plat_lgrp_latency(lgrp_handle_t from, lgrp_handle_t to) 512 { 513 /* 514 * Return min remote latency when there are more than two lgroups 515 * (root and child) and getting latency between two different lgroups 516 * or root is involved 517 */ 518 if (lgrp_optimizations() && (from != to || 519 from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE)) 520 return (21); 521 else 522 return (19); 523 } 524 525 /* 526 * No platform drivers on this platform 527 */ 528 char *platform_module_list[] = { 529 (char *)0 530 }; 531 532 /*ARGSUSED*/ 533 void 534 plat_tod_fault(enum tod_fault_type tod_bad) 535 { 536 } 537 538 /*ARGSUSED*/ 539 int 540 plat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id, 541 int flt_in_memory, ushort_t flt_status, char *buf, int buflen, int *lenp) 542 { 543 if (flt_in_memory && (p2get_mem_unum != NULL)) 544 return (p2get_mem_unum(synd_code, P2ALIGN(flt_addr, 8), 545 buf, buflen, lenp)); 546 else 547 return (ENOTSUP); 548 } 549 550 /* 551 * This platform hook gets called from mc_add_mem_unum_label() in the mc-us3 552 * driver giving each platform the opportunity to add platform 553 * specific label information to the unum for ECC error logging purposes. 554 */ 555 void 556 plat_add_mem_unum_label(char *unum, int mcid, int bank, int dimm) 557 { 558 _NOTE(ARGUNUSED(bank, dimm)) 559 560 char board = CHERRYSTONE_GETSLOT_LABEL(mcid); 561 char old_unum[UNUM_NAMLEN]; 562 563 strcpy(old_unum, unum); 564 snprintf(unum, UNUM_NAMLEN, "Slot %c: %s", board, old_unum); 565 } 566 567 int 568 plat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp) 569 { 570 char board = CHERRYSTONE_GETSLOT_LABEL(cpuid); 571 572 if (snprintf(buf, buflen, "Slot %c", board) >= buflen) { 573 return (ENOSPC); 574 } else { 575 *lenp = strlen(buf); 576 return (0); 577 } 578 } 579 580 /* 581 * Cherrystone's BBC pcf8584 controller is used by both OBP and the OS's i2c 582 * drivers. The 'eeprom' command executes OBP code to handle property requests. 583 * If eeprom didn't do this, or if the controllers were partitioned so that all 584 * devices on a given controller were driven by either OBP or the OS, this 585 * wouldn't be necessary. 586 * 587 * Note that getprop doesn't have the same issue as it reads from cached 588 * memory in OBP. 589 */ 590 591 /* 592 * Common locking enter code 593 */ 594 void 595 plat_setprop_enter(void) 596 { 597 mutex_enter(&cherry_pcf8584_mutex); 598 } 599 600 /* 601 * Common locking exit code 602 */ 603 void 604 plat_setprop_exit(void) 605 { 606 mutex_exit(&cherry_pcf8584_mutex); 607 } 608 609 /* 610 * Called by pcf8584 driver 611 */ 612 void 613 plat_shared_i2c_enter(dev_info_t *i2cnexus_dip) 614 { 615 if (i2cnexus_dip == shared_pcf8584_dip) { 616 plat_setprop_enter(); 617 } 618 } 619 620 /* 621 * Called by pcf8584 driver 622 */ 623 void 624 plat_shared_i2c_exit(dev_info_t *i2cnexus_dip) 625 { 626 if (i2cnexus_dip == shared_pcf8584_dip) { 627 plat_setprop_exit(); 628 } 629 } 630