xref: /titanic_50/usr/src/uts/sun4/io/px/px_pec.c (revision 2654012f83cec5dc15b61dfe3e4a4915f186e7a6)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 /*
29  * PCI Express PEC implementation:
30  *	initialization
31  *	Bus error interrupt handler
32  */
33 
34 #include <sys/types.h>
35 #include <sys/kmem.h>
36 #include <sys/spl.h>
37 #include <sys/sysmacros.h>
38 #include <sys/sunddi.h>
39 #include <sys/machsystm.h>	/* ldphysio() */
40 #include <sys/async.h>
41 #include <sys/ddi_impldefs.h>
42 #include <sys/ontrap.h>
43 #include <sys/membar.h>
44 #include "px_obj.h"
45 
46 /*LINTLIBRARY*/
47 
48 extern uint_t px_ranges_phi_mask;
49 
50 static uint_t px_pec_error_intr(caddr_t a);
51 static int    px_pec_msg_add_intr(px_t *px_p);
52 static void   px_pec_msg_rem_intr(px_t *px_p);
53 
54 int
55 px_pec_attach(px_t *px_p)
56 {
57 	px_pec_t *pec_p;
58 	int i, len;
59 	int nrange = px_p->px_ranges_length / sizeof (px_ranges_t);
60 	dev_info_t *dip = px_p->px_dip;
61 	px_ranges_t *rangep = px_p->px_ranges_p;
62 	int ret;
63 
64 	/*
65 	 * Allocate a state structure for the PEC and cross-link it
66 	 * to its per px node state structure.
67 	 */
68 	pec_p = kmem_zalloc(sizeof (px_pec_t), KM_SLEEP);
69 	px_p->px_pec_p = pec_p;
70 	pec_p->pec_px_p = px_p;
71 
72 	len = snprintf(pec_p->pec_nameinst_str,
73 	    sizeof (pec_p->pec_nameinst_str),
74 	    "%s%d", NAMEINST(dip));
75 	pec_p->pec_nameaddr_str = pec_p->pec_nameinst_str + ++len;
76 	(void) snprintf(pec_p->pec_nameaddr_str,
77 	    sizeof (pec_p->pec_nameinst_str) - len,
78 	    "%s@%s", NAMEADDR(dip));
79 
80 	/*
81 	 * Add interrupt handlers to process correctable/fatal/non fatal
82 	 * PCIE messages.
83 	 */
84 	if ((ret = px_pec_msg_add_intr(px_p)) != DDI_SUCCESS) {
85 		px_pec_msg_rem_intr(px_p);
86 		return (ret);
87 	}
88 
89 	/*
90 	 * Get this pec's mem32 and mem64 segments to determine whether
91 	 * a dma object originates from ths pec. i.e. dev to dev dma
92 	 */
93 	for (i = 0; i < nrange; i++, rangep++) {
94 		uint64_t rng_addr, rng_size, *pfnbp, *pfnlp;
95 		uint32_t rng_type = rangep->child_high & PCI_ADDR_MASK;
96 
97 		switch (rng_type) {
98 			case PCI_ADDR_MEM32:
99 				pfnbp = &pec_p->pec_base32_pfn;
100 				pfnlp = &pec_p->pec_last32_pfn;
101 				break;
102 
103 			case PCI_ADDR_MEM64:
104 				pfnbp = &pec_p->pec_base64_pfn;
105 				pfnlp = &pec_p->pec_last64_pfn;
106 				break;
107 
108 			case PCI_ADDR_CONFIG:
109 			case PCI_ADDR_IO:
110 			default:
111 				continue;
112 		}
113 		rng_addr = (uint64_t)(rangep->parent_high &
114 		    px_ranges_phi_mask) << 32;
115 		rng_addr |= (uint64_t)rangep->parent_low;
116 		rng_size = (uint64_t)rangep->size_high << 32;
117 		rng_size |= (uint64_t)rangep->size_low;
118 
119 		*pfnbp = mmu_btop(rng_addr);
120 		*pfnlp = mmu_btop(rng_addr + rng_size);
121 	}
122 
123 	/*
124 	 * This lock is for serializing safe acc calls. It is not associated
125 	 * with an iblock cookie.
126 	 */
127 	mutex_init(&pec_p->pec_pokefault_mutex, NULL, MUTEX_DRIVER, NULL);
128 
129 	return (DDI_SUCCESS);
130 }
131 
132 void
133 px_pec_detach(px_t *px_p)
134 {
135 	dev_info_t *dip = px_p->px_dip;
136 	px_pec_t *pec_p = px_p->px_pec_p;
137 
138 	/*
139 	 * Free the pokefault mutex.
140 	 */
141 	DBG(DBG_DETACH, dip, "px_pec_detach:\n");
142 	mutex_destroy(&pec_p->pec_pokefault_mutex);
143 
144 	/*
145 	 * Remove interrupt handlers to process correctable/fatal/non fatal
146 	 * PCIE messages.
147 	 */
148 	px_pec_msg_rem_intr(px_p);
149 
150 	/*
151 	 * Free the pec state structure.
152 	 */
153 	kmem_free(pec_p, sizeof (px_pec_t));
154 	px_p->px_pec_p = NULL;
155 }
156 
157 /*
158  * pec_msg_add_intr:
159  *
160  * Add interrupt handlers to process correctable/fatal/non fatal
161  * PCIE messages.
162  */
163 static int
164 px_pec_msg_add_intr(px_t *px_p)
165 {
166 	dev_info_t		*dip = px_p->px_dip;
167 	px_pec_t		*pec_p = px_p->px_pec_p;
168 	ddi_intr_handle_impl_t	hdl;
169 	int			ret = DDI_SUCCESS;
170 
171 	DBG(DBG_MSG, px_p->px_dip, "px_pec_msg_add_intr\n");
172 
173 	/* Initialize handle */
174 	bzero(&hdl, sizeof (ddi_intr_handle_impl_t));
175 	hdl.ih_cb_func = (ddi_intr_handler_t *)px_err_fabric_intr;
176 	hdl.ih_ver = DDI_INTR_VERSION;
177 	hdl.ih_state = DDI_IHDL_STATE_ALLOC;
178 	hdl.ih_dip = dip;
179 
180 	/* Add correctable error message handler */
181 	hdl.ih_pri = PX_ERR_LOW_PIL;
182 
183 	if ((ret = px_add_msiq_intr(dip, dip, &hdl,
184 	    MSG_REC, (msgcode_t)PCIE_CORR_MSG,
185 	    &pec_p->pec_corr_msg_msiq_id)) != DDI_SUCCESS) {
186 		DBG(DBG_MSG, px_p->px_dip,
187 		    "PCIE_CORR_MSG registration failed\n");
188 		return (DDI_FAILURE);
189 	}
190 
191 	px_lib_msg_setmsiq(dip, PCIE_CORR_MSG, pec_p->pec_corr_msg_msiq_id);
192 	px_lib_msg_setvalid(dip, PCIE_CORR_MSG, PCIE_MSG_VALID);
193 
194 	if ((ret = px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
195 	    px_msiqid_to_devino(px_p, pec_p->pec_corr_msg_msiq_id),
196 	    PX_ERR_LOW_PIL, PX_INTR_STATE_ENABLE, MSG_REC,
197 	    PCIE_CORR_MSG)) != DDI_SUCCESS) {
198 		DBG(DBG_MSG, px_p->px_dip,
199 		    "PCIE_CORR_MSG update interrupt state failed\n");
200 		return (DDI_FAILURE);
201 	}
202 
203 	/* Add non-fatal error message handler */
204 	hdl.ih_pri = PX_ERR_PIL;
205 
206 	if ((ret = px_add_msiq_intr(dip, dip, &hdl,
207 	    MSG_REC, (msgcode_t)PCIE_NONFATAL_MSG,
208 	    &pec_p->pec_non_fatal_msg_msiq_id)) != DDI_SUCCESS) {
209 		DBG(DBG_MSG, px_p->px_dip,
210 		    "PCIE_NONFATAL_MSG registration failed\n");
211 		return (DDI_FAILURE);
212 	}
213 
214 	px_lib_msg_setmsiq(dip, PCIE_NONFATAL_MSG,
215 	    pec_p->pec_non_fatal_msg_msiq_id);
216 	px_lib_msg_setvalid(dip, PCIE_NONFATAL_MSG, PCIE_MSG_VALID);
217 
218 	if ((ret = px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
219 	    px_msiqid_to_devino(px_p, pec_p->pec_non_fatal_msg_msiq_id),
220 	    PX_ERR_PIL, PX_INTR_STATE_ENABLE, MSG_REC,
221 	    PCIE_NONFATAL_MSG)) != DDI_SUCCESS) {
222 		DBG(DBG_MSG, px_p->px_dip,
223 		    "PCIE_NONFATAL_MSG update interrupt state failed\n");
224 		return (DDI_FAILURE);
225 	}
226 
227 	/* Add fatal error message handler */
228 	hdl.ih_pri = PX_ERR_PIL;
229 
230 	if ((ret = px_add_msiq_intr(dip, dip, &hdl,
231 	    MSG_REC, (msgcode_t)PCIE_FATAL_MSG,
232 	    &pec_p->pec_fatal_msg_msiq_id)) != DDI_SUCCESS) {
233 		DBG(DBG_MSG, px_p->px_dip,
234 		    "PCIE_FATAL_MSG registration failed\n");
235 		return (DDI_FAILURE);
236 	}
237 
238 	px_lib_msg_setmsiq(dip, PCIE_FATAL_MSG, pec_p->pec_fatal_msg_msiq_id);
239 	px_lib_msg_setvalid(dip, PCIE_FATAL_MSG, PCIE_MSG_VALID);
240 
241 	if ((ret = px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
242 	    px_msiqid_to_devino(px_p, pec_p->pec_fatal_msg_msiq_id), PX_ERR_PIL,
243 	    PX_INTR_STATE_ENABLE, MSG_REC, PCIE_FATAL_MSG)) != DDI_SUCCESS) {
244 		DBG(DBG_MSG, px_p->px_dip,
245 		    "PCIE_FATAL_MSG update interrupt state failed\n");
246 		return (DDI_FAILURE);
247 	}
248 
249 	return (ret);
250 }
251 
252 /*
253  * px_pec_msg_rem_intr:
254  *
255  * Remove interrupt handlers to process correctable/fatal/non fatal
256  * PCIE messages. For now, all these PCIe messages are mapped to
257  * same MSIQ.
258  */
259 static void
260 px_pec_msg_rem_intr(px_t *px_p)
261 {
262 	dev_info_t		*dip = px_p->px_dip;
263 	px_pec_t		*pec_p = px_p->px_pec_p;
264 	ddi_intr_handle_impl_t	hdl;
265 
266 	DBG(DBG_MSG, px_p->px_dip, "px_pec_msg_rem_intr: dip 0x%p\n", dip);
267 
268 	/* Initialize handle */
269 	bzero(&hdl, sizeof (ddi_intr_handle_impl_t));
270 	hdl.ih_ver = DDI_INTR_VERSION;
271 	hdl.ih_state = DDI_IHDL_STATE_ALLOC;
272 	hdl.ih_dip = dip;
273 
274 	/* Remove correctable error message handler */
275 	if (pec_p->pec_corr_msg_msiq_id >= 0) {
276 		px_lib_msg_setvalid(dip, PCIE_CORR_MSG, PCIE_MSG_INVALID);
277 
278 		hdl.ih_pri = PX_ERR_LOW_PIL;
279 		(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC,
280 		    PCIE_CORR_MSG, pec_p->pec_corr_msg_msiq_id);
281 
282 		(void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
283 		    px_msiqid_to_devino(px_p, pec_p->pec_corr_msg_msiq_id),
284 		    PX_ERR_LOW_PIL, PX_INTR_STATE_DISABLE, MSG_REC,
285 		    PCIE_CORR_MSG);
286 
287 		pec_p->pec_corr_msg_msiq_id = (msiqid_t)-1;
288 	}
289 
290 	/* Remove non-fatal error message handler */
291 	if (pec_p->pec_non_fatal_msg_msiq_id >= 0) {
292 		px_lib_msg_setvalid(dip, PCIE_NONFATAL_MSG,
293 		    PCIE_MSG_INVALID);
294 
295 		hdl.ih_pri = PX_ERR_PIL;
296 		(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC,
297 		    PCIE_NONFATAL_MSG, pec_p->pec_non_fatal_msg_msiq_id);
298 
299 		(void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
300 		    px_msiqid_to_devino(px_p, pec_p->pec_non_fatal_msg_msiq_id),
301 		    PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC,
302 		    PCIE_NONFATAL_MSG);
303 
304 		pec_p->pec_non_fatal_msg_msiq_id = (msiqid_t)-1;
305 	}
306 
307 	/* Remove fatal error message handler */
308 	if (pec_p->pec_fatal_msg_msiq_id >= 0) {
309 		px_lib_msg_setvalid(dip, PCIE_FATAL_MSG, PCIE_MSG_INVALID);
310 
311 		hdl.ih_pri = PX_ERR_PIL;
312 		(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC,
313 		    PCIE_FATAL_MSG, pec_p->pec_fatal_msg_msiq_id);
314 
315 		(void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
316 		    px_msiqid_to_devino(px_p, pec_p->pec_fatal_msg_msiq_id),
317 		    PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC, PCIE_FATAL_MSG);
318 
319 		pec_p->pec_fatal_msg_msiq_id = (msiqid_t)-1;
320 	}
321 }
322