xref: /titanic_50/usr/src/uts/sparc/io/pciex/pcieb_sparc.c (revision 48bc00d6814e04ff3edb32cafe7d1bc580baff68)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 /* SPARC specific code used by the pcieb driver */
27 
28 #include <sys/types.h>
29 #include <sys/ddi.h>
30 #include <sys/kmem.h>
31 #include <sys/sysmacros.h>
32 #include <sys/sunddi.h>
33 #include <sys/sunndi.h>
34 #include <sys/pcie.h>
35 #include <sys/pci_cap.h>
36 #include <sys/pcie_impl.h>
37 #include <io/pciex/pcieb.h>
38 #include "pcieb_plx.h"
39 
40 /*LINTLIBRARY*/
41 
42 /* PLX specific functions */
43 #ifdef	PX_PLX
44 static void plx_ro_disable(pcieb_devstate_t *pcieb);
45 #ifdef	PRINT_PLX_SEEPROM_CRC
46 static void pcieb_print_plx_seeprom_crc_data(pcieb_devstate_t *pcieb_p);
47 #endif /* PRINT_PLX_SEEPROM_CRC */
48 #endif /* PX_PLX */
49 
50 int
51 pcieb_plat_peekpoke(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t ctlop,
52     void *arg, void *result)
53 {
54 	return (ddi_ctlops(dip, rdip, ctlop, arg, result));
55 }
56 
57 /*ARGSUSED*/
58 void
59 pcieb_plat_attach_workaround(dev_info_t *dip)
60 {
61 }
62 
63 int
64 pcieb_plat_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
65     ddi_intr_handle_impl_t *hdlp, void *result)
66 {
67 	dev_info_t	*cdip = rdip;
68 	pci_regspec_t	*pci_rp;
69 	int		reglen, len;
70 	uint32_t	d, intr;
71 
72 	if ((intr_op == DDI_INTROP_SUPPORTED_TYPES) ||
73 	    (hdlp->ih_type != DDI_INTR_TYPE_FIXED))
74 		goto done;
75 
76 	/*
77 	 * If the interrupt-map property is defined at this
78 	 * node, it will have performed the interrupt
79 	 * translation as part of the property, so no
80 	 * rotation needs to be done.
81 	 */
82 	if (ddi_getproplen(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
83 	    "interrupt-map", &len) == DDI_PROP_SUCCESS)
84 		goto done;
85 
86 	cdip = pcie_get_my_childs_dip(dip, rdip);
87 
88 	/*
89 	 * Use the devices reg property to determine its
90 	 * PCI bus number and device number.
91 	 */
92 	if (ddi_getlongprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS,
93 	    "reg", (caddr_t)&pci_rp, &reglen) != DDI_SUCCESS)
94 		return (DDI_FAILURE);
95 
96 	intr = hdlp->ih_vector;
97 
98 	/* spin the interrupt */
99 	d = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi);
100 	if ((intr >= PCI_INTA) && (intr <= PCI_INTD))
101 		hdlp->ih_vector = ((intr - 1 + (d % 4)) % 4 + 1);
102 	else
103 		cmn_err(CE_WARN, "%s%d: %s: PCI intr=%x out of range",
104 		    ddi_driver_name(rdip), ddi_get_instance(rdip),
105 		    ddi_driver_name(dip), intr);
106 
107 	kmem_free(pci_rp, reglen);
108 
109 done:
110 	/* Pass up the request to our parent. */
111 	return (i_ddi_intr_ops(dip, rdip, intr_op, hdlp, result));
112 }
113 
114 int
115 pcieb_plat_pcishpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle)
116 {
117 	uint16_t cap_ptr;
118 	if ((PCI_CAP_LOCATE(config_handle, PCI_CAP_ID_PCI_HOTPLUG, &cap_ptr)) !=
119 	    DDI_FAILURE) {
120 		return (DDI_SUCCESS);
121 	}
122 
123 	return (DDI_FAILURE);
124 }
125 
126 /*
127  *  Disable PM on PLX. For PLX Transitioning one port on this switch to
128  *  low power causes links on other ports on the same station to die.
129  *  Due to PLX erratum #34, we can't allow the downstream device go to
130  *  non-D0 state.
131  */
132 boolean_t
133 pcieb_plat_pwr_disable(dev_info_t *dip)
134 {
135 	uint16_t vendor_id = (PCIE_DIP2UPBUS(dip)->bus_dev_ven_id) & 0xFFFF;
136 	return (IS_PLX_VENDORID(vendor_id) ? B_TRUE : B_FALSE);
137 }
138 
139 /*ARGSUSED*/
140 boolean_t
141 pcieb_plat_msi_supported(dev_info_t *dip)
142 {
143 	return (B_TRUE);
144 }
145 
146 /*ARGSUSED*/
147 void
148 pcieb_plat_intr_attach(pcieb_devstate_t *pcieb)
149 {
150 }
151 
152 /*ARGSUSED*/
153 int
154 pcieb_plat_ctlops(dev_info_t *rdip, ddi_ctl_enum_t ctlop, void *arg)
155 {
156 	return (DDI_SUCCESS);
157 }
158 
159 /*ARGSUSED*/
160 void
161 pcieb_plat_ioctl_hotplug(dev_info_t *dip, int rv, int cmd)
162 {
163 }
164 
165 void
166 pcieb_plat_initchild(dev_info_t *child)
167 {
168 	intptr_t ppd = NULL;
169 	/*
170 	 * XXX set ppd to 1 to disable iommu BDF protection on SPARC.
171 	 * It relies on unused parent private data for PCI devices.
172 	 */
173 	if (ddi_prop_exists(DDI_DEV_T_NONE, child, DDI_PROP_DONTPASS,
174 	    "dvma-share"))
175 		ppd = 1;
176 
177 	ddi_set_parent_data(child, (void *)ppd);
178 }
179 
180 void
181 pcieb_plat_uninitchild(dev_info_t *child)
182 {
183 	/*
184 	 * XXX Clear parent private data used as a flag to disable
185 	 * iommu BDF protection
186 	 */
187 	if ((intptr_t)ddi_get_parent_data(child) == 1)
188 		ddi_set_parent_data(child, NULL);
189 }
190 
191 #ifdef PX_PLX
192 /*
193  * These are PLX specific workarounds needed during attach.
194  */
195 void
196 pcieb_attach_plx_workarounds(pcieb_devstate_t *pcieb)
197 {
198 	dev_info_t	*dip = pcieb->pcieb_dip;
199 	pcie_bus_t	*bus_p = PCIE_DIP2BUS(dip);
200 	ddi_acc_handle_t	config_handle = bus_p->bus_cfg_hdl;
201 	uint_t		bus_num, primary, secondary;
202 	uint8_t		dev_type = bus_p->bus_dev_type;
203 	uint16_t	vendor_id = bus_p->bus_dev_ven_id & 0xFFFF;
204 	int 		ce_mask = 0;
205 
206 	if (!IS_PLX_VENDORID(vendor_id))
207 		return;
208 
209 	/*
210 	 * Due to a PLX HW bug we need to disable the receiver error CE on all
211 	 * ports. To this end we create a property "pcie_ce_mask" with value
212 	 * set to PCIE_AER_CE_RECEIVER_ERR. The pcie module will check for this
213 	 * property before setting the AER CE mask. Be sure to honor all other
214 	 * pcie_ce_mask settings.
215 	 */
216 	ce_mask = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
217 	    "pcie_ce_mask", 0);
218 	(void) ddi_prop_update_int(DDI_DEV_T_NONE, dip,
219 	    "pcie_ce_mask", (PCIE_AER_CE_RECEIVER_ERR|ce_mask));
220 
221 	/*
222 	 * There is a bug in the PLX 8114 bridge, such that an 8-bit
223 	 * write to the secondary bus number register will corrupt an
224 	 * internal shadow copy of the primary bus number.  Reading
225 	 * out the registers and writing the same values back as
226 	 * 16-bits resolves the problem.  This bug was reported by
227 	 * PLX as errata #19.
228 	 */
229 	primary = pci_config_get8(config_handle, PCI_BCNF_PRIBUS);
230 	secondary = pci_config_get8(config_handle, PCI_BCNF_SECBUS);
231 	bus_num = (secondary << 8) | primary;
232 	pci_config_put16(config_handle, PCI_BCNF_PRIBUS, bus_num);
233 
234 	/*
235 	 * Workaround for a race condition between hotplug
236 	 * initialization and actual MSI interrupt registration
237 	 * for hotplug functionality. The hotplug initialization
238 	 * generates an INTx interrupt for hotplug events and this
239 	 * INTx interrupt may interfere with shared leaf drivers
240 	 * using same INTx interrupt, which may eventually block
241 	 * the leaf drivers.
242 	 */
243 	if ((dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN) ||
244 	    (dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) ||
245 	    (dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) ||
246 	    (dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE)) {
247 		pci_config_put16(config_handle, PCI_CONF_COMM,
248 		    pci_config_get16(config_handle, PCI_CONF_COMM) |
249 		    PCI_COMM_INTX_DISABLE);
250 	}
251 
252 	/*
253 	 * Disable PLX Special Relaxed Ordering
254 	 */
255 	plx_ro_disable(pcieb);
256 
257 #ifdef	PRINT_PLX_SEEPROM_CRC
258 	/* check seeprom CRC to ensure the platform config is right */
259 	(void) pcieb_print_plx_seeprom_crc_data(pcieb);
260 #endif /* PRINT_PLX_SEEPROM_CRC */
261 }
262 
263 /*
264  * These are PLX specific workarounds called during child's initchild.
265  */
266 int
267 pcieb_init_plx_workarounds(pcieb_devstate_t *pcieb, dev_info_t *child)
268 {
269 	int		i;
270 	int		result = DDI_FAILURE;
271 	uint16_t	reg = 0;
272 	ddi_acc_handle_t	config_handle;
273 	uint16_t	vendor_id =
274 	    (PCIE_DIP2UPBUS(pcieb->pcieb_dip))->bus_dev_ven_id & 0xFFFF;
275 
276 	if (!IS_PLX_VENDORID(vendor_id))
277 		return (DDI_SUCCESS);
278 
279 	/*
280 	 * Due to a PLX HW bug, a SW workaround to prevent the chip from
281 	 * wedging is needed.  SW just needs to tranfer 64 TLPs from
282 	 * the downstream port to the child device.
283 	 * The most benign way of doing this is to read the ID register
284 	 * 64 times.  This SW workaround should have minimum performance
285 	 * impact and shouldn't cause a problem for all other bridges
286 	 * and switches.
287 	 *
288 	 * The code needs to be written in a way to make sure it isn't
289 	 * optimized out.
290 	 */
291 	if (!pxb_tlp_count) {
292 		result = DDI_SUCCESS;
293 		goto done;
294 	}
295 
296 	if (pci_config_setup(child, &config_handle) != DDI_SUCCESS) {
297 		result = DDI_FAILURE;
298 		goto done;
299 	}
300 
301 	for (i = 0; i < pxb_tlp_count; i += 1)
302 		reg |= pci_config_get16(config_handle, PCI_CONF_VENID);
303 
304 	if (PCIE_IS_PCIE_BDG(PCIE_DIP2BUS(pcieb->pcieb_dip)))
305 		pcieb_set_pci_perf_parameters(child, config_handle);
306 
307 	pci_config_teardown(&config_handle);
308 	result = DDI_SUCCESS;
309 done:
310 	return (result);
311 }
312 
313 /*
314  * Disable PLX specific relaxed ordering mode.	Due to PLX
315  * erratum #6, use of this mode with Cut-Through Cancellation
316  * can result in dropped Completion type packets.
317  *
318  * Clear the Relaxed Ordering Mode on 8533 and 8548 switches.
319  * To disable RO, clear bit 5 in offset 0x664, an undocumented
320  * bit in the PLX spec, on Ports 0, 8 and 12.  Proprietary PLX
321  * registers are normally accessible only via memspace from Port
322  * 0.  If port 0 is attached go ahead and disable RO on Port 0,
323  * 8 and 12, if they exist.
324  */
325 static void
326 plx_ro_disable(pcieb_devstate_t *pcieb)
327 {
328 	pcie_bus_t		*bus_p = PCIE_DIP2BUS(pcieb->pcieb_dip);
329 	dev_info_t		*dip = pcieb->pcieb_dip;
330 	uint16_t		device_id = bus_p->bus_dev_ven_id >> 16;
331 	pci_regspec_t		*reg_spec, *addr_spec;
332 	int			rlen, alen;
333 	int			orig_rsize, new_rsize;
334 	uint_t			rnum, anum;
335 	ddi_device_acc_attr_t	attr;
336 	ddi_acc_handle_t	hdl;
337 	caddr_t			regsp;
338 	uint32_t		val, port_enable;
339 	char			*offset;
340 	char			*port_offset;
341 
342 	if (!((device_id == PXB_DEVICE_PLX_8533) ||
343 	    (device_id == PXB_DEVICE_PLX_8548)))
344 		return;
345 
346 	/* You can also only do this on Port 0 */
347 	val = PCIE_CAP_GET(32, bus_p, PCIE_LINKCAP);
348 	val = (val >> PCIE_LINKCAP_PORT_NUMBER_SHIFT) &
349 	    PCIE_LINKCAP_PORT_NUMBER_MASK;
350 
351 	PCIEB_DEBUG(DBG_ATTACH, dip, "PLX RO Disable : bdf=0x%x port=%d\n",
352 	    bus_p->bus_bdf, val);
353 
354 	if (val != 0)
355 		return;
356 
357 	/*
358 	 * Read the reg property, but allocate extra space incase we need to add
359 	 * a new entry later.
360 	 */
361 	if (ddi_getproplen(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "reg",
362 	    &orig_rsize) != DDI_SUCCESS)
363 		return;
364 
365 	new_rsize = orig_rsize + sizeof (pci_regspec_t);
366 	reg_spec = kmem_alloc(new_rsize, KM_SLEEP);
367 
368 	if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "reg",
369 	    (caddr_t)reg_spec, &orig_rsize) != DDI_SUCCESS)
370 		goto fail;
371 
372 	/* Find the mem32 reg property */
373 	rlen = orig_rsize / sizeof (pci_regspec_t);
374 	for (rnum = 0; rnum < rlen; rnum++) {
375 		if ((reg_spec[rnum].pci_phys_hi & PCI_ADDR_MASK) ==
376 		    PCI_ADDR_MEM32)
377 			goto fix;
378 	}
379 
380 	/*
381 	 * Mem32 reg property was not found.
382 	 * Look for it in assign-address property.
383 	 */
384 	addr_spec = bus_p->bus_assigned_addr;
385 	alen = bus_p->bus_assigned_entries;
386 	for (anum = 0; anum < alen; anum++) {
387 		if ((addr_spec[anum].pci_phys_hi & PCI_ADDR_MASK) ==
388 		    PCI_ADDR_MEM32)
389 			goto update;
390 	}
391 
392 	/* Unable to find mem space assigned address, give up. */
393 	goto fail;
394 
395 update:
396 	/*
397 	 * Add the mem32 access to the reg spec.
398 	 * Use the last entry which was previously allocated.
399 	 */
400 	reg_spec[rnum].pci_phys_hi = (addr_spec[anum].pci_phys_hi &
401 	    ~PCI_REG_REL_M);
402 	reg_spec[rnum].pci_phys_mid = 0;
403 	reg_spec[rnum].pci_phys_low = 0;
404 	reg_spec[rnum].pci_size_hi = addr_spec[anum].pci_size_hi;
405 	reg_spec[rnum].pci_size_low = addr_spec[anum].pci_size_low;
406 
407 	/* Create the new reg_spec data and update the property */
408 	if (ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg",
409 	    (int *)reg_spec, (new_rsize / sizeof (int))) != DDI_SUCCESS)
410 		goto fail;
411 
412 fix:
413 	attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
414 	attr.devacc_attr_endian_flags  = DDI_STRUCTURE_LE_ACC;
415 	attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
416 
417 	if (ddi_regs_map_setup(dip, rnum, &regsp, 0, 0, &attr,
418 	    &hdl) != DDI_SUCCESS)
419 		goto fail;
420 
421 	/* Grab register which shows which ports are enabled */
422 	offset = (char *)regsp + PLX_INGRESS_PORT_ENABLE;
423 	port_enable = ddi_get32(hdl, (uint32_t *)offset);
424 
425 	if ((port_enable == 0xFFFFFFFF) || (port_enable == 0))
426 		goto done;
427 
428 	offset = (char *)regsp + PLX_INGRESS_CONTROL_SHADOW;
429 
430 	/* Disable RO on Port 0 */
431 	port_offset = 0x0 + offset;
432 	val = ddi_get32(hdl, (uint32_t *)port_offset);
433 	if (val & PLX_RO_MODE_BIT)
434 		val ^= PLX_RO_MODE_BIT;
435 	ddi_put32(hdl, (uint32_t *)port_offset, val);
436 
437 	/* Disable RO on Port 8, but make sure its enabled */
438 	if (!(port_enable & (1 << 8)))
439 		goto port12;
440 
441 	port_offset = (8 * 0x1000) + offset;
442 	val = ddi_get32(hdl, (uint32_t *)port_offset);
443 	if (val & PLX_RO_MODE_BIT)
444 		val ^= PLX_RO_MODE_BIT;
445 	ddi_put32(hdl, (uint32_t *)port_offset, val);
446 
447 port12:
448 	/* Disable RO on Port 12, but make sure it exists */
449 	if (!(port_enable & (1 << 12)))
450 		goto done;
451 
452 	port_offset = (12 * 0x1000) + offset;
453 	val = ddi_get32(hdl, (uint32_t *)port_offset);
454 	if (val & PLX_RO_MODE_BIT)
455 		val ^= PLX_RO_MODE_BIT;
456 	ddi_put32(hdl, (uint32_t *)port_offset, val);
457 
458 	goto done;
459 
460 done:
461 	ddi_regs_map_free(&hdl);
462 fail:
463 	kmem_free(reg_spec, new_rsize);
464 }
465 
466 #ifdef	PRINT_PLX_SEEPROM_CRC
467 static void
468 pcieb_print_plx_seeprom_crc_data(pcieb_devstate_t *pcieb_p)
469 {
470 	ddi_acc_handle_t h;
471 	dev_info_t *dip = pcieb_p->pcieb_dip;
472 	uint16_t vendorid = (PCIE_DIP2BUS(dip)->bus_dev_ven_id) & 0xFFFF;
473 	int nregs;
474 	caddr_t mp;
475 	off_t bar_size;
476 	ddi_device_acc_attr_t mattr = {
477 		DDI_DEVICE_ATTR_V0,
478 		DDI_STRUCTURE_LE_ACC,
479 		DDI_STRICTORDER_ACC
480 	};
481 	uint32_t addr_reg_off = 0x260, data_reg_off = 0x264, data = 0x6BE4;
482 
483 	if (vendorid != PXB_VENDOR_PLX)
484 		return;
485 	if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS)
486 		return;
487 	if (nregs < 2)	/* check for CONF entry only, no BARs */
488 		return;
489 	if (ddi_dev_regsize(dip, 1, &bar_size) != DDI_SUCCESS)
490 		return;
491 	if (ddi_regs_map_setup(dip, 1, (caddr_t *)&mp, 0, bar_size,
492 	    &mattr, &h) != DDI_SUCCESS)
493 		return;
494 	ddi_put32(h, (uint32_t *)((uchar_t *)mp + addr_reg_off), data);
495 	delay(drv_usectohz(1000000));
496 	printf("%s#%d: EEPROM StatusReg = %x, CRC = %x\n",
497 	    ddi_driver_name(dip), ddi_get_instance(dip),
498 	    ddi_get32(h, (uint32_t *)((uchar_t *)mp + addr_reg_off)),
499 	    ddi_get32(h, (uint32_t *)((uchar_t *)mp + data_reg_off)));
500 #ifdef PLX_HOT_RESET_DISABLE
501 	/* prevent hot reset from propogating downstream. */
502 	data = ddi_get32(h, (uint32_t *)((uchar_t *)mp + 0x1DC));
503 	ddi_put32(h, (uint32_t *)((uchar_t *)mp + 0x1DC), data | 0x80000);
504 	delay(drv_usectohz(1000000));
505 	printf("%s#%d: EEPROM 0x1DC prewrite=%x postwrite=%x\n",
506 	    ddi_driver_name(dip), ddi_get_instance(dip), data,
507 	    ddi_get32(h, (uint32_t *)((uchar_t *)mp + 0x1DC)));
508 #endif /* PLX_HOT_RESET_DISABLE */
509 	ddi_regs_map_free(&h);
510 }
511 #endif /* PRINT_PLX_SEEPROM_CRC */
512 #endif /* PX_PLX */
513