1 /* BEGIN CSTYLED */ 2 3 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 4 */ 5 /* 6 * 7 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 8 * All Rights Reserved. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a 11 * copy of this software and associated documentation files (the 12 * "Software"), to deal in the Software without restriction, including 13 * without limitation the rights to use, copy, modify, merge, publish, 14 * distribute, sub license, and/or sell copies of the Software, and to 15 * permit persons to whom the Software is furnished to do so, subject to 16 * the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 23 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 25 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 26 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 27 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 28 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 29 * 30 */ 31 32 /* 33 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 34 * Use is subject to license terms. 35 */ 36 37 #ifndef _I915_DRV_H 38 #define _I915_DRV_H 39 40 /* General customization: 41 */ 42 43 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 44 45 #define DRIVER_NAME "i915" 46 #define DRIVER_DESC "Intel Graphics" 47 #define DRIVER_DATE "20060929" 48 49 #if defined(__SVR4) && defined(__sun) 50 #define spinlock_t kmutex_t 51 #endif 52 53 /* Interface history: 54 * 55 * 1.1: Original. 56 * 1.2: Add Power Management 57 * 1.3: Add vblank support 58 * 1.4: Fix cmdbuffer path, add heap destroy 59 */ 60 #define DRIVER_MAJOR 1 61 #define DRIVER_MINOR 4 62 #define DRIVER_PATCHLEVEL 0 63 64 #if defined(__linux__) 65 #define I915_HAVE_FENCE 66 #define I915_HAVE_BUFFER 67 #endif 68 69 typedef struct _drm_i915_ring_buffer { 70 int tail_mask; 71 unsigned long Start; 72 unsigned long End; 73 unsigned long Size; 74 u8 *virtual_start; 75 int head; 76 int tail; 77 int space; 78 drm_local_map_t map; 79 } drm_i915_ring_buffer_t; 80 81 struct mem_block { 82 struct mem_block *next; 83 struct mem_block *prev; 84 int start; 85 int size; 86 drm_file_t *filp; /* 0: free, -1: heap, other: real files */ 87 }; 88 89 typedef struct _drm_i915_vbl_swap { 90 struct list_head head; 91 drm_drawable_t drw_id; 92 unsigned int pipe; 93 unsigned int sequence; 94 } drm_i915_vbl_swap_t; 95 96 typedef struct s3_i915_private { 97 ddi_acc_handle_t saveHandle; 98 caddr_t saveAddr; 99 uint32_t pgtbl_ctl; 100 uint8_t saveLBB; 101 uint32_t saveDSPACNTR; 102 uint32_t saveDSPBCNTR; 103 uint32_t saveDSPARB; 104 uint32_t savePIPEACONF; 105 uint32_t savePIPEBCONF; 106 uint32_t savePIPEASRC; 107 uint32_t savePIPEBSRC; 108 uint32_t saveFPA0; 109 uint32_t saveFPA1; 110 uint32_t saveDPLL_A; 111 uint32_t saveDPLL_A_MD; 112 uint32_t saveHTOTAL_A; 113 uint32_t saveHBLANK_A; 114 uint32_t saveHSYNC_A; 115 uint32_t saveVTOTAL_A; 116 uint32_t saveVBLANK_A; 117 uint32_t saveVSYNC_A; 118 uint32_t saveBCLRPAT_A; 119 uint32_t saveDSPASTRIDE; 120 uint32_t saveDSPASIZE; 121 uint32_t saveDSPAPOS; 122 uint32_t saveDSPABASE; 123 uint32_t saveDSPASURF; 124 uint32_t saveDSPATILEOFF; 125 uint32_t savePFIT_PGM_RATIOS; 126 uint32_t saveBLC_PWM_CTL; 127 uint32_t saveBLC_PWM_CTL2; 128 uint32_t saveFPB0; 129 uint32_t saveFPB1; 130 uint32_t saveDPLL_B; 131 uint32_t saveDPLL_B_MD; 132 uint32_t saveHTOTAL_B; 133 uint32_t saveHBLANK_B; 134 uint32_t saveHSYNC_B; 135 uint32_t saveVTOTAL_B; 136 uint32_t saveVBLANK_B; 137 uint32_t saveVSYNC_B; 138 uint32_t saveBCLRPAT_B; 139 uint32_t saveDSPBSTRIDE; 140 uint32_t saveDSPBSIZE; 141 uint32_t saveDSPBPOS; 142 uint32_t saveDSPBBASE; 143 uint32_t saveDSPBSURF; 144 uint32_t saveDSPBTILEOFF; 145 uint32_t saveVCLK_DIVISOR_VGA0; 146 uint32_t saveVCLK_DIVISOR_VGA1; 147 uint32_t saveVCLK_POST_DIV; 148 uint32_t saveVGACNTRL; 149 uint32_t saveADPA; 150 uint32_t saveLVDS; 151 uint32_t saveLVDSPP_ON; 152 uint32_t saveLVDSPP_OFF; 153 uint32_t saveDVOA; 154 uint32_t saveDVOB; 155 uint32_t saveDVOC; 156 uint32_t savePP_ON; 157 uint32_t savePP_OFF; 158 uint32_t savePP_CONTROL; 159 uint32_t savePP_CYCLE; 160 uint32_t savePFIT_CONTROL; 161 uint32_t save_palette_a[256]; 162 uint32_t save_palette_b[256]; 163 uint32_t saveFBC_CFB_BASE; 164 uint32_t saveFBC_LL_BASE; 165 uint32_t saveFBC_CONTROL; 166 uint32_t saveFBC_CONTROL2; 167 uint32_t saveIER; 168 uint32_t saveIIR; 169 uint32_t saveIMR; 170 uint32_t saveD_STATE; 171 uint32_t saveCG_2D_DIS; 172 uint32_t saveMI_ARB_STATE; 173 uint32_t savePIPEASTAT; 174 uint32_t savePIPEBSTAT; 175 uint32_t saveCACHE_MODE_0; 176 uint32_t saveSWF0[16]; 177 uint32_t saveSWF1[16]; 178 uint32_t saveSWF2[3]; 179 uint8_t saveMSR; 180 uint8_t saveSR[8]; 181 uint8_t saveGR[25]; 182 uint8_t saveAR_INDEX; 183 uint8_t saveAR[21]; 184 uint8_t saveDACMASK; 185 uint8_t saveDACDATA[256*3]; /* 256 3-byte colors */ 186 uint8_t saveCR[37]; 187 } s3_i915_private_t; 188 189 typedef struct drm_i915_private { 190 drm_local_map_t *sarea; 191 drm_local_map_t *mmio_map; 192 193 drm_i915_sarea_t *sarea_priv; 194 drm_i915_ring_buffer_t ring; 195 196 drm_dma_handle_t *status_page_dmah; 197 void *hw_status_page; 198 dma_addr_t dma_status_page; 199 uint32_t counter; 200 unsigned int status_gfx_addr; 201 drm_local_map_t hws_map; 202 203 unsigned int cpp; 204 int back_offset; 205 int front_offset; 206 int current_page; 207 int page_flipping; 208 int use_mi_batchbuffer_start; 209 210 wait_queue_head_t irq_queue; 211 atomic_t irq_received; 212 atomic_t irq_emitted; 213 214 int tex_lru_log_granularity; 215 int allow_batchbuffer; 216 struct mem_block *agp_heap; 217 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 218 int vblank_pipe; 219 spinlock_t user_irq_lock; 220 int user_irq_refcount; 221 int fence_irq_on; 222 uint32_t irq_enable_reg; 223 int irq_enabled; 224 225 #ifdef I915_HAVE_FENCE 226 uint32_t flush_sequence; 227 uint32_t flush_flags; 228 uint32_t flush_pending; 229 uint32_t saved_flush_status; 230 #endif 231 #ifdef I915_HAVE_BUFFER 232 void *agp_iomap; 233 #endif 234 spinlock_t swaps_lock; 235 drm_i915_vbl_swap_t vbl_swaps; 236 unsigned int swaps_pending; 237 238 } drm_i915_private_t; 239 240 enum intel_chip_family { 241 CHIP_I8XX = 0x01, 242 CHIP_I9XX = 0x02, 243 CHIP_I915 = 0x04, 244 CHIP_I965 = 0x08, 245 }; 246 247 extern drm_ioctl_desc_t i915_ioctls[]; 248 extern int i915_max_ioctl; 249 250 /* i915_dma.c */ 251 extern void i915_kernel_lost_context(drm_device_t * dev); 252 extern int i915_driver_load(struct drm_device *, unsigned long flags); 253 extern int i915_driver_unload(struct drm_device *dev); 254 extern void i915_driver_lastclose(drm_device_t * dev); 255 extern void i915_driver_preclose(drm_device_t * dev, drm_file_t *filp); 256 extern int i915_driver_device_is_agp(drm_device_t * dev); 257 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 258 unsigned long arg); 259 extern int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush); 260 261 262 /* i915_irq.c */ 263 extern int i915_irq_emit(DRM_IOCTL_ARGS); 264 extern int i915_irq_wait(DRM_IOCTL_ARGS); 265 266 extern int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); 267 extern int i915_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence); 268 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 269 extern void i915_driver_irq_preinstall(drm_device_t * dev); 270 extern void i915_driver_irq_postinstall(drm_device_t * dev); 271 extern void i915_driver_irq_uninstall(drm_device_t * dev); 272 extern int i915_emit_irq(drm_device_t * dev); 273 extern void i915_user_irq_on(drm_i915_private_t *dev_priv); 274 extern void i915_user_irq_off(drm_i915_private_t *dev_priv); 275 276 /* i915_mem.c */ 277 extern int i915_mem_alloc(DRM_IOCTL_ARGS); 278 extern int i915_mem_free(DRM_IOCTL_ARGS); 279 extern int i915_mem_init_heap(DRM_IOCTL_ARGS); 280 extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS); 281 extern void i915_mem_takedown(struct mem_block **heap); 282 extern void i915_mem_release(drm_device_t * dev, 283 drm_file_t *filp, struct mem_block *heap); 284 extern struct mem_block **get_heap(drm_i915_private_t *, int); 285 extern struct mem_block *find_block_by_proc(struct mem_block *, drm_file_t *); 286 extern void mark_block(drm_device_t *, struct mem_block *, int); 287 extern void free_block(struct mem_block *); 288 289 #ifdef I915_HAVE_FENCE 290 /* i915_fence.c */ 291 292 293 extern void i915_fence_handler(drm_device_t *dev); 294 extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t class, 295 uint32_t flags, 296 uint32_t *sequence, 297 uint32_t *native_type); 298 extern void i915_poke_flush(drm_device_t *dev, uint32_t class); 299 extern int i915_fence_has_irq(drm_device_t *dev, uint32_t class, uint32_t flags); 300 #endif 301 302 #ifdef I915_HAVE_BUFFER 303 /* i915_buffer.c */ 304 extern drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t *dev); 305 extern int i915_fence_types(drm_buffer_object_t *bo, uint32_t *class, uint32_t *type); 306 extern int i915_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags); 307 extern int i915_init_mem_type(drm_device_t *dev, uint32_t type, 308 drm_mem_type_manager_t *man); 309 extern uint32_t i915_evict_mask(drm_buffer_object_t *bo); 310 extern int i915_move(drm_buffer_object_t *bo, int evict, 311 int no_wait, drm_bo_mem_reg_t *new_mem); 312 313 #endif 314 315 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 316 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 317 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 318 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 319 #define S3_READ(reg) \ 320 *(uint32_t volatile *)((uintptr_t)s3_priv->saveAddr + (reg)) 321 #define S3_WRITE(reg, val) \ 322 *(uint32_t volatile *)((uintptr_t)s3_priv->saveAddr + (reg)) = (val) 323 324 #define RING_LOCALS unsigned int outring, ringmask, outcount; \ 325 volatile unsigned char *virt; 326 327 #define BEGIN_LP_RING(n) do { \ 328 if (dev_priv->ring.space < (n)*4) \ 329 (void) i915_wait_ring(dev, (n)*4, __FUNCTION__); \ 330 outcount = 0; \ 331 outring = dev_priv->ring.tail; \ 332 ringmask = dev_priv->ring.tail_mask; \ 333 virt = dev_priv->ring.virtual_start; \ 334 } while (*"\0") 335 336 #define OUT_RING(n) do { \ 337 *(volatile unsigned int *)(void *)(virt + outring) = (n); \ 338 outcount++; \ 339 outring += 4; \ 340 outring &= ringmask; \ 341 } while (*"\0") 342 343 #define ADVANCE_LP_RING() do { \ 344 dev_priv->ring.tail = outring; \ 345 dev_priv->ring.space -= outcount * 4; \ 346 I915_WRITE(LP_RING + RING_TAIL, outring); \ 347 } while (*"\0") 348 349 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller); 350 351 /* Extended config space */ 352 #define LBB 0xf4 353 354 /* VGA stuff */ 355 356 #define VGA_ST01_MDA 0x3ba 357 #define VGA_ST01_CGA 0x3da 358 359 #define VGA_MSR_WRITE 0x3c2 360 #define VGA_MSR_READ 0x3cc 361 #define VGA_MSR_MEM_EN (1<<1) 362 #define VGA_MSR_CGA_MODE (1<<0) 363 364 #define VGA_SR_INDEX 0x3c4 365 #define VGA_SR_DATA 0x3c5 366 367 #define VGA_AR_INDEX 0x3c0 368 #define VGA_AR_VID_EN (1<<5) 369 #define VGA_AR_DATA_WRITE 0x3c0 370 #define VGA_AR_DATA_READ 0x3c1 371 372 #define VGA_GR_INDEX 0x3ce 373 #define VGA_GR_DATA 0x3cf 374 /* GR05 */ 375 #define VGA_GR_MEM_READ_MODE_SHIFT 3 376 #define VGA_GR_MEM_READ_MODE_PLANE 1 377 /* GR06 */ 378 #define VGA_GR_MEM_MODE_MASK 0xc 379 #define VGA_GR_MEM_MODE_SHIFT 2 380 #define VGA_GR_MEM_A0000_AFFFF 0 381 #define VGA_GR_MEM_A0000_BFFFF 1 382 #define VGA_GR_MEM_B0000_B7FFF 2 383 #define VGA_GR_MEM_B0000_BFFFF 3 384 385 #define VGA_DACMASK 0x3c6 386 #define VGA_DACRX 0x3c7 387 #define VGA_DACWX 0x3c8 388 #define VGA_DACDATA 0x3c9 389 390 #define VGA_CR_INDEX_MDA 0x3b4 391 #define VGA_CR_DATA_MDA 0x3b5 392 #define VGA_CR_INDEX_CGA 0x3d4 393 #define VGA_CR_DATA_CGA 0x3d5 394 395 396 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 397 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) 398 #define CMD_REPORT_HEAD (7<<23) 399 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) 400 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) 401 402 #define INST_PARSER_CLIENT 0x00000000 403 #define INST_OP_FLUSH 0x02000000 404 #define INST_FLUSH_MAP_CACHE 0x00000001 405 406 #define CMD_MI_FLUSH (0x04 << 23) 407 #define MI_NO_WRITE_FLUSH (1 << 2) 408 #define MI_READ_FLUSH (1 << 0) 409 #define MI_EXE_FLUSH (1 << 1) 410 411 #define BB1_START_ADDR_MASK (~0x7) 412 #define BB1_PROTECTED (1<<0) 413 #define BB1_UNPROTECTED (0<<0) 414 #define BB2_END_ADDR_MASK (~0x7) 415 416 #define I915REG_PGTBL_CTRL 0x2020 417 #define I915REG_HWSTAM 0x02098 418 #define I915REG_INT_IDENTITY_R 0x020a4 419 #define I915REG_INT_MASK_R 0x020a8 420 #define I915REG_INT_ENABLE_R 0x020a0 421 #define I915REG_INSTPM 0x020c0 422 423 #define I915REG_PIPEASTAT 0x70024 424 #define I915REG_PIPEBSTAT 0x71024 425 426 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) 427 #define I915_VBLANK_CLEAR (1UL<<1) 428 429 #define SRX_INDEX 0x3c4 430 #define SRX_DATA 0x3c5 431 #define SR01 1 432 #define SR01_SCREEN_OFF (1<<5) 433 434 #define PPCR 0x61204 435 #define PPCR_ON (1<<0) 436 437 #define DVOB 0x61140 438 #define DVOB_ON (1<<31) 439 #define DVOC 0x61160 440 #define DVOC_ON (1<<31) 441 #define LVDS 0x61180 442 #define LVDS_ON (1<<31) 443 444 #define ADPA 0x61100 445 #define ADPA_DPMS_MASK (~(3<<10)) 446 #define ADPA_DPMS_ON (0<<10) 447 #define ADPA_DPMS_SUSPEND (1<<10) 448 #define ADPA_DPMS_STANDBY (2<<10) 449 #define ADPA_DPMS_OFF (3<<10) 450 451 #ifdef NOPID 452 #undef NOPID 453 #endif 454 #define NOPID 0x2094 455 #define LP_RING 0x2030 456 #define HP_RING 0x2040 457 #define RING_TAIL 0x00 458 #define TAIL_ADDR 0x001FFFF8 459 #define RING_HEAD 0x04 460 #define HEAD_WRAP_COUNT 0xFFE00000 461 #define HEAD_WRAP_ONE 0x00200000 462 #define HEAD_ADDR 0x001FFFFC 463 #define RING_START 0x08 464 #define START_ADDR 0x0xFFFFF000 465 #define RING_LEN 0x0C 466 #define RING_NR_PAGES 0x001FF000 467 #define RING_REPORT_MASK 0x00000006 468 #define RING_REPORT_64K 0x00000002 469 #define RING_REPORT_128K 0x00000004 470 #define RING_NO_REPORT 0x00000000 471 #define RING_VALID_MASK 0x00000001 472 #define RING_VALID 0x00000001 473 #define RING_INVALID 0x00000000 474 475 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 476 #define SC_UPDATE_SCISSOR (0x1<<1) 477 #define SC_ENABLE_MASK (0x1<<0) 478 #define SC_ENABLE (0x1<<0) 479 480 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 481 #define SCI_YMIN_MASK (0xffff<<16) 482 #define SCI_XMIN_MASK (0xffff<<0) 483 #define SCI_YMAX_MASK (0xffff<<16) 484 #define SCI_XMAX_MASK (0xffff<<0) 485 486 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 487 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 488 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 489 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 490 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 491 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 492 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 493 494 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 495 496 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 497 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 498 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 499 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 500 501 #define MI_BATCH_BUFFER ((0x30<<23)|1) 502 #define MI_BATCH_BUFFER_START (0x31<<23) 503 #define MI_BATCH_BUFFER_END (0xA<<23) 504 #define MI_BATCH_NON_SECURE (1) 505 506 #define MI_WAIT_FOR_EVENT ((0x3<<23)) 507 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 508 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 509 510 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) 511 512 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 513 #define ASYNC_FLIP (1<<22) 514 515 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 516 517 #define BREADCRUMB_OFFSET 32 /* dword offset 20h */ 518 #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[BREADCRUMB_OFFSET]) 519 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 520 521 /* 522 * add here for S3 support 523 */ 524 #define DPLL_A 0x06014 525 #define DPLL_B 0x06018 526 # define DPLL_VCO_ENABLE 0x80000000 /* (1 << 31) */ 527 # define DPLL_DVO_HIGH_SPEED (1 << 30) 528 # define DPLL_SYNCLOCK_ENABLE (1 << 29) 529 # define DPLL_VGA_MODE_DIS (1 << 28) 530 # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 531 # define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 532 # define DPLL_MODE_MASK (3 << 26) 533 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 534 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 535 # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 536 # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 537 # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 538 # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 539 540 /** 541 * The i830 generation, in DAC/serial mode, defines p1 as two plus this 542 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. 543 */ 544 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 545 /** 546 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 547 * this field (only one bit may be set). 548 */ 549 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 550 # define DPLL_FPA01_P1_POST_DIV_SHIFT 16 551 # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */ 552 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 553 # define PLL_REF_INPUT_DREFCLK (0 << 13) 554 # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 555 # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 556 # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 557 # define PLL_REF_INPUT_MASK (3 << 13) 558 # define PLL_LOAD_PULSE_PHASE_SHIFT 9 559 /* 560 * Parallel to Serial Load Pulse phase selection. 561 * Selects the phase for the 10X DPLL clock for the PCIe 562 * digital display port. The range is 4 to 13; 10 or more 563 * is just a flip delay. The default is 6 564 */ 565 # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 566 # define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 567 568 /** 569 * SDVO multiplier for 945G/GM. Not used on 965. 570 * 571 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 572 */ 573 # define SDVO_MULTIPLIER_MASK 0x000000ff 574 # define SDVO_MULTIPLIER_SHIFT_HIRES 4 575 # define SDVO_MULTIPLIER_SHIFT_VGA 0 576 577 /** @defgroup DPLL_MD 578 * @{ 579 */ 580 /** Pipe A SDVO/UDI clock multiplier/divider register for G965. */ 581 #define DPLL_A_MD 0x0601c 582 /** Pipe B SDVO/UDI clock multiplier/divider register for G965. */ 583 #define DPLL_B_MD 0x06020 584 /** 585 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 586 * 587 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 588 */ 589 # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 590 # define DPLL_MD_UDI_DIVIDER_SHIFT 24 591 /** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 592 # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 593 # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 594 /** 595 * SDVO/UDI pixel multiplier. 596 * 597 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 598 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 599 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 600 * dummy bytes in the datastream at an increased clock rate, with both sides of 601 * the link knowing how many bytes are fill. 602 * 603 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 604 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 605 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 606 * through an SDVO command. 607 * 608 * This register field has values of multiplication factor minus 1, with 609 * a maximum multiplier of 5 for SDVO. 610 */ 611 # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 612 # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 613 /** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 614 * This best be set to the default value (3) or the CRT won't work. No, 615 * I don't entirely understand what this does... 616 */ 617 # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 618 # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 619 /** @} */ 620 621 #define DPLL_TEST 0x606c 622 # define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 623 # define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 624 # define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 625 # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 626 # define DPLLB_TEST_N_BYPASS (1 << 19) 627 # define DPLLB_TEST_M_BYPASS (1 << 18) 628 # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 629 # define DPLLA_TEST_N_BYPASS (1 << 3) 630 # define DPLLA_TEST_M_BYPASS (1 << 2) 631 # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 632 633 /* 634 * Palette registers 635 */ 636 #define PALETTE_A 0x0a000 637 #define PALETTE_B 0x0a800 638 639 #define FPA0 0x06040 640 #define FPA1 0x06044 641 #define FPB0 0x06048 642 #define FPB1 0x0604c 643 644 #define D_STATE 0x6104 645 #define CG_2D_DIS 0x6200 646 #define CG_3D_DIS 0x6204 647 648 #define MI_ARB_STATE 0x20e4 649 650 /* 651 * Cache mode 0 reg. 652 * - Manipulating render cache behaviour is central 653 * to the concept of zone rendering, tuning this reg can help avoid 654 * unnecessary render cache reads and even writes (for z/stencil) 655 * at beginning and end of scene. 656 * 657 * - To change a bit, write to this reg with a mask bit set and the 658 * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set. 659 */ 660 #define CACHE_MODE_0 0x2120 661 662 /* I830 CRTC registers */ 663 #define HTOTAL_A 0x60000 664 #define HBLANK_A 0x60004 665 #define HSYNC_A 0x60008 666 #define VTOTAL_A 0x6000c 667 #define VBLANK_A 0x60010 668 #define VSYNC_A 0x60014 669 #define PIPEASRC 0x6001c 670 #define BCLRPAT_A 0x60020 671 #define VSYNCSHIFT_A 0x60028 672 673 #define HTOTAL_B 0x61000 674 #define HBLANK_B 0x61004 675 #define HSYNC_B 0x61008 676 #define VTOTAL_B 0x6100c 677 #define VBLANK_B 0x61010 678 #define VSYNC_B 0x61014 679 #define PIPEBSRC 0x6101c 680 #define BCLRPAT_B 0x61020 681 #define VSYNCSHIFT_B 0x61028 682 683 #define DSPACNTR 0x70180 684 #define DSPBCNTR 0x71180 685 #define DISPLAY_PLANE_ENABLE (1<<31) 686 #define DISPLAY_PLANE_DISABLE 0 687 #define DISPPLANE_GAMMA_ENABLE (1<<30) 688 #define DISPPLANE_GAMMA_DISABLE 0 689 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 690 #define DISPPLANE_8BPP (0x2<<26) 691 #define DISPPLANE_15_16BPP (0x4<<26) 692 #define DISPPLANE_16BPP (0x5<<26) 693 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 694 #define DISPPLANE_32BPP (0x7<<26) 695 #define DISPPLANE_STEREO_ENABLE (1<<25) 696 #define DISPPLANE_STEREO_DISABLE 0 697 #define DISPPLANE_SEL_PIPE_MASK (1<<24) 698 #define DISPPLANE_SEL_PIPE_A 0 699 #define DISPPLANE_SEL_PIPE_B (1<<24) 700 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 701 #define DISPPLANE_SRC_KEY_DISABLE 0 702 #define DISPPLANE_LINE_DOUBLE (1<<20) 703 #define DISPPLANE_NO_LINE_DOUBLE 0 704 #define DISPPLANE_STEREO_POLARITY_FIRST 0 705 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 706 /* plane B only */ 707 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 708 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 709 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 710 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 711 712 #define DSPABASE 0x70184 713 #define DSPASTRIDE 0x70188 714 715 #define DSPBBASE 0x71184 716 #define DSPBADDR DSPBBASE 717 #define DSPBSTRIDE 0x71188 718 719 #define DSPAKEYVAL 0x70194 720 #define DSPAKEYMASK 0x70198 721 722 #define DSPAPOS 0x7018C /* reserved */ 723 #define DSPASIZE 0x70190 724 #define DSPBPOS 0x7118C 725 #define DSPBSIZE 0x71190 726 727 #define DSPASURF 0x7019C 728 #define DSPATILEOFF 0x701A4 729 730 #define DSPBSURF 0x7119C 731 #define DSPBTILEOFF 0x711A4 732 733 #define PIPEACONF 0x70008 734 #define PIPEACONF_ENABLE (1<<31) 735 #define PIPEACONF_DISABLE 0 736 #define PIPEACONF_DOUBLE_WIDE (1<<30) 737 #define I965_PIPECONF_ACTIVE (1<<30) 738 #define PIPEACONF_SINGLE_WIDE 0 739 #define PIPEACONF_PIPE_UNLOCKED 0 740 #define PIPEACONF_PIPE_LOCKED (1<<25) 741 #define PIPEACONF_PALETTE 0 742 #define PIPEACONF_GAMMA (1<<24) 743 #define PIPECONF_FORCE_BORDER (1<<25) 744 #define PIPECONF_PROGRESSIVE (0 << 21) 745 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 746 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 747 748 #define PIPEBCONF 0x71008 749 #define PIPEBCONF_ENABLE (1<<31) 750 #define PIPEBCONF_DISABLE 0 751 #define PIPEBCONF_DOUBLE_WIDE (1<<30) 752 #define PIPEBCONF_DISABLE 0 753 #define PIPEBCONF_GAMMA (1<<24) 754 #define PIPEBCONF_PALETTE 0 755 756 #define BLC_PWM_CTL 0x61254 757 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 758 759 #define BLC_PWM_CTL2 0x61250 760 761 #define PFIT_CONTROL 0x61230 762 #define PFIT_PGM_RATIOS 0x61234 763 764 /** 765 * Indicates that all dependencies of the panel are on: 766 * 767 * - PLL enabled 768 * - pipe enabled 769 * - LVDS/DVOB/DVOC on 770 */ 771 # define PP_READY (1 << 30) # define PP_SEQUENCE_NONE (0 << 28) 772 # define PP_SEQUENCE_ON (1 << 28) # define PP_SEQUENCE_OFF (2 << 28) 773 # define PP_SEQUENCE_MASK 0x30000000 774 #define PP_CONTROL 0x61204 775 # define POWER_TARGET_ON (1 << 0) 776 777 #define LVDSPP_ON 0x61208 778 #define LVDSPP_OFF 0x6120c 779 #define PP_CYCLE 0x61210 780 781 /* Framebuffer compression */ 782 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 783 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 784 #define FBC_CONTROL 0x03208 785 786 #define VGACNTRL 0x71400 787 788 #define VCLK_DIVISOR_VGA0 0x6000 789 #define VCLK_DIVISOR_VGA1 0x6004 790 #define VCLK_POST_DIV 0x6010 791 792 /* Framebuffer compression */ 793 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 794 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 795 #define FBC_CONTROL 0x03208 796 #define FBC_CTL_EN (1<<31) 797 #define FBC_CTL_PERIODIC (1<<30) 798 #define FBC_CTL_INTERVAL_SHIFT (16) 799 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 800 #define FBC_CTL_STRIDE_SHIFT (5) 801 #define FBC_CTL_FENCENO (1<<0) #define FBC_COMMAND 0x0320c 802 #define FBC_CMD_COMPRESS (1<<0) #define FBC_STATUS 0x03210 803 #define FBC_STAT_COMPRESSING (1<<31) 804 #define FBC_STAT_COMPRESSED (1<<30) 805 #define FBC_STAT_MODIFIED (1<<29) 806 #define FBC_STAT_CURRENT_LINE (1<<0) 807 #define FBC_CONTROL2 0x03214 808 #define FBC_CTL_FENCE_DBL (0<<4) 809 #define FBC_CTL_IDLE_IMM (0<<2) 810 #define FBC_CTL_IDLE_FULL (1<<2) 811 #define FBC_CTL_IDLE_LINE (2<<2) 812 #define FBC_CTL_IDLE_DEBUG (3<<2) 813 #define FBC_CTL_CPU_FENCE (1<<1) 814 #define FBC_CTL_PLANEA (0<<0) 815 #define FBC_CTL_PLANEB (1<<0) 816 #define FBC_FENCE_OFF 0x0321b 817 818 #define FBC_LL_SIZE (1536) 819 #define FBC_LL_PAD (32) 820 821 #define DSPARB 0x70030 822 823 /* 824 * Some BIOS scratch area registers. The 845 (and 830?) store the amount 825 * of video memory available to the BIOS in SWF1. 826 */ 827 828 #define SWF0 0x71410 829 830 /* 831 * 855 scratch registers. 832 */ 833 #define SWF10 0x70410 834 835 #define SWF30 0x72414 836 837 #define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577 838 #define PCI_DEVICE_ID_INTEL_82845G_IG 0x2562 839 #define PCI_DEVICE_ID_INTEL_82855GM_IG 0x3582 840 #define PCI_DEVICE_ID_INTEL_82865_IG 0x2572 841 #define PCI_DEVICE_ID_INTEL_82915G_IG 0x2582 842 #define PCI_DEVICE_ID_INTEL_82915GM_IG 0x2592 843 #define PCI_DEVICE_ID_INTEL_82945G_IG 0x2772 844 #define PCI_DEVICE_ID_INTEL_82945GM_IG 0x27A2 845 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE 846 #define PCI_DEVICE_ID_INTEL_82946_GZ 0x2972 847 #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 848 #define PCI_DEVICE_ID_INTEL_82Q963_IG 0x2992 849 #define PCI_DEVICE_ID_INTEL_82G965_IG 0x29a2 850 #define PCI_DEVICE_ID_INTEL_GM965_IG 0x2a02 851 #define PCI_DEVICE_ID_INTEL_GME965_IG 0x2a12 852 #define PCI_DEVICE_ID_INTEL_82G33_IG 0x29c2 853 #define PCI_DEVICE_ID_INTEL_82Q35_IG 0x29b2 854 #define PCI_DEVICE_ID_INTEL_82Q33_IG 0x29d2 855 #define PCI_DEVICE_ID_INTEL_CANTIGA_IG 0x2a42 856 #define PCI_DEVICE_ID_INTEL_EL_IG 0x2e02 857 #define PCI_DEVICE_ID_INTEL_82Q45_IG 0x2e12 858 #define PCI_DEVICE_ID_INTEL_82G45_IG 0x2e22 859 860 861 #define IS_I830(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82830_CGC) 862 #define IS_845G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82845G_IG) 863 #define IS_I85X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG) 864 #define IS_I855(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG) 865 #define IS_I865G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82865_IG) 866 867 #define IS_I915G(dev) (dev->pci_device == PCI_DEVICE_ID_INTEL_82915G_IG) 868 #define IS_I915GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82915GM_IG) 869 #define IS_I945G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945G_IG) 870 #define IS_I945GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GM_IG || \ 871 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GME_IG) 872 873 #define IS_I965G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82946_GZ || \ 874 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G35_IG || \ 875 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q963_IG || \ 876 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G965_IG || \ 877 (dev)->pci_device == PCI_DEVICE_ID_INTEL_GM965_IG || \ 878 (dev)->pci_device == PCI_DEVICE_ID_INTEL_GME965_IG || \ 879 (dev)->pci_device == PCI_DEVICE_ID_INTEL_CANTIGA_IG || \ 880 (dev)->pci_device == PCI_DEVICE_ID_INTEL_EL_IG || \ 881 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q45_IG || \ 882 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G45_IG) 883 884 #define IS_I965GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_GM965_IG) 885 886 #define IS_GM45(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_CANTIGA_IG) 887 888 #define IS_G4X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_EL_IG || \ 889 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q45_IG || \ 890 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G45_IG) 891 892 #define IS_G33(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82G33_IG || \ 893 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q35_IG || \ 894 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q33_IG) 895 896 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 897 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 898 899 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 900 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev)) 901 902 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) 903 904 #endif /* _I915_DRV_H */ 905