1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/fasttrap_isa.h> 30 #include <sys/fasttrap_impl.h> 31 #include <sys/dtrace.h> 32 #include <sys/dtrace_impl.h> 33 #include <sys/cmn_err.h> 34 #include <sys/regset.h> 35 #include <sys/privregs.h> 36 #include <sys/segments.h> 37 #include <sys/sysmacros.h> 38 #include <sys/trap.h> 39 40 /* 41 * Lossless User-Land Tracing on x86 42 * --------------------------------- 43 * 44 * The execution of most instructions is not dependent on the address; for 45 * these instructions it is sufficient to copy them into the user process's 46 * address space and execute them. To effectively single-step an instruction 47 * in user-land, we copy out the following sequence of instructions to scratch 48 * space in the user thread's ulwp_t structure. 49 * 50 * We then set the program counter (%eip or %rip) to point to this scratch 51 * space. Once execution resumes, the original instruction is executed and 52 * then control flow is redirected to what was originally the subsequent 53 * instruction. If the kernel attemps to deliver a signal while single- 54 * stepping, the signal is deferred and the program counter is moved into the 55 * second sequence of instructions. The second sequence ends in a trap into 56 * the kernel where the deferred signal is then properly handled and delivered. 57 * 58 * For instructions whose execute is position dependent, we perform simple 59 * emulation. These instructions are limited to control transfer 60 * instructions in 32-bit mode, but in 64-bit mode there's the added wrinkle 61 * of %rip-relative addressing that means that almost any instruction can be 62 * position dependent. For all the details on how we emulate generic 63 * instructions included %rip-relative instructions, see the code in 64 * fasttrap_pid_probe() below where we handle instructions of type 65 * FASTTRAP_T_COMMON (under the header: Generic Instruction Tracing). 66 */ 67 68 #define FASTTRAP_MODRM_MOD(modrm) (((modrm) >> 6) & 0x3) 69 #define FASTTRAP_MODRM_REG(modrm) (((modrm) >> 3) & 0x7) 70 #define FASTTRAP_MODRM_RM(modrm) ((modrm) & 0x7) 71 #define FASTTRAP_MODRM(mod, reg, rm) (((mod) << 6) | ((reg) << 3) | (rm)) 72 73 #define FASTTRAP_SIB_SCALE(sib) (((sib) >> 6) & 0x3) 74 #define FASTTRAP_SIB_INDEX(sib) (((sib) >> 3) & 0x7) 75 #define FASTTRAP_SIB_BASE(sib) ((sib) & 0x7) 76 77 #define FASTTRAP_REX_W(rex) (((rex) >> 3) & 1) 78 #define FASTTRAP_REX_R(rex) (((rex) >> 2) & 1) 79 #define FASTTRAP_REX_X(rex) (((rex) >> 1) & 1) 80 #define FASTTRAP_REX_B(rex) ((rex) & 1) 81 #define FASTTRAP_REX(w, r, x, b) \ 82 (0x40 | ((w) << 3) | ((r) << 2) | ((x) << 1) | (b)) 83 84 /* 85 * Single-byte op-codes. 86 */ 87 #define FASTTRAP_PUSHL_EBP 0x55 88 89 #define FASTTRAP_JO 0x70 90 #define FASTTRAP_JNO 0x71 91 #define FASTTRAP_JB 0x72 92 #define FASTTRAP_JAE 0x73 93 #define FASTTRAP_JE 0x74 94 #define FASTTRAP_JNE 0x75 95 #define FASTTRAP_JBE 0x76 96 #define FASTTRAP_JA 0x77 97 #define FASTTRAP_JS 0x78 98 #define FASTTRAP_JNS 0x79 99 #define FASTTRAP_JP 0x7a 100 #define FASTTRAP_JNP 0x7b 101 #define FASTTRAP_JL 0x7c 102 #define FASTTRAP_JGE 0x7d 103 #define FASTTRAP_JLE 0x7e 104 #define FASTTRAP_JG 0x7f 105 106 #define FASTTRAP_MOV_EAX 0xb8 107 #define FASTTRAP_MOV_ECX 0xb9 108 109 #define FASTTRAP_RET16 0xc2 110 #define FASTTRAP_RET 0xc3 111 112 #define FASTTRAP_LOOPNZ 0xe0 113 #define FASTTRAP_LOOPZ 0xe1 114 #define FASTTRAP_LOOP 0xe2 115 #define FASTTRAP_JCXZ 0xe3 116 117 #define FASTTRAP_CALL 0xe8 118 #define FASTTRAP_JMP32 0xe9 119 #define FASTTRAP_JMP8 0xeb 120 121 #define FASTTRAP_INT3 0xcc 122 #define FASTTRAP_INT 0xcd 123 124 #define FASTTRAP_2_BYTE_OP 0x0f 125 #define FASTTRAP_GROUP5_OP 0xff 126 127 /* 128 * Two-byte op-codes (second byte only). 129 */ 130 #define FASTTRAP_0F_JO 0x80 131 #define FASTTRAP_0F_JNO 0x81 132 #define FASTTRAP_0F_JB 0x82 133 #define FASTTRAP_0F_JAE 0x83 134 #define FASTTRAP_0F_JE 0x84 135 #define FASTTRAP_0F_JNE 0x85 136 #define FASTTRAP_0F_JBE 0x86 137 #define FASTTRAP_0F_JA 0x87 138 #define FASTTRAP_0F_JS 0x88 139 #define FASTTRAP_0F_JNS 0x89 140 #define FASTTRAP_0F_JP 0x8a 141 #define FASTTRAP_0F_JNP 0x8b 142 #define FASTTRAP_0F_JL 0x8c 143 #define FASTTRAP_0F_JGE 0x8d 144 #define FASTTRAP_0F_JLE 0x8e 145 #define FASTTRAP_0F_JG 0x8f 146 147 #define FASTTRAP_EFLAGS_OF 0x800 148 #define FASTTRAP_EFLAGS_DF 0x400 149 #define FASTTRAP_EFLAGS_SF 0x080 150 #define FASTTRAP_EFLAGS_ZF 0x040 151 #define FASTTRAP_EFLAGS_AF 0x010 152 #define FASTTRAP_EFLAGS_PF 0x004 153 #define FASTTRAP_EFLAGS_CF 0x001 154 155 /* 156 * Instruction prefixes. 157 */ 158 #define FASTTRAP_PREFIX_OPERAND 0x66 159 #define FASTTRAP_PREFIX_ADDRESS 0x67 160 #define FASTTRAP_PREFIX_CS 0x2E 161 #define FASTTRAP_PREFIX_DS 0x3E 162 #define FASTTRAP_PREFIX_ES 0x26 163 #define FASTTRAP_PREFIX_FS 0x64 164 #define FASTTRAP_PREFIX_GS 0x65 165 #define FASTTRAP_PREFIX_SS 0x36 166 #define FASTTRAP_PREFIX_LOCK 0xF0 167 #define FASTTRAP_PREFIX_REP 0xF3 168 #define FASTTRAP_PREFIX_REPNE 0xF2 169 170 #define FASTTRAP_NOREG 0xff 171 172 /* 173 * Map between instruction register encodings and the kernel constants which 174 * correspond to indicies into struct regs. 175 */ 176 #ifdef __amd64 177 static const uint8_t regmap[16] = { 178 REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP, REG_RSI, REG_RDI, 179 REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15, 180 }; 181 #else 182 static const uint8_t regmap[8] = { 183 EAX, ECX, EDX, EBX, UESP, EBP, ESI, EDI 184 }; 185 #endif 186 187 static ulong_t fasttrap_getreg(struct regs *, uint_t); 188 189 static uint64_t 190 fasttrap_anarg(struct regs *rp, int function_entry, int argno) 191 { 192 uint64_t value; 193 int shift = function_entry ? 1 : 0; 194 195 #ifdef __amd64 196 if (curproc->p_model == DATAMODEL_LP64) { 197 uintptr_t *stack; 198 199 /* 200 * In 64-bit mode, the first six arguments are stored in 201 * registers. 202 */ 203 if (argno < 6) 204 return ((&rp->r_rdi)[argno]); 205 206 stack = (uintptr_t *)rp->r_sp; 207 DTRACE_CPUFLAG_SET(CPU_DTRACE_NOFAULT); 208 value = dtrace_fulword(&stack[argno - 6 + shift]); 209 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_NOFAULT | CPU_DTRACE_BADADDR); 210 } else { 211 #endif 212 uint32_t *stack = (uint32_t *)rp->r_sp; 213 DTRACE_CPUFLAG_SET(CPU_DTRACE_NOFAULT); 214 value = dtrace_fuword32(&stack[argno + shift]); 215 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_NOFAULT | CPU_DTRACE_BADADDR); 216 #ifdef __amd64 217 } 218 #endif 219 220 return (value); 221 } 222 223 /*ARGSUSED*/ 224 int 225 fasttrap_tracepoint_init(proc_t *p, fasttrap_tracepoint_t *tp, uintptr_t pc, 226 fasttrap_probe_type_t type) 227 { 228 uint8_t instr[FASTTRAP_MAX_INSTR_SIZE + 10]; 229 size_t len = FASTTRAP_MAX_INSTR_SIZE; 230 size_t first = MIN(len, PAGESIZE - (pc & PAGEOFFSET)); 231 uint_t start = 0; 232 int rmindex; 233 uint8_t rex = 0; 234 235 /* 236 * Read the instruction at the given address out of the process's 237 * address space. We don't have to worry about a debugger 238 * changing this instruction before we overwrite it with our trap 239 * instruction since P_PR_LOCK is set. Since instructions can span 240 * pages, we potentially read the instruction in two parts. If the 241 * second part fails, we just zero out that part of the instruction. 242 */ 243 if (uread(p, &instr[0], first, pc) != 0) 244 return (-1); 245 if (len > first && 246 uread(p, &instr[first], len - first, pc + first) != 0) { 247 bzero(&instr[first], len - first); 248 len = first; 249 } 250 251 /* 252 * If the disassembly fails, then we have a malformed instruction. 253 */ 254 if ((tp->ftt_size = dtrace_instr_size_isa(instr, p->p_model, 255 &rmindex)) <= 0) 256 return (-1); 257 258 /* 259 * Make sure the disassembler isn't completely broken. 260 */ 261 ASSERT(-1 <= rmindex && rmindex < tp->ftt_size); 262 263 /* 264 * If the computed size is greater than the number of bytes read, 265 * then it was a malformed instruction possibly because it fell on a 266 * page boundary and the subsequent page was missing or because of 267 * some malicious user. 268 */ 269 if (tp->ftt_size > len) 270 return (-1); 271 272 /* 273 * Find the start of the instruction's opcode by processing any 274 * legacy prefixes. 275 */ 276 for (;;) { 277 switch (instr[start]) { 278 case FASTTRAP_PREFIX_OPERAND: 279 case FASTTRAP_PREFIX_ADDRESS: 280 case FASTTRAP_PREFIX_CS: 281 case FASTTRAP_PREFIX_DS: 282 case FASTTRAP_PREFIX_ES: 283 case FASTTRAP_PREFIX_FS: 284 case FASTTRAP_PREFIX_GS: 285 case FASTTRAP_PREFIX_SS: 286 case FASTTRAP_PREFIX_LOCK: 287 case FASTTRAP_PREFIX_REP: 288 case FASTTRAP_PREFIX_REPNE: 289 start++; 290 continue; 291 } 292 break; 293 } 294 295 #ifdef __amd64 296 /* 297 * Identify the REX prefix on 64-bit processes. 298 */ 299 if (p->p_model == DATAMODEL_LP64 && (instr[start] & 0xf0) == 0x40) 300 rex = instr[start++]; 301 #endif 302 303 /* 304 * Now that we're pretty sure that the instruction is okay, copy the 305 * valid part to the tracepoint. 306 */ 307 bcopy(instr, tp->ftt_instr, FASTTRAP_MAX_INSTR_SIZE); 308 309 tp->ftt_type = FASTTRAP_T_COMMON; 310 if (instr[start] == FASTTRAP_2_BYTE_OP) { 311 switch (instr[start + 1]) { 312 case FASTTRAP_0F_JO: 313 case FASTTRAP_0F_JNO: 314 case FASTTRAP_0F_JB: 315 case FASTTRAP_0F_JAE: 316 case FASTTRAP_0F_JE: 317 case FASTTRAP_0F_JNE: 318 case FASTTRAP_0F_JBE: 319 case FASTTRAP_0F_JA: 320 case FASTTRAP_0F_JS: 321 case FASTTRAP_0F_JNS: 322 case FASTTRAP_0F_JP: 323 case FASTTRAP_0F_JNP: 324 case FASTTRAP_0F_JL: 325 case FASTTRAP_0F_JGE: 326 case FASTTRAP_0F_JLE: 327 case FASTTRAP_0F_JG: 328 tp->ftt_type = FASTTRAP_T_JCC; 329 tp->ftt_code = (instr[start + 1] & 0x0f) | FASTTRAP_JO; 330 tp->ftt_dest = pc + tp->ftt_size + 331 *(int32_t *)&instr[start + 2]; 332 break; 333 } 334 } else if (instr[start] == FASTTRAP_GROUP5_OP) { 335 uint_t mod = FASTTRAP_MODRM_MOD(instr[start + 1]); 336 uint_t reg = FASTTRAP_MODRM_REG(instr[start + 1]); 337 uint_t rm = FASTTRAP_MODRM_RM(instr[start + 1]); 338 339 if (reg == 2 || reg == 4) { 340 uint_t i, sz; 341 342 if (reg == 2) 343 tp->ftt_type = FASTTRAP_T_CALL; 344 else 345 tp->ftt_type = FASTTRAP_T_JMP; 346 347 if (mod == 3) 348 tp->ftt_code = 2; 349 else 350 tp->ftt_code = 1; 351 352 ASSERT(p->p_model == DATAMODEL_LP64 || rex == 0); 353 354 /* 355 * See AMD x86-64 Architecture Programmer's Manual 356 * Volume 3, Section 1.2.7, Table 1-12, and 357 * Appendix A.3.1, Table A-15. 358 */ 359 if (mod != 3 && rm == 4) { 360 uint8_t sib = instr[start + 2]; 361 uint_t index = FASTTRAP_SIB_INDEX(sib); 362 uint_t base = FASTTRAP_SIB_BASE(sib); 363 364 tp->ftt_scale = FASTTRAP_SIB_SCALE(sib); 365 366 tp->ftt_index = (index == 4) ? 367 FASTTRAP_NOREG : 368 regmap[index | (FASTTRAP_REX_X(rex) << 3)]; 369 tp->ftt_base = (mod == 0 && base == 5) ? 370 FASTTRAP_NOREG : 371 regmap[base | (FASTTRAP_REX_B(rex) << 3)]; 372 373 i = 3; 374 sz = mod == 1 ? 1 : 4; 375 } else { 376 /* 377 * In 64-bit mode, mod == 0 and r/m == 5 378 * denotes %rip-relative addressing; in 32-bit 379 * mode, the base register isn't used. In both 380 * modes, there is a 32-bit operand. 381 */ 382 if (mod == 0 && rm == 5) { 383 #ifdef __amd64 384 if (p->p_model == DATAMODEL_LP64) 385 tp->ftt_base = REG_RIP; 386 else 387 #endif 388 tp->ftt_base = FASTTRAP_NOREG; 389 sz = 4; 390 } else { 391 uint8_t base = rm | 392 (FASTTRAP_REX_B(rex) << 3); 393 394 tp->ftt_base = regmap[base]; 395 sz = mod == 1 ? 1 : mod == 2 ? 4 : 0; 396 } 397 tp->ftt_index = FASTTRAP_NOREG; 398 i = 2; 399 } 400 401 if (sz == 1) 402 tp->ftt_dest = *(int8_t *)&instr[start + i]; 403 else if (sz == 4) 404 tp->ftt_dest = *(int32_t *)&instr[start + i]; 405 else 406 tp->ftt_dest = 0; 407 } 408 } else { 409 switch (instr[start]) { 410 case FASTTRAP_RET: 411 tp->ftt_type = FASTTRAP_T_RET; 412 break; 413 414 case FASTTRAP_RET16: 415 tp->ftt_type = FASTTRAP_T_RET16; 416 tp->ftt_dest = *(uint16_t *)&instr[start + 1]; 417 break; 418 419 case FASTTRAP_JO: 420 case FASTTRAP_JNO: 421 case FASTTRAP_JB: 422 case FASTTRAP_JAE: 423 case FASTTRAP_JE: 424 case FASTTRAP_JNE: 425 case FASTTRAP_JBE: 426 case FASTTRAP_JA: 427 case FASTTRAP_JS: 428 case FASTTRAP_JNS: 429 case FASTTRAP_JP: 430 case FASTTRAP_JNP: 431 case FASTTRAP_JL: 432 case FASTTRAP_JGE: 433 case FASTTRAP_JLE: 434 case FASTTRAP_JG: 435 tp->ftt_type = FASTTRAP_T_JCC; 436 tp->ftt_code = instr[start]; 437 tp->ftt_dest = pc + tp->ftt_size + 438 (int8_t)instr[start + 1]; 439 break; 440 441 case FASTTRAP_LOOPNZ: 442 case FASTTRAP_LOOPZ: 443 case FASTTRAP_LOOP: 444 tp->ftt_type = FASTTRAP_T_LOOP; 445 tp->ftt_code = instr[start]; 446 tp->ftt_dest = pc + tp->ftt_size + 447 (int8_t)instr[start + 1]; 448 break; 449 450 case FASTTRAP_JCXZ: 451 tp->ftt_type = FASTTRAP_T_JCXZ; 452 tp->ftt_dest = pc + tp->ftt_size + 453 (int8_t)instr[start + 1]; 454 break; 455 456 case FASTTRAP_CALL: 457 tp->ftt_type = FASTTRAP_T_CALL; 458 tp->ftt_dest = pc + tp->ftt_size + 459 *(int32_t *)&instr[start + 1]; 460 tp->ftt_code = 0; 461 break; 462 463 case FASTTRAP_JMP32: 464 tp->ftt_type = FASTTRAP_T_JMP; 465 tp->ftt_dest = pc + tp->ftt_size + 466 *(int32_t *)&instr[start + 1]; 467 break; 468 case FASTTRAP_JMP8: 469 tp->ftt_type = FASTTRAP_T_JMP; 470 tp->ftt_dest = pc + tp->ftt_size + 471 (int8_t)instr[start + 1]; 472 break; 473 474 case FASTTRAP_PUSHL_EBP: 475 if (start == 0) 476 tp->ftt_type = FASTTRAP_T_PUSHL_EBP; 477 break; 478 479 case FASTTRAP_INT3: 480 /* 481 * The pid provider shares the int3 trap with debugger 482 * breakpoints so we can't instrument them. 483 */ 484 ASSERT(instr[start] == FASTTRAP_INSTR); 485 return (-1); 486 } 487 } 488 489 #ifdef __amd64 490 if (p->p_model == DATAMODEL_LP64 && tp->ftt_type == FASTTRAP_T_COMMON) { 491 /* 492 * If the process is 64-bit and the instruction type is still 493 * FASTTRAP_T_COMMON -- meaning we're going to copy it out an 494 * execute it -- we need to watch for %rip-relative 495 * addressing mode. See the portion of fasttrap_pid_probe() 496 * below where we handle tracepoints with type 497 * FASTTRAP_T_COMMON for how we emulate instructions that 498 * employ %rip-relative addressing. 499 */ 500 if (rmindex != -1) { 501 uint_t mod = FASTTRAP_MODRM_MOD(instr[rmindex]); 502 uint_t reg = FASTTRAP_MODRM_REG(instr[rmindex]); 503 uint_t rm = FASTTRAP_MODRM_RM(instr[rmindex]); 504 505 ASSERT(rmindex > start); 506 507 if (mod == 0 && rm == 5) { 508 /* 509 * We need to be sure to avoid other 510 * registers used by this instruction. While 511 * the reg field may determine the op code 512 * rather than denoting a register, assuming 513 * that it denotes a register is always safe. 514 * We leave the REX field intact and use 515 * whatever value's there for simplicity. 516 */ 517 if (reg != 0) { 518 tp->ftt_ripmode = FASTTRAP_RIP_1 | 519 (FASTTRAP_RIP_X * 520 FASTTRAP_REX_B(rex)); 521 rm = 0; 522 } else { 523 tp->ftt_ripmode = FASTTRAP_RIP_2 | 524 (FASTTRAP_RIP_X * 525 FASTTRAP_REX_B(rex)); 526 rm = 1; 527 } 528 529 tp->ftt_modrm = tp->ftt_instr[rmindex]; 530 tp->ftt_instr[rmindex] = 531 FASTTRAP_MODRM(2, reg, rm); 532 } 533 } 534 } 535 #endif 536 537 return (0); 538 } 539 540 int 541 fasttrap_tracepoint_install(proc_t *p, fasttrap_tracepoint_t *tp) 542 { 543 fasttrap_instr_t instr = FASTTRAP_INSTR; 544 545 if (uwrite(p, &instr, 1, tp->ftt_pc) != 0) 546 return (-1); 547 548 return (0); 549 } 550 551 int 552 fasttrap_tracepoint_remove(proc_t *p, fasttrap_tracepoint_t *tp) 553 { 554 uint8_t instr; 555 556 /* 557 * Distinguish between read or write failures and a changed 558 * instruction. 559 */ 560 if (uread(p, &instr, 1, tp->ftt_pc) != 0) 561 return (0); 562 if (instr != FASTTRAP_INSTR) 563 return (0); 564 if (uwrite(p, &tp->ftt_instr[0], 1, tp->ftt_pc) != 0) 565 return (-1); 566 567 return (0); 568 } 569 570 static uintptr_t 571 fasttrap_fulword_noerr(const void *uaddr) 572 { 573 uintptr_t ret; 574 575 if (fasttrap_fulword(uaddr, &ret) == 0) 576 return (ret); 577 578 return (0); 579 } 580 581 static uint32_t 582 fasttrap_fuword32_noerr(const void *uaddr) 583 { 584 uint32_t ret; 585 586 if (fasttrap_fuword32(uaddr, &ret) == 0) 587 return (ret); 588 589 return (0); 590 } 591 592 static void 593 fasttrap_return_common(struct regs *rp, uintptr_t pc, pid_t pid, 594 uintptr_t new_pc) 595 { 596 fasttrap_tracepoint_t *tp; 597 fasttrap_bucket_t *bucket; 598 fasttrap_id_t *id; 599 kmutex_t *pid_mtx; 600 601 pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock; 602 mutex_enter(pid_mtx); 603 bucket = &fasttrap_tpoints.fth_table[FASTTRAP_TPOINTS_INDEX(pid, pc)]; 604 605 for (tp = bucket->ftb_data; tp != NULL; tp = tp->ftt_next) { 606 if (pid == tp->ftt_pid && pc == tp->ftt_pc && 607 !tp->ftt_proc->ftpc_defunct) 608 break; 609 } 610 611 /* 612 * Don't sweat it if we can't find the tracepoint again; unlike 613 * when we're in fasttrap_pid_probe(), finding the tracepoint here 614 * is not essential to the correct execution of the process. 615 */ 616 if (tp == NULL) { 617 mutex_exit(pid_mtx); 618 return; 619 } 620 621 for (id = tp->ftt_retids; id != NULL; id = id->fti_next) { 622 /* 623 * If there's a branch that could act as a return site, we 624 * need to trace it, and check here if the program counter is 625 * external to the function. 626 */ 627 if (tp->ftt_type != FASTTRAP_T_RET && 628 tp->ftt_type != FASTTRAP_T_RET16 && 629 new_pc - id->fti_probe->ftp_faddr < 630 id->fti_probe->ftp_fsize) 631 continue; 632 633 dtrace_probe(id->fti_probe->ftp_id, 634 pc - id->fti_probe->ftp_faddr, 635 rp->r_r0, rp->r_r1, 0, 0); 636 } 637 638 mutex_exit(pid_mtx); 639 } 640 641 static void 642 fasttrap_sigsegv(proc_t *p, kthread_t *t, uintptr_t addr) 643 { 644 sigqueue_t *sqp = kmem_zalloc(sizeof (sigqueue_t), KM_SLEEP); 645 646 sqp->sq_info.si_signo = SIGSEGV; 647 sqp->sq_info.si_code = SEGV_MAPERR; 648 sqp->sq_info.si_addr = (caddr_t)addr; 649 650 mutex_enter(&p->p_lock); 651 sigaddqa(p, t, sqp); 652 mutex_exit(&p->p_lock); 653 654 if (t != NULL) 655 aston(t); 656 } 657 658 #ifdef __amd64 659 static void 660 fasttrap_usdt_args64(fasttrap_probe_t *probe, struct regs *rp, int argc, 661 uintptr_t *argv) 662 { 663 int i, x, cap = MIN(argc, probe->ftp_nargs); 664 uintptr_t *stack = (uintptr_t *)rp->r_sp; 665 666 for (i = 0; i < cap; i++) { 667 x = probe->ftp_argmap[i]; 668 669 if (x < 6) 670 argv[i] = (&rp->r_rdi)[x]; 671 else 672 argv[i] = fasttrap_fulword_noerr(&stack[x]); 673 } 674 675 for (; i < argc; i++) { 676 argv[i] = 0; 677 } 678 } 679 #endif 680 681 static void 682 fasttrap_usdt_args32(fasttrap_probe_t *probe, struct regs *rp, int argc, 683 uint32_t *argv) 684 { 685 int i, x, cap = MIN(argc, probe->ftp_nargs); 686 uint32_t *stack = (uint32_t *)rp->r_sp; 687 688 for (i = 0; i < cap; i++) { 689 x = probe->ftp_argmap[i]; 690 691 argv[i] = fasttrap_fuword32_noerr(&stack[x]); 692 } 693 694 for (; i < argc; i++) { 695 argv[i] = 0; 696 } 697 } 698 699 int 700 fasttrap_pid_probe(struct regs *rp) 701 { 702 proc_t *p = curproc; 703 uintptr_t pc = rp->r_pc - 1, new_pc = 0; 704 fasttrap_bucket_t *bucket; 705 kmutex_t *pid_mtx; 706 fasttrap_tracepoint_t *tp, tp_local; 707 pid_t pid; 708 dtrace_icookie_t cookie; 709 uint_t is_enabled = 0; 710 711 /* 712 * It's possible that a user (in a veritable orgy of bad planning) 713 * could redirect this thread's flow of control before it reached the 714 * return probe fasttrap. In this case we need to kill the process 715 * since it's in a unrecoverable state. 716 */ 717 if (curthread->t_dtrace_step) { 718 ASSERT(curthread->t_dtrace_on); 719 fasttrap_sigtrap(p, curthread, pc); 720 return (0); 721 } 722 723 /* 724 * Clear all user tracing flags. 725 */ 726 curthread->t_dtrace_ft = 0; 727 curthread->t_dtrace_pc = 0; 728 curthread->t_dtrace_npc = 0; 729 curthread->t_dtrace_scrpc = 0; 730 curthread->t_dtrace_astpc = 0; 731 #ifdef __amd64 732 curthread->t_dtrace_regv = 0; 733 #endif 734 735 /* 736 * Treat a child created by a call to vfork(2) as if it were its 737 * parent. We know that there's only one thread of control in such a 738 * process: this one. 739 */ 740 while (p->p_flag & SVFORK) { 741 p = p->p_parent; 742 } 743 744 pid = p->p_pid; 745 pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock; 746 mutex_enter(pid_mtx); 747 bucket = &fasttrap_tpoints.fth_table[FASTTRAP_TPOINTS_INDEX(pid, pc)]; 748 749 /* 750 * Lookup the tracepoint that the process just hit. 751 */ 752 for (tp = bucket->ftb_data; tp != NULL; tp = tp->ftt_next) { 753 if (pid == tp->ftt_pid && pc == tp->ftt_pc && 754 !tp->ftt_proc->ftpc_defunct) 755 break; 756 } 757 758 /* 759 * If we couldn't find a matching tracepoint, either a tracepoint has 760 * been inserted without using the pid<pid> ioctl interface (see 761 * fasttrap_ioctl), or somehow we have mislaid this tracepoint. 762 */ 763 if (tp == NULL) { 764 mutex_exit(pid_mtx); 765 return (-1); 766 } 767 768 /* 769 * Set the program counter to the address of the traced instruction 770 * so that it looks right in ustack() output. 771 */ 772 rp->r_pc = pc; 773 774 if (tp->ftt_ids != NULL) { 775 fasttrap_id_t *id; 776 777 #ifdef __amd64 778 if (p->p_model == DATAMODEL_LP64) { 779 for (id = tp->ftt_ids; id != NULL; id = id->fti_next) { 780 fasttrap_probe_t *probe = id->fti_probe; 781 782 if (id->fti_ptype == DTFTP_ENTRY) { 783 /* 784 * We note that this was an entry 785 * probe to help ustack() find the 786 * first caller. 787 */ 788 cookie = dtrace_interrupt_disable(); 789 DTRACE_CPUFLAG_SET(CPU_DTRACE_ENTRY); 790 dtrace_probe(probe->ftp_id, rp->r_rdi, 791 rp->r_rsi, rp->r_rdx, rp->r_rcx, 792 rp->r_r8); 793 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_ENTRY); 794 dtrace_interrupt_enable(cookie); 795 } else if (id->fti_ptype == DTFTP_IS_ENABLED) { 796 /* 797 * Note that in this case, we don't 798 * call dtrace_probe() since it's only 799 * an artificial probe meant to change 800 * the flow of control so that it 801 * encounters the true probe. 802 */ 803 is_enabled = 1; 804 } else if (probe->ftp_argmap == NULL) { 805 dtrace_probe(probe->ftp_id, rp->r_rdi, 806 rp->r_rsi, rp->r_rdx, rp->r_rcx, 807 rp->r_r8); 808 } else { 809 uintptr_t t[5]; 810 811 fasttrap_usdt_args64(probe, rp, 812 sizeof (t) / sizeof (t[0]), t); 813 814 dtrace_probe(probe->ftp_id, t[0], t[1], 815 t[2], t[3], t[4]); 816 } 817 } 818 } else { 819 #endif 820 uintptr_t s0, s1, s2, s3, s4, s5; 821 uint32_t *stack = (uint32_t *)rp->r_sp; 822 823 /* 824 * In 32-bit mode, all arguments are passed on the 825 * stack. If this is a function entry probe, we need 826 * to skip the first entry on the stack as it 827 * represents the return address rather than a 828 * parameter to the function. 829 */ 830 s0 = fasttrap_fuword32_noerr(&stack[0]); 831 s1 = fasttrap_fuword32_noerr(&stack[1]); 832 s2 = fasttrap_fuword32_noerr(&stack[2]); 833 s3 = fasttrap_fuword32_noerr(&stack[3]); 834 s4 = fasttrap_fuword32_noerr(&stack[4]); 835 s5 = fasttrap_fuword32_noerr(&stack[5]); 836 837 for (id = tp->ftt_ids; id != NULL; id = id->fti_next) { 838 fasttrap_probe_t *probe = id->fti_probe; 839 840 if (id->fti_ptype == DTFTP_ENTRY) { 841 /* 842 * We note that this was an entry 843 * probe to help ustack() find the 844 * first caller. 845 */ 846 cookie = dtrace_interrupt_disable(); 847 DTRACE_CPUFLAG_SET(CPU_DTRACE_ENTRY); 848 dtrace_probe(probe->ftp_id, s1, s2, 849 s3, s4, s5); 850 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_ENTRY); 851 dtrace_interrupt_enable(cookie); 852 } else if (id->fti_ptype == DTFTP_IS_ENABLED) { 853 /* 854 * Note that in this case, we don't 855 * call dtrace_probe() since it's only 856 * an artificial probe meant to change 857 * the flow of control so that it 858 * encounters the true probe. 859 */ 860 is_enabled = 1; 861 } else if (probe->ftp_argmap == NULL) { 862 dtrace_probe(probe->ftp_id, s0, s1, 863 s2, s3, s4); 864 } else { 865 uint32_t t[5]; 866 867 fasttrap_usdt_args32(probe, rp, 868 sizeof (t) / sizeof (t[0]), t); 869 870 dtrace_probe(probe->ftp_id, t[0], t[1], 871 t[2], t[3], t[4]); 872 } 873 } 874 #ifdef __amd64 875 } 876 #endif 877 } 878 879 /* 880 * We're about to do a bunch of work so we cache a local copy of 881 * the tracepoint to emulate the instruction, and then find the 882 * tracepoint again later if we need to light up any return probes. 883 */ 884 tp_local = *tp; 885 mutex_exit(pid_mtx); 886 tp = &tp_local; 887 888 /* 889 * Set the program counter to appear as though the traced instruction 890 * had completely executed. This ensures that fasttrap_getreg() will 891 * report the expected value for REG_RIP. 892 */ 893 rp->r_pc = pc + tp->ftt_size; 894 895 /* 896 * If there's an is-enabled probe connected to this tracepoint it 897 * means that there was a 'xorl %eax, %eax' or 'xorq %rax, %rax' 898 * instruction that was placed there by DTrace when the binary was 899 * linked. As this probe is, in fact, enabled, we need to stuff 1 900 * into %eax or %rax. Accordingly, we can bypass all the instruction 901 * emulation logic since we know the inevitable result. It's possible 902 * that a user could construct a scenario where the 'is-enabled' 903 * probe was on some other instruction, but that would be a rather 904 * exotic way to shoot oneself in the foot. 905 */ 906 if (is_enabled) { 907 rp->r_r0 = 1; 908 new_pc = rp->r_pc; 909 goto done; 910 } 911 912 /* 913 * We emulate certain types of instructions to ensure correctness 914 * (in the case of position dependent instructions) or optimize 915 * common cases. The rest we have the thread execute back in user- 916 * land. 917 */ 918 switch (tp->ftt_type) { 919 case FASTTRAP_T_RET: 920 case FASTTRAP_T_RET16: 921 { 922 uintptr_t dst; 923 uintptr_t addr; 924 int ret; 925 926 /* 927 * We have to emulate _every_ facet of the behavior of a ret 928 * instruction including what happens if the load from %esp 929 * fails; in that case, we send a SIGSEGV. 930 */ 931 #ifdef __amd64 932 if (p->p_model == DATAMODEL_NATIVE) { 933 #endif 934 ret = fasttrap_fulword((void *)rp->r_sp, &dst); 935 addr = rp->r_sp + sizeof (uintptr_t); 936 #ifdef __amd64 937 } else { 938 uint32_t dst32; 939 ret = fasttrap_fuword32((void *)rp->r_sp, &dst32); 940 dst = dst32; 941 addr = rp->r_sp + sizeof (uint32_t); 942 } 943 #endif 944 945 if (ret == -1) { 946 fasttrap_sigsegv(p, curthread, rp->r_sp); 947 new_pc = pc; 948 break; 949 } 950 951 if (tp->ftt_type == FASTTRAP_T_RET16) 952 addr += tp->ftt_dest; 953 954 rp->r_sp = addr; 955 new_pc = dst; 956 break; 957 } 958 959 case FASTTRAP_T_JCC: 960 { 961 uint_t taken; 962 963 switch (tp->ftt_code) { 964 case FASTTRAP_JO: 965 taken = (rp->r_ps & FASTTRAP_EFLAGS_OF) != 0; 966 break; 967 case FASTTRAP_JNO: 968 taken = (rp->r_ps & FASTTRAP_EFLAGS_OF) == 0; 969 break; 970 case FASTTRAP_JB: 971 taken = (rp->r_ps & FASTTRAP_EFLAGS_CF) != 0; 972 break; 973 case FASTTRAP_JAE: 974 taken = (rp->r_ps & FASTTRAP_EFLAGS_CF) == 0; 975 break; 976 case FASTTRAP_JE: 977 taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) != 0; 978 break; 979 case FASTTRAP_JNE: 980 taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) == 0; 981 break; 982 case FASTTRAP_JBE: 983 taken = (rp->r_ps & FASTTRAP_EFLAGS_CF) != 0 || 984 (rp->r_ps & FASTTRAP_EFLAGS_ZF) != 0; 985 break; 986 case FASTTRAP_JA: 987 taken = (rp->r_ps & FASTTRAP_EFLAGS_CF) == 0 && 988 (rp->r_ps & FASTTRAP_EFLAGS_ZF) == 0; 989 break; 990 case FASTTRAP_JS: 991 taken = (rp->r_ps & FASTTRAP_EFLAGS_SF) != 0; 992 break; 993 case FASTTRAP_JNS: 994 taken = (rp->r_ps & FASTTRAP_EFLAGS_SF) == 0; 995 break; 996 case FASTTRAP_JP: 997 taken = (rp->r_ps & FASTTRAP_EFLAGS_PF) != 0; 998 break; 999 case FASTTRAP_JNP: 1000 taken = (rp->r_ps & FASTTRAP_EFLAGS_PF) == 0; 1001 break; 1002 case FASTTRAP_JL: 1003 taken = ((rp->r_ps & FASTTRAP_EFLAGS_SF) == 0) != 1004 ((rp->r_ps & FASTTRAP_EFLAGS_OF) == 0); 1005 break; 1006 case FASTTRAP_JGE: 1007 taken = ((rp->r_ps & FASTTRAP_EFLAGS_SF) == 0) == 1008 ((rp->r_ps & FASTTRAP_EFLAGS_OF) == 0); 1009 break; 1010 case FASTTRAP_JLE: 1011 taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) != 0 || 1012 ((rp->r_ps & FASTTRAP_EFLAGS_SF) == 0) != 1013 ((rp->r_ps & FASTTRAP_EFLAGS_OF) == 0); 1014 break; 1015 case FASTTRAP_JG: 1016 taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) == 0 && 1017 ((rp->r_ps & FASTTRAP_EFLAGS_SF) == 0) == 1018 ((rp->r_ps & FASTTRAP_EFLAGS_OF) == 0); 1019 break; 1020 1021 } 1022 1023 if (taken) 1024 new_pc = tp->ftt_dest; 1025 else 1026 new_pc = pc + tp->ftt_size; 1027 break; 1028 } 1029 1030 case FASTTRAP_T_LOOP: 1031 { 1032 uint_t taken; 1033 #ifdef __amd64 1034 greg_t cx = rp->r_rcx--; 1035 #else 1036 greg_t cx = rp->r_ecx--; 1037 #endif 1038 1039 switch (tp->ftt_code) { 1040 case FASTTRAP_LOOPNZ: 1041 taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) == 0 && 1042 cx != 0; 1043 break; 1044 case FASTTRAP_LOOPZ: 1045 taken = (rp->r_ps & FASTTRAP_EFLAGS_ZF) != 0 && 1046 cx != 0; 1047 break; 1048 case FASTTRAP_LOOP: 1049 taken = (cx != 0); 1050 break; 1051 } 1052 1053 if (taken) 1054 new_pc = tp->ftt_dest; 1055 else 1056 new_pc = pc + tp->ftt_size; 1057 break; 1058 } 1059 1060 case FASTTRAP_T_JCXZ: 1061 { 1062 #ifdef __amd64 1063 greg_t cx = rp->r_rcx; 1064 #else 1065 greg_t cx = rp->r_ecx; 1066 #endif 1067 1068 if (cx == 0) 1069 new_pc = tp->ftt_dest; 1070 else 1071 new_pc = pc + tp->ftt_size; 1072 break; 1073 } 1074 1075 case FASTTRAP_T_PUSHL_EBP: 1076 { 1077 int ret; 1078 uintptr_t addr; 1079 #ifdef __amd64 1080 if (p->p_model == DATAMODEL_NATIVE) { 1081 #endif 1082 addr = rp->r_sp - sizeof (uintptr_t); 1083 ret = fasttrap_sulword((void *)addr, rp->r_fp); 1084 #ifdef __amd64 1085 } else { 1086 addr = rp->r_sp - sizeof (uint32_t); 1087 ret = fasttrap_suword32((void *)addr, 1088 (uint32_t)rp->r_fp); 1089 } 1090 #endif 1091 1092 if (ret == -1) { 1093 fasttrap_sigsegv(p, curthread, addr); 1094 new_pc = pc; 1095 break; 1096 } 1097 1098 rp->r_sp = addr; 1099 new_pc = pc + tp->ftt_size; 1100 break; 1101 } 1102 1103 case FASTTRAP_T_JMP: 1104 case FASTTRAP_T_CALL: 1105 if (tp->ftt_code == 0) { 1106 new_pc = tp->ftt_dest; 1107 } else { 1108 uintptr_t addr = tp->ftt_dest; 1109 1110 if (tp->ftt_base != FASTTRAP_NOREG) 1111 addr += fasttrap_getreg(rp, tp->ftt_base); 1112 if (tp->ftt_index != FASTTRAP_NOREG) 1113 addr += fasttrap_getreg(rp, tp->ftt_index) << 1114 tp->ftt_scale; 1115 1116 if (tp->ftt_code == 1) { 1117 #ifdef __amd64 1118 if (p->p_model == DATAMODEL_NATIVE) { 1119 #endif 1120 uintptr_t value; 1121 if (fasttrap_fulword((void *)addr, 1122 &value) == -1) { 1123 fasttrap_sigsegv(p, curthread, 1124 addr); 1125 new_pc = pc; 1126 break; 1127 } 1128 new_pc = value; 1129 #ifdef __amd64 1130 } else { 1131 uint32_t value; 1132 if (fasttrap_fuword32((void *)addr, 1133 &value) == -1) { 1134 fasttrap_sigsegv(p, curthread, 1135 addr); 1136 new_pc = pc; 1137 break; 1138 } 1139 new_pc = value; 1140 } 1141 #endif 1142 } else { 1143 new_pc = addr; 1144 } 1145 } 1146 1147 /* 1148 * If this is a call instruction, we need to push the return 1149 * address onto the stack. If this fails, we send the process 1150 * a SIGSEGV and reset the pc to emulate what would happen if 1151 * this instruction weren't traced. 1152 */ 1153 if (tp->ftt_type == FASTTRAP_T_CALL) { 1154 int ret; 1155 uintptr_t addr; 1156 #ifdef __amd64 1157 if (p->p_model == DATAMODEL_NATIVE) { 1158 addr = rp->r_sp - sizeof (uintptr_t); 1159 ret = fasttrap_sulword((void *)addr, 1160 pc + tp->ftt_size); 1161 } else { 1162 #endif 1163 addr = rp->r_sp - sizeof (uint32_t); 1164 ret = fasttrap_suword32((void *)addr, 1165 (uint32_t)(pc + tp->ftt_size)); 1166 #ifdef __amd64 1167 } 1168 #endif 1169 1170 if (ret == -1) { 1171 fasttrap_sigsegv(p, curthread, addr); 1172 new_pc = pc; 1173 break; 1174 } 1175 1176 rp->r_sp = addr; 1177 } 1178 1179 break; 1180 1181 case FASTTRAP_T_COMMON: 1182 { 1183 uintptr_t addr; 1184 uint8_t scratch[2 * FASTTRAP_MAX_INSTR_SIZE + 5 + 2]; 1185 uint_t i = 0; 1186 klwp_t *lwp = ttolwp(curthread); 1187 1188 /* 1189 * Compute the address of the ulwp_t and step over the 1190 * ul_self pointer. The method used to store the user-land 1191 * thread pointer is very different on 32- and 64-bit 1192 * kernels. 1193 */ 1194 #if defined(__amd64) 1195 if (p->p_model == DATAMODEL_LP64) { 1196 addr = lwp->lwp_pcb.pcb_fsbase; 1197 addr += sizeof (void *); 1198 } else { 1199 addr = lwp->lwp_pcb.pcb_gsbase; 1200 addr += sizeof (caddr32_t); 1201 } 1202 #elif defined(__i386) 1203 addr = USEGD_GETBASE(&lwp->lwp_pcb.pcb_gsdesc); 1204 addr += sizeof (void *); 1205 #endif 1206 1207 /* 1208 * Generic Instruction Tracing 1209 * --------------------------- 1210 * 1211 * This is the layout of the scratch space in the user-land 1212 * thread structure for our generated instructions. 1213 * 1214 * 32-bit mode bytes 1215 * ------------------------ ----- 1216 * a: <original instruction> <= 15 1217 * jmp <pc + tp->ftt_size> 5 1218 * b: <original instrction> <= 15 1219 * int T_DTRACE_RET 2 1220 * ----- 1221 * <= 37 1222 * 1223 * 64-bit mode bytes 1224 * ------------------------ ----- 1225 * a: <original instruction> <= 15 1226 * jmp 0(%rip) 6 1227 * <pc + tp->ftt_size> 8 1228 * b: <original instruction> <= 15 1229 * int T_DTRACE_RET 2 1230 * ----- 1231 * <= 46 1232 * 1233 * The %pc is set to a, and curthread->t_dtrace_astpc is set 1234 * to b. If we encounter a signal on the way out of the 1235 * kernel, trap() will set %pc to curthread->t_dtrace_astpc 1236 * so that we execute the original instruction and re-enter 1237 * the kernel rather than redirecting to the next instruction. 1238 * 1239 * If there are return probes (so we know that we're going to 1240 * need to reenter the kernel after executing the original 1241 * instruction), the scratch space will just contain the 1242 * original instruction followed by an interrupt -- the same 1243 * data as at b. 1244 * 1245 * %rip-relative Addressing 1246 * ------------------------ 1247 * 1248 * There's a further complication in 64-bit mode due to %rip- 1249 * relative addressing. While this is clearly a beneficial 1250 * architectural decision for position independent code, it's 1251 * hard not to see it as a personal attack against the pid 1252 * provider since before there was a relatively small set of 1253 * instructions to emulate; with %rip-relative addressing, 1254 * almost every instruction can potentially depend on the 1255 * address at which it's executed. Rather than emulating 1256 * the broad spectrum of instructions that can now be 1257 * position dependent, we emulate jumps and others as in 1258 * 32-bit mode, and take a different tack for instructions 1259 * using %rip-relative addressing. 1260 * 1261 * For every instruction that uses the ModRM byte, the 1262 * in-kernel disassembler reports its location. We use the 1263 * ModRM byte to identify that an instruction uses 1264 * %rip-relative addressing and to see what other registers 1265 * the instruction uses. To emulate those instructions, 1266 * we modify the instruction to be %rax-relative rather than 1267 * %rip-relative (or %rcx-relative if the instruction uses 1268 * %rax; or %r8- or %r9-relative if the REX.B is present so 1269 * we don't have to rewrite the REX prefix). We then load 1270 * the value that %rip would have been into the scratch 1271 * register and generate an instruction to reset the scratch 1272 * register back to its original value. The instruction 1273 * sequence looks like this: 1274 * 1275 * 64-mode %rip-relative bytes 1276 * ------------------------ ----- 1277 * a: <modified instruction> <= 15 1278 * movq $<value>, %<scratch> 6 1279 * jmp 0(%rip) 6 1280 * <pc + tp->ftt_size> 8 1281 * b: <modified instruction> <= 15 1282 * int T_DTRACE_RET 2 1283 * ----- 1284 * 52 1285 * 1286 * We set curthread->t_dtrace_regv so that upon receiving 1287 * a signal we can reset the value of the scratch register. 1288 */ 1289 1290 ASSERT(tp->ftt_size < FASTTRAP_MAX_INSTR_SIZE); 1291 1292 curthread->t_dtrace_scrpc = addr; 1293 bcopy(tp->ftt_instr, &scratch[i], tp->ftt_size); 1294 i += tp->ftt_size; 1295 1296 #ifdef __amd64 1297 if (tp->ftt_ripmode != 0) { 1298 greg_t *reg; 1299 1300 ASSERT(p->p_model == DATAMODEL_LP64); 1301 ASSERT(tp->ftt_ripmode & 1302 (FASTTRAP_RIP_1 | FASTTRAP_RIP_2)); 1303 1304 /* 1305 * If this was a %rip-relative instruction, we change 1306 * it to be either a %rax- or %rcx-relative 1307 * instruction (depending on whether those registers 1308 * are used as another operand; or %r8- or %r9- 1309 * relative depending on the value of REX.B). We then 1310 * set that register and generate a movq instruction 1311 * to reset the value. 1312 */ 1313 if (tp->ftt_ripmode & FASTTRAP_RIP_X) 1314 scratch[i++] = FASTTRAP_REX(1, 0, 0, 1); 1315 else 1316 scratch[i++] = FASTTRAP_REX(1, 0, 0, 0); 1317 1318 if (tp->ftt_ripmode & FASTTRAP_RIP_1) 1319 scratch[i++] = FASTTRAP_MOV_EAX; 1320 else 1321 scratch[i++] = FASTTRAP_MOV_ECX; 1322 1323 switch (tp->ftt_ripmode) { 1324 case FASTTRAP_RIP_1: 1325 reg = &rp->r_rax; 1326 curthread->t_dtrace_reg = REG_RAX; 1327 break; 1328 case FASTTRAP_RIP_2: 1329 reg = &rp->r_rcx; 1330 curthread->t_dtrace_reg = REG_RCX; 1331 break; 1332 case FASTTRAP_RIP_1 | FASTTRAP_RIP_X: 1333 reg = &rp->r_r8; 1334 curthread->t_dtrace_reg = REG_R8; 1335 break; 1336 case FASTTRAP_RIP_2 | FASTTRAP_RIP_X: 1337 reg = &rp->r_r9; 1338 curthread->t_dtrace_reg = REG_R9; 1339 break; 1340 } 1341 1342 *(uint64_t *)&scratch[i] = *reg; 1343 curthread->t_dtrace_regv = *reg; 1344 *reg = pc + tp->ftt_size; 1345 i += sizeof (uint64_t); 1346 } 1347 #endif 1348 1349 /* 1350 * Generate the branch instruction to what would have 1351 * normally been the subsequent instruction. In 32-bit mode, 1352 * this is just a relative branch; in 64-bit mode this is a 1353 * %rip-relative branch that loads the 64-bit pc value 1354 * immediately after the jmp instruction. 1355 */ 1356 #ifdef __amd64 1357 if (p->p_model == DATAMODEL_LP64) { 1358 scratch[i++] = FASTTRAP_GROUP5_OP; 1359 scratch[i++] = FASTTRAP_MODRM(0, 4, 5); 1360 *(uint32_t *)&scratch[i] = 0; 1361 i += sizeof (uint32_t); 1362 *(uint64_t *)&scratch[i] = pc + tp->ftt_size; 1363 i += sizeof (uint64_t); 1364 } else { 1365 #endif 1366 /* 1367 * Set up the jmp to the next instruction; note that 1368 * the size of the traced instruction cancels out. 1369 */ 1370 scratch[i++] = FASTTRAP_JMP32; 1371 *(uint32_t *)&scratch[i] = pc - addr - 5; 1372 i += sizeof (uint32_t); 1373 #ifdef __amd64 1374 } 1375 #endif 1376 1377 curthread->t_dtrace_astpc = addr + i; 1378 bcopy(tp->ftt_instr, &scratch[i], tp->ftt_size); 1379 i += tp->ftt_size; 1380 scratch[i++] = FASTTRAP_INT; 1381 scratch[i++] = T_DTRACE_RET; 1382 1383 if (fasttrap_copyout(scratch, (char *)addr, i)) { 1384 fasttrap_sigtrap(p, curthread, pc); 1385 new_pc = pc; 1386 break; 1387 } 1388 1389 if (tp->ftt_retids != NULL) { 1390 curthread->t_dtrace_step = 1; 1391 curthread->t_dtrace_ret = 1; 1392 new_pc = curthread->t_dtrace_astpc; 1393 } else { 1394 new_pc = curthread->t_dtrace_scrpc; 1395 } 1396 1397 curthread->t_dtrace_pc = pc; 1398 curthread->t_dtrace_npc = pc + tp->ftt_size; 1399 curthread->t_dtrace_on = 1; 1400 break; 1401 } 1402 1403 default: 1404 panic("fasttrap: mishandled an instruction"); 1405 } 1406 1407 done: 1408 /* 1409 * If there were no return probes when we first found the tracepoint, 1410 * we should feel no obligation to honor any return probes that were 1411 * subsequently enabled -- they'll just have to wait until the next 1412 * time around. 1413 */ 1414 if (tp->ftt_retids != NULL) { 1415 /* 1416 * We need to wait until the results of the instruction are 1417 * apparent before invoking any return probes. If this 1418 * instruction was emulated we can just call 1419 * fasttrap_return_common(); if it needs to be executed, we 1420 * need to wait until the user thread returns to the kernel. 1421 */ 1422 if (tp->ftt_type != FASTTRAP_T_COMMON) { 1423 /* 1424 * Set the program counter to the address of the traced 1425 * instruction so that it looks right in ustack() 1426 * output. We had previously set it to the end of the 1427 * instruction to simplify %rip-relative addressing. 1428 */ 1429 rp->r_pc = pc; 1430 1431 fasttrap_return_common(rp, pc, pid, new_pc); 1432 } else { 1433 ASSERT(curthread->t_dtrace_ret != 0); 1434 ASSERT(curthread->t_dtrace_pc == pc); 1435 ASSERT(curthread->t_dtrace_scrpc != 0); 1436 ASSERT(new_pc == curthread->t_dtrace_astpc); 1437 } 1438 } 1439 1440 ASSERT(new_pc != 0); 1441 rp->r_pc = new_pc; 1442 1443 return (0); 1444 } 1445 1446 int 1447 fasttrap_return_probe(struct regs *rp) 1448 { 1449 proc_t *p = curproc; 1450 uintptr_t pc = curthread->t_dtrace_pc; 1451 uintptr_t npc = curthread->t_dtrace_npc; 1452 1453 curthread->t_dtrace_pc = 0; 1454 curthread->t_dtrace_npc = 0; 1455 curthread->t_dtrace_scrpc = 0; 1456 curthread->t_dtrace_astpc = 0; 1457 1458 /* 1459 * Treat a child created by a call to vfork(2) as if it were its 1460 * parent. We know that there's only one thread of control in such a 1461 * process: this one. 1462 */ 1463 while (p->p_flag & SVFORK) { 1464 p = p->p_parent; 1465 } 1466 1467 /* 1468 * We set rp->r_pc to the address of the traced instruction so 1469 * that it appears to dtrace_probe() that we're on the original 1470 * instruction, and so that the user can't easily detect our 1471 * complex web of lies. dtrace_return_probe() (our caller) 1472 * will correctly set %pc after we return. 1473 */ 1474 rp->r_pc = pc; 1475 1476 fasttrap_return_common(rp, pc, p->p_pid, npc); 1477 1478 return (0); 1479 } 1480 1481 /*ARGSUSED*/ 1482 uint64_t 1483 fasttrap_pid_getarg(void *arg, dtrace_id_t id, void *parg, int argno, 1484 int aframes) 1485 { 1486 return (fasttrap_anarg(ttolwp(curthread)->lwp_regs, 1, argno)); 1487 } 1488 1489 /*ARGSUSED*/ 1490 uint64_t 1491 fasttrap_usdt_getarg(void *arg, dtrace_id_t id, void *parg, int argno, 1492 int aframes) 1493 { 1494 return (fasttrap_anarg(ttolwp(curthread)->lwp_regs, 0, argno)); 1495 } 1496 1497 static ulong_t 1498 fasttrap_getreg(struct regs *rp, uint_t reg) 1499 { 1500 #ifdef __amd64 1501 switch (reg) { 1502 case REG_R15: return (rp->r_r15); 1503 case REG_R14: return (rp->r_r14); 1504 case REG_R13: return (rp->r_r13); 1505 case REG_R12: return (rp->r_r12); 1506 case REG_R11: return (rp->r_r11); 1507 case REG_R10: return (rp->r_r10); 1508 case REG_R9: return (rp->r_r9); 1509 case REG_R8: return (rp->r_r8); 1510 case REG_RDI: return (rp->r_rdi); 1511 case REG_RSI: return (rp->r_rsi); 1512 case REG_RBP: return (rp->r_rbp); 1513 case REG_RBX: return (rp->r_rbx); 1514 case REG_RDX: return (rp->r_rdx); 1515 case REG_RCX: return (rp->r_rcx); 1516 case REG_RAX: return (rp->r_rax); 1517 case REG_TRAPNO: return (rp->r_trapno); 1518 case REG_ERR: return (rp->r_err); 1519 case REG_RIP: return (rp->r_rip); 1520 case REG_CS: return (rp->r_cs); 1521 case REG_RFL: return (rp->r_rfl); 1522 case REG_RSP: return (rp->r_rsp); 1523 case REG_SS: return (rp->r_ss); 1524 case REG_FS: return (rp->r_fs); 1525 case REG_GS: return (rp->r_gs); 1526 case REG_DS: return (rp->r_ds); 1527 case REG_ES: return (rp->r_es); 1528 case REG_FSBASE: return (rp->r_fsbase); 1529 case REG_GSBASE: return (rp->r_gsbase); 1530 } 1531 1532 panic("dtrace: illegal register constant"); 1533 /*NOTREACHED*/ 1534 #else 1535 if (reg >= _NGREG) 1536 panic("dtrace: illegal register constant"); 1537 1538 return (((greg_t *)&rp->r_gs)[reg]); 1539 #endif 1540 } 1541