1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_MACHCPUVAR_H 27 #define _SYS_MACHCPUVAR_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/inttypes.h> 36 #include <sys/xc_levels.h> 37 #include <sys/tss.h> 38 #include <sys/segments.h> 39 #include <sys/rm_platter.h> 40 #include <sys/avintr.h> 41 #include <sys/mmu.h> 42 #include <sys/pte.h> 43 44 #ifndef _ASM 45 /* 46 * Machine specific fields of the cpu struct 47 * defined in common/sys/cpuvar.h. 48 * 49 * Note: This is kinda kludgy but seems to be the best 50 * of our alternatives. 51 */ 52 typedef void *cpu_pri_lev_t; 53 54 struct cpuid_info; 55 struct cmi; 56 57 struct machcpu { 58 /* define all the x_call stuff */ 59 volatile int xc_pend[X_CALL_LEVELS]; 60 volatile int xc_wait[X_CALL_LEVELS]; 61 volatile int xc_ack[X_CALL_LEVELS]; 62 volatile int xc_state[X_CALL_LEVELS]; 63 volatile int xc_retval[X_CALL_LEVELS]; 64 65 int mcpu_nodeid; /* node-id */ 66 int mcpu_pri; /* CPU priority */ 67 cpu_pri_lev_t mcpu_pri_data; /* ptr to machine dependent */ 68 /* data for setting priority */ 69 /* level */ 70 71 uint_t mcpu_mask; /* bitmask for this cpu (1<<cpu_id) */ 72 struct hat *mcpu_current_hat; /* cpu's current hat */ 73 74 struct hat_cpu_info *mcpu_hat_info; 75 76 /* i86 hardware table addresses that cannot be shared */ 77 user_desc_t *mcpu_gdt; /* GDT */ 78 gate_desc_t *mcpu_idt; /* IDT */ 79 struct tss *mcpu_tss; /* TSS */ 80 81 struct cpu_tables *mcpu_cp_tables; /* pointer to space acquired */ 82 /* while starting up */ 83 /* auxillary processors */ 84 kmutex_t mcpu_ppaddr_mutex; 85 86 caddr_t mcpu_caddr1; /* per cpu CADDR1 */ 87 caddr_t mcpu_caddr2; /* per cpu CADDR2 */ 88 void *mcpu_caddr1pte; 89 void *mcpu_caddr2pte; 90 struct softint mcpu_softinfo; 91 uint64_t pil_high_start[HIGH_LEVELS]; 92 uint64_t intrstat[PIL_MAX + 1][2]; 93 struct cpuid_info *mcpu_cpi; 94 struct cmi *mcpu_cmi; /* CPU module state */ 95 void *mcpu_cmidata; 96 #if defined(__amd64) 97 greg_t mcpu_rtmp_rsp; /* syscall: temporary %rsp stash */ 98 greg_t mcpu_rtmp_r15; /* syscall: temporary %r15 stash */ 99 #endif 100 }; 101 102 #define NINTR_THREADS (LOCK_LEVEL-1) /* number of interrupt threads */ 103 104 #endif /* _ASM */ 105 106 #define cpu_nodeid cpu_m.mcpu_nodeid 107 #define cpu_pri cpu_m.mcpu_pri 108 #define cpu_pri_data cpu_m.mcpu_pri_data 109 #define cpu_mask cpu_m.mcpu_mask 110 #define cpu_current_hat cpu_m.mcpu_current_hat 111 #define cpu_hat_info cpu_m.mcpu_hat_info 112 #define cpu_ppaddr_mutex cpu_m.mcpu_ppaddr_mutex 113 #define cpu_gdt cpu_m.mcpu_gdt 114 #define cpu_idt cpu_m.mcpu_idt 115 #define cpu_tss cpu_m.mcpu_tss 116 #define cpu_ldt cpu_m.mcpu_ldt 117 #define cpu_caddr1 cpu_m.mcpu_caddr1 118 #define cpu_caddr2 cpu_m.mcpu_caddr2 119 #define cpu_softinfo cpu_m.mcpu_softinfo 120 #define cpu_caddr1pte cpu_m.mcpu_caddr1pte 121 #define cpu_caddr2pte cpu_m.mcpu_caddr2pte 122 123 #ifdef __cplusplus 124 } 125 #endif 126 127 #endif /* _SYS_MACHCPUVAR_H */ 128