1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_APIC_APIC_H 27 #define _SYS_APIC_APIC_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/psm_types.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #include <sys/psm_common.h> 38 39 #define APIC_IO_ADDR 0xfec00000 40 #define APIC_LOCAL_ADDR 0xfee00000 41 #define APIC_IO_MEMLEN 0xf 42 #define APIC_LOCAL_MEMLEN 0xfffff 43 44 /* Local Unit ID register */ 45 #define APIC_LID_REG 0x8 46 47 /* I/o Unit Version Register */ 48 #define APIC_VERS_REG 0xc 49 50 /* Task Priority register */ 51 #define APIC_TASK_REG 0x20 52 53 /* EOI register */ 54 #define APIC_EOI_REG 0x2c 55 56 /* Remote Read register */ 57 #define APIC_REMOTE_READ 0x30 58 59 /* Logical Destination register */ 60 #define APIC_DEST_REG 0x34 61 62 /* Destination Format rgister */ 63 #define APIC_FORMAT_REG 0x38 64 65 /* Spurious Interrupt Vector register */ 66 #define APIC_SPUR_INT_REG 0x3c 67 68 /* Error Status Register */ 69 #define APIC_ERROR_STATUS 0xa0 70 71 /* Interrupt Command registers */ 72 #define APIC_INT_CMD1 0xc0 73 #define APIC_INT_CMD2 0xc4 74 75 /* Timer Vector Table register */ 76 #define APIC_LOCAL_TIMER 0xc8 77 78 /* Local Interrupt Vector registers */ 79 #define APIC_PCINT_VECT 0xd0 80 #define APIC_INT_VECT0 0xd4 81 #define APIC_INT_VECT1 0xd8 82 #define APIC_ERR_VECT 0xdc 83 84 /* IPL for performance counter interrupts */ 85 #define APIC_PCINT_IPL 0xe 86 #define APIC_LVT_MASK 0x10000 /* Mask bit (16) in LVT */ 87 88 /* Initial Count register */ 89 #define APIC_INIT_COUNT 0xe0 90 91 /* Current Count Register */ 92 #define APIC_CURR_COUNT 0xe4 93 #define APIC_CURR_ADD 0x39 /* used for remote read command */ 94 #define CURR_COUNT_OFFSET (sizeof (int32_t) * APIC_CURR_COUNT) 95 96 /* Divider Configuration Register */ 97 #define APIC_DIVIDE_REG 0xf8 98 99 /* IRR register */ 100 #define APIC_IRR_REG 0x80 101 102 /* ISR register */ 103 #define APIC_ISR_REG 0x40 104 105 #define APIC_IO_REG 0x0 106 #define APIC_IO_DATA 0x4 107 108 /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */ 109 #define APIC_ID_BIT_OFFSET 24 110 #define APIC_ICR_ID_BIT_OFFSET 24 111 #define APIC_LDR_ID_BIT_OFFSET 24 112 113 /* 114 * Choose between flat and clustered models by writing the following to the 115 * FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will 116 * disable logical destination mode. 117 * Does not seem to be in the docs for local APICs on the processors. 118 */ 119 #define APIC_FLAT_MODEL 0xFFFFFFFFUL 120 #define APIC_CLUSTER_MODEL 0x0FFFFFFF 121 122 /* 123 * The commands which follow are window selectors written to APIC_IO_REG 124 * before data can be read/written from/to APIC_IO_DATA 125 */ 126 127 #define APIC_ID_CMD 0x0 128 #define APIC_VERS_CMD 0x1 129 #define APIC_RDT_CMD 0x10 130 #define APIC_RDT_CMD2 0x11 131 132 #define APIC_INTEGRATED_VERS 0x10 /* 0x10 & above indicates integrated */ 133 #define IOAPIC_VER_82489DX 0x01 /* Version ID: 82489DX External APIC */ 134 135 #define APIC_INT_SPURIOUS -1 136 137 #define APIC_IMCR_P1 0x22 /* int mode conf register port 1 */ 138 #define APIC_IMCR_P2 0x23 /* int mode conf register port 2 */ 139 #define APIC_IMCR_SELECT 0x70 /* select imcr by writing into P1 */ 140 #define APIC_IMCR_PIC 0x0 /* selects PIC mode (8259-> BSP) */ 141 #define APIC_IMCR_APIC 0x1 /* selects APIC mode (8259->APIC) */ 142 143 #define APIC_CT_VECT 0x4ac /* conf table vector */ 144 #define APIC_CT_SIZE 1024 /* conf table size */ 145 146 #define APIC_ID 'MPAT' /* conf table signature */ 147 148 149 /* 150 * MP floating pointer structure defined in Intel MP Spec 1.1 151 */ 152 struct apic_mpfps_hdr { 153 uint32_t mpfps_sig; /* _MP_ (0x5F4D505F) */ 154 uint32_t mpfps_mpct_paddr; /* paddr of MP configuration tbl */ 155 uchar_t mpfps_length; /* in paragraph (16-bytes units) */ 156 uchar_t mpfps_spec_rev; /* version number of MP spec */ 157 uchar_t mpfps_checksum; /* checksum of complete structure */ 158 uchar_t mpfps_featinfo1; /* mp feature info bytes 1 */ 159 uchar_t mpfps_featinfo2; /* mp feature info bytes 2 */ 160 uchar_t mpfps_featinfo3; /* mp feature info bytes 3 */ 161 uchar_t mpfps_featinfo4; /* mp feature info bytes 4 */ 162 uchar_t mpfps_featinfo5; /* mp feature info bytes 5 */ 163 }; 164 165 #define MPFPS_FEATINFO2_IMCRP 0x80 /* IMCRP presence bit */ 166 167 #define APIC_MPS_OEM_ID_LEN 8 168 #define APIC_MPS_PROD_ID_LEN 12 169 170 struct apic_mp_cnf_hdr { 171 uint_t mpcnf_sig; 172 173 uint_t mpcnf_tbl_length: 16, 174 mpcnf_spec: 8, 175 mpcnf_cksum: 8; 176 177 char mpcnf_oem_str[APIC_MPS_OEM_ID_LEN]; 178 179 char mpcnf_prod_str[APIC_MPS_PROD_ID_LEN]; 180 181 uint_t mpcnf_oem_ptr; 182 183 uint_t mpcnf_oem_tbl_size: 16, 184 mpcnf_entry_cnt: 16; 185 186 uint_t mpcnf_local_apic; 187 188 uint_t mpcnf_resv; 189 }; 190 191 struct apic_procent { 192 uint_t proc_entry: 8, 193 proc_apicid: 8, 194 proc_version: 8, 195 proc_cpuflags: 8; 196 197 uint_t proc_stepping: 4, 198 proc_model: 4, 199 proc_family: 4, 200 proc_type: 2, /* undocumented feature */ 201 proc_resv1: 18; 202 203 uint_t proc_feature; 204 205 uint_t proc_resv2; 206 207 uint_t proc_resv3; 208 }; 209 210 /* 211 * proc_cpuflags definitions 212 */ 213 #define CPUFLAGS_EN 1 /* if not set, this processor is unusable */ 214 #define CPUFLAGS_BP 2 /* set if this is the bootstrap processor */ 215 216 217 struct apic_bus { 218 uchar_t bus_entry; 219 uchar_t bus_id; 220 ushort_t bus_str1; 221 uint_t bus_str2; 222 }; 223 224 struct apic_io_entry { 225 uint_t io_entry: 8, 226 io_apicid: 8, 227 io_version: 8, 228 io_flags: 8; 229 230 uint_t io_apic_addr; 231 }; 232 233 #define IOAPIC_FLAGS_EN 0x01 /* this I/O apic is enable or not */ 234 235 #define MAX_IO_APIC 32 /* maximum # of IOAPICs supported */ 236 237 struct apic_io_intr { 238 uint_t intr_entry: 8, 239 intr_type: 8, 240 intr_po: 2, 241 intr_el: 2, 242 intr_resv: 12; 243 244 uint_t intr_busid: 8, 245 intr_irq: 8, 246 intr_destid: 8, 247 intr_destintin: 8; 248 }; 249 250 /* 251 * intr_type definitions 252 */ 253 #define IO_INTR_INT 0x00 254 #define IO_INTR_NMI 0x01 255 #define IO_INTR_SMI 0x02 256 #define IO_INTR_EXTINT 0x03 257 258 /* 259 * destination APIC ID 260 */ 261 #define INTR_ALL_APIC 0xff 262 263 264 /* local vector table */ 265 #define AV_MASK 0x10000 266 267 /* interrupt command register 32-63 */ 268 #define AV_TOALL 0x7fffffff 269 #define AV_HIGH_ORDER 0x40000000 270 #define AV_IM_OFF 0x40000000 271 272 /* interrupt command register 0-31 */ 273 #define AV_FIXED 0x000 274 #define AV_LOPRI 0x100 275 #define AV_REMOTE 0x300 276 #define AV_NMI 0x400 277 #define AV_RESET 0x500 278 #define AV_STARTUP 0x600 279 #define AV_EXTINT 0x700 280 281 #define AV_PDEST 0x000 282 #define AV_LDEST 0x800 283 284 /* IO & Local APIC Bit Definitions */ 285 #define RDT_VECTOR(x) ((uchar_t)((x) & 0xFF)) 286 #define AV_PENDING 0x1000 287 #define AV_ACTIVE_LOW 0x2000 /* only for integrated APIC */ 288 #define AV_REMOTE_IRR 0x4000 /* IOAPIC RDT-specific */ 289 #define AV_LEVEL 0x8000 290 #define AV_DEASSERT AV_LEVEL 291 #define AV_ASSERT 0xc000 292 293 #define AV_READ_PENDING 0x10000 294 #define AV_REMOTE_STATUS 0x20000 /* 1 = valid, 0 = invalid */ 295 296 #define AV_SH_SELF 0x40000 /* Short hand for self */ 297 #define AV_SH_ALL_INCSELF 0x80000 /* All processors */ 298 #define AV_SH_ALL_EXCSELF 0xc0000 /* All excluding self */ 299 /* spurious interrupt vector register */ 300 #define AV_UNIT_ENABLE 0x100 301 302 /* timer vector table */ 303 #define AV_TIME 0x20000 /* Set timer mode to periodic */ 304 305 #define APIC_MAXVAL 0xffffffffUL 306 #define APIC_TIME_MIN 0x5000 307 #define APIC_TIME_COUNT 0x4000 308 309 /* 310 * Range of the low byte value in apic_tick before starting calibration 311 */ 312 #define APIC_LB_MIN 0x60 313 #define APIC_LB_MAX 0xe0 314 315 #define APIC_MAX_VECTOR 255 316 #define APIC_RESV_VECT 0x00 317 #define APIC_RESV_IRQ 0xfe 318 #define APIC_BASE_VECT 0x20 /* This will come in as interrupt 0 */ 319 #define APIC_AVAIL_VECTOR (APIC_MAX_VECTOR+1-APIC_BASE_VECT) 320 #define APIC_VECTOR_PER_IPL 0x10 /* # of vectors before PRI changes */ 321 #define APIC_VECTOR(ipl) (apic_ipltopri[ipl] | APIC_RESV_VECT) 322 #define APIC_VECTOR_MASK 0x0f 323 #define APIC_HI_PRI_VECTS 2 /* vects reserved for hi pri reqs */ 324 #define APIC_IPL_MASK 0xf0 325 #define APIC_IPL_SHIFT 4 /* >> to get ipl part of vector */ 326 #define APIC_FIRST_FREE_IRQ 0x10 327 #define APIC_MAX_ISA_IRQ 15 328 #define APIC_IPL0 0x0f /* let IDLE_IPL be the lowest */ 329 #define APIC_IDLE_IPL 0x00 330 331 #define APIC_MASK_ALL 0xf0 /* Mask all interrupts */ 332 333 /* spurious interrupt vector */ 334 #define APIC_SPUR_INTR 0xFF 335 336 /* special or reserve vectors */ 337 #define APIC_CHECK_RESERVE_VECTORS(v) \ 338 ((v == T_FASTTRAP) || (v == APIC_SPUR_INTR) || (v == T_SYSCALLINT) || \ 339 (v == T_DTRACE_RET) || (v == T_INT80)) 340 341 /* cmos shutdown code for BIOS */ 342 #define BIOS_SHUTDOWN 0x0a 343 344 /* define the entry types for BIOS information tables as defined in PC+MP */ 345 #define APIC_CPU_ENTRY 0 346 #define APIC_BUS_ENTRY 1 347 #define APIC_IO_ENTRY 2 348 #define APIC_IO_INTR_ENTRY 3 349 #define APIC_LOCAL_INTR_ENTRY 4 350 #define APIC_MPTBL_ADDR (639 * 1024) 351 /* 352 * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB 353 * of system base memory or in ROM between 0xF0000 and 0xFFFFF 354 */ 355 #define MPFPS_RAM_WIN_LEN 1024 356 #define MPFPS_ROM_WIN_START (uint32_t)0xf0000 357 #define MPFPS_ROM_WIN_LEN 0x10000 358 359 #define EISA_LEVEL_CNTL 0x4D0 360 361 /* definitions for apic_irq_table */ 362 #define FREE_INDEX (short)-1 /* empty slot */ 363 #define RESERVE_INDEX (short)-2 /* ipi, softintr, clkintr */ 364 #define ACPI_INDEX (short)-3 /* ACPI */ 365 #define MSI_INDEX (short)-4 /* MSI */ 366 #define MSIX_INDEX (short)-5 /* MSI-X */ 367 #define DEFAULT_INDEX (short)0x7FFF 368 /* biggest positive no. to avoid conflict with actual index */ 369 370 #define APIC_IS_MSI_OR_MSIX_INDEX(index) \ 371 ((index) == MSI_INDEX || (index) == MSIX_INDEX) 372 373 /* 374 * definitions for MSI Address 375 */ 376 #define MSI_ADDR_HDR APIC_LOCAL_ADDR 377 #define MSI_ADDR_DEST_SHIFT 12 /* Destination CPU's apic id */ 378 #define MSI_ADDR_RH_FIXED 0x0 /* Redirection Hint Fixed */ 379 #define MSI_ADDR_RH_LOPRI 0x1 /* Redirection Hint Lowest priority */ 380 #define MSI_ADDR_RH_SHIFT 3 381 #define MSI_ADDR_DM_PHYSICAL 0x0 /* Physical Destination Mode */ 382 #define MSI_ADDR_DM_LOGICAL 0x1 /* Logical Destination Mode */ 383 #define MSI_ADDR_DM_SHIFT 2 384 385 /* 386 * definitions for MSI Data 387 */ 388 #define MSI_DATA_DELIVERY_FIXED 0x0 /* Fixed delivery */ 389 #define MSI_DATA_DELIVERY_LOPRI 0x1 /* Lowest priority delivery */ 390 #define MSI_DATA_DELIVERY_SMI 0x2 391 #define MSI_DATA_DELIVERY_NMI 0x4 392 #define MSI_DATA_DELIVERY_INIT 0x5 393 #define MSI_DATA_DELIVERY_EXTINT 0x7 394 #define MSI_DATA_DELIVERY_SHIFT 8 395 #define MSI_DATA_TM_EDGE 0x0 /* MSI is edge sensitive */ 396 #define MSI_DATA_TM_LEVEL 0x1 /* level sensitive */ 397 #define MSI_DATA_TM_SHIFT 15 398 #define MSI_DATA_LEVEL_DEASSERT 0x0 399 #define MSI_DATA_LEVEL_ASSERT 0x1 /* Edge always assert */ 400 #define MSI_DATA_LEVEL_SHIFT 14 401 402 /* 403 * use to define each irq setup by the apic 404 */ 405 typedef struct apic_irq { 406 short airq_mps_intr_index; /* index into mps interrupt entries */ 407 /* table */ 408 uchar_t airq_intin_no; 409 uchar_t airq_ioapicindex; 410 dev_info_t *airq_dip; /* device corresponding to this interrupt */ 411 /* 412 * IRQ could be shared (in H/W) in which case dip & major will be 413 * for the one that was last added at this level. We cannot keep a 414 * linked list as delspl does not tell us which device has just 415 * been unloaded. For most servers where we are worried about 416 * performance, interrupt should not be shared & should not be 417 * a problem. This does not cause any correctness issue - dip is 418 * used only as an optimisation to avoid going thru all the tables 419 * in translate IRQ (which is always called twice due to brokenness 420 * in the way IPLs are determined for devices). major is used only 421 * to bind interrupts corresponding to the same device on the same 422 * CPU. Not finding major will just cause it to be potentially bound 423 * to another CPU. 424 */ 425 major_t airq_major; /* major number corresponding to the device */ 426 ushort_t airq_rdt_entry; /* level, polarity & trig mode */ 427 uchar_t airq_cpu; /* Which CPU are we bound to ? */ 428 uchar_t airq_temp_cpu; /* Could be diff from cpu due to disable_intr */ 429 uchar_t airq_vector; /* Vector chosen for this irq */ 430 uchar_t airq_share; /* number of interrupts at this irq */ 431 uchar_t airq_share_id; /* id to identify source from irqno */ 432 uchar_t airq_ipl; /* The ipl at which this is handled */ 433 iflag_t airq_iflag; /* interrupt flag */ 434 uchar_t airq_origirq; /* original irq passed in */ 435 uint_t airq_busy; /* How frequently did clock find */ 436 /* us in this */ 437 struct apic_irq *airq_next; /* chain of shared intpts */ 438 } apic_irq_t; 439 440 #define IRQ_USER_BOUND 0x80 /* user requested bind if set in airq_cpu */ 441 #define IRQ_UNBOUND (uchar_t)-1 /* set in airq_cpu and airq_temp_cpu */ 442 #define IRQ_UNINIT (uchar_t)-2 /* in airq_temp_cpu till addspl called */ 443 444 /* Macros to help deal with shared interrupts */ 445 #define VIRTIRQ(irqno, share_id) ((irqno) | ((share_id) << 8)) 446 #define IRQINDEX(irq) ((irq) & 0xFF) /* Mask to get irq from virtual irq */ 447 448 typedef struct apic_cpus_info { 449 uchar_t aci_local_id; 450 uchar_t aci_local_ver; 451 uchar_t aci_status; 452 uchar_t aci_redistribute; /* Selected for redistribution */ 453 uint_t aci_busy; /* Number of ticks we were in ISR */ 454 uint_t aci_spur_cnt; /* # of spurious intpts on this cpu */ 455 uint_t aci_ISR_in_progress; /* big enough to hold 1 << MAXIPL */ 456 uchar_t aci_curipl; /* IPL of current ISR */ 457 uchar_t aci_current[MAXIPL]; /* Current IRQ at each IPL */ 458 uint32_t aci_bound; /* # of user requested binds ? */ 459 uint32_t aci_temp_bound; /* # of non user IRQ binds */ 460 uchar_t aci_idle; /* The CPU is idle */ 461 /* 462 * fill to make sure each struct is in seperate cache line. 463 * Or atleast that ISR_in_progress/curipl is not shared with something 464 * that is read/written heavily by another CPU. 465 * Given kmem_alloc guarantees alignment to 8 bytes, having 8 466 * bytes on each side will isolate us in a 16 byte cache line. 467 */ 468 } apic_cpus_info_t; 469 470 #define APIC_CPU_ONLINE 1 471 #define APIC_CPU_INTR_ENABLE 2 472 473 /* 474 * Various poweroff methods and ports & bits for them 475 */ 476 #define APIC_POWEROFF_NONE 0 477 #define APIC_POWEROFF_VIA_RTC 1 478 #define APIC_POWEROFF_VIA_ASPEN_BMC 2 479 #define APIC_POWEROFF_VIA_SITKA_BMC 3 480 481 /* For RTC */ 482 #define RTC_REGA 0x0a 483 #define PFR_REG 0x4a /* extended control register */ 484 #define PAB_CBIT 0x08 485 #define WF_FLAG 0x02 486 #define KS_FLAG 0x01 487 #define EXT_BANK 0x10 488 489 /* For Aspen/Drake BMC */ 490 491 #define CC_SMS_GET_STATUS 0x40 492 #define CC_SMS_WR_START 0x41 493 #define CC_SMS_WR_NEXT 0x42 494 #define CC_SMS_WR_END 0x43 495 496 #define MISMIC_DATA_REGISTER 0x0ca9 497 #define MISMIC_CNTL_REGISTER 0x0caa 498 #define MISMIC_FLAG_REGISTER 0x0cab 499 500 #define MISMIC_BUSY_MASK 0x01 501 502 /* For Sitka/Cabrillo BMC */ 503 504 #define SMS_GET_STATUS 0x60 505 #define SMS_WRITE_START 0x61 506 #define SMS_WRITE_END 0x62 507 508 #define SMS_DATA_REGISTER 0x0ca2 509 #define SMS_STATUS_REGISTER 0x0ca3 510 #define SMS_COMMAND_REGISTER 0x0ca3 511 512 #define SMS_IBF_MASK 0x02 513 #define SMS_STATE_MASK 0xc0 514 515 #define SMS_IDLE_STATE 0x00 516 #define SMS_READ_STATE 0x40 517 #define SMS_WRITE_STATE 0x80 518 #define SMS_ERROR_STATE 0xc0 519 520 extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg); 521 extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value); 522 523 /* Macros for reading/writing the IOAPIC RDT entries */ 524 #define READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin) \ 525 ioapic_read(ioapic_ix, APIC_RDT_CMD + (2 * (ipin))) 526 527 #define READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin) \ 528 ioapic_read(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin))) 529 530 #define WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin, value) \ 531 ioapic_write(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)), value) 532 533 #define WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin, value) \ 534 ioapic_write(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)), value) 535 536 /* Used by PSM_INTR_OP_GET_INTR to return device information. */ 537 typedef struct { 538 uint16_t avgi_req_flags; /* request flags - to kernel */ 539 uint8_t avgi_num_devs; /* # devs on this ino - from kernel */ 540 uint8_t avgi_vector; /* vector */ 541 uint32_t avgi_cpu_id; /* cpu of interrupt - from kernel */ 542 dev_info_t **avgi_dip_list; /* kmem_alloc'ed list of dev_infos. */ 543 /* Contains num_devs elements. */ 544 } apic_get_intr_t; 545 546 /* Masks for avgi_req_flags. */ 547 #define PSMGI_REQ_CPUID 0x1 /* Request CPU ID */ 548 #define PSMGI_REQ_NUM_DEVS 0x2 /* Request num of devices on vector */ 549 #define PSMGI_REQ_VECTOR 0x4 550 #define PSMGI_REQ_GET_DEVS 0x8 /* Request device list */ 551 #define PSMGI_REQ_ALL 0xf /* Request everything */ 552 553 /* Other flags */ 554 #define PSMGI_INTRBY_VEC 0 /* Vec passed. xlate to IRQ needed */ 555 #define PSMGI_INTRBY_IRQ 0x8000 /* IRQ passed. no xlate needed */ 556 #define PSMGI_INTRBY_FLAGS 0x8000 /* Mask for this flag */ 557 558 /* 559 * Use scaled-fixed-point arithmetic to calculate apic ticks. 560 * Round when dividing (by adding half of divisor to dividend) 561 * for one extra bit of precision. 562 */ 563 564 #define SF (1ULL<<20) /* Scaling Factor: scale by 2^20 */ 565 #define APIC_TICKS_TO_NSECS(ticks) ((((int64_t)(ticks) * SF) + \ 566 apic_ticks_per_SFnsecs / 2) / \ 567 apic_ticks_per_SFnsecs); 568 #define APIC_NSECS_TO_TICKS(nsecs) (((int64_t)(nsecs) * \ 569 apic_ticks_per_SFnsecs + (SF/2)) / SF) 570 571 extern int apic_verbose; 572 573 /* Flag definitions for apic_verbose */ 574 #define APIC_VERBOSE_IOAPIC_FLAG 0x00000001 575 #define APIC_VERBOSE_IRQ_FLAG 0x00000002 576 #define APIC_VERBOSE_POWEROFF_FLAG 0x00000004 577 #define APIC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000008 578 579 580 #define APIC_VERBOSE_IOAPIC(fmt) \ 581 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) \ 582 cmn_err fmt; 583 584 #define APIC_VERBOSE_IRQ(fmt) \ 585 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) \ 586 cmn_err fmt; 587 588 #define APIC_VERBOSE_POWEROFF(fmt) \ 589 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \ 590 prom_printf fmt; 591 592 #ifdef DEBUG 593 #define DENT 0x0001 594 extern int apic_debug; 595 /* 596 * set apic_restrict_vector to the # of vectors we want to allow per range 597 * useful in testing shared interrupt logic by setting it to 2 or 3 598 */ 599 extern int apic_restrict_vector; 600 601 #define APIC_DEBUG_MSGBUFSIZE 2048 602 extern int apic_debug_msgbuf[]; 603 extern int apic_debug_msgbufindex; 604 605 /* 606 * Put "int" info into debug buffer. No MP consistency, but light weight. 607 * Good enough for most debugging. 608 */ 609 #define APIC_DEBUG_BUF_PUT(x) \ 610 apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \ 611 if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \ 612 apic_debug_msgbufindex = 0; 613 614 #endif /* DEBUG */ 615 616 extern int apic_error; 617 /* values which apic_error can take. Not catastrophic, but may help debug */ 618 #define APIC_ERR_BOOT_EOI 0x1 619 #define APIC_ERR_GET_IPIVECT_FAIL 0x2 620 #define APIC_ERR_INVALID_INDEX 0x4 621 #define APIC_ERR_MARK_VECTOR_FAIL 0x8 622 #define APIC_ERR_APIC_ERROR 0x40000000 623 #define APIC_ERR_NMI 0x80000000 624 625 /* 626 * ACPI definitions 627 */ 628 /* _PIC method arguments */ 629 #define ACPI_PIC_MODE 0 630 #define ACPI_APIC_MODE 1 631 632 /* APIC error flags we care about */ 633 #define APIC_SEND_CS_ERROR 0x01 634 #define APIC_RECV_CS_ERROR 0x02 635 #define APIC_CS_ERRORS (APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR) 636 637 /* Maximum number of times to retry reprogramming at apic_intr_exit time */ 638 #define APIC_REPROGRAM_MAX_TRIES 10000 639 640 /* Parameter to ioapic_init_intr(): Should ioapic ints be masked? */ 641 #define IOAPIC_MASK 1 642 #define IOAPIC_NOMASK 0 643 644 #define INTR_ROUND_ROBIN_WITH_AFFINITY 0 645 #define INTR_ROUND_ROBIN 1 646 #define INTR_LOWEST_PRIORITY 2 647 648 649 650 struct ioapic_reprogram_data { 651 boolean_t done; 652 apic_irq_t *irqp; 653 /* The CPU to which the int will be bound */ 654 int bindcpu; 655 /* # times the reprogram timeout was called */ 656 unsigned tries; 657 }; 658 659 /* The irq # is implicit in the array index: */ 660 extern struct ioapic_reprogram_data apic_reprogram_info[]; 661 662 extern void apic_intr_exit(int ipl, int irq); 663 extern int apic_probe_common(); 664 extern void apic_init_common(); 665 extern void ioapic_init_intr(); 666 extern void ioapic_disable_redirection(); 667 extern int apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 668 extern int apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 669 extern void apic_cleanup_busy(); 670 extern void apic_intr_redistribute(); 671 extern uchar_t apic_xlate_vector(uchar_t vector); 672 extern uchar_t apic_allocate_vector(int ipl, int irq, int pri); 673 extern void apic_free_vector(uchar_t vector); 674 extern int apic_allocate_irq(int irq); 675 extern uchar_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, 676 uchar_t intin); 677 extern int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, 678 struct ioapic_reprogram_data *drep); 679 extern int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu); 680 extern int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type); 681 extern int apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, 682 psm_intr_op_t intr_op, int *result); 683 extern boolean_t apic_cpu_in_range(int cpu); 684 extern int apic_check_msi_support(); 685 extern apic_irq_t *apic_find_irq(dev_info_t *dip, struct intrspec *ispec, 686 int type); 687 extern int apic_navail_vector(dev_info_t *dip, int pri); 688 extern int apic_alloc_vectors(dev_info_t *dip, int inum, int count, int pri, 689 int type, int behavior); 690 extern void apic_free_vectors(dev_info_t *dip, int inum, int count, int pri, 691 int type); 692 extern int apic_get_vector_intr_info(int vecirq, 693 apic_get_intr_t *intr_params_p); 694 extern uchar_t apic_find_multi_vectors(int pri, int count); 695 extern int apic_setup_io_intr(void *p, int irq, boolean_t deferred); 696 extern uint32_t *mapin_apic(uint32_t addr, size_t len, int flags); 697 extern uint32_t *mapin_ioapic(uint32_t addr, size_t len, int flags); 698 extern void mapout_apic(caddr_t addr, size_t len); 699 extern void mapout_ioapic(caddr_t addr, size_t len); 700 extern uchar_t apic_modify_vector(uchar_t vector, int irq); 701 extern int apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum); 702 extern int apic_pci_msi_disable_mode(dev_info_t *rdip, int type, int inum); 703 extern int apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum); 704 705 extern volatile uint32_t *apicadr; /* virtual addr of local APIC */ 706 extern int apic_forceload; 707 extern apic_cpus_info_t *apic_cpus; 708 extern cpuset_t apic_cpumask; 709 extern uint_t apic_flag; 710 extern uchar_t apic_ipltopri[MAXIPL+1]; 711 extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 712 extern int apic_max_device_irq; 713 extern int apic_min_device_irq; 714 extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 715 extern volatile uint32_t *apicioadr[MAX_IO_APIC]; 716 extern uchar_t apic_io_id[MAX_IO_APIC]; 717 extern lock_t apic_ioapic_lock; 718 extern uint32_t apic_physaddr[MAX_IO_APIC]; 719 extern kmutex_t airq_mutex; 720 extern int apic_first_avail_irq; 721 extern uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL]; 722 extern int apic_imcrp; 723 extern int apic_revector_pending; 724 extern char apic_level_intr[APIC_MAX_VECTOR+1]; 725 extern uchar_t apic_resv_vector[MAXIPL+1]; 726 extern int apic_sample_factor_redistribution; 727 extern int apic_int_busy_mark; 728 extern int apic_int_free_mark; 729 extern int apic_diff_for_redistribution; 730 extern int apic_poweroff_method; 731 extern int apic_enable_acpi; 732 extern int apic_nproc; 733 extern int apic_next_bind_cpu; 734 extern int apic_redistribute_sample_interval; 735 extern int apic_multi_msi_enable; 736 extern int apic_multi_msi_max; 737 extern int apic_sci_vect; 738 739 740 741 #ifdef __cplusplus 742 } 743 #endif 744 745 #endif /* _SYS_APIC_APIC_H */ 746