1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_AUXV_386_H 27 #define _SYS_AUXV_386_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Flags used in AT_SUN_HWCAP elements to describe various userland 37 * instruction set extensions available on different processors. 38 * The basic assumption is that of the i386 ABI; that is, i386 plus i387 39 * floating point. 40 * 41 * Note that if a given bit is set; the implication is that the kernel 42 * provides all the underlying architectural support for the correct 43 * functioning of the extended instruction(s). 44 */ 45 #define AV_386_FPU 0x00001 /* x87-style floating point */ 46 #define AV_386_TSC 0x00002 /* rdtsc insn */ 47 #define AV_386_CX8 0x00004 /* cmpxchg8b insn */ 48 #define AV_386_SEP 0x00008 /* sysenter and sysexit */ 49 #define AV_386_AMD_SYSC 0x00010 /* AMD's syscall and sysret */ 50 #define AV_386_CMOV 0x00020 /* conditional move insns */ 51 #define AV_386_MMX 0x00040 /* MMX insns */ 52 #define AV_386_AMD_MMX 0x00080 /* AMD's MMX insns */ 53 #define AV_386_AMD_3DNow 0x00100 /* AMD's 3Dnow! insns */ 54 #define AV_386_AMD_3DNowx 0x00200 /* AMD's 3Dnow! extended insns */ 55 #define AV_386_FXSR 0x00400 /* fxsave and fxrstor */ 56 #define AV_386_SSE 0x00800 /* SSE insns and regs */ 57 #define AV_386_SSE2 0x01000 /* SSE2 insns and regs */ 58 #define AV_386_PAUSE 0x02000 /* use pause insn (in spin loops) */ 59 #define AV_386_SSE3 0x04000 /* SSE3 insns and regs */ 60 #define AV_386_MON 0x08000 /* monitor/mwait insns */ 61 #define AV_386_CX16 0x10000 /* cmpxchg16b insn */ 62 #define AV_386_AHF 0x20000 /* lahf/sahf insns */ 63 #define AV_386_TSCP 0x40000 /* rdtscp instruction */ 64 #define AV_386_AMD_SSE4A 0x80000 /* AMD's SSE4A insns */ 65 #define AV_386_POPCNT 0x100000 /* POPCNT insn */ 66 #define AV_386_AMD_LZCNT 0x200000 /* AMD's LZCNT insn */ 67 #define AV_386_SSSE3 0x400000 /* Intel SSSE3 insns */ 68 #define AV_386_SSE4_1 0x800000 /* Intel SSE4.1 insns */ 69 #define AV_386_SSE4_2 0x1000000 /* Intel SSE4.2 insns */ 70 71 #define FMT_AV_386 \ 72 "\20" \ 73 "\31sse4.2" \ 74 "\30sse4.1\27ssse3\26amd_lzcnt\25popcnt" \ 75 "\24amd_sse4a\23tscp\22ahf\21cx16" \ 76 "\20mon\17sse3\16pause\15sse2\14sse\13fxsr\12amd3dx\11amd3d" \ 77 "\10amdmmx\7mmx\6cmov\5amdsysc\4sep\3cx8\2tsc\1fpu" 78 79 #ifdef __cplusplus 80 } 81 #endif 82 83 #endif /* !_SYS_AUXV_386_H */ 84