1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright (c) 2002-2005 Neterion, Inc. 29 * All right Reserved. 30 * 31 * FileName : xgell.h 32 * 33 * Description: Link Layer driver declaration 34 * 35 */ 36 37 #ifndef _SYS_XGELL_H 38 #define _SYS_XGELL_H 39 40 #pragma ident "%Z%%M% %I% %E% SMI" 41 42 #include <sys/types.h> 43 #include <sys/errno.h> 44 #include <sys/param.h> 45 #include <sys/stropts.h> 46 #include <sys/stream.h> 47 #include <sys/strsubr.h> 48 #include <sys/kmem.h> 49 #include <sys/conf.h> 50 #include <sys/devops.h> 51 #include <sys/ksynch.h> 52 #include <sys/stat.h> 53 #include <sys/modctl.h> 54 #include <sys/debug.h> 55 #include <sys/pci.h> 56 #include <sys/ethernet.h> 57 #include <sys/vlan.h> 58 #include <sys/dlpi.h> 59 #include <sys/taskq.h> 60 #include <sys/cyclic.h> 61 62 #include <sys/pattr.h> 63 #include <sys/strsun.h> 64 65 #include <sys/mac.h> 66 #include <sys/mac_ether.h> 67 68 #ifdef __cplusplus 69 extern "C" { 70 #endif 71 72 #define XGELL_DESC "Xframe I/II 10Gb Ethernet %I%" 73 #define XGELL_IFNAME "xge" 74 #define XGELL_TX_LEVEL_LOW 8 75 #define XGELL_TX_LEVEL_HIGH 32 76 77 #include <xgehal.h> 78 79 #if defined(__sparc) || defined(__amd64) 80 #define XGELL_L3_ALIGNED 1 81 #endif 82 83 /* Control driver to copy or DMA received packets */ 84 #define XGELL_DMA_BUFFER_SIZE_LOWAT 256 85 86 /* There default values can be overrided by vaules in xge.conf */ 87 #define XGELL_RX_BUFFER_TOTAL (1024 * 6) /* 6K */ 88 #define XGELL_RX_BUFFER_POST_HIWAT (1024 * 3) /* 3K */ 89 #define XGELL_RX_BUFFER_RECYCLE_HIWAT 64 90 91 #define XGELL_RING_MAIN_QID 0 92 93 /* About 1s */ 94 #define XGE_DEV_POLL_TICKS drv_usectohz(1000000) 95 96 /* 97 * If HAL could provide defualt values to all tunables, we'll remove following 98 * macros. 99 * Before removing, please refer to xgehal-config.h for more details. 100 */ 101 #define XGE_HAL_DEFAULT_USE_HARDCODE -1 102 103 /* 104 * The reason to define different values for Link Utilization interrupts is 105 * different performance numbers between SPARC and x86 platforms. 106 */ 107 #if defined(__sparc) 108 #define XGE_HAL_DEFAULT_TX_URANGE_A 2 109 #define XGE_HAL_DEFAULT_TX_UFC_A 1 110 #define XGE_HAL_DEFAULT_TX_URANGE_B 5 111 #define XGE_HAL_DEFAULT_TX_UFC_B 10 112 #define XGE_HAL_DEFAULT_TX_URANGE_C 10 113 #define XGE_HAL_DEFAULT_TX_UFC_C 40 114 #define XGE_HAL_DEFAULT_TX_UFC_D 80 115 #define XGE_HAL_DEFAULT_TX_TIMER_CI_EN 1 116 #define XGE_HAL_DEFAULT_TX_TIMER_AC_EN 1 117 #define XGE_HAL_DEFAULT_TX_TIMER_VAL 4000 118 #define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS 128 119 #define XGE_HAL_DEFAULT_RX_URANGE_A 2 120 #define XGE_HAL_DEFAULT_RX_UFC_A 1 121 #define XGE_HAL_DEFAULT_RX_URANGE_B 5 122 #define XGE_HAL_DEFAULT_RX_UFC_B 10 123 #define XGE_HAL_DEFAULT_RX_URANGE_C 10 124 #define XGE_HAL_DEFAULT_RX_UFC_C 40 125 #define XGE_HAL_DEFAULT_RX_UFC_D 80 126 #define XGE_HAL_DEFAULT_RX_TIMER_AC_EN 1 127 #define XGE_HAL_DEFAULT_RX_TIMER_VAL 24 128 #else 129 #define XGE_HAL_DEFAULT_TX_URANGE_A 10 130 #define XGE_HAL_DEFAULT_TX_UFC_A 1 131 #define XGE_HAL_DEFAULT_TX_URANGE_B 20 132 #define XGE_HAL_DEFAULT_TX_UFC_B 10 133 #define XGE_HAL_DEFAULT_TX_URANGE_C 50 134 #define XGE_HAL_DEFAULT_TX_UFC_C 40 135 #define XGE_HAL_DEFAULT_TX_UFC_D 80 136 #define XGE_HAL_DEFAULT_TX_TIMER_CI_EN 1 137 #define XGE_HAL_DEFAULT_TX_TIMER_AC_EN 1 138 #define XGE_HAL_DEFAULT_TX_TIMER_VAL 4000 139 #define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS 128 140 #define XGE_HAL_DEFAULT_RX_URANGE_A 10 141 #define XGE_HAL_DEFAULT_RX_UFC_A 1 142 #define XGE_HAL_DEFAULT_RX_URANGE_B 20 143 #define XGE_HAL_DEFAULT_RX_UFC_B 10 144 #define XGE_HAL_DEFAULT_RX_URANGE_C 50 145 #define XGE_HAL_DEFAULT_RX_UFC_C 40 146 #define XGE_HAL_DEFAULT_RX_UFC_D 80 147 #define XGE_HAL_DEFAULT_RX_TIMER_AC_EN 1 148 #define XGE_HAL_DEFAULT_RX_TIMER_VAL 24 149 #endif 150 151 #define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_J 2048 152 #define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_N 4096 153 #define XGE_HAL_DEFAULT_FIFO_QUEUE_INTR 0 154 #define XGE_HAL_DEFAULT_FIFO_RESERVE_THRESHOLD 0 155 #define XGE_HAL_DEFAULT_FIFO_MEMBLOCK_SIZE PAGESIZE 156 157 #ifdef XGELL_TX_NOMAP_COPY 158 159 #define XGE_HAL_DEFAULT_FIFO_FRAGS 1 160 #define XGE_HAL_DEFAULT_FIFO_FRAGS_THRESHOLD 0 161 #define XGE_HAL_DEFAULT_FIFO_ALIGNMENT_SIZE (XGE_HAL_MAC_HEADER_MAX_SIZE + \ 162 XGE_HAL_DEFAULT_MTU) 163 #define XGE_HAL_DEFAULT_FIFO_MAX_ALIGNED_FRAGS 1 164 #else 165 166 #if defined(__x86) 167 #define XGE_HAL_DEFAULT_FIFO_FRAGS 32 168 #else 169 #define XGE_HAL_DEFAULT_FIFO_FRAGS 16 170 #endif 171 #define XGE_HAL_DEFAULT_FIFO_FRAGS_THRESHOLD 4 172 #define XGE_HAL_DEFAULT_FIFO_ALIGNMENT_SIZE sizeof (uint64_t) 173 #define XGE_HAL_DEFAULT_FIFO_MAX_ALIGNED_FRAGS 6 174 175 #endif /* XGELL_TX_NOMAP_COPY */ 176 177 #define XGE_HAL_DEFAULT_RING_QUEUE_BLOCKS_J 16 178 #define XGE_HAL_DEFAULT_RING_QUEUE_BLOCKS_N 32 179 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_DEFAULT 1 180 #define XGE_HAL_DEFAULT_RING_QUEUE_SIZE 64 181 #define XGE_HAL_DEFAULT_BACKOFF_INTERVAL_US 35 182 #define XGE_HAL_DEFAULT_RING_PRIORITY 0 183 #define XGE_HAL_DEFAULT_RING_MEMBLOCK_SIZE PAGESIZE 184 185 #define XGE_HAL_DEFAULT_RING_NUM 8 186 #define XGE_HAL_DEFAULT_TMAC_UTIL_PERIOD 5 187 #define XGE_HAL_DEFAULT_RMAC_UTIL_PERIOD 5 188 #define XGE_HAL_DEFAULT_RMAC_HIGH_PTIME 65535 189 #define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q0Q3 187 190 #define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q4Q7 187 191 #define XGE_HAL_DEFAULT_INITIAL_MTU XGE_HAL_DEFAULT_MTU /* 1500 */ 192 #define XGE_HAL_DEFAULT_ISR_POLLING_CNT 4 193 #define XGE_HAL_DEFAULT_LATENCY_TIMER 255 194 #define XGE_HAL_DEFAULT_SPLIT_TRANSACTION 1 /* 2 splits */ 195 #define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT -1 196 #define XGE_HAL_DEFAULT_MMRB_COUNT 1 /* 1k */ 197 #define XGE_HAL_DEFAULT_SHARED_SPLITS 0 198 #define XGE_HAL_DEFAULT_STATS_REFRESH_TIME 1 199 #define XGE_HAL_PCI_FREQ_MHERZ_DEFAULT 133 200 201 /* 202 * default the size of buffers allocated for ndd interface functions 203 */ 204 #define XGELL_STATS_BUFSIZE 4096 205 #define XGELL_PCICONF_BUFSIZE 2048 206 #define XGELL_ABOUT_BUFSIZE 512 207 #define XGELL_IOCTL_BUFSIZE 64 208 #define XGELL_DEVCONF_BUFSIZE 4096 209 210 /* 211 * xgell_event_e 212 * 213 * This enumeration derived from xgehal_event_e. It extends it 214 * for the reason to get serialized context. 215 */ 216 /* Renamb the macro from HAL */ 217 #define XGELL_EVENT_BASE XGE_LL_EVENT_BASE 218 typedef enum xgell_event_e { 219 /* LL events */ 220 XGELL_EVENT_RESCHED_NEEDED = XGELL_EVENT_BASE + 1, 221 } xgell_event_e; 222 223 typedef struct { 224 int rx_buffer_total; 225 int rx_buffer_post_hiwat; 226 int rx_buffer_recycle_hiwat; 227 } xgell_config_t; 228 229 typedef struct xgell_rx_buffer_t { 230 struct xgell_rx_buffer_t *next; 231 void *vaddr; 232 dma_addr_t dma_addr; 233 ddi_dma_handle_t dma_handle; 234 ddi_acc_handle_t dma_acch; 235 void *lldev; 236 frtn_t frtn; 237 #ifdef XGELL_L3_ALIGNED 238 unsigned char header[XGE_HAL_TCPIP_HEADER_MAX_SIZE * 2 239 + 8]; 240 #endif 241 } xgell_rx_buffer_t; 242 243 /* Buffer pool for all rings */ 244 typedef struct xgell_rx_buffer_pool_t { 245 uint_t total; /* total buffers */ 246 uint_t size; /* buffer size */ 247 xgell_rx_buffer_t *head; /* header pointer */ 248 uint_t recycle_hiwat; /* hiwat to recycle */ 249 uint_t free; /* free buffers */ 250 uint_t post; /* posted buffers */ 251 uint_t post_hiwat; /* hiwat to stop post */ 252 spinlock_t pool_lock; /* buffer pool lock */ 253 } xgell_rx_buffer_pool_t; 254 255 typedef struct xgelldev xgelldev_t; 256 257 typedef struct xgell_ring_t { 258 xge_hal_channel_h channelh; 259 xgelldev_t *lldev; 260 mac_resource_handle_t handle; /* per ring cookie */ 261 } xgell_ring_t; 262 263 struct xgelldev { 264 caddr_t ndp; 265 mac_handle_t mh; 266 int instance; 267 dev_info_t *dev_info; 268 xge_hal_device_h devh; 269 xgell_ring_t ring_main; 270 xgell_rx_buffer_pool_t bf_pool; 271 int resched_avail; 272 int resched_send; 273 int resched_retry; 274 xge_hal_channel_h fifo_channel; 275 volatile int is_initialized; 276 xgell_config_t config; 277 volatile int in_reset; 278 timeout_id_t timeout_id; 279 kmutex_t genlock; 280 }; 281 282 typedef struct { 283 mblk_t *mblk; 284 #if !defined(XGELL_TX_NOMAP_COPY) 285 ddi_dma_handle_t dma_handles[XGE_HAL_DEFAULT_FIFO_FRAGS]; 286 int handle_cnt; 287 #endif 288 } xgell_txd_priv_t; 289 290 typedef struct { 291 xgell_rx_buffer_t *rx_buffer; 292 } xgell_rxd_priv_t; 293 294 int xgell_device_alloc(xge_hal_device_h devh, dev_info_t *dev_info, 295 xgelldev_t **lldev_out); 296 297 void xgell_device_free(xgelldev_t *lldev); 298 299 int xgell_device_register(xgelldev_t *lldev, xgell_config_t *config); 300 301 int xgell_device_unregister(xgelldev_t *lldev); 302 303 void xgell_callback_link_up(void *userdata); 304 305 void xgell_callback_link_down(void *userdata); 306 307 int xgell_onerr_reset(xgelldev_t *lldev); 308 309 void xge_device_poll_now(void *data); 310 311 #ifdef __cplusplus 312 } 313 #endif 314 315 #endif /* _SYS_XGELL_H */ 316