1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include "rge.h" 29 30 /* 31 * This is the string displayed by modinfo, etc. 32 * Make sure you keep the version ID up to date! 33 */ 34 static char rge_ident[] = "Realtek 1Gb Ethernet v%I%"; 35 36 /* 37 * Used for buffers allocated by ddi_dma_mem_alloc() 38 */ 39 static ddi_dma_attr_t dma_attr_buf = { 40 DMA_ATTR_V0, /* dma_attr version */ 41 (uint32_t)0, /* dma_attr_addr_lo */ 42 (uint32_t)0xFFFFFFFF, /* dma_attr_addr_hi */ 43 (uint32_t)0xFFFFFFFF, /* dma_attr_count_max */ 44 (uint32_t)16, /* dma_attr_align */ 45 0xFFFFFFFF, /* dma_attr_burstsizes */ 46 1, /* dma_attr_minxfer */ 47 (uint32_t)0xFFFFFFFF, /* dma_attr_maxxfer */ 48 (uint32_t)0xFFFFFFFF, /* dma_attr_seg */ 49 1, /* dma_attr_sgllen */ 50 1, /* dma_attr_granular */ 51 0, /* dma_attr_flags */ 52 }; 53 54 /* 55 * Used for BDs allocated by ddi_dma_mem_alloc() 56 */ 57 static ddi_dma_attr_t dma_attr_desc = { 58 DMA_ATTR_V0, /* dma_attr version */ 59 (uint32_t)0, /* dma_attr_addr_lo */ 60 (uint32_t)0xFFFFFFFF, /* dma_attr_addr_hi */ 61 (uint32_t)0xFFFFFFFF, /* dma_attr_count_max */ 62 (uint32_t)256, /* dma_attr_align */ 63 0xFFFFFFFF, /* dma_attr_burstsizes */ 64 1, /* dma_attr_minxfer */ 65 (uint32_t)0xFFFFFFFF, /* dma_attr_maxxfer */ 66 (uint32_t)0xFFFFFFFF, /* dma_attr_seg */ 67 1, /* dma_attr_sgllen */ 68 1, /* dma_attr_granular */ 69 0, /* dma_attr_flags */ 70 }; 71 72 /* 73 * PIO access attributes for registers 74 */ 75 static ddi_device_acc_attr_t rge_reg_accattr = { 76 DDI_DEVICE_ATTR_V0, 77 DDI_STRUCTURE_LE_ACC, 78 DDI_STRICTORDER_ACC, 79 DDI_DEFAULT_ACC 80 }; 81 82 /* 83 * DMA access attributes for descriptors 84 */ 85 static ddi_device_acc_attr_t rge_desc_accattr = { 86 DDI_DEVICE_ATTR_V0, 87 DDI_NEVERSWAP_ACC, 88 DDI_STRICTORDER_ACC, 89 DDI_DEFAULT_ACC 90 }; 91 92 /* 93 * DMA access attributes for data 94 */ 95 static ddi_device_acc_attr_t rge_buf_accattr = { 96 DDI_DEVICE_ATTR_V0, 97 DDI_NEVERSWAP_ACC, 98 DDI_STRICTORDER_ACC, 99 DDI_DEFAULT_ACC 100 }; 101 102 /* 103 * Property names 104 */ 105 static char debug_propname[] = "rge_debug_flags"; 106 static char mtu_propname[] = "default_mtu"; 107 static char msi_propname[] = "msi_enable"; 108 109 static int rge_m_start(void *); 110 static void rge_m_stop(void *); 111 static int rge_m_promisc(void *, boolean_t); 112 static int rge_m_multicst(void *, boolean_t, const uint8_t *); 113 static int rge_m_unicst(void *, const uint8_t *); 114 static void rge_m_resources(void *); 115 static void rge_m_ioctl(void *, queue_t *, mblk_t *); 116 static boolean_t rge_m_getcapab(void *, mac_capab_t, void *); 117 118 #define RGE_M_CALLBACK_FLAGS (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB) 119 120 static mac_callbacks_t rge_m_callbacks = { 121 RGE_M_CALLBACK_FLAGS, 122 rge_m_stat, 123 rge_m_start, 124 rge_m_stop, 125 rge_m_promisc, 126 rge_m_multicst, 127 rge_m_unicst, 128 rge_m_tx, 129 rge_m_resources, 130 rge_m_ioctl, 131 rge_m_getcapab 132 }; 133 134 /* 135 * Allocate an area of memory and a DMA handle for accessing it 136 */ 137 static int 138 rge_alloc_dma_mem(rge_t *rgep, size_t memsize, ddi_dma_attr_t *dma_attr_p, 139 ddi_device_acc_attr_t *acc_attr_p, uint_t dma_flags, dma_area_t *dma_p) 140 { 141 caddr_t vaddr; 142 int err; 143 144 /* 145 * Allocate handle 146 */ 147 err = ddi_dma_alloc_handle(rgep->devinfo, dma_attr_p, 148 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl); 149 if (err != DDI_SUCCESS) { 150 dma_p->dma_hdl = NULL; 151 return (DDI_FAILURE); 152 } 153 154 /* 155 * Allocate memory 156 */ 157 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, acc_attr_p, 158 dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING), 159 DDI_DMA_SLEEP, NULL, &vaddr, &dma_p->alength, &dma_p->acc_hdl); 160 if (err != DDI_SUCCESS) { 161 ddi_dma_free_handle(&dma_p->dma_hdl); 162 dma_p->dma_hdl = NULL; 163 dma_p->acc_hdl = NULL; 164 return (DDI_FAILURE); 165 } 166 167 /* 168 * Bind the two together 169 */ 170 dma_p->mem_va = vaddr; 171 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 172 vaddr, dma_p->alength, dma_flags, DDI_DMA_SLEEP, NULL, 173 &dma_p->cookie, &dma_p->ncookies); 174 if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1) { 175 ddi_dma_mem_free(&dma_p->acc_hdl); 176 ddi_dma_free_handle(&dma_p->dma_hdl); 177 dma_p->acc_hdl = NULL; 178 dma_p->dma_hdl = NULL; 179 return (DDI_FAILURE); 180 } 181 182 dma_p->nslots = ~0U; 183 dma_p->size = ~0U; 184 dma_p->token = ~0U; 185 dma_p->offset = 0; 186 return (DDI_SUCCESS); 187 } 188 189 /* 190 * Free one allocated area of DMAable memory 191 */ 192 static void 193 rge_free_dma_mem(dma_area_t *dma_p) 194 { 195 if (dma_p->dma_hdl != NULL) { 196 if (dma_p->ncookies) { 197 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 198 dma_p->ncookies = 0; 199 } 200 ddi_dma_free_handle(&dma_p->dma_hdl); 201 dma_p->dma_hdl = NULL; 202 } 203 204 if (dma_p->acc_hdl != NULL) { 205 ddi_dma_mem_free(&dma_p->acc_hdl); 206 dma_p->acc_hdl = NULL; 207 } 208 } 209 210 /* 211 * Utility routine to carve a slice off a chunk of allocated memory, 212 * updating the chunk descriptor accordingly. The size of the slice 213 * is given by the product of the <qty> and <size> parameters. 214 */ 215 static void 216 rge_slice_chunk(dma_area_t *slice, dma_area_t *chunk, 217 uint32_t qty, uint32_t size) 218 { 219 static uint32_t sequence = 0xbcd5704a; 220 size_t totsize; 221 222 totsize = qty*size; 223 ASSERT(size >= 0); 224 ASSERT(totsize <= chunk->alength); 225 226 *slice = *chunk; 227 slice->nslots = qty; 228 slice->size = size; 229 slice->alength = totsize; 230 slice->token = ++sequence; 231 232 chunk->mem_va = (caddr_t)chunk->mem_va + totsize; 233 chunk->alength -= totsize; 234 chunk->offset += totsize; 235 chunk->cookie.dmac_laddress += totsize; 236 chunk->cookie.dmac_size -= totsize; 237 } 238 239 static int 240 rge_alloc_bufs(rge_t *rgep) 241 { 242 size_t txdescsize; 243 size_t rxdescsize; 244 int err; 245 246 /* 247 * Allocate memory & handle for packet statistics 248 */ 249 err = rge_alloc_dma_mem(rgep, 250 RGE_STATS_DUMP_SIZE, 251 &dma_attr_desc, 252 &rge_desc_accattr, 253 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 254 &rgep->dma_area_stats); 255 if (err != DDI_SUCCESS) 256 return (DDI_FAILURE); 257 rgep->hw_stats = DMA_VPTR(rgep->dma_area_stats); 258 259 /* 260 * Allocate memory & handle for Tx descriptor ring 261 */ 262 txdescsize = RGE_SEND_SLOTS * sizeof (rge_bd_t); 263 err = rge_alloc_dma_mem(rgep, 264 txdescsize, 265 &dma_attr_desc, 266 &rge_desc_accattr, 267 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 268 &rgep->dma_area_txdesc); 269 if (err != DDI_SUCCESS) 270 return (DDI_FAILURE); 271 272 /* 273 * Allocate memory & handle for Rx descriptor ring 274 */ 275 rxdescsize = RGE_RECV_SLOTS * sizeof (rge_bd_t); 276 err = rge_alloc_dma_mem(rgep, 277 rxdescsize, 278 &dma_attr_desc, 279 &rge_desc_accattr, 280 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 281 &rgep->dma_area_rxdesc); 282 if (err != DDI_SUCCESS) 283 return (DDI_FAILURE); 284 285 return (DDI_SUCCESS); 286 } 287 288 /* 289 * rge_free_bufs() -- free descriptors/buffers allocated for this 290 * device instance. 291 */ 292 static void 293 rge_free_bufs(rge_t *rgep) 294 { 295 rge_free_dma_mem(&rgep->dma_area_stats); 296 rge_free_dma_mem(&rgep->dma_area_txdesc); 297 rge_free_dma_mem(&rgep->dma_area_rxdesc); 298 } 299 300 /* 301 * ========== Transmit and receive ring reinitialisation ========== 302 */ 303 304 /* 305 * These <reinit> routines each reset the rx/tx rings to an initial 306 * state, assuming that the corresponding <init> routine has already 307 * been called exactly once. 308 */ 309 static void 310 rge_reinit_send_ring(rge_t *rgep) 311 { 312 sw_sbd_t *ssbdp; 313 rge_bd_t *bdp; 314 uint32_t slot; 315 316 /* 317 * re-init send ring 318 */ 319 DMA_ZERO(rgep->tx_desc); 320 ssbdp = rgep->sw_sbds; 321 bdp = rgep->tx_ring; 322 for (slot = 0; slot < RGE_SEND_SLOTS; slot++) { 323 bdp->host_buf_addr = 324 RGE_BSWAP_32(ssbdp->pbuf.cookie.dmac_laddress); 325 bdp->host_buf_addr_hi = 326 RGE_BSWAP_32(ssbdp->pbuf.cookie.dmac_laddress >> 32); 327 /* last BD in Tx ring */ 328 if (slot == (RGE_SEND_SLOTS - 1)) 329 bdp->flags_len = RGE_BSWAP_32(BD_FLAG_EOR); 330 ssbdp++; 331 bdp++; 332 } 333 DMA_SYNC(rgep->tx_desc, DDI_DMA_SYNC_FORDEV); 334 rgep->tx_next = 0; 335 rgep->tc_next = 0; 336 rgep->tc_tail = 0; 337 rgep->tx_flow = 0; 338 rgep->tx_free = RGE_SEND_SLOTS; 339 } 340 341 static void 342 rge_reinit_recv_ring(rge_t *rgep) 343 { 344 rge_bd_t *bdp; 345 sw_rbd_t *srbdp; 346 dma_area_t *pbuf; 347 uint32_t slot; 348 349 /* 350 * re-init receive ring 351 */ 352 DMA_ZERO(rgep->rx_desc); 353 srbdp = rgep->sw_rbds; 354 bdp = rgep->rx_ring; 355 for (slot = 0; slot < RGE_RECV_SLOTS; slot++) { 356 pbuf = &srbdp->rx_buf->pbuf; 357 bdp->host_buf_addr = 358 RGE_BSWAP_32(pbuf->cookie.dmac_laddress + rgep->head_room); 359 bdp->host_buf_addr_hi = 360 RGE_BSWAP_32(pbuf->cookie.dmac_laddress >> 32); 361 bdp->flags_len = RGE_BSWAP_32(BD_FLAG_HW_OWN | 362 (rgep->rxbuf_size - rgep->head_room)); 363 /* last BD in Tx ring */ 364 if (slot == (RGE_RECV_SLOTS - 1)) 365 bdp->flags_len |= RGE_BSWAP_32(BD_FLAG_EOR); 366 srbdp++; 367 bdp++; 368 } 369 DMA_SYNC(rgep->rx_desc, DDI_DMA_SYNC_FORDEV); 370 rgep->watchdog = 0; 371 rgep->rx_next = 0; 372 } 373 374 static void 375 rge_reinit_buf_ring(rge_t *rgep) 376 { 377 378 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY) 379 return; 380 381 /* 382 * If all the up-sending buffers haven't been returned to driver, 383 * use bcopy() only in rx process. 384 */ 385 if (rgep->rx_free != RGE_BUF_SLOTS) 386 rgep->rx_bcopy = B_TRUE; 387 } 388 389 static void 390 rge_reinit_rings(rge_t *rgep) 391 { 392 rge_reinit_send_ring(rgep); 393 rge_reinit_recv_ring(rgep); 394 rge_reinit_buf_ring(rgep); 395 } 396 397 static void 398 rge_fini_send_ring(rge_t *rgep) 399 { 400 sw_sbd_t *ssbdp; 401 uint32_t slot; 402 403 ssbdp = rgep->sw_sbds; 404 for (slot = 0; slot < RGE_SEND_SLOTS; ++slot) { 405 rge_free_dma_mem(&ssbdp->pbuf); 406 ssbdp++; 407 } 408 409 kmem_free(rgep->sw_sbds, RGE_SEND_SLOTS * sizeof (sw_sbd_t)); 410 rgep->sw_sbds = NULL; 411 } 412 413 static void 414 rge_fini_recv_ring(rge_t *rgep) 415 { 416 sw_rbd_t *srbdp; 417 uint32_t slot; 418 419 srbdp = rgep->sw_rbds; 420 for (slot = 0; slot < RGE_RECV_SLOTS; ++srbdp, ++slot) { 421 if (srbdp->rx_buf) { 422 if (srbdp->rx_buf->mp != NULL) { 423 freemsg(srbdp->rx_buf->mp); 424 srbdp->rx_buf->mp = NULL; 425 } 426 rge_free_dma_mem(&srbdp->rx_buf->pbuf); 427 kmem_free(srbdp->rx_buf, sizeof (dma_buf_t)); 428 srbdp->rx_buf = NULL; 429 } 430 } 431 432 kmem_free(rgep->sw_rbds, RGE_RECV_SLOTS * sizeof (sw_rbd_t)); 433 rgep->sw_rbds = NULL; 434 } 435 436 static void 437 rge_fini_buf_ring(rge_t *rgep) 438 { 439 sw_rbd_t *srbdp; 440 uint32_t slot; 441 442 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY) 443 return; 444 445 ASSERT(rgep->rx_free == RGE_BUF_SLOTS); 446 447 srbdp = rgep->free_srbds; 448 for (slot = 0; slot < RGE_BUF_SLOTS; ++srbdp, ++slot) { 449 if (srbdp->rx_buf != NULL) { 450 if (srbdp->rx_buf->mp != NULL) { 451 freemsg(srbdp->rx_buf->mp); 452 srbdp->rx_buf->mp = NULL; 453 } 454 rge_free_dma_mem(&srbdp->rx_buf->pbuf); 455 kmem_free(srbdp->rx_buf, sizeof (dma_buf_t)); 456 srbdp->rx_buf = NULL; 457 } 458 } 459 460 kmem_free(rgep->free_srbds, RGE_BUF_SLOTS * sizeof (sw_rbd_t)); 461 rgep->free_srbds = NULL; 462 } 463 464 static void 465 rge_fini_rings(rge_t *rgep) 466 { 467 rge_fini_send_ring(rgep); 468 rge_fini_recv_ring(rgep); 469 rge_fini_buf_ring(rgep); 470 } 471 472 static int 473 rge_init_send_ring(rge_t *rgep) 474 { 475 uint32_t slot; 476 sw_sbd_t *ssbdp; 477 dma_area_t *pbuf; 478 dma_area_t desc; 479 int err; 480 481 /* 482 * Allocate the array of s/w Tx Buffer Descriptors 483 */ 484 ssbdp = kmem_zalloc(RGE_SEND_SLOTS*sizeof (*ssbdp), KM_SLEEP); 485 rgep->sw_sbds = ssbdp; 486 487 /* 488 * Init send ring 489 */ 490 rgep->tx_desc = rgep->dma_area_txdesc; 491 DMA_ZERO(rgep->tx_desc); 492 rgep->tx_ring = rgep->tx_desc.mem_va; 493 494 desc = rgep->tx_desc; 495 for (slot = 0; slot < RGE_SEND_SLOTS; slot++) { 496 rge_slice_chunk(&ssbdp->desc, &desc, 1, sizeof (rge_bd_t)); 497 498 /* 499 * Allocate memory & handle for Tx buffers 500 */ 501 pbuf = &ssbdp->pbuf; 502 err = rge_alloc_dma_mem(rgep, rgep->txbuf_size, 503 &dma_attr_buf, &rge_buf_accattr, 504 DDI_DMA_WRITE | DDI_DMA_STREAMING, pbuf); 505 if (err != DDI_SUCCESS) { 506 rge_error(rgep, 507 "rge_init_send_ring: alloc tx buffer failed"); 508 rge_fini_send_ring(rgep); 509 return (DDI_FAILURE); 510 } 511 ssbdp++; 512 } 513 ASSERT(desc.alength == 0); 514 515 DMA_SYNC(rgep->tx_desc, DDI_DMA_SYNC_FORDEV); 516 return (DDI_SUCCESS); 517 } 518 519 static int 520 rge_init_recv_ring(rge_t *rgep) 521 { 522 uint32_t slot; 523 sw_rbd_t *srbdp; 524 dma_buf_t *rx_buf; 525 dma_area_t *pbuf; 526 int err; 527 528 /* 529 * Allocate the array of s/w Rx Buffer Descriptors 530 */ 531 srbdp = kmem_zalloc(RGE_RECV_SLOTS*sizeof (*srbdp), KM_SLEEP); 532 rgep->sw_rbds = srbdp; 533 534 /* 535 * Init receive ring 536 */ 537 rgep->rx_next = 0; 538 rgep->rx_desc = rgep->dma_area_rxdesc; 539 DMA_ZERO(rgep->rx_desc); 540 rgep->rx_ring = rgep->rx_desc.mem_va; 541 542 for (slot = 0; slot < RGE_RECV_SLOTS; slot++) { 543 srbdp->rx_buf = rx_buf = 544 kmem_zalloc(sizeof (dma_buf_t), KM_SLEEP); 545 546 /* 547 * Allocate memory & handle for Rx buffers 548 */ 549 pbuf = &rx_buf->pbuf; 550 err = rge_alloc_dma_mem(rgep, rgep->rxbuf_size, 551 &dma_attr_buf, &rge_buf_accattr, 552 DDI_DMA_READ | DDI_DMA_STREAMING, pbuf); 553 if (err != DDI_SUCCESS) { 554 rge_fini_recv_ring(rgep); 555 rge_error(rgep, 556 "rge_init_recv_ring: alloc rx buffer failed"); 557 return (DDI_FAILURE); 558 } 559 560 pbuf->alength -= rgep->head_room; 561 pbuf->offset += rgep->head_room; 562 if (!(rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY)) { 563 rx_buf->rx_recycle.free_func = rge_rx_recycle; 564 rx_buf->rx_recycle.free_arg = (caddr_t)rx_buf; 565 rx_buf->private = (caddr_t)rgep; 566 rx_buf->mp = desballoc(DMA_VPTR(rx_buf->pbuf), 567 rgep->rxbuf_size, 0, &rx_buf->rx_recycle); 568 if (rx_buf->mp == NULL) { 569 rge_fini_recv_ring(rgep); 570 rge_problem(rgep, 571 "rge_init_recv_ring: desballoc() failed"); 572 return (DDI_FAILURE); 573 } 574 } 575 srbdp++; 576 } 577 DMA_SYNC(rgep->rx_desc, DDI_DMA_SYNC_FORDEV); 578 return (DDI_SUCCESS); 579 } 580 581 static int 582 rge_init_buf_ring(rge_t *rgep) 583 { 584 uint32_t slot; 585 sw_rbd_t *free_srbdp; 586 dma_buf_t *rx_buf; 587 dma_area_t *pbuf; 588 int err; 589 590 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY) { 591 rgep->rx_bcopy = B_TRUE; 592 return (DDI_SUCCESS); 593 } 594 595 /* 596 * Allocate the array of s/w free Buffer Descriptors 597 */ 598 free_srbdp = kmem_zalloc(RGE_BUF_SLOTS*sizeof (*free_srbdp), KM_SLEEP); 599 rgep->free_srbds = free_srbdp; 600 601 /* 602 * Init free buffer ring 603 */ 604 rgep->rc_next = 0; 605 rgep->rf_next = 0; 606 rgep->rx_bcopy = B_FALSE; 607 rgep->rx_free = RGE_BUF_SLOTS; 608 for (slot = 0; slot < RGE_BUF_SLOTS; slot++) { 609 free_srbdp->rx_buf = rx_buf = 610 kmem_zalloc(sizeof (dma_buf_t), KM_SLEEP); 611 612 /* 613 * Allocate memory & handle for free Rx buffers 614 */ 615 pbuf = &rx_buf->pbuf; 616 err = rge_alloc_dma_mem(rgep, rgep->rxbuf_size, 617 &dma_attr_buf, &rge_buf_accattr, 618 DDI_DMA_READ | DDI_DMA_STREAMING, pbuf); 619 if (err != DDI_SUCCESS) { 620 rge_fini_buf_ring(rgep); 621 rge_error(rgep, 622 "rge_init_buf_ring: alloc rx free buffer failed"); 623 return (DDI_FAILURE); 624 } 625 pbuf->alength -= rgep->head_room; 626 pbuf->offset += rgep->head_room; 627 rx_buf->rx_recycle.free_func = rge_rx_recycle; 628 rx_buf->rx_recycle.free_arg = (caddr_t)rx_buf; 629 rx_buf->private = (caddr_t)rgep; 630 rx_buf->mp = desballoc(DMA_VPTR(rx_buf->pbuf), 631 rgep->rxbuf_size, 0, &rx_buf->rx_recycle); 632 if (rx_buf->mp == NULL) { 633 rge_fini_buf_ring(rgep); 634 rge_problem(rgep, 635 "rge_init_buf_ring: desballoc() failed"); 636 return (DDI_FAILURE); 637 } 638 free_srbdp++; 639 } 640 return (DDI_SUCCESS); 641 } 642 643 static int 644 rge_init_rings(rge_t *rgep) 645 { 646 int err; 647 648 err = rge_init_send_ring(rgep); 649 if (err != DDI_SUCCESS) 650 return (DDI_FAILURE); 651 652 err = rge_init_recv_ring(rgep); 653 if (err != DDI_SUCCESS) { 654 rge_fini_send_ring(rgep); 655 return (DDI_FAILURE); 656 } 657 658 err = rge_init_buf_ring(rgep); 659 if (err != DDI_SUCCESS) { 660 rge_fini_send_ring(rgep); 661 rge_fini_recv_ring(rgep); 662 return (DDI_FAILURE); 663 } 664 665 return (DDI_SUCCESS); 666 } 667 668 /* 669 * ========== Internal state management entry points ========== 670 */ 671 672 #undef RGE_DBG 673 #define RGE_DBG RGE_DBG_NEMO /* debug flag for this code */ 674 675 /* 676 * These routines provide all the functionality required by the 677 * corresponding MAC layer entry points, but don't update the 678 * MAC state so they can be called internally without disturbing 679 * our record of what NEMO thinks we should be doing ... 680 */ 681 682 /* 683 * rge_reset() -- reset h/w & rings to initial state 684 */ 685 static void 686 rge_reset(rge_t *rgep) 687 { 688 ASSERT(mutex_owned(rgep->genlock)); 689 690 /* 691 * Grab all the other mutexes in the world (this should 692 * ensure no other threads are manipulating driver state) 693 */ 694 mutex_enter(rgep->rx_lock); 695 mutex_enter(rgep->rc_lock); 696 rw_enter(rgep->errlock, RW_WRITER); 697 698 (void) rge_chip_reset(rgep); 699 rge_reinit_rings(rgep); 700 rge_chip_init(rgep); 701 702 /* 703 * Free the world ... 704 */ 705 rw_exit(rgep->errlock); 706 mutex_exit(rgep->rc_lock); 707 mutex_exit(rgep->rx_lock); 708 709 RGE_DEBUG(("rge_reset($%p) done", (void *)rgep)); 710 } 711 712 /* 713 * rge_stop() -- stop processing, don't reset h/w or rings 714 */ 715 static void 716 rge_stop(rge_t *rgep) 717 { 718 ASSERT(mutex_owned(rgep->genlock)); 719 720 rge_chip_stop(rgep, B_FALSE); 721 722 RGE_DEBUG(("rge_stop($%p) done", (void *)rgep)); 723 } 724 725 /* 726 * rge_start() -- start transmitting/receiving 727 */ 728 static void 729 rge_start(rge_t *rgep) 730 { 731 ASSERT(mutex_owned(rgep->genlock)); 732 733 /* 734 * Start chip processing, including enabling interrupts 735 */ 736 rge_chip_start(rgep); 737 rgep->watchdog = 0; 738 } 739 740 /* 741 * rge_restart - restart transmitting/receiving after error or suspend 742 */ 743 void 744 rge_restart(rge_t *rgep) 745 { 746 uint32_t i; 747 748 ASSERT(mutex_owned(rgep->genlock)); 749 /* 750 * Wait for posted buffer to be freed... 751 */ 752 if (!rgep->rx_bcopy) { 753 for (i = 0; i < RXBUFF_FREE_LOOP; i++) { 754 if (rgep->rx_free == RGE_BUF_SLOTS) 755 break; 756 drv_usecwait(1000); 757 RGE_DEBUG(("rge_restart: waiting for rx buf free...")); 758 } 759 } 760 rge_reset(rgep); 761 rgep->stats.chip_reset++; 762 if (rgep->rge_mac_state == RGE_MAC_STARTED) { 763 rge_start(rgep); 764 rgep->resched_needed = B_TRUE; 765 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL); 766 } 767 } 768 769 770 /* 771 * ========== Nemo-required management entry points ========== 772 */ 773 774 #undef RGE_DBG 775 #define RGE_DBG RGE_DBG_NEMO /* debug flag for this code */ 776 777 /* 778 * rge_m_stop() -- stop transmitting/receiving 779 */ 780 static void 781 rge_m_stop(void *arg) 782 { 783 rge_t *rgep = arg; /* private device info */ 784 uint32_t i; 785 786 /* 787 * Just stop processing, then record new MAC state 788 */ 789 mutex_enter(rgep->genlock); 790 rge_stop(rgep); 791 rgep->link_up_msg = rgep->link_down_msg = " (stopped)"; 792 /* 793 * Wait for posted buffer to be freed... 794 */ 795 if (!rgep->rx_bcopy) { 796 for (i = 0; i < RXBUFF_FREE_LOOP; i++) { 797 if (rgep->rx_free == RGE_BUF_SLOTS) 798 break; 799 drv_usecwait(1000); 800 RGE_DEBUG(("rge_m_stop: waiting for rx buf free...")); 801 } 802 } 803 rgep->rge_mac_state = RGE_MAC_STOPPED; 804 RGE_DEBUG(("rge_m_stop($%p) done", arg)); 805 mutex_exit(rgep->genlock); 806 } 807 808 /* 809 * rge_m_start() -- start transmitting/receiving 810 */ 811 static int 812 rge_m_start(void *arg) 813 { 814 rge_t *rgep = arg; /* private device info */ 815 816 mutex_enter(rgep->genlock); 817 818 /* 819 * Clear hw/sw statistics 820 */ 821 DMA_ZERO(rgep->dma_area_stats); 822 bzero(&rgep->stats, sizeof (rge_stats_t)); 823 824 /* 825 * Start processing and record new MAC state 826 */ 827 rge_reset(rgep); 828 rgep->link_up_msg = rgep->link_down_msg = " (initialized)"; 829 rge_start(rgep); 830 rgep->rge_mac_state = RGE_MAC_STARTED; 831 RGE_DEBUG(("rge_m_start($%p) done", arg)); 832 833 mutex_exit(rgep->genlock); 834 835 return (0); 836 } 837 838 /* 839 * rge_m_unicst_set() -- set the physical network address 840 */ 841 static int 842 rge_m_unicst(void *arg, const uint8_t *macaddr) 843 { 844 rge_t *rgep = arg; /* private device info */ 845 846 /* 847 * Remember the new current address in the driver state 848 * Sync the chip's idea of the address too ... 849 */ 850 mutex_enter(rgep->genlock); 851 bcopy(macaddr, rgep->netaddr, ETHERADDRL); 852 rge_chip_sync(rgep, RGE_SET_MAC); 853 mutex_exit(rgep->genlock); 854 855 return (0); 856 } 857 858 /* 859 * Compute the index of the required bit in the multicast hash map. 860 * This must mirror the way the hardware actually does it! 861 */ 862 static uint32_t 863 rge_hash_index(const uint8_t *mca) 864 { 865 uint32_t crc = (uint32_t)RGE_HASH_CRC; 866 uint32_t const POLY = RGE_HASH_POLY; 867 uint32_t msb; 868 int bytes; 869 uchar_t currentbyte; 870 uint32_t index; 871 int bit; 872 873 for (bytes = 0; bytes < ETHERADDRL; bytes++) { 874 currentbyte = mca[bytes]; 875 for (bit = 0; bit < 8; bit++) { 876 msb = crc >> 31; 877 crc <<= 1; 878 if (msb ^ (currentbyte & 1)) 879 crc ^= POLY; 880 currentbyte >>= 1; 881 } 882 } 883 index = crc >> 26; 884 /* the index value is between 0 and 63(0x3f) */ 885 886 return (index); 887 } 888 889 /* 890 * rge_m_multicst_add() -- enable/disable a multicast address 891 */ 892 static int 893 rge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 894 { 895 rge_t *rgep = arg; /* private device info */ 896 struct ether_addr *addr; 897 uint32_t index; 898 uint32_t reg; 899 uint8_t *hashp; 900 901 mutex_enter(rgep->genlock); 902 hashp = rgep->mcast_hash; 903 addr = (struct ether_addr *)mca; 904 /* 905 * Calculate the Multicast address hash index value 906 * Normally, the position of MAR0-MAR7 is 907 * MAR0: offset 0x08, ..., MAR7: offset 0x0F. 908 * 909 * For pcie chipset, the position of MAR0-MAR7 is 910 * different from others: 911 * MAR0: offset 0x0F, ..., MAR7: offset 0x08. 912 */ 913 index = rge_hash_index(addr->ether_addr_octet); 914 if (rgep->chipid.is_pcie) 915 reg = (~(index / RGE_MCAST_NUM)) & 0x7; 916 else 917 reg = index / RGE_MCAST_NUM; 918 919 if (add) { 920 if (rgep->mcast_refs[index]++) { 921 mutex_exit(rgep->genlock); 922 return (0); 923 } 924 hashp[reg] |= 1 << (index % RGE_MCAST_NUM); 925 } else { 926 if (--rgep->mcast_refs[index]) { 927 mutex_exit(rgep->genlock); 928 return (0); 929 } 930 hashp[reg] &= ~ (1 << (index % RGE_MCAST_NUM)); 931 } 932 933 /* 934 * Set multicast register 935 */ 936 rge_chip_sync(rgep, RGE_SET_MUL); 937 938 mutex_exit(rgep->genlock); 939 return (0); 940 } 941 942 /* 943 * rge_m_promisc() -- set or reset promiscuous mode on the board 944 * 945 * Program the hardware to enable/disable promiscuous and/or 946 * receive-all-multicast modes. 947 */ 948 static int 949 rge_m_promisc(void *arg, boolean_t on) 950 { 951 rge_t *rgep = arg; 952 953 /* 954 * Store MAC layer specified mode and pass to chip layer to update h/w 955 */ 956 mutex_enter(rgep->genlock); 957 958 if (rgep->promisc == on) { 959 mutex_exit(rgep->genlock); 960 return (0); 961 } 962 rgep->promisc = on; 963 rge_chip_sync(rgep, RGE_SET_PROMISC); 964 RGE_DEBUG(("rge_m_promisc_set($%p) done", arg)); 965 mutex_exit(rgep->genlock); 966 return (0); 967 } 968 969 /* 970 * Loopback ioctl code 971 */ 972 973 static lb_property_t loopmodes[] = { 974 { normal, "normal", RGE_LOOP_NONE }, 975 { internal, "PHY", RGE_LOOP_INTERNAL_PHY }, 976 { internal, "MAC", RGE_LOOP_INTERNAL_MAC } 977 }; 978 979 static enum ioc_reply 980 rge_set_loop_mode(rge_t *rgep, uint32_t mode) 981 { 982 const char *msg; 983 984 /* 985 * If the mode isn't being changed, there's nothing to do ... 986 */ 987 if (mode == rgep->param_loop_mode) 988 return (IOC_ACK); 989 990 /* 991 * Validate the requested mode and prepare a suitable message 992 * to explain the link down/up cycle that the change will 993 * probably induce ... 994 */ 995 switch (mode) { 996 default: 997 return (IOC_INVAL); 998 999 case RGE_LOOP_NONE: 1000 msg = " (loopback disabled)"; 1001 break; 1002 1003 case RGE_LOOP_INTERNAL_PHY: 1004 msg = " (PHY internal loopback selected)"; 1005 break; 1006 1007 case RGE_LOOP_INTERNAL_MAC: 1008 msg = " (MAC internal loopback selected)"; 1009 break; 1010 } 1011 1012 /* 1013 * All OK; tell the caller to reprogram 1014 * the PHY and/or MAC for the new mode ... 1015 */ 1016 rgep->link_down_msg = rgep->link_up_msg = msg; 1017 rgep->param_loop_mode = mode; 1018 return (IOC_RESTART_ACK); 1019 } 1020 1021 static enum ioc_reply 1022 rge_loop_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 1023 { 1024 lb_info_sz_t *lbsp; 1025 lb_property_t *lbpp; 1026 uint32_t *lbmp; 1027 int cmd; 1028 1029 _NOTE(ARGUNUSED(wq)) 1030 1031 /* 1032 * Validate format of ioctl 1033 */ 1034 if (mp->b_cont == NULL) 1035 return (IOC_INVAL); 1036 1037 cmd = iocp->ioc_cmd; 1038 switch (cmd) { 1039 default: 1040 /* NOTREACHED */ 1041 rge_error(rgep, "rge_loop_ioctl: invalid cmd 0x%x", cmd); 1042 return (IOC_INVAL); 1043 1044 case LB_GET_INFO_SIZE: 1045 if (iocp->ioc_count != sizeof (lb_info_sz_t)) 1046 return (IOC_INVAL); 1047 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 1048 *lbsp = sizeof (loopmodes); 1049 return (IOC_REPLY); 1050 1051 case LB_GET_INFO: 1052 if (iocp->ioc_count != sizeof (loopmodes)) 1053 return (IOC_INVAL); 1054 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 1055 bcopy(loopmodes, lbpp, sizeof (loopmodes)); 1056 return (IOC_REPLY); 1057 1058 case LB_GET_MODE: 1059 if (iocp->ioc_count != sizeof (uint32_t)) 1060 return (IOC_INVAL); 1061 lbmp = (uint32_t *)mp->b_cont->b_rptr; 1062 *lbmp = rgep->param_loop_mode; 1063 return (IOC_REPLY); 1064 1065 case LB_SET_MODE: 1066 if (iocp->ioc_count != sizeof (uint32_t)) 1067 return (IOC_INVAL); 1068 lbmp = (uint32_t *)mp->b_cont->b_rptr; 1069 return (rge_set_loop_mode(rgep, *lbmp)); 1070 } 1071 } 1072 1073 /* 1074 * Specific rge IOCTLs, the MAC layer handles the generic ones. 1075 */ 1076 static void 1077 rge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 1078 { 1079 rge_t *rgep = arg; 1080 struct iocblk *iocp; 1081 enum ioc_reply status; 1082 boolean_t need_privilege; 1083 int err; 1084 int cmd; 1085 1086 /* 1087 * Validate the command before bothering with the mutex ... 1088 */ 1089 iocp = (struct iocblk *)mp->b_rptr; 1090 iocp->ioc_error = 0; 1091 need_privilege = B_TRUE; 1092 cmd = iocp->ioc_cmd; 1093 switch (cmd) { 1094 default: 1095 miocnak(wq, mp, 0, EINVAL); 1096 return; 1097 1098 case RGE_MII_READ: 1099 case RGE_MII_WRITE: 1100 case RGE_DIAG: 1101 case RGE_PEEK: 1102 case RGE_POKE: 1103 case RGE_PHY_RESET: 1104 case RGE_SOFT_RESET: 1105 case RGE_HARD_RESET: 1106 break; 1107 1108 case LB_GET_INFO_SIZE: 1109 case LB_GET_INFO: 1110 case LB_GET_MODE: 1111 need_privilege = B_FALSE; 1112 /* FALLTHRU */ 1113 case LB_SET_MODE: 1114 break; 1115 1116 case ND_GET: 1117 need_privilege = B_FALSE; 1118 /* FALLTHRU */ 1119 case ND_SET: 1120 break; 1121 } 1122 1123 if (need_privilege) { 1124 /* 1125 * Check for specific net_config privilege 1126 */ 1127 err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 1128 if (err != 0) { 1129 miocnak(wq, mp, 0, err); 1130 return; 1131 } 1132 } 1133 1134 mutex_enter(rgep->genlock); 1135 1136 switch (cmd) { 1137 default: 1138 _NOTE(NOTREACHED) 1139 status = IOC_INVAL; 1140 break; 1141 1142 case RGE_MII_READ: 1143 case RGE_MII_WRITE: 1144 case RGE_DIAG: 1145 case RGE_PEEK: 1146 case RGE_POKE: 1147 case RGE_PHY_RESET: 1148 case RGE_SOFT_RESET: 1149 case RGE_HARD_RESET: 1150 status = rge_chip_ioctl(rgep, wq, mp, iocp); 1151 break; 1152 1153 case LB_GET_INFO_SIZE: 1154 case LB_GET_INFO: 1155 case LB_GET_MODE: 1156 case LB_SET_MODE: 1157 status = rge_loop_ioctl(rgep, wq, mp, iocp); 1158 break; 1159 1160 case ND_GET: 1161 case ND_SET: 1162 status = rge_nd_ioctl(rgep, wq, mp, iocp); 1163 break; 1164 } 1165 1166 /* 1167 * Do we need to reprogram the PHY and/or the MAC? 1168 * Do it now, while we still have the mutex. 1169 * 1170 * Note: update the PHY first, 'cos it controls the 1171 * speed/duplex parameters that the MAC code uses. 1172 */ 1173 switch (status) { 1174 case IOC_RESTART_REPLY: 1175 case IOC_RESTART_ACK: 1176 rge_phy_update(rgep); 1177 break; 1178 } 1179 1180 mutex_exit(rgep->genlock); 1181 1182 /* 1183 * Finally, decide how to reply 1184 */ 1185 switch (status) { 1186 default: 1187 case IOC_INVAL: 1188 /* 1189 * Error, reply with a NAK and EINVAL or the specified error 1190 */ 1191 miocnak(wq, mp, 0, iocp->ioc_error == 0 ? 1192 EINVAL : iocp->ioc_error); 1193 break; 1194 1195 case IOC_DONE: 1196 /* 1197 * OK, reply already sent 1198 */ 1199 break; 1200 1201 case IOC_RESTART_ACK: 1202 case IOC_ACK: 1203 /* 1204 * OK, reply with an ACK 1205 */ 1206 miocack(wq, mp, 0, 0); 1207 break; 1208 1209 case IOC_RESTART_REPLY: 1210 case IOC_REPLY: 1211 /* 1212 * OK, send prepared reply as ACK or NAK 1213 */ 1214 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1215 M_IOCACK : M_IOCNAK; 1216 qreply(wq, mp); 1217 break; 1218 } 1219 } 1220 1221 static void 1222 rge_m_resources(void *arg) 1223 { 1224 rge_t *rgep = arg; 1225 mac_rx_fifo_t mrf; 1226 1227 mutex_enter(rgep->genlock); 1228 1229 /* 1230 * Register Rx rings as resources and save mac 1231 * resource id for future reference 1232 */ 1233 mrf.mrf_type = MAC_RX_FIFO; 1234 mrf.mrf_blank = rge_chip_blank; 1235 mrf.mrf_arg = (void *)rgep; 1236 mrf.mrf_normal_blank_time = RGE_RX_INT_TIME; 1237 mrf.mrf_normal_pkt_count = RGE_RX_INT_PKTS; 1238 rgep->handle = mac_resource_add(rgep->mh, (mac_resource_t *)&mrf); 1239 1240 mutex_exit(rgep->genlock); 1241 } 1242 1243 /* ARGSUSED */ 1244 static boolean_t 1245 rge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 1246 { 1247 switch (cap) { 1248 case MAC_CAPAB_HCKSUM: { 1249 uint32_t *hcksum_txflags = cap_data; 1250 *hcksum_txflags = HCKSUM_INET_FULL_V4 | HCKSUM_IPHDRCKSUM; 1251 break; 1252 } 1253 case MAC_CAPAB_POLL: 1254 /* 1255 * There's nothing for us to fill in, simply returning 1256 * B_TRUE stating that we support polling is sufficient. 1257 */ 1258 break; 1259 default: 1260 return (B_FALSE); 1261 } 1262 return (B_TRUE); 1263 } 1264 1265 /* 1266 * ============ Init MSI/Fixed Interrupt routines ============== 1267 */ 1268 1269 /* 1270 * rge_add_intrs: 1271 * 1272 * Register FIXED or MSI interrupts. 1273 */ 1274 static int 1275 rge_add_intrs(rge_t *rgep, int intr_type) 1276 { 1277 dev_info_t *dip = rgep->devinfo; 1278 int avail; 1279 int actual; 1280 int intr_size; 1281 int count; 1282 int i, j; 1283 int ret; 1284 1285 /* Get number of interrupts */ 1286 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 1287 if ((ret != DDI_SUCCESS) || (count == 0)) { 1288 rge_error(rgep, "ddi_intr_get_nintrs() failure, ret: %d, " 1289 "count: %d", ret, count); 1290 return (DDI_FAILURE); 1291 } 1292 1293 /* Get number of available interrupts */ 1294 ret = ddi_intr_get_navail(dip, intr_type, &avail); 1295 if ((ret != DDI_SUCCESS) || (avail == 0)) { 1296 rge_error(rgep, "ddi_intr_get_navail() failure, " 1297 "ret: %d, avail: %d\n", ret, avail); 1298 return (DDI_FAILURE); 1299 } 1300 1301 /* Allocate an array of interrupt handles */ 1302 intr_size = count * sizeof (ddi_intr_handle_t); 1303 rgep->htable = kmem_alloc(intr_size, KM_SLEEP); 1304 rgep->intr_rqst = count; 1305 1306 /* Call ddi_intr_alloc() */ 1307 ret = ddi_intr_alloc(dip, rgep->htable, intr_type, 0, 1308 count, &actual, DDI_INTR_ALLOC_NORMAL); 1309 if (ret != DDI_SUCCESS || actual == 0) { 1310 rge_error(rgep, "ddi_intr_alloc() failed %d\n", ret); 1311 kmem_free(rgep->htable, intr_size); 1312 return (DDI_FAILURE); 1313 } 1314 if (actual < count) { 1315 rge_log(rgep, "ddi_intr_alloc() Requested: %d, Received: %d\n", 1316 count, actual); 1317 } 1318 rgep->intr_cnt = actual; 1319 1320 /* 1321 * Get priority for first msi, assume remaining are all the same 1322 */ 1323 if ((ret = ddi_intr_get_pri(rgep->htable[0], &rgep->intr_pri)) != 1324 DDI_SUCCESS) { 1325 rge_error(rgep, "ddi_intr_get_pri() failed %d\n", ret); 1326 /* Free already allocated intr */ 1327 for (i = 0; i < actual; i++) { 1328 (void) ddi_intr_free(rgep->htable[i]); 1329 } 1330 kmem_free(rgep->htable, intr_size); 1331 return (DDI_FAILURE); 1332 } 1333 1334 /* Test for high level mutex */ 1335 if (rgep->intr_pri >= ddi_intr_get_hilevel_pri()) { 1336 rge_error(rgep, "rge_add_intrs:" 1337 "Hi level interrupt not supported"); 1338 for (i = 0; i < actual; i++) 1339 (void) ddi_intr_free(rgep->htable[i]); 1340 kmem_free(rgep->htable, intr_size); 1341 return (DDI_FAILURE); 1342 } 1343 1344 /* Call ddi_intr_add_handler() */ 1345 for (i = 0; i < actual; i++) { 1346 if ((ret = ddi_intr_add_handler(rgep->htable[i], rge_intr, 1347 (caddr_t)rgep, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 1348 rge_error(rgep, "ddi_intr_add_handler() " 1349 "failed %d\n", ret); 1350 /* Remove already added intr */ 1351 for (j = 0; j < i; j++) 1352 (void) ddi_intr_remove_handler(rgep->htable[j]); 1353 /* Free already allocated intr */ 1354 for (i = 0; i < actual; i++) { 1355 (void) ddi_intr_free(rgep->htable[i]); 1356 } 1357 kmem_free(rgep->htable, intr_size); 1358 return (DDI_FAILURE); 1359 } 1360 } 1361 1362 if ((ret = ddi_intr_get_cap(rgep->htable[0], &rgep->intr_cap)) 1363 != DDI_SUCCESS) { 1364 rge_error(rgep, "ddi_intr_get_cap() failed %d\n", ret); 1365 for (i = 0; i < actual; i++) { 1366 (void) ddi_intr_remove_handler(rgep->htable[i]); 1367 (void) ddi_intr_free(rgep->htable[i]); 1368 } 1369 kmem_free(rgep->htable, intr_size); 1370 return (DDI_FAILURE); 1371 } 1372 1373 return (DDI_SUCCESS); 1374 } 1375 1376 /* 1377 * rge_rem_intrs: 1378 * 1379 * Unregister FIXED or MSI interrupts 1380 */ 1381 static void 1382 rge_rem_intrs(rge_t *rgep) 1383 { 1384 int i; 1385 1386 /* Disable all interrupts */ 1387 if (rgep->intr_cap & DDI_INTR_FLAG_BLOCK) { 1388 /* Call ddi_intr_block_disable() */ 1389 (void) ddi_intr_block_disable(rgep->htable, rgep->intr_cnt); 1390 } else { 1391 for (i = 0; i < rgep->intr_cnt; i++) { 1392 (void) ddi_intr_disable(rgep->htable[i]); 1393 } 1394 } 1395 1396 /* Call ddi_intr_remove_handler() */ 1397 for (i = 0; i < rgep->intr_cnt; i++) { 1398 (void) ddi_intr_remove_handler(rgep->htable[i]); 1399 (void) ddi_intr_free(rgep->htable[i]); 1400 } 1401 1402 kmem_free(rgep->htable, rgep->intr_rqst * sizeof (ddi_intr_handle_t)); 1403 } 1404 1405 /* 1406 * ========== Per-instance setup/teardown code ========== 1407 */ 1408 1409 #undef RGE_DBG 1410 #define RGE_DBG RGE_DBG_INIT /* debug flag for this code */ 1411 1412 static void 1413 rge_unattach(rge_t *rgep) 1414 { 1415 /* 1416 * Flag that no more activity may be initiated 1417 */ 1418 rgep->progress &= ~PROGRESS_READY; 1419 rgep->rge_mac_state = RGE_MAC_UNATTACH; 1420 1421 /* 1422 * Quiesce the PHY and MAC (leave it reset but still powered). 1423 * Clean up and free all RGE data structures 1424 */ 1425 if (rgep->cyclic_id) { 1426 mutex_enter(&cpu_lock); 1427 cyclic_remove(rgep->cyclic_id); 1428 mutex_exit(&cpu_lock); 1429 } 1430 1431 if (rgep->progress & PROGRESS_KSTATS) 1432 rge_fini_kstats(rgep); 1433 1434 if (rgep->progress & PROGRESS_PHY) 1435 (void) rge_phy_reset(rgep); 1436 1437 if (rgep->progress & PROGRESS_INIT) { 1438 mutex_enter(rgep->genlock); 1439 (void) rge_chip_reset(rgep); 1440 mutex_exit(rgep->genlock); 1441 rge_fini_rings(rgep); 1442 } 1443 1444 if (rgep->progress & PROGRESS_INTR) { 1445 rge_rem_intrs(rgep); 1446 mutex_destroy(rgep->rc_lock); 1447 mutex_destroy(rgep->rx_lock); 1448 mutex_destroy(rgep->tc_lock); 1449 mutex_destroy(rgep->tx_lock); 1450 rw_destroy(rgep->errlock); 1451 mutex_destroy(rgep->genlock); 1452 } 1453 1454 if (rgep->progress & PROGRESS_FACTOTUM) 1455 (void) ddi_intr_remove_softint(rgep->factotum_hdl); 1456 1457 if (rgep->progress & PROGRESS_RESCHED) 1458 (void) ddi_intr_remove_softint(rgep->resched_hdl); 1459 1460 rge_free_bufs(rgep); 1461 1462 if (rgep->progress & PROGRESS_NDD) 1463 rge_nd_cleanup(rgep); 1464 1465 if (rgep->progress & PROGRESS_REGS) 1466 ddi_regs_map_free(&rgep->io_handle); 1467 1468 if (rgep->progress & PROGRESS_CFG) 1469 pci_config_teardown(&rgep->cfg_handle); 1470 1471 ddi_remove_minor_node(rgep->devinfo, NULL); 1472 kmem_free(rgep, sizeof (*rgep)); 1473 } 1474 1475 static int 1476 rge_resume(dev_info_t *devinfo) 1477 { 1478 rge_t *rgep; /* Our private data */ 1479 chip_id_t *cidp; 1480 chip_id_t chipid; 1481 1482 rgep = ddi_get_driver_private(devinfo); 1483 if (rgep == NULL) 1484 return (DDI_FAILURE); 1485 1486 /* 1487 * Refuse to resume if the data structures aren't consistent 1488 */ 1489 if (rgep->devinfo != devinfo) 1490 return (DDI_FAILURE); 1491 1492 /* 1493 * Read chip ID & set up config space command register(s) 1494 * Refuse to resume if the chip has changed its identity! 1495 */ 1496 cidp = &rgep->chipid; 1497 rge_chip_cfg_init(rgep, &chipid); 1498 if (chipid.vendor != cidp->vendor) 1499 return (DDI_FAILURE); 1500 if (chipid.device != cidp->device) 1501 return (DDI_FAILURE); 1502 if (chipid.revision != cidp->revision) 1503 return (DDI_FAILURE); 1504 1505 /* 1506 * All OK, reinitialise h/w & kick off NEMO scheduling 1507 */ 1508 mutex_enter(rgep->genlock); 1509 rge_restart(rgep); 1510 mutex_exit(rgep->genlock); 1511 return (DDI_SUCCESS); 1512 } 1513 1514 1515 /* 1516 * attach(9E) -- Attach a device to the system 1517 * 1518 * Called once for each board successfully probed. 1519 */ 1520 static int 1521 rge_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 1522 { 1523 rge_t *rgep; /* Our private data */ 1524 mac_register_t *macp; 1525 chip_id_t *cidp; 1526 cyc_handler_t cychand; 1527 cyc_time_t cyctime; 1528 int intr_types; 1529 caddr_t regs; 1530 int instance; 1531 int i; 1532 int err; 1533 1534 /* 1535 * we don't support high level interrupts in the driver 1536 */ 1537 if (ddi_intr_hilevel(devinfo, 0) != 0) { 1538 cmn_err(CE_WARN, 1539 "rge_attach -- unsupported high level interrupt"); 1540 return (DDI_FAILURE); 1541 } 1542 1543 instance = ddi_get_instance(devinfo); 1544 RGE_GTRACE(("rge_attach($%p, %d) instance %d", 1545 (void *)devinfo, cmd, instance)); 1546 RGE_BRKPT(NULL, "rge_attach"); 1547 1548 switch (cmd) { 1549 default: 1550 return (DDI_FAILURE); 1551 1552 case DDI_RESUME: 1553 return (rge_resume(devinfo)); 1554 1555 case DDI_ATTACH: 1556 break; 1557 } 1558 1559 rgep = kmem_zalloc(sizeof (*rgep), KM_SLEEP); 1560 ddi_set_driver_private(devinfo, rgep); 1561 rgep->devinfo = devinfo; 1562 1563 /* 1564 * Initialize more fields in RGE private data 1565 */ 1566 rgep->rge_mac_state = RGE_MAC_ATTACH; 1567 rgep->debug = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 1568 DDI_PROP_DONTPASS, debug_propname, rge_debug); 1569 rgep->default_mtu = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 1570 DDI_PROP_DONTPASS, mtu_propname, ETHERMTU); 1571 rgep->msi_enable = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 1572 DDI_PROP_DONTPASS, msi_propname, B_TRUE); 1573 (void) snprintf(rgep->ifname, sizeof (rgep->ifname), "%s%d", 1574 RGE_DRIVER_NAME, instance); 1575 1576 /* 1577 * Map config space registers 1578 * Read chip ID & set up config space command register(s) 1579 * 1580 * Note: this leaves the chip accessible by Memory Space 1581 * accesses, but with interrupts and Bus Mastering off. 1582 * This should ensure that nothing untoward will happen 1583 * if it has been left active by the (net-)bootloader. 1584 * We'll re-enable Bus Mastering once we've reset the chip, 1585 * and allow interrupts only when everything else is set up. 1586 */ 1587 err = pci_config_setup(devinfo, &rgep->cfg_handle); 1588 if (err != DDI_SUCCESS) { 1589 rge_problem(rgep, "pci_config_setup() failed"); 1590 goto attach_fail; 1591 } 1592 rgep->progress |= PROGRESS_CFG; 1593 cidp = &rgep->chipid; 1594 bzero(cidp, sizeof (*cidp)); 1595 rge_chip_cfg_init(rgep, cidp); 1596 1597 /* 1598 * Map operating registers 1599 */ 1600 err = ddi_regs_map_setup(devinfo, 1, ®s, 1601 0, 0, &rge_reg_accattr, &rgep->io_handle); 1602 if (err != DDI_SUCCESS) { 1603 rge_problem(rgep, "ddi_regs_map_setup() failed"); 1604 goto attach_fail; 1605 } 1606 rgep->io_regs = regs; 1607 rgep->progress |= PROGRESS_REGS; 1608 1609 /* 1610 * Register NDD-tweakable parameters 1611 */ 1612 if (rge_nd_init(rgep)) { 1613 rge_problem(rgep, "rge_nd_init() failed"); 1614 goto attach_fail; 1615 } 1616 rgep->progress |= PROGRESS_NDD; 1617 1618 /* 1619 * Characterise the device, so we know its requirements. 1620 * Then allocate the appropriate TX and RX descriptors & buffers. 1621 */ 1622 rge_chip_ident(rgep); 1623 err = rge_alloc_bufs(rgep); 1624 if (err != DDI_SUCCESS) { 1625 rge_problem(rgep, "DMA buffer allocation failed"); 1626 goto attach_fail; 1627 } 1628 1629 /* 1630 * Add the softint handlers: 1631 * 1632 * Both of these handlers are used to avoid restrictions on the 1633 * context and/or mutexes required for some operations. In 1634 * particular, the hardware interrupt handler and its subfunctions 1635 * can detect a number of conditions that we don't want to handle 1636 * in that context or with that set of mutexes held. So, these 1637 * softints are triggered instead: 1638 * 1639 * the <resched> softint is triggered if if we have previously 1640 * had to refuse to send a packet because of resource shortage 1641 * (we've run out of transmit buffers), but the send completion 1642 * interrupt handler has now detected that more buffers have 1643 * become available. 1644 * 1645 * the <factotum> is triggered if the h/w interrupt handler 1646 * sees the <link state changed> or <error> bits in the status 1647 * block. It's also triggered periodically to poll the link 1648 * state, just in case we aren't getting link status change 1649 * interrupts ... 1650 */ 1651 err = ddi_intr_add_softint(devinfo, &rgep->resched_hdl, 1652 DDI_INTR_SOFTPRI_MIN, rge_reschedule, (caddr_t)rgep); 1653 if (err != DDI_SUCCESS) { 1654 rge_problem(rgep, "ddi_intr_add_softint() failed"); 1655 goto attach_fail; 1656 } 1657 rgep->progress |= PROGRESS_RESCHED; 1658 err = ddi_intr_add_softint(devinfo, &rgep->factotum_hdl, 1659 DDI_INTR_SOFTPRI_MIN, rge_chip_factotum, (caddr_t)rgep); 1660 if (err != DDI_SUCCESS) { 1661 rge_problem(rgep, "ddi_intr_add_softint() failed"); 1662 goto attach_fail; 1663 } 1664 rgep->progress |= PROGRESS_FACTOTUM; 1665 1666 /* 1667 * Get supported interrupt types 1668 */ 1669 if (ddi_intr_get_supported_types(devinfo, &intr_types) 1670 != DDI_SUCCESS) { 1671 rge_error(rgep, "ddi_intr_get_supported_types failed\n"); 1672 goto attach_fail; 1673 } 1674 1675 /* 1676 * Add the h/w interrupt handler and initialise mutexes 1677 */ 1678 if ((intr_types & DDI_INTR_TYPE_MSI) && rgep->msi_enable) { 1679 if (rge_add_intrs(rgep, DDI_INTR_TYPE_MSI) != DDI_SUCCESS) { 1680 rge_error(rgep, "MSI registration failed, " 1681 "trying FIXED interrupt type\n"); 1682 } else { 1683 rge_log(rgep, "Using MSI interrupt type\n"); 1684 rgep->intr_type = DDI_INTR_TYPE_MSI; 1685 rgep->progress |= PROGRESS_INTR; 1686 } 1687 } 1688 if (!(rgep->progress & PROGRESS_INTR) && 1689 (intr_types & DDI_INTR_TYPE_FIXED)) { 1690 if (rge_add_intrs(rgep, DDI_INTR_TYPE_FIXED) != DDI_SUCCESS) { 1691 rge_error(rgep, "FIXED interrupt " 1692 "registration failed\n"); 1693 goto attach_fail; 1694 } 1695 rge_log(rgep, "Using FIXED interrupt type\n"); 1696 rgep->intr_type = DDI_INTR_TYPE_FIXED; 1697 rgep->progress |= PROGRESS_INTR; 1698 } 1699 if (!(rgep->progress & PROGRESS_INTR)) { 1700 rge_error(rgep, "No interrupts registered\n"); 1701 goto attach_fail; 1702 } 1703 mutex_init(rgep->genlock, NULL, MUTEX_DRIVER, 1704 DDI_INTR_PRI(rgep->intr_pri)); 1705 rw_init(rgep->errlock, NULL, RW_DRIVER, 1706 DDI_INTR_PRI(rgep->intr_pri)); 1707 mutex_init(rgep->tx_lock, NULL, MUTEX_DRIVER, 1708 DDI_INTR_PRI(rgep->intr_pri)); 1709 mutex_init(rgep->tc_lock, NULL, MUTEX_DRIVER, 1710 DDI_INTR_PRI(rgep->intr_pri)); 1711 mutex_init(rgep->rx_lock, NULL, MUTEX_DRIVER, 1712 DDI_INTR_PRI(rgep->intr_pri)); 1713 mutex_init(rgep->rc_lock, NULL, MUTEX_DRIVER, 1714 DDI_INTR_PRI(rgep->intr_pri)); 1715 1716 /* 1717 * Initialize rings 1718 */ 1719 err = rge_init_rings(rgep); 1720 if (err != DDI_SUCCESS) { 1721 rge_problem(rgep, "rge_init_rings() failed"); 1722 goto attach_fail; 1723 } 1724 rgep->progress |= PROGRESS_INIT; 1725 1726 /* 1727 * Now that mutex locks are initialized, enable interrupts. 1728 */ 1729 if (rgep->intr_cap & DDI_INTR_FLAG_BLOCK) { 1730 /* Call ddi_intr_block_enable() for MSI interrupts */ 1731 (void) ddi_intr_block_enable(rgep->htable, rgep->intr_cnt); 1732 } else { 1733 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 1734 for (i = 0; i < rgep->intr_cnt; i++) { 1735 (void) ddi_intr_enable(rgep->htable[i]); 1736 } 1737 } 1738 1739 /* 1740 * Initialise link state variables 1741 * Stop, reset & reinitialise the chip. 1742 * Initialise the (internal) PHY. 1743 */ 1744 rgep->param_link_up = LINK_STATE_UNKNOWN; 1745 rgep->link_up_msg = rgep->link_down_msg = " (initialised)"; 1746 1747 /* 1748 * Reset chip & rings to initial state; also reset address 1749 * filtering, promiscuity, loopback mode. 1750 */ 1751 mutex_enter(rgep->genlock); 1752 (void) rge_chip_reset(rgep); 1753 rge_chip_sync(rgep, RGE_GET_MAC); 1754 bzero(rgep->mcast_hash, sizeof (rgep->mcast_hash)); 1755 bzero(rgep->mcast_refs, sizeof (rgep->mcast_refs)); 1756 rgep->promisc = B_FALSE; 1757 rgep->param_loop_mode = RGE_LOOP_NONE; 1758 mutex_exit(rgep->genlock); 1759 rge_phy_init(rgep); 1760 rgep->progress |= PROGRESS_PHY; 1761 1762 /* 1763 * Create & initialise named kstats 1764 */ 1765 rge_init_kstats(rgep, instance); 1766 rgep->progress |= PROGRESS_KSTATS; 1767 1768 if ((macp = mac_alloc(MAC_VERSION)) == NULL) 1769 goto attach_fail; 1770 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 1771 macp->m_driver = rgep; 1772 macp->m_dip = devinfo; 1773 macp->m_src_addr = rgep->netaddr; 1774 macp->m_callbacks = &rge_m_callbacks; 1775 macp->m_min_sdu = 0; 1776 macp->m_max_sdu = rgep->default_mtu; 1777 1778 /* 1779 * Finally, we're ready to register ourselves with the MAC layer 1780 * interface; if this succeeds, we're all ready to start() 1781 */ 1782 err = mac_register(macp, &rgep->mh); 1783 mac_free(macp); 1784 if (err != 0) 1785 goto attach_fail; 1786 1787 cychand.cyh_func = rge_chip_cyclic; 1788 cychand.cyh_arg = rgep; 1789 cychand.cyh_level = CY_LOCK_LEVEL; 1790 cyctime.cyt_when = 0; 1791 cyctime.cyt_interval = RGE_CYCLIC_PERIOD; 1792 mutex_enter(&cpu_lock); 1793 rgep->cyclic_id = cyclic_add(&cychand, &cyctime); 1794 mutex_exit(&cpu_lock); 1795 1796 rgep->progress |= PROGRESS_READY; 1797 return (DDI_SUCCESS); 1798 1799 attach_fail: 1800 rge_unattach(rgep); 1801 return (DDI_FAILURE); 1802 } 1803 1804 /* 1805 * rge_suspend() -- suspend transmit/receive for powerdown 1806 */ 1807 static int 1808 rge_suspend(rge_t *rgep) 1809 { 1810 /* 1811 * Stop processing and idle (powerdown) the PHY ... 1812 */ 1813 mutex_enter(rgep->genlock); 1814 rge_stop(rgep); 1815 mutex_exit(rgep->genlock); 1816 1817 return (DDI_SUCCESS); 1818 } 1819 1820 /* 1821 * detach(9E) -- Detach a device from the system 1822 */ 1823 static int 1824 rge_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 1825 { 1826 rge_t *rgep; 1827 1828 RGE_GTRACE(("rge_detach($%p, %d)", (void *)devinfo, cmd)); 1829 1830 rgep = ddi_get_driver_private(devinfo); 1831 1832 switch (cmd) { 1833 default: 1834 return (DDI_FAILURE); 1835 1836 case DDI_SUSPEND: 1837 return (rge_suspend(rgep)); 1838 1839 case DDI_DETACH: 1840 break; 1841 } 1842 1843 /* 1844 * If there is any posted buffer, the driver should reject to be 1845 * detached. Need notice upper layer to release them. 1846 */ 1847 if (!(rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY) && 1848 rgep->rx_free != RGE_BUF_SLOTS) 1849 return (DDI_FAILURE); 1850 1851 /* 1852 * Unregister from the MAC layer subsystem. This can fail, in 1853 * particular if there are DLPI style-2 streams still open - 1854 * in which case we just return failure without shutting 1855 * down chip operations. 1856 */ 1857 if (mac_unregister(rgep->mh) != 0) 1858 return (DDI_FAILURE); 1859 1860 /* 1861 * All activity stopped, so we can clean up & exit 1862 */ 1863 rge_unattach(rgep); 1864 return (DDI_SUCCESS); 1865 } 1866 1867 1868 /* 1869 * ========== Module Loading Data & Entry Points ========== 1870 */ 1871 1872 #undef RGE_DBG 1873 #define RGE_DBG RGE_DBG_INIT /* debug flag for this code */ 1874 DDI_DEFINE_STREAM_OPS(rge_dev_ops, nulldev, nulldev, rge_attach, rge_detach, 1875 nodev, NULL, D_MP, NULL); 1876 1877 static struct modldrv rge_modldrv = { 1878 &mod_driverops, /* Type of module. This one is a driver */ 1879 rge_ident, /* short description */ 1880 &rge_dev_ops /* driver specific ops */ 1881 }; 1882 1883 static struct modlinkage modlinkage = { 1884 MODREV_1, (void *)&rge_modldrv, NULL 1885 }; 1886 1887 1888 int 1889 _info(struct modinfo *modinfop) 1890 { 1891 return (mod_info(&modlinkage, modinfop)); 1892 } 1893 1894 int 1895 _init(void) 1896 { 1897 int status; 1898 1899 mac_init_ops(&rge_dev_ops, "rge"); 1900 status = mod_install(&modlinkage); 1901 if (status == DDI_SUCCESS) 1902 mutex_init(rge_log_mutex, NULL, MUTEX_DRIVER, NULL); 1903 else 1904 mac_fini_ops(&rge_dev_ops); 1905 1906 return (status); 1907 } 1908 1909 int 1910 _fini(void) 1911 { 1912 int status; 1913 1914 status = mod_remove(&modlinkage); 1915 if (status == DDI_SUCCESS) { 1916 mac_fini_ops(&rge_dev_ops); 1917 mutex_destroy(rge_log_mutex); 1918 } 1919 return (status); 1920 } 1921