1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _RGE_HW_H 27 #define _RGE_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/types.h> 36 37 38 /* 39 * First section: 40 * Identification of the various Realtek GigE chips 41 */ 42 43 /* 44 * Driver support device 45 */ 46 #define VENDOR_ID_REALTECK 0x10EC 47 #define DEVICE_ID_8169 0x8169 /* PCI */ 48 #define DEVICE_ID_8110 0x8169 /* PCI */ 49 #define DEVICE_ID_8168 0x8168 /* PCI-E */ 50 #define DEVICE_ID_8111 0x8168 /* PCI-E */ 51 #define DEVICE_ID_8169SC 0x8167 /* PCI */ 52 #define DEVICE_ID_8110SC 0x8167 /* PCI */ 53 #define DEVICE_ID_8101E 0x8136 /* 10/100M PCI-E */ 54 55 #define RGE_REGISTER_MAX 0x0100 56 57 58 /* 59 * Second section: 60 * Offsets of important registers & definitions for bits therein 61 */ 62 /* 63 * MAC address register, initial value is autoloaded from the 64 * EEPROM EthernetID field 65 */ 66 #define ID_0_REG 0x0000 67 #define ID_1_REG 0x0001 68 #define ID_2_REG 0x0002 69 #define ID_3_REG 0x0003 70 #define ID_4_REG 0x0004 71 #define ID_5_REG 0x0005 72 73 /* 74 * Multicast register 75 */ 76 #define MULTICAST_0_REG 0x0008 77 #define MULTICAST_1_REG 0x0009 78 #define MULTICAST_2_REG 0x000a 79 #define MULTICAST_3_REG 0x000b 80 #define MULTICAST_4_REG 0x000c 81 #define MULTICAST_5_REG 0x000d 82 #define MULTICAST_6_REG 0x000e 83 #define MULTICAST_7_REG 0x000f 84 #define RGE_MCAST_NUM 8 /* total 8 registers: MAR0 - MAR7 */ 85 86 /* 87 * Dump Tally Counter Command register 88 */ 89 #define DUMP_COUNTER_REG_0 0x0010 90 #define DUMP_COUNTER_REG_RESV 0x00000037 91 #define DUMP_START 0x00000008 92 #define DUMP_COUNTER_REG_1 0x0014 93 94 /* 95 * Register for start address of transmit descriptors 96 */ 97 #define NORMAL_TX_RING_ADDR_LO_REG 0x0020 98 #define NORMAL_TX_RING_ADDR_HI_REG 0x0024 99 #define HIGH_TX_RING_ADDR_LO_REG 0x0028 100 #define HIGH_TX_RING_ADDR_HI_REG 0x002c 101 102 /* 103 * Commond register 104 */ 105 #define RT_COMMAND_REG 0x0037 106 #define RT_COMMAND_RESV 0xe3 107 #define RT_COMMAND_RESET 0x10 108 #define RT_COMMAND_RX_ENABLE 0x08 109 #define RT_COMMAND_TX_ENABLE 0x04 110 111 /* 112 * Transmit priority polling register 113 */ 114 #define TX_RINGS_POLL_REG 0x0038 115 #define HIGH_TX_RING_POLL 0x80 116 #define NORMAL_TX_RING_POLL 0x40 117 #define FORCE_SW_INT 0x01 118 119 /* 120 * Interrupt mask & status register 121 */ 122 #define INT_MASK_REG 0x003c 123 #define INT_STATUS_REG 0x003e 124 #define SYS_ERR_INT 0x8000 125 #define TIME_OUT_INT 0x4000 126 #define SW_INT 0x0100 127 #define NO_TXDESC_INT 0x0080 128 #define RX_FIFO_OVERFLOW_INT 0x0040 129 #define LINK_CHANGE_INT 0x0020 130 #define NO_RXDESC_INT 0x0010 131 #define TX_ERR_INT 0x0008 132 #define TX_OK_INT 0x0004 133 #define RX_ERR_INT 0x0002 134 #define RX_OK_INT 0x0001 135 136 #define INT_REG_RESV 0x3e00 137 #define INT_MASK_ALL 0xffff 138 #define INT_MASK_NONE 0x0000 139 #define RGE_RX_INT (RX_OK_INT | RX_ERR_INT | \ 140 NO_RXDESC_INT) 141 #define RGE_INT_MASK (RGE_RX_INT | LINK_CHANGE_INT) 142 143 /* 144 * Transmit configuration register 145 */ 146 #define TX_CONFIG_REG 0x0040 147 #define TX_CONFIG_REG_RESV 0x8070f8ff 148 #define HW_VERSION_ID_0 0x7c000000 149 #define INTER_FRAME_GAP_BITS 0x03080000 150 #define TX_INTERFRAME_GAP_802_3 0x03000000 151 #define HW_VERSION_ID_1 0x00800000 152 #define MAC_LOOPBACK_ENABLE 0x00060000 153 #define CRC_APPEND_ENABLE 0x00010000 154 #define TX_DMA_BURST_BITS 0x00000700 155 156 #define TX_DMA_BURST_UNLIMIT 0x00000700 157 #define TX_DMA_BURST_1024B 0x00000600 158 #define TX_DMA_BURST_512B 0x00000500 159 #define TX_DMA_BURST_256B 0x00000400 160 #define TX_DMA_BURST_128B 0x00000300 161 #define TX_DMA_BURST_64B 0x00000200 162 #define TX_DMA_BURST_32B 0x00000100 163 #define TX_DMA_BURST_16B 0x00000000 164 165 #define MAC_VER_8169 0x00000000 166 #define MAC_VER_8169S_D 0x00800000 167 #define MAC_VER_8169S_E 0x04000000 168 #define MAC_VER_8169SB 0x10000000 169 #define MAC_VER_8169SC 0x18000000 170 #define MAC_VER_8168 0x20000000 171 #define MAC_VER_8168B_B 0x30000000 172 #define MAC_VER_8168B_C 0x38000000 173 #define MAC_VER_8101E 0x34000000 174 175 #define TX_CONFIG_DEFAULT (TX_INTERFRAME_GAP_802_3 | \ 176 TX_DMA_BURST_1024B) 177 /* 178 * Receive configuration register 179 */ 180 #define RX_CONFIG_REG 0x0044 181 #define RX_CONFIG_REG_RESV 0xfffe1880 182 #define RX_RER8_ENABLE 0x00010000 183 #define RX_FIFO_THRESHOLD_BITS 0x0000e000 184 #define RX_FIFO_THRESHOLD_NONE 0x0000e000 185 #define RX_FIFO_THRESHOLD_1024B 0x0000c000 186 #define RX_FIFO_THRESHOLD_512B 0x0000a000 187 #define RX_FIFO_THRESHOLD_256B 0x00008000 188 #define RX_FIFO_THRESHOLD_128B 0x00006000 189 #define RX_FIFO_THRESHOLD_64B 0x00004000 190 #define RX_DMA_BURST_BITS 0x00000700 191 #define RX_DMA_BURST_UNLIMITED 0x00000700 192 #define RX_DMA_BURST_1024B 0x00000600 193 #define RX_DMA_BURST_512B 0x00000500 194 #define RX_DMA_BURST_256B 0x00000400 195 #define RX_DMA_BURST_128B 0x00000300 196 #define RX_DMA_BURST_64B 0x00000200 197 #define RX_EEPROM_9356 0x00000040 198 #define RX_ACCEPT_ERR_PKT 0x00000020 199 #define RX_ACCEPT_RUNT_PKT 0x00000010 200 #define RX_ACCEPT_BROADCAST_PKT 0x000000008 201 #define RX_ACCEPT_MULTICAST_PKT 0x000000004 202 #define RX_ACCEPT_MAC_MATCH_PKT 0x000000002 203 #define RX_ACCEPT_ALL_PKT 0x000000001 204 205 #define RX_CONFIG_DEFAULT (RX_FIFO_THRESHOLD_NONE | \ 206 RX_DMA_BURST_1024B | \ 207 RX_ACCEPT_BROADCAST_PKT | \ 208 RX_ACCEPT_MULTICAST_PKT | \ 209 RX_ACCEPT_MAC_MATCH_PKT) 210 211 /* 212 * Timer count register 213 */ 214 #define TIMER_COUNT_REG 0x0048 215 216 /* 217 * Missed packet counter: indicates the number of packets 218 * discarded due to Rx FIFO overflow 219 */ 220 #define RX_PKT_MISS_COUNT_REG 0x004c 221 222 /* 223 * 93c46(93c56) commond register: 224 */ 225 #define RT_93c46_COMMOND_REG 0x0050 226 #define RT_93c46_MODE_BITS 0xc0 227 #define RT_93c46_MODE_NORMAL 0x00 228 #define RT_93c46_MODE_AUTOLOAD 0x40 229 #define RT_93c46_MODE_PROGRAM 0x80 230 #define RT_93c46_MODE_CONFIG 0xc0 231 232 #define RT_93c46_EECS 0x08 233 #define RT_93c46_EESK 0x04 234 #define RT_93c46_EEDI 0x02 235 #define RT_93c46_EEDO 0x01 236 237 /* 238 * Configuration registers 239 */ 240 #define RT_CONFIG_0_REG 0x0051 241 #define RT_CONFIG_1_REG 0x0052 242 #define RT_CONFIG_2_REG 0x0053 243 #define RT_CONFIG_3_REG 0x0054 244 #define RT_CONFIG_4_REG 0x0055 245 #define RT_CONFIG_5_REG 0x0056 246 247 /* 248 * Timer interrupt register 249 */ 250 #define TIMER_INT_REG 0x0058 251 #define TIMER_INT_NONE 0x00000000 252 253 /* 254 * PHY access register 255 */ 256 #define PHY_ACCESS_REG 0x0060 257 #define PHY_ACCESS_WR_FLAG 0x80000000 258 #define PHY_ACCESS_REG_BITS 0x001f0000 259 #define PHY_ACCESS_DATA_BITS 0x0000ffff 260 #define PHY_DATA_MASK 0xffff 261 #define PHY_REG_MASK 0x1f 262 #define PHY_REG_SHIFT 16 263 264 /* 265 * CSI data register (for PCIE chipset) 266 */ 267 #define RT_CSI_DATA_REG 0x0064 268 269 /* 270 * CSI access register (for PCIE chipset) 271 */ 272 #define RT_CSI_ACCESS_REG 0x0068 273 274 /* 275 * PHY status register 276 */ 277 #define PHY_STATUS_REG 0x006c 278 #define PHY_STATUS_TBI 0x80 279 #define PHY_STATUS_TX_FLOW 0x40 280 #define PHY_STATUS_RX_FLOW 0x20 281 #define PHY_STATUS_1000MF 0x10 282 #define PHY_STATUS_100M 0x08 283 #define PHY_STATUS_10M 0x04 284 #define PHY_STATUS_LINK_UP 0x02 285 #define PHY_STATUS_DUPLEX_FULL 0x01 286 287 #define RGE_SPEED_1000M 1000 288 #define RGE_SPEED_100M 100 289 #define RGE_SPEED_10M 10 290 #define RGE_SPEED_UNKNOWN 0 291 292 /* 293 * EPHY access register (for PCIE chipset) 294 */ 295 #define EPHY_ACCESS_REG 0x0080 296 #define EPHY_ACCESS_WR_FLAG 0x80000000 297 #define EPHY_ACCESS_REG_BITS 0x001f0000 298 #define EPHY_ACCESS_DATA_BITS 0x0000ffff 299 #define EPHY_DATA_MASK 0xffff 300 #define EPHY_REG_MASK 0x1f 301 #define EPHY_REG_SHIFT 16 302 303 /* 304 * Receive packet maximum size register 305 * -- the maximum rx size supported is (16K - 1) bytes 306 */ 307 #define RX_MAX_PKTSIZE_REG 0x00da 308 #define RX_PKTSIZE_JUMBO 0x1bfa /* 7K bytes */ 309 #define RX_PKTSIZE_STD 0x05fa /* 1530 bytes */ 310 #define RX_PKTSIZE_STD_8101E 0x3fff 311 312 /* 313 * C+ command register 314 */ 315 #define CPLUS_COMMAND_REG 0x00e0 316 #define CPLUS_RESERVE 0xfd87 317 #define CPLUS_BIT14 0x4000 318 #define CPLUS_BIG_ENDIAN 0x0400 319 #define RX_VLAN_DETAG 0x0040 320 #define RX_CKSM_OFFLOAD 0x0020 321 #define DUAL_PCI_CYCLE 0x0010 322 #define MUL_PCI_RW_ENABLE 0x0008 323 324 /* 325 * Receive descriptor start address 326 */ 327 #define RX_RING_ADDR_LO_REG 0x00e4 328 #define RX_RING_ADDR_HI_REG 0x00e8 329 330 /* 331 * Max transmit packet size register 332 */ 333 #define TX_MAX_PKTSIZE_REG 0x00ec 334 #define TX_MAX_PKTSIZE_REG_RESV 0xc0 335 #define TX_PKTSIZE_JUMBO 0x3b /* Realtek suggested value */ 336 #define TX_PKTSIZE_STD 0x32 /* document suggested value */ 337 #define TX_PKTSIZE_STD_8101E 0x3f 338 339 #define RESV_82_REG 0x0082 340 #define RESV_E2_REG 0x00e2 341 342 /* 343 * PHY registers 344 */ 345 /* 346 * Basic mode control register 347 */ 348 #define PHY_BMCR_REG 0x00 349 #define PHY_RESET 0x8000 350 #define PHY_LOOPBACK 0x4000 351 #define PHY_SPEED_0 0x2000 352 #define PHY_SPEED_1 0x0040 353 #define PHY_SPEED_BITS (PHY_SPEED_0 | PHY_SPEED_1) 354 #define PHY_SPEED_1000M PHY_SPEED_1 355 #define PHY_SPEED_100M PHY_SPEED_0 356 #define PHY_SPEED_10M 0x0000 357 #define PHY_SPEED_RES (PHY_SPEED_0 | PHY_SPEED_1) 358 #define PHY_AUTO_NEGO 0x1000 359 #define PHY_RESTART_ANTO_NEGO 0x0200 360 #define PHY_DUPLEX_FULL 0x0100 361 #define PHY_BMCR_CLEAR 0xff40 362 363 /* 364 * Basic mode status register 365 */ 366 #define PHY_BMSR_REG 0x01 367 #define PHY_100BASE_T4 0x8000 368 #define PHY_100BASE_TX_FULL 0x4000 369 #define PHY_100BASE_TX_HALF 0x2000 370 #define PHY_10BASE_T_FULL 0x1000 371 #define PHY_10BASE_T_HALF 0x0800 372 #define PHY_100BASE_T2_FULL 0x0400 373 #define PHY_100BASE_T2_HALF 0x0200 374 #define PHY_1000BASE_T_EXT 0x0100 375 #define PHY_AUTO_NEGO_END 0x0020 376 #define PHY_REMOTE_FAULT 0x0010 377 #define PHY_AUTO_NEGO_ABLE 0x0008 378 #define PHY_LINK_UP 0x0004 379 #define PHY_JABBER_DETECT 0x0002 380 #define PHY_EXT_ABLE 0x0001 381 382 /* 383 * PHY identifier register 384 */ 385 #define PHY_ID_REG_1 0x02 386 #define PHY_ID_REG_2 0x03 387 #define PHY_VER_MASK 0x000f 388 #define PHY_VER_S 0x0000 389 #define PHY_VER_SB 0x0010 390 391 /* 392 * Auto-negotiation advertising register 393 */ 394 #define PHY_ANAR_REG 0x04 395 #define ANAR_NEXT_PAGE 0x8000 396 #define ANAR_REMOTE_FAULT 0x2000 397 #define ANAR_ASY_PAUSE 0x0800 398 #define ANAR_PAUSE 0x0400 399 #define ANAR_100BASE_T4 0x0200 400 #define ANAR_100BASE_TX_FULL 0x0100 401 #define ANAR_100BASE_TX_HALF 0x0080 402 #define ANAR_10BASE_T_FULL 0x0040 403 #define ANAR_10BASE_T_HALF 0x0020 404 #define ANAR_RESV_BITS 0x501f 405 406 /* 407 * Auto-negotiation link partner ability register 408 */ 409 #define PHY_ANLPAR_REG 0x05 410 411 /* 412 * Auto-negotiation expansion register 413 */ 414 #define PHY_ANER_REG 0x06 415 416 /* 417 * Auto-negotiation next page transmit register 418 */ 419 #define PHY_ANNPTR_REG 0x07 420 421 /* 422 * Auto-negotiation next page receive register 423 */ 424 #define PHY_ANNPRR_REG 0x08 425 426 /* 427 * 1000Base-T control register 428 */ 429 #define PHY_GBCR_REG 0x09 430 #define GBCR_MODE_JITTER 0x2000 431 #define GBCR_MODE_MASTER 0x4000 432 #define GBCR_MODE_SLAVE 0x6000 433 #define GBCR_1000BASE_T_FULL 0x0200 434 #define GBCR_1000BASE_T_HALF 0x0100 435 #define GBCR_DEFAULT 0x273a 436 437 /* 438 * 1000Base-T status register 439 */ 440 #define PHY_GBSR_REG 0x0a 441 #define LP_1000BASE_T_FULL 0x0800 442 #define LP_1000BASE_T_HALF 0x0400 443 444 /* 445 * 1000Base-T extended status register 446 */ 447 #define PHY_GBESR_REG 0x0f 448 449 #define PHY_1F_REG 0x1f 450 #define PHY_1D_REG 0x1d 451 #define PHY_1C_REG 0x1c 452 #define PHY_1B_REG 0x1b 453 #define PHY_18_REG 0x18 454 #define PHY_15_REG 0x15 455 #define PHY_13_REG 0x13 456 #define PHY_12_REG 0x12 457 #define PHY_0E_REG 0x0e 458 #define PHY_0C_REG 0x0c 459 #define PHY_0B_REG 0x0b 460 461 /* 462 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 463 */ 464 465 #define MII_AN_LPNXTPG 8 466 #define MII_1000BASE_T_CONTROL 9 467 #define MII_1000BASE_T_STATUS 10 468 #define MII_IEEE_EXT_STATUS 15 469 470 /* 471 * New bits in the MII_CONTROL register 472 */ 473 #define MII_CONTROL_1000MB 0x0040 474 475 /* 476 * New bits in the MII_AN_ADVERT register 477 */ 478 #define MII_ABILITY_ASYM_PAUSE 0x0800 479 #define MII_ABILITY_PAUSE 0x0400 480 481 /* 482 * Values for the <selector> field of the MII_AN_ADVERT register 483 */ 484 #define MII_AN_SELECTOR_8023 0x0001 485 486 /* 487 * Bits in the MII_1000BASE_T_CONTROL register 488 * 489 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 490 * (otherwise, roles are automatically negotiated). When this bit is set, 491 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 492 */ 493 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 494 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 495 #define MII_1000BT_CTL_ADV_FDX 0x0200 496 #define MII_1000BT_CTL_ADV_HDX 0x0100 497 498 /* 499 * Vendor-specific MII registers 500 */ 501 #define MII_EXT_CONTROL MII_VENDOR(0) 502 #define MII_EXT_STATUS MII_VENDOR(1) 503 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 504 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 505 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 506 #define MII_AUX_CONTROL MII_VENDOR(8) 507 #define MII_AUX_STATUS MII_VENDOR(9) 508 #define MII_INTR_STATUS MII_VENDOR(10) 509 #define MII_INTR_MASK MII_VENDOR(11) 510 #define MII_HCD_STATUS MII_VENDOR(13) 511 512 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 513 514 /* 515 * Bits in the MII_AUX_STATUS register 516 */ 517 #define MII_AUX_STATUS_MODE_MASK 0x0700 518 #define MII_AUX_STATUS_MODE_1000_F 0x0700 519 #define MII_AUX_STATUS_MODE_1000_H 0x0600 520 #define MII_AUX_STATUS_MODE_100_F 0x0500 521 #define MII_AUX_STATUS_MODE_100_4 0x0400 522 #define MII_AUX_STATUS_MODE_100_H 0x0300 523 #define MII_AUX_STATUS_MODE_10_F 0x0200 524 #define MII_AUX_STATUS_MODE_10_H 0x0100 525 #define MII_AUX_STATUS_MODE_NONE 0x0000 526 #define MII_AUX_STATUS_MODE_SHIFT 8 527 528 #define MII_AUX_STATUS_PAR_FAULT 0x0080 529 #define MII_AUX_STATUS_REM_FAULT 0x0040 530 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 531 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 532 533 #define MII_AUX_STATUS_LINKUP 0x0004 534 #define MII_AUX_STATUS_RX_PAUSE 0x0002 535 #define MII_AUX_STATUS_TX_PAUSE 0x0001 536 537 /* 538 * Third section: 539 * Hardware-defined data structures 540 * 541 * Note that the chip is naturally little-endian, so, for a little-endian 542 * host, the structures defined below match those descibed in the PRM. 543 * For big-endian hosts, some structures have to be swapped around. 544 */ 545 546 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 547 #error Host endianness not defined 548 #endif 549 550 /* 551 * Architectural constants: absolute maximum numbers of each type of ring 552 */ 553 554 #define RGE_SEND_SLOTS 1024 555 #define RGE_RECV_SLOTS 1024 556 #define RGE_BUFF_SIZE_STD 1536 /* 1536 bytes */ 557 #define RGE_BUFF_SIZE_JUMBO 7168 /* maximum 7K */ 558 #define RGE_JUMBO_SIZE 7014 559 #define RGE_JUMBO_MTU 7000 560 #define RGE_STATS_DUMP_SIZE 64 561 562 typedef struct rge_bd { 563 volatile uint32_t flags_len; 564 volatile uint32_t vlan_tag; 565 volatile uint32_t host_buf_addr; 566 volatile uint32_t host_buf_addr_hi; 567 } rge_bd_t; 568 569 #define BD_FLAG_HW_OWN 0x80000000 570 #define BD_FLAG_EOR 0x40000000 571 #define BD_FLAG_PKT_START 0x20000000 572 #define BD_FLAG_PKT_END 0x10000000 573 574 #define RBD_FLAG_MULTICAST 0x08000000 575 #define RBD_FLAG_UNICAST 0x04000000 576 #define RBD_FLAG_BROADCAST 0x02000000 577 #define RBD_FLAG_PKT_4096 0x00400000 578 #define RBD_FLAG_ERROR 0x00200000 579 #define RBD_FLAG_RUNT 0x00100000 580 #define RBD_FLAG_CRC_ERR 0x00080000 581 #define RBD_FLAG_PROTOCOL 0x00060000 582 #define RBD_FLAG_IP 0x00060000 583 #define RBD_FLAG_UDP 0x00040000 584 #define RBD_FLAG_TCP 0x00020000 585 #define RBD_FLAG_NONE_IP 0x00000000 586 #define RBD_IP_CKSUM_ERR 0x00010000 587 #define RBD_UDP_CKSUM_ERR 0x00008000 588 #define RBD_TCP_CKSUM_ERR 0x00004000 589 #define RBD_CKSUM_ERR 0x0001c000 590 #define RBD_FLAGS_MASK 0xffffc000 591 #define RBD_LEN_MASK 0x00003fff 592 593 #define RBD_VLAN_PKT 0x00010000 594 #define RBD_VLAN_TAG 0x0000ffff 595 596 597 #define SBD_FLAG_LARGE_SEND 0x08000000 598 #define SBD_FLAG_SEG_MAX 0x07ff0000 599 #define SBD_FLAG_IP_CKSUM 0x00040000 600 #define SBD_FLAG_UDP_CKSUM 0x00020000 601 #define SBD_FLAG_TCP_CKSUM 0x00010000 602 #define SBD_FLAG_TCP_UDP_CKSUM 0x00030000 603 #define SBD_LEN_MASK 0x0000ffff 604 605 #define SBD_VLAN_PKT 0x00020000 606 #define SBD_VLAN_TAG 0x0000ffff 607 608 #define SBD_FLAG_TX_PKT (BD_FLAG_HW_OWN | BD_FLAG_PKT_START | \ 609 BD_FLAG_PKT_END) 610 611 /* 612 * Chip VLAN TCI format 613 * bit0-3: VIDH The high 4 bits of a 12-bit VLAN ID 614 * bit4: CFI Canonical format indicator 615 * bit5-7: 3-bit 8-level priority 616 * bit8-15: The low 8 bits of a 12-bit VLAN ID 617 */ 618 #define TCI_OS2CHIP(tci) (((tci & 0xff) << 8) | (tci >> 8)) 619 #define TCI_CHIP2OS(tci) (((tci & 0xff00) >> 8) | (tci << 8)) 620 621 /* 622 * Hardware-defined Status Block 623 */ 624 typedef struct rge_hw_stats { 625 uint64_t xmt_ok; 626 uint64_t rcv_ok; 627 uint64_t xmt_err; 628 uint32_t rcv_err; 629 uint16_t in_discards; 630 uint16_t frame_err; 631 uint32_t xmt_1col; 632 uint32_t xmt_mcol; 633 uint64_t unicast_rcv; 634 uint64_t brdcst_rcv; 635 uint32_t multi_rcv; 636 uint16_t xmt_abt; 637 uint16_t xmt_undrn; 638 } rge_hw_stats_t; /* total 64 bytes */ 639 640 #ifdef __cplusplus 641 } 642 #endif 643 644 #endif /* _RGE_HW_H */ 645