1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 /* 26 * Copyright 2012 DEY Storage Systems, Inc. All rights reserved. 27 * Copyright 2013 Nexenta Systems, Inc. All rights reserved. 28 */ 29 30 /* 31 * ********************************************************************** 32 * * 33 * Module Name: * 34 * e1000g_main.c * 35 * * 36 * Abstract: * 37 * This file contains the interface routines for the solaris OS. * 38 * It has all DDI entry point routines and GLD entry point routines. * 39 * * 40 * This file also contains routines that take care of initialization * 41 * uninit routine and interrupt routine. * 42 * * 43 * ********************************************************************** 44 */ 45 46 #include <sys/dlpi.h> 47 #include <sys/mac.h> 48 #include "e1000g_sw.h" 49 #include "e1000g_debug.h" 50 51 static char ident[] = "Intel PRO/1000 Ethernet"; 52 /* LINTED E_STATIC_UNUSED */ 53 static char e1000g_version[] = "Driver Ver. 5.3.24"; 54 55 /* 56 * Proto types for DDI entry points 57 */ 58 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 59 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 60 static int e1000g_quiesce(dev_info_t *); 61 62 /* 63 * init and intr routines prototype 64 */ 65 static int e1000g_resume(dev_info_t *); 66 static int e1000g_suspend(dev_info_t *); 67 static uint_t e1000g_intr_pciexpress(caddr_t); 68 static uint_t e1000g_intr(caddr_t); 69 static void e1000g_intr_work(struct e1000g *, uint32_t); 70 #pragma inline(e1000g_intr_work) 71 static int e1000g_init(struct e1000g *); 72 static int e1000g_start(struct e1000g *, boolean_t); 73 static void e1000g_stop(struct e1000g *, boolean_t); 74 static int e1000g_m_start(void *); 75 static void e1000g_m_stop(void *); 76 static int e1000g_m_promisc(void *, boolean_t); 77 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 78 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 79 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 80 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 81 uint_t, const void *); 82 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 83 uint_t, void *); 84 static void e1000g_m_propinfo(void *, const char *, mac_prop_id_t, 85 mac_prop_info_handle_t); 86 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 87 const void *); 88 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, void *); 89 static void e1000g_init_locks(struct e1000g *); 90 static void e1000g_destroy_locks(struct e1000g *); 91 static int e1000g_identify_hardware(struct e1000g *); 92 static int e1000g_regs_map(struct e1000g *); 93 static int e1000g_set_driver_params(struct e1000g *); 94 static void e1000g_set_bufsize(struct e1000g *); 95 static int e1000g_register_mac(struct e1000g *); 96 static boolean_t e1000g_rx_drain(struct e1000g *); 97 static boolean_t e1000g_tx_drain(struct e1000g *); 98 static void e1000g_init_unicst(struct e1000g *); 99 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 100 static int e1000g_alloc_rx_data(struct e1000g *); 101 static void e1000g_release_multicast(struct e1000g *); 102 static void e1000g_pch_limits(struct e1000g *); 103 static uint32_t e1000g_mtu2maxframe(uint32_t); 104 105 /* 106 * Local routines 107 */ 108 static boolean_t e1000g_reset_adapter(struct e1000g *); 109 static void e1000g_tx_clean(struct e1000g *); 110 static void e1000g_rx_clean(struct e1000g *); 111 static void e1000g_link_timer(void *); 112 static void e1000g_local_timer(void *); 113 static boolean_t e1000g_link_check(struct e1000g *); 114 static boolean_t e1000g_stall_check(struct e1000g *); 115 static void e1000g_smartspeed(struct e1000g *); 116 static void e1000g_get_conf(struct e1000g *); 117 static boolean_t e1000g_get_prop(struct e1000g *, char *, int, int, int, 118 int *); 119 static void enable_watchdog_timer(struct e1000g *); 120 static void disable_watchdog_timer(struct e1000g *); 121 static void start_watchdog_timer(struct e1000g *); 122 static void restart_watchdog_timer(struct e1000g *); 123 static void stop_watchdog_timer(struct e1000g *); 124 static void stop_link_timer(struct e1000g *); 125 static void stop_82547_timer(e1000g_tx_ring_t *); 126 static void e1000g_force_speed_duplex(struct e1000g *); 127 static void e1000g_setup_max_mtu(struct e1000g *); 128 static void e1000g_get_max_frame_size(struct e1000g *); 129 static boolean_t is_valid_mac_addr(uint8_t *); 130 static void e1000g_unattach(dev_info_t *, struct e1000g *); 131 static int e1000g_get_bar_info(dev_info_t *, int, bar_info_t *); 132 #ifdef E1000G_DEBUG 133 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 134 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 135 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 136 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 137 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 138 struct iocblk *, mblk_t *); 139 #endif 140 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 141 struct iocblk *, mblk_t *); 142 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 143 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 144 static void e1000g_set_internal_loopback(struct e1000g *); 145 static void e1000g_set_external_loopback_1000(struct e1000g *); 146 static void e1000g_set_external_loopback_100(struct e1000g *); 147 static void e1000g_set_external_loopback_10(struct e1000g *); 148 static int e1000g_add_intrs(struct e1000g *); 149 static int e1000g_intr_add(struct e1000g *, int); 150 static int e1000g_rem_intrs(struct e1000g *); 151 static int e1000g_enable_intrs(struct e1000g *); 152 static int e1000g_disable_intrs(struct e1000g *); 153 static boolean_t e1000g_link_up(struct e1000g *); 154 #ifdef __sparc 155 static boolean_t e1000g_find_mac_address(struct e1000g *); 156 #endif 157 static void e1000g_get_phy_state(struct e1000g *); 158 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 159 const void *impl_data); 160 static void e1000g_fm_init(struct e1000g *Adapter); 161 static void e1000g_fm_fini(struct e1000g *Adapter); 162 static void e1000g_param_sync(struct e1000g *); 163 static void e1000g_get_driver_control(struct e1000_hw *); 164 static void e1000g_release_driver_control(struct e1000_hw *); 165 static void e1000g_restore_promisc(struct e1000g *Adapter); 166 167 char *e1000g_priv_props[] = { 168 "_tx_bcopy_threshold", 169 "_tx_interrupt_enable", 170 "_tx_intr_delay", 171 "_tx_intr_abs_delay", 172 "_rx_bcopy_threshold", 173 "_max_num_rcv_packets", 174 "_rx_intr_delay", 175 "_rx_intr_abs_delay", 176 "_intr_throttling_rate", 177 "_intr_adaptive", 178 "_adv_pause_cap", 179 "_adv_asym_pause_cap", 180 NULL 181 }; 182 183 static struct cb_ops cb_ws_ops = { 184 nulldev, /* cb_open */ 185 nulldev, /* cb_close */ 186 nodev, /* cb_strategy */ 187 nodev, /* cb_print */ 188 nodev, /* cb_dump */ 189 nodev, /* cb_read */ 190 nodev, /* cb_write */ 191 nodev, /* cb_ioctl */ 192 nodev, /* cb_devmap */ 193 nodev, /* cb_mmap */ 194 nodev, /* cb_segmap */ 195 nochpoll, /* cb_chpoll */ 196 ddi_prop_op, /* cb_prop_op */ 197 NULL, /* cb_stream */ 198 D_MP | D_HOTPLUG, /* cb_flag */ 199 CB_REV, /* cb_rev */ 200 nodev, /* cb_aread */ 201 nodev /* cb_awrite */ 202 }; 203 204 static struct dev_ops ws_ops = { 205 DEVO_REV, /* devo_rev */ 206 0, /* devo_refcnt */ 207 NULL, /* devo_getinfo */ 208 nulldev, /* devo_identify */ 209 nulldev, /* devo_probe */ 210 e1000g_attach, /* devo_attach */ 211 e1000g_detach, /* devo_detach */ 212 nodev, /* devo_reset */ 213 &cb_ws_ops, /* devo_cb_ops */ 214 NULL, /* devo_bus_ops */ 215 ddi_power, /* devo_power */ 216 e1000g_quiesce /* devo_quiesce */ 217 }; 218 219 static struct modldrv modldrv = { 220 &mod_driverops, /* Type of module. This one is a driver */ 221 ident, /* Discription string */ 222 &ws_ops, /* driver ops */ 223 }; 224 225 static struct modlinkage modlinkage = { 226 MODREV_1, &modldrv, NULL 227 }; 228 229 /* Access attributes for register mapping */ 230 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 231 DDI_DEVICE_ATTR_V1, 232 DDI_STRUCTURE_LE_ACC, 233 DDI_STRICTORDER_ACC, 234 DDI_FLAGERR_ACC 235 }; 236 237 #define E1000G_M_CALLBACK_FLAGS \ 238 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO) 239 240 static mac_callbacks_t e1000g_m_callbacks = { 241 E1000G_M_CALLBACK_FLAGS, 242 e1000g_m_stat, 243 e1000g_m_start, 244 e1000g_m_stop, 245 e1000g_m_promisc, 246 e1000g_m_multicst, 247 NULL, 248 e1000g_m_tx, 249 NULL, 250 e1000g_m_ioctl, 251 e1000g_m_getcapab, 252 NULL, 253 NULL, 254 e1000g_m_setprop, 255 e1000g_m_getprop, 256 e1000g_m_propinfo 257 }; 258 259 /* 260 * Global variables 261 */ 262 uint32_t e1000g_jumbo_mtu = MAXIMUM_MTU_9K; 263 uint32_t e1000g_mblks_pending = 0; 264 /* 265 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 266 * Here we maintain a private dev_info list if e1000g_force_detach is 267 * enabled. If we force the driver to detach while there are still some 268 * rx buffers retained in the upper layer, we have to keep a copy of the 269 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 270 * structure will be freed after the driver is detached. However when we 271 * finally free those rx buffers released by the upper layer, we need to 272 * refer to the dev_info to free the dma buffers. So we save a copy of 273 * the dev_info for this purpose. On x86 platform, we assume this copy 274 * of dev_info is always valid, but on SPARC platform, it could be invalid 275 * after the system board level DR operation. For this reason, the global 276 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 277 */ 278 #ifdef __sparc 279 boolean_t e1000g_force_detach = B_FALSE; 280 #else 281 boolean_t e1000g_force_detach = B_TRUE; 282 #endif 283 private_devi_list_t *e1000g_private_devi_list = NULL; 284 285 /* 286 * The mutex e1000g_rx_detach_lock is defined to protect the processing of 287 * the private dev_info list, and to serialize the processing of rx buffer 288 * freeing and rx buffer recycling. 289 */ 290 kmutex_t e1000g_rx_detach_lock; 291 /* 292 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 293 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 294 * If there are many e1000g instances, the system may run out of DVMA 295 * resources during the initialization of the instances, then the flag will 296 * be changed to "USE_DMA". Because different e1000g instances are initialized 297 * in parallel, we need to use this lock to protect the flag. 298 */ 299 krwlock_t e1000g_dma_type_lock; 300 301 /* 302 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 303 * Based on the information from Intel, the 82546 chipset has some hardware 304 * problem. When one port is being reset and the other port is trying to 305 * access the eeprom, it could cause system hang or panic. To workaround this 306 * hardware problem, we use a global mutex to prevent such operations from 307 * happening simultaneously on different instances. This workaround is applied 308 * to all the devices supported by this driver. 309 */ 310 kmutex_t e1000g_nvm_lock; 311 312 /* 313 * Loadable module configuration entry points for the driver 314 */ 315 316 /* 317 * _init - module initialization 318 */ 319 int 320 _init(void) 321 { 322 int status; 323 324 mac_init_ops(&ws_ops, WSNAME); 325 status = mod_install(&modlinkage); 326 if (status != DDI_SUCCESS) 327 mac_fini_ops(&ws_ops); 328 else { 329 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL); 330 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 331 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 332 } 333 334 return (status); 335 } 336 337 /* 338 * _fini - module finalization 339 */ 340 int 341 _fini(void) 342 { 343 int status; 344 345 if (e1000g_mblks_pending != 0) 346 return (EBUSY); 347 348 status = mod_remove(&modlinkage); 349 if (status == DDI_SUCCESS) { 350 mac_fini_ops(&ws_ops); 351 352 if (e1000g_force_detach) { 353 private_devi_list_t *devi_node; 354 355 mutex_enter(&e1000g_rx_detach_lock); 356 while (e1000g_private_devi_list != NULL) { 357 devi_node = e1000g_private_devi_list; 358 e1000g_private_devi_list = 359 e1000g_private_devi_list->next; 360 361 kmem_free(devi_node->priv_dip, 362 sizeof (struct dev_info)); 363 kmem_free(devi_node, 364 sizeof (private_devi_list_t)); 365 } 366 mutex_exit(&e1000g_rx_detach_lock); 367 } 368 369 mutex_destroy(&e1000g_rx_detach_lock); 370 rw_destroy(&e1000g_dma_type_lock); 371 mutex_destroy(&e1000g_nvm_lock); 372 } 373 374 return (status); 375 } 376 377 /* 378 * _info - module information 379 */ 380 int 381 _info(struct modinfo *modinfop) 382 { 383 return (mod_info(&modlinkage, modinfop)); 384 } 385 386 /* 387 * e1000g_attach - driver attach 388 * 389 * This function is the device-specific initialization entry 390 * point. This entry point is required and must be written. 391 * The DDI_ATTACH command must be provided in the attach entry 392 * point. When attach() is called with cmd set to DDI_ATTACH, 393 * all normal kernel services (such as kmem_alloc(9F)) are 394 * available for use by the driver. 395 * 396 * The attach() function will be called once for each instance 397 * of the device on the system with cmd set to DDI_ATTACH. 398 * Until attach() succeeds, the only driver entry points which 399 * may be called are open(9E) and getinfo(9E). 400 */ 401 static int 402 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 403 { 404 struct e1000g *Adapter; 405 struct e1000_hw *hw; 406 struct e1000g_osdep *osdep; 407 int instance; 408 409 switch (cmd) { 410 default: 411 e1000g_log(NULL, CE_WARN, 412 "Unsupported command send to e1000g_attach... "); 413 return (DDI_FAILURE); 414 415 case DDI_RESUME: 416 return (e1000g_resume(devinfo)); 417 418 case DDI_ATTACH: 419 break; 420 } 421 422 /* 423 * get device instance number 424 */ 425 instance = ddi_get_instance(devinfo); 426 427 /* 428 * Allocate soft data structure 429 */ 430 Adapter = 431 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 432 433 Adapter->dip = devinfo; 434 Adapter->instance = instance; 435 Adapter->tx_ring->adapter = Adapter; 436 Adapter->rx_ring->adapter = Adapter; 437 438 hw = &Adapter->shared; 439 osdep = &Adapter->osdep; 440 hw->back = osdep; 441 osdep->adapter = Adapter; 442 443 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 444 445 /* 446 * Initialize for fma support 447 */ 448 (void) e1000g_get_prop(Adapter, "fm-capable", 449 0, 0x0f, 450 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 451 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE, 452 &Adapter->fm_capabilities); 453 e1000g_fm_init(Adapter); 454 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 455 456 /* 457 * PCI Configure 458 */ 459 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 460 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 461 goto attach_fail; 462 } 463 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 464 465 /* 466 * Setup hardware 467 */ 468 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 469 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 470 goto attach_fail; 471 } 472 473 /* 474 * Map in the device registers. 475 */ 476 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 477 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 478 goto attach_fail; 479 } 480 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 481 482 /* 483 * Initialize driver parameters 484 */ 485 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 486 goto attach_fail; 487 } 488 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 489 490 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 491 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 492 goto attach_fail; 493 } 494 495 /* 496 * Initialize interrupts 497 */ 498 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 499 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 500 goto attach_fail; 501 } 502 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 503 504 /* 505 * Initialize mutex's for this device. 506 * Do this before enabling the interrupt handler and 507 * register the softint to avoid the condition where 508 * interrupt handler can try using uninitialized mutex 509 */ 510 e1000g_init_locks(Adapter); 511 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 512 513 /* 514 * Initialize Driver Counters 515 */ 516 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 517 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 518 goto attach_fail; 519 } 520 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 521 522 /* 523 * Initialize chip hardware and software structures 524 */ 525 rw_enter(&Adapter->chip_lock, RW_WRITER); 526 if (e1000g_init(Adapter) != DDI_SUCCESS) { 527 rw_exit(&Adapter->chip_lock); 528 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 529 goto attach_fail; 530 } 531 rw_exit(&Adapter->chip_lock); 532 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 533 534 /* 535 * Register the driver to the MAC 536 */ 537 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 538 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 539 goto attach_fail; 540 } 541 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 542 543 /* 544 * Now that mutex locks are initialized, and the chip is also 545 * initialized, enable interrupts. 546 */ 547 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 548 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 549 goto attach_fail; 550 } 551 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 552 553 /* 554 * If e1000g_force_detach is enabled, in global private dip list, 555 * we will create a new entry, which maintains the priv_dip for DR 556 * supports after driver detached. 557 */ 558 if (e1000g_force_detach) { 559 private_devi_list_t *devi_node; 560 561 Adapter->priv_dip = 562 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 563 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 564 sizeof (struct dev_info)); 565 566 devi_node = 567 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 568 569 mutex_enter(&e1000g_rx_detach_lock); 570 devi_node->priv_dip = Adapter->priv_dip; 571 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 572 devi_node->pending_rx_count = 0; 573 574 Adapter->priv_devi_node = devi_node; 575 576 if (e1000g_private_devi_list == NULL) { 577 devi_node->prev = NULL; 578 devi_node->next = NULL; 579 e1000g_private_devi_list = devi_node; 580 } else { 581 devi_node->prev = NULL; 582 devi_node->next = e1000g_private_devi_list; 583 e1000g_private_devi_list->prev = devi_node; 584 e1000g_private_devi_list = devi_node; 585 } 586 mutex_exit(&e1000g_rx_detach_lock); 587 } 588 589 Adapter->e1000g_state = E1000G_INITIALIZED; 590 return (DDI_SUCCESS); 591 592 attach_fail: 593 e1000g_unattach(devinfo, Adapter); 594 return (DDI_FAILURE); 595 } 596 597 static int 598 e1000g_register_mac(struct e1000g *Adapter) 599 { 600 struct e1000_hw *hw = &Adapter->shared; 601 mac_register_t *mac; 602 int err; 603 604 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 605 return (DDI_FAILURE); 606 607 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 608 mac->m_driver = Adapter; 609 mac->m_dip = Adapter->dip; 610 mac->m_src_addr = hw->mac.addr; 611 mac->m_callbacks = &e1000g_m_callbacks; 612 mac->m_min_sdu = 0; 613 mac->m_max_sdu = Adapter->default_mtu; 614 mac->m_margin = VLAN_TAGSZ; 615 mac->m_priv_props = e1000g_priv_props; 616 mac->m_v12n = MAC_VIRT_LEVEL1; 617 618 err = mac_register(mac, &Adapter->mh); 619 mac_free(mac); 620 621 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 622 } 623 624 static int 625 e1000g_identify_hardware(struct e1000g *Adapter) 626 { 627 struct e1000_hw *hw = &Adapter->shared; 628 struct e1000g_osdep *osdep = &Adapter->osdep; 629 630 /* Get the device id */ 631 hw->vendor_id = 632 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 633 hw->device_id = 634 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 635 hw->revision_id = 636 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 637 hw->subsystem_device_id = 638 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 639 hw->subsystem_vendor_id = 640 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 641 642 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 643 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 644 "MAC type could not be set properly."); 645 return (DDI_FAILURE); 646 } 647 648 return (DDI_SUCCESS); 649 } 650 651 static int 652 e1000g_regs_map(struct e1000g *Adapter) 653 { 654 dev_info_t *devinfo = Adapter->dip; 655 struct e1000_hw *hw = &Adapter->shared; 656 struct e1000g_osdep *osdep = &Adapter->osdep; 657 off_t mem_size; 658 bar_info_t bar_info; 659 int offset, rnumber; 660 661 rnumber = ADAPTER_REG_SET; 662 /* Get size of adapter register memory */ 663 if (ddi_dev_regsize(devinfo, rnumber, &mem_size) != 664 DDI_SUCCESS) { 665 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 666 "ddi_dev_regsize for registers failed"); 667 return (DDI_FAILURE); 668 } 669 670 /* Map adapter register memory */ 671 if ((ddi_regs_map_setup(devinfo, rnumber, 672 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 673 &osdep->reg_handle)) != DDI_SUCCESS) { 674 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 675 "ddi_regs_map_setup for registers failed"); 676 goto regs_map_fail; 677 } 678 679 /* ICH needs to map flash memory */ 680 switch (hw->mac.type) { 681 case e1000_ich8lan: 682 case e1000_ich9lan: 683 case e1000_ich10lan: 684 case e1000_pchlan: 685 case e1000_pch2lan: 686 rnumber = ICH_FLASH_REG_SET; 687 688 /* get flash size */ 689 if (ddi_dev_regsize(devinfo, rnumber, 690 &mem_size) != DDI_SUCCESS) { 691 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 692 "ddi_dev_regsize for ICH flash failed"); 693 goto regs_map_fail; 694 } 695 696 /* map flash in */ 697 if (ddi_regs_map_setup(devinfo, rnumber, 698 (caddr_t *)&hw->flash_address, 0, 699 mem_size, &e1000g_regs_acc_attr, 700 &osdep->ich_flash_handle) != DDI_SUCCESS) { 701 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 702 "ddi_regs_map_setup for ICH flash failed"); 703 goto regs_map_fail; 704 } 705 break; 706 default: 707 break; 708 } 709 710 /* map io space */ 711 switch (hw->mac.type) { 712 case e1000_82544: 713 case e1000_82540: 714 case e1000_82545: 715 case e1000_82546: 716 case e1000_82541: 717 case e1000_82541_rev_2: 718 /* find the IO bar */ 719 rnumber = -1; 720 for (offset = PCI_CONF_BASE1; 721 offset <= PCI_CONF_BASE5; offset += 4) { 722 if (e1000g_get_bar_info(devinfo, offset, &bar_info) 723 != DDI_SUCCESS) 724 continue; 725 if (bar_info.type == E1000G_BAR_IO) { 726 rnumber = bar_info.rnumber; 727 break; 728 } 729 } 730 731 if (rnumber < 0) { 732 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 733 "No io space is found"); 734 goto regs_map_fail; 735 } 736 737 /* get io space size */ 738 if (ddi_dev_regsize(devinfo, rnumber, 739 &mem_size) != DDI_SUCCESS) { 740 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 741 "ddi_dev_regsize for io space failed"); 742 goto regs_map_fail; 743 } 744 745 /* map io space */ 746 if ((ddi_regs_map_setup(devinfo, rnumber, 747 (caddr_t *)&hw->io_base, 0, mem_size, 748 &e1000g_regs_acc_attr, 749 &osdep->io_reg_handle)) != DDI_SUCCESS) { 750 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 751 "ddi_regs_map_setup for io space failed"); 752 goto regs_map_fail; 753 } 754 break; 755 default: 756 hw->io_base = 0; 757 break; 758 } 759 760 return (DDI_SUCCESS); 761 762 regs_map_fail: 763 if (osdep->reg_handle != NULL) 764 ddi_regs_map_free(&osdep->reg_handle); 765 if (osdep->ich_flash_handle != NULL) 766 ddi_regs_map_free(&osdep->ich_flash_handle); 767 return (DDI_FAILURE); 768 } 769 770 static int 771 e1000g_set_driver_params(struct e1000g *Adapter) 772 { 773 struct e1000_hw *hw; 774 775 hw = &Adapter->shared; 776 777 /* Set MAC type and initialize hardware functions */ 778 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 779 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 780 "Could not setup hardware functions"); 781 return (DDI_FAILURE); 782 } 783 784 /* Get bus information */ 785 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 786 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 787 "Could not get bus information"); 788 return (DDI_FAILURE); 789 } 790 791 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 792 793 hw->mac.autoneg_failed = B_TRUE; 794 795 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 796 hw->phy.autoneg_wait_to_complete = B_FALSE; 797 798 /* Adaptive IFS related changes */ 799 hw->mac.adaptive_ifs = B_TRUE; 800 801 /* Enable phy init script for IGP phy of 82541/82547 */ 802 if ((hw->mac.type == e1000_82547) || 803 (hw->mac.type == e1000_82541) || 804 (hw->mac.type == e1000_82547_rev_2) || 805 (hw->mac.type == e1000_82541_rev_2)) 806 e1000_init_script_state_82541(hw, B_TRUE); 807 808 /* Enable the TTL workaround for 82541/82547 */ 809 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 810 811 #ifdef __sparc 812 Adapter->strip_crc = B_TRUE; 813 #else 814 Adapter->strip_crc = B_FALSE; 815 #endif 816 817 /* setup the maximum MTU size of the chip */ 818 e1000g_setup_max_mtu(Adapter); 819 820 /* Get speed/duplex settings in conf file */ 821 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 822 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 823 e1000g_force_speed_duplex(Adapter); 824 825 /* Get Jumbo Frames settings in conf file */ 826 e1000g_get_max_frame_size(Adapter); 827 828 /* Get conf file properties */ 829 e1000g_get_conf(Adapter); 830 831 /* enforce PCH limits */ 832 e1000g_pch_limits(Adapter); 833 834 /* Set Rx/Tx buffer size */ 835 e1000g_set_bufsize(Adapter); 836 837 /* Master Latency Timer */ 838 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 839 840 /* copper options */ 841 if (hw->phy.media_type == e1000_media_type_copper) { 842 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 843 hw->phy.disable_polarity_correction = B_FALSE; 844 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 845 } 846 847 /* The initial link state should be "unknown" */ 848 Adapter->link_state = LINK_STATE_UNKNOWN; 849 850 /* Initialize rx parameters */ 851 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 852 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 853 854 /* Initialize tx parameters */ 855 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 856 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 857 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 858 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 859 860 /* Initialize rx parameters */ 861 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 862 863 return (DDI_SUCCESS); 864 } 865 866 static void 867 e1000g_setup_max_mtu(struct e1000g *Adapter) 868 { 869 struct e1000_mac_info *mac = &Adapter->shared.mac; 870 struct e1000_phy_info *phy = &Adapter->shared.phy; 871 872 switch (mac->type) { 873 /* types that do not support jumbo frames */ 874 case e1000_ich8lan: 875 case e1000_82573: 876 case e1000_82583: 877 Adapter->max_mtu = ETHERMTU; 878 break; 879 /* ich9 supports jumbo frames except on one phy type */ 880 case e1000_ich9lan: 881 if (phy->type == e1000_phy_ife) 882 Adapter->max_mtu = ETHERMTU; 883 else 884 Adapter->max_mtu = MAXIMUM_MTU_9K; 885 break; 886 /* pch can do jumbo frames up to 4K */ 887 case e1000_pchlan: 888 Adapter->max_mtu = MAXIMUM_MTU_4K; 889 break; 890 /* pch2 can do jumbo frames up to 9K */ 891 case e1000_pch2lan: 892 Adapter->max_mtu = MAXIMUM_MTU_9K; 893 break; 894 /* types with a special limit */ 895 case e1000_82571: 896 case e1000_82572: 897 case e1000_82574: 898 case e1000_80003es2lan: 899 case e1000_ich10lan: 900 if (e1000g_jumbo_mtu >= ETHERMTU && 901 e1000g_jumbo_mtu <= MAXIMUM_MTU_9K) { 902 Adapter->max_mtu = e1000g_jumbo_mtu; 903 } else { 904 Adapter->max_mtu = MAXIMUM_MTU_9K; 905 } 906 break; 907 /* default limit is 16K */ 908 default: 909 Adapter->max_mtu = FRAME_SIZE_UPTO_16K - 910 sizeof (struct ether_vlan_header) - ETHERFCSL; 911 break; 912 } 913 } 914 915 static void 916 e1000g_set_bufsize(struct e1000g *Adapter) 917 { 918 struct e1000_mac_info *mac = &Adapter->shared.mac; 919 uint64_t rx_size; 920 uint64_t tx_size; 921 922 dev_info_t *devinfo = Adapter->dip; 923 #ifdef __sparc 924 ulong_t iommu_pagesize; 925 #endif 926 /* Get the system page size */ 927 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 928 929 #ifdef __sparc 930 iommu_pagesize = dvma_pagesize(devinfo); 931 if (iommu_pagesize != 0) { 932 if (Adapter->sys_page_sz == iommu_pagesize) { 933 if (iommu_pagesize > 0x4000) 934 Adapter->sys_page_sz = 0x4000; 935 } else { 936 if (Adapter->sys_page_sz > iommu_pagesize) 937 Adapter->sys_page_sz = iommu_pagesize; 938 } 939 } 940 if (Adapter->lso_enable) { 941 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 942 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 943 } else { 944 Adapter->dvma_page_num = Adapter->max_frame_size / 945 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 946 } 947 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 948 #endif 949 950 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 951 952 if (Adapter->mem_workaround_82546 && 953 ((mac->type == e1000_82545) || 954 (mac->type == e1000_82546) || 955 (mac->type == e1000_82546_rev_3))) { 956 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 957 } else { 958 rx_size = Adapter->max_frame_size; 959 if ((rx_size > FRAME_SIZE_UPTO_2K) && 960 (rx_size <= FRAME_SIZE_UPTO_4K)) 961 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 962 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 963 (rx_size <= FRAME_SIZE_UPTO_8K)) 964 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 965 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 966 (rx_size <= FRAME_SIZE_UPTO_16K)) 967 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 968 else 969 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 970 } 971 Adapter->rx_buffer_size += E1000G_IPALIGNROOM; 972 973 tx_size = Adapter->max_frame_size; 974 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 975 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 976 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 977 (tx_size <= FRAME_SIZE_UPTO_8K)) 978 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 979 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 980 (tx_size <= FRAME_SIZE_UPTO_16K)) 981 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 982 else 983 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 984 985 /* 986 * For Wiseman adapters we have an requirement of having receive 987 * buffers aligned at 256 byte boundary. Since Livengood does not 988 * require this and forcing it for all hardwares will have 989 * performance implications, I am making it applicable only for 990 * Wiseman and for Jumbo frames enabled mode as rest of the time, 991 * it is okay to have normal frames...but it does involve a 992 * potential risk where we may loose data if buffer is not 993 * aligned...so all wiseman boards to have 256 byte aligned 994 * buffers 995 */ 996 if (mac->type < e1000_82543) 997 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 998 else 999 Adapter->rx_buf_align = 1; 1000 } 1001 1002 /* 1003 * e1000g_detach - driver detach 1004 * 1005 * The detach() function is the complement of the attach routine. 1006 * If cmd is set to DDI_DETACH, detach() is used to remove the 1007 * state associated with a given instance of a device node 1008 * prior to the removal of that instance from the system. 1009 * 1010 * The detach() function will be called once for each instance 1011 * of the device for which there has been a successful attach() 1012 * once there are no longer any opens on the device. 1013 * 1014 * Interrupts routine are disabled, All memory allocated by this 1015 * driver are freed. 1016 */ 1017 static int 1018 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 1019 { 1020 struct e1000g *Adapter; 1021 boolean_t rx_drain; 1022 1023 switch (cmd) { 1024 default: 1025 return (DDI_FAILURE); 1026 1027 case DDI_SUSPEND: 1028 return (e1000g_suspend(devinfo)); 1029 1030 case DDI_DETACH: 1031 break; 1032 } 1033 1034 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1035 if (Adapter == NULL) 1036 return (DDI_FAILURE); 1037 1038 rx_drain = e1000g_rx_drain(Adapter); 1039 if (!rx_drain && !e1000g_force_detach) 1040 return (DDI_FAILURE); 1041 1042 if (mac_unregister(Adapter->mh) != 0) { 1043 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 1044 return (DDI_FAILURE); 1045 } 1046 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 1047 1048 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 1049 1050 if (!e1000g_force_detach && !rx_drain) 1051 return (DDI_FAILURE); 1052 1053 e1000g_unattach(devinfo, Adapter); 1054 1055 return (DDI_SUCCESS); 1056 } 1057 1058 /* 1059 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 1060 */ 1061 void 1062 e1000g_free_priv_devi_node(private_devi_list_t *devi_node) 1063 { 1064 ASSERT(e1000g_private_devi_list != NULL); 1065 ASSERT(devi_node != NULL); 1066 1067 if (devi_node->prev != NULL) 1068 devi_node->prev->next = devi_node->next; 1069 if (devi_node->next != NULL) 1070 devi_node->next->prev = devi_node->prev; 1071 if (devi_node == e1000g_private_devi_list) 1072 e1000g_private_devi_list = devi_node->next; 1073 1074 kmem_free(devi_node->priv_dip, 1075 sizeof (struct dev_info)); 1076 kmem_free(devi_node, 1077 sizeof (private_devi_list_t)); 1078 } 1079 1080 static void 1081 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1082 { 1083 private_devi_list_t *devi_node; 1084 int result; 1085 1086 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1087 (void) e1000g_disable_intrs(Adapter); 1088 } 1089 1090 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1091 (void) mac_unregister(Adapter->mh); 1092 } 1093 1094 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1095 (void) e1000g_rem_intrs(Adapter); 1096 } 1097 1098 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1099 (void) ddi_prop_remove_all(devinfo); 1100 } 1101 1102 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1103 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1104 } 1105 1106 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1107 stop_link_timer(Adapter); 1108 1109 mutex_enter(&e1000g_nvm_lock); 1110 result = e1000_reset_hw(&Adapter->shared); 1111 mutex_exit(&e1000g_nvm_lock); 1112 1113 if (result != E1000_SUCCESS) { 1114 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1115 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1116 } 1117 } 1118 1119 e1000g_release_multicast(Adapter); 1120 1121 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1122 if (Adapter->osdep.reg_handle != NULL) 1123 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1124 if (Adapter->osdep.ich_flash_handle != NULL) 1125 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1126 if (Adapter->osdep.io_reg_handle != NULL) 1127 ddi_regs_map_free(&Adapter->osdep.io_reg_handle); 1128 } 1129 1130 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1131 if (Adapter->osdep.cfg_handle != NULL) 1132 pci_config_teardown(&Adapter->osdep.cfg_handle); 1133 } 1134 1135 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1136 e1000g_destroy_locks(Adapter); 1137 } 1138 1139 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1140 e1000g_fm_fini(Adapter); 1141 } 1142 1143 mutex_enter(&e1000g_rx_detach_lock); 1144 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) { 1145 devi_node = Adapter->priv_devi_node; 1146 devi_node->flag |= E1000G_PRIV_DEVI_DETACH; 1147 1148 if (devi_node->pending_rx_count == 0) { 1149 e1000g_free_priv_devi_node(devi_node); 1150 } 1151 } 1152 mutex_exit(&e1000g_rx_detach_lock); 1153 1154 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1155 1156 /* 1157 * Another hotplug spec requirement, 1158 * run ddi_set_driver_private(devinfo, null); 1159 */ 1160 ddi_set_driver_private(devinfo, NULL); 1161 } 1162 1163 /* 1164 * Get the BAR type and rnumber for a given PCI BAR offset 1165 */ 1166 static int 1167 e1000g_get_bar_info(dev_info_t *dip, int bar_offset, bar_info_t *bar_info) 1168 { 1169 pci_regspec_t *regs; 1170 uint_t regs_length; 1171 int type, rnumber, rcount; 1172 1173 ASSERT((bar_offset >= PCI_CONF_BASE0) && 1174 (bar_offset <= PCI_CONF_BASE5)); 1175 1176 /* 1177 * Get the DDI "reg" property 1178 */ 1179 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 1180 DDI_PROP_DONTPASS, "reg", (int **)®s, 1181 ®s_length) != DDI_PROP_SUCCESS) { 1182 return (DDI_FAILURE); 1183 } 1184 1185 rcount = regs_length * sizeof (int) / sizeof (pci_regspec_t); 1186 /* 1187 * Check the BAR offset 1188 */ 1189 for (rnumber = 0; rnumber < rcount; ++rnumber) { 1190 if (PCI_REG_REG_G(regs[rnumber].pci_phys_hi) == bar_offset) { 1191 type = regs[rnumber].pci_phys_hi & PCI_ADDR_MASK; 1192 break; 1193 } 1194 } 1195 1196 ddi_prop_free(regs); 1197 1198 if (rnumber >= rcount) 1199 return (DDI_FAILURE); 1200 1201 switch (type) { 1202 case PCI_ADDR_CONFIG: 1203 bar_info->type = E1000G_BAR_CONFIG; 1204 break; 1205 case PCI_ADDR_IO: 1206 bar_info->type = E1000G_BAR_IO; 1207 break; 1208 case PCI_ADDR_MEM32: 1209 bar_info->type = E1000G_BAR_MEM32; 1210 break; 1211 case PCI_ADDR_MEM64: 1212 bar_info->type = E1000G_BAR_MEM64; 1213 break; 1214 default: 1215 return (DDI_FAILURE); 1216 } 1217 bar_info->rnumber = rnumber; 1218 return (DDI_SUCCESS); 1219 } 1220 1221 static void 1222 e1000g_init_locks(struct e1000g *Adapter) 1223 { 1224 e1000g_tx_ring_t *tx_ring; 1225 e1000g_rx_ring_t *rx_ring; 1226 1227 rw_init(&Adapter->chip_lock, NULL, 1228 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1229 mutex_init(&Adapter->link_lock, NULL, 1230 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1231 mutex_init(&Adapter->watchdog_lock, NULL, 1232 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1233 1234 tx_ring = Adapter->tx_ring; 1235 1236 mutex_init(&tx_ring->tx_lock, NULL, 1237 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1238 mutex_init(&tx_ring->usedlist_lock, NULL, 1239 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1240 mutex_init(&tx_ring->freelist_lock, NULL, 1241 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1242 1243 rx_ring = Adapter->rx_ring; 1244 1245 mutex_init(&rx_ring->rx_lock, NULL, 1246 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1247 } 1248 1249 static void 1250 e1000g_destroy_locks(struct e1000g *Adapter) 1251 { 1252 e1000g_tx_ring_t *tx_ring; 1253 e1000g_rx_ring_t *rx_ring; 1254 1255 tx_ring = Adapter->tx_ring; 1256 mutex_destroy(&tx_ring->tx_lock); 1257 mutex_destroy(&tx_ring->usedlist_lock); 1258 mutex_destroy(&tx_ring->freelist_lock); 1259 1260 rx_ring = Adapter->rx_ring; 1261 mutex_destroy(&rx_ring->rx_lock); 1262 1263 mutex_destroy(&Adapter->link_lock); 1264 mutex_destroy(&Adapter->watchdog_lock); 1265 rw_destroy(&Adapter->chip_lock); 1266 1267 /* destory mutex initialized in shared code */ 1268 e1000_destroy_hw_mutex(&Adapter->shared); 1269 } 1270 1271 static int 1272 e1000g_resume(dev_info_t *devinfo) 1273 { 1274 struct e1000g *Adapter; 1275 1276 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1277 if (Adapter == NULL) 1278 e1000g_log(Adapter, CE_PANIC, 1279 "Instance pointer is null\n"); 1280 1281 if (Adapter->dip != devinfo) 1282 e1000g_log(Adapter, CE_PANIC, 1283 "Devinfo is not the same as saved devinfo\n"); 1284 1285 rw_enter(&Adapter->chip_lock, RW_WRITER); 1286 1287 if (Adapter->e1000g_state & E1000G_STARTED) { 1288 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1289 rw_exit(&Adapter->chip_lock); 1290 /* 1291 * We note the failure, but return success, as the 1292 * system is still usable without this controller. 1293 */ 1294 e1000g_log(Adapter, CE_WARN, 1295 "e1000g_resume: failed to restart controller\n"); 1296 return (DDI_SUCCESS); 1297 } 1298 /* Enable and start the watchdog timer */ 1299 enable_watchdog_timer(Adapter); 1300 } 1301 1302 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1303 1304 rw_exit(&Adapter->chip_lock); 1305 1306 return (DDI_SUCCESS); 1307 } 1308 1309 static int 1310 e1000g_suspend(dev_info_t *devinfo) 1311 { 1312 struct e1000g *Adapter; 1313 1314 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1315 if (Adapter == NULL) 1316 return (DDI_FAILURE); 1317 1318 rw_enter(&Adapter->chip_lock, RW_WRITER); 1319 1320 Adapter->e1000g_state |= E1000G_SUSPENDED; 1321 1322 /* if the port isn't plumbed, we can simply return */ 1323 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1324 rw_exit(&Adapter->chip_lock); 1325 return (DDI_SUCCESS); 1326 } 1327 1328 e1000g_stop(Adapter, B_FALSE); 1329 1330 rw_exit(&Adapter->chip_lock); 1331 1332 /* Disable and stop all the timers */ 1333 disable_watchdog_timer(Adapter); 1334 stop_link_timer(Adapter); 1335 stop_82547_timer(Adapter->tx_ring); 1336 1337 return (DDI_SUCCESS); 1338 } 1339 1340 static int 1341 e1000g_init(struct e1000g *Adapter) 1342 { 1343 uint32_t pba; 1344 uint32_t high_water; 1345 struct e1000_hw *hw; 1346 clock_t link_timeout; 1347 int result; 1348 1349 hw = &Adapter->shared; 1350 1351 /* 1352 * reset to put the hardware in a known state 1353 * before we try to do anything with the eeprom 1354 */ 1355 mutex_enter(&e1000g_nvm_lock); 1356 result = e1000_reset_hw(hw); 1357 mutex_exit(&e1000g_nvm_lock); 1358 1359 if (result != E1000_SUCCESS) { 1360 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1361 goto init_fail; 1362 } 1363 1364 mutex_enter(&e1000g_nvm_lock); 1365 result = e1000_validate_nvm_checksum(hw); 1366 if (result < E1000_SUCCESS) { 1367 /* 1368 * Some PCI-E parts fail the first check due to 1369 * the link being in sleep state. Call it again, 1370 * if it fails a second time its a real issue. 1371 */ 1372 result = e1000_validate_nvm_checksum(hw); 1373 } 1374 mutex_exit(&e1000g_nvm_lock); 1375 1376 if (result < E1000_SUCCESS) { 1377 e1000g_log(Adapter, CE_WARN, 1378 "Invalid NVM checksum. Please contact " 1379 "the vendor to update the NVM."); 1380 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1381 goto init_fail; 1382 } 1383 1384 result = 0; 1385 #ifdef __sparc 1386 /* 1387 * First, we try to get the local ethernet address from OBP. If 1388 * failed, then we get it from the EEPROM of NIC card. 1389 */ 1390 result = e1000g_find_mac_address(Adapter); 1391 #endif 1392 /* Get the local ethernet address. */ 1393 if (!result) { 1394 mutex_enter(&e1000g_nvm_lock); 1395 result = e1000_read_mac_addr(hw); 1396 mutex_exit(&e1000g_nvm_lock); 1397 } 1398 1399 if (result < E1000_SUCCESS) { 1400 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1401 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1402 goto init_fail; 1403 } 1404 1405 /* check for valid mac address */ 1406 if (!is_valid_mac_addr(hw->mac.addr)) { 1407 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1408 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1409 goto init_fail; 1410 } 1411 1412 /* Set LAA state for 82571 chipset */ 1413 e1000_set_laa_state_82571(hw, B_TRUE); 1414 1415 /* Master Latency Timer implementation */ 1416 if (Adapter->master_latency_timer) { 1417 pci_config_put8(Adapter->osdep.cfg_handle, 1418 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1419 } 1420 1421 if (hw->mac.type < e1000_82547) { 1422 /* 1423 * Total FIFO is 64K 1424 */ 1425 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1426 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1427 else 1428 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1429 } else if ((hw->mac.type == e1000_82571) || 1430 (hw->mac.type == e1000_82572) || 1431 (hw->mac.type == e1000_80003es2lan)) { 1432 /* 1433 * Total FIFO is 48K 1434 */ 1435 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1436 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1437 else 1438 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1439 } else if (hw->mac.type == e1000_82573) { 1440 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1441 } else if (hw->mac.type == e1000_82574) { 1442 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1443 pba = E1000_READ_REG(hw, E1000_PBA); 1444 } else if (hw->mac.type == e1000_ich8lan) { 1445 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1446 } else if (hw->mac.type == e1000_ich9lan) { 1447 pba = E1000_PBA_10K; 1448 } else if (hw->mac.type == e1000_ich10lan) { 1449 pba = E1000_PBA_10K; 1450 } else if (hw->mac.type == e1000_pchlan) { 1451 pba = E1000_PBA_26K; 1452 } else if (hw->mac.type == e1000_pch2lan) { 1453 pba = E1000_PBA_26K; 1454 } else { 1455 /* 1456 * Total FIFO is 40K 1457 */ 1458 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1459 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1460 else 1461 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1462 } 1463 E1000_WRITE_REG(hw, E1000_PBA, pba); 1464 1465 /* 1466 * These parameters set thresholds for the adapter's generation(Tx) 1467 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1468 * settings. Flow control is enabled or disabled in the configuration 1469 * file. 1470 * High-water mark is set down from the top of the rx fifo (not 1471 * sensitive to max_frame_size) and low-water is set just below 1472 * high-water mark. 1473 * The high water mark must be low enough to fit one full frame above 1474 * it in the rx FIFO. Should be the lower of: 1475 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1476 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1477 * Rx FIFO size minus one full frame. 1478 */ 1479 high_water = min(((pba << 10) * 9 / 10), 1480 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1481 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1482 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1483 ((pba << 10) - Adapter->max_frame_size))); 1484 1485 hw->fc.high_water = high_water & 0xFFF8; 1486 hw->fc.low_water = hw->fc.high_water - 8; 1487 1488 if (hw->mac.type == e1000_80003es2lan) 1489 hw->fc.pause_time = 0xFFFF; 1490 else 1491 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1492 hw->fc.send_xon = B_TRUE; 1493 1494 /* 1495 * Reset the adapter hardware the second time. 1496 */ 1497 mutex_enter(&e1000g_nvm_lock); 1498 result = e1000_reset_hw(hw); 1499 mutex_exit(&e1000g_nvm_lock); 1500 1501 if (result != E1000_SUCCESS) { 1502 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1503 goto init_fail; 1504 } 1505 1506 /* disable wakeup control by default */ 1507 if (hw->mac.type >= e1000_82544) 1508 E1000_WRITE_REG(hw, E1000_WUC, 0); 1509 1510 /* 1511 * MWI should be disabled on 82546. 1512 */ 1513 if (hw->mac.type == e1000_82546) 1514 e1000_pci_clear_mwi(hw); 1515 else 1516 e1000_pci_set_mwi(hw); 1517 1518 /* 1519 * Configure/Initialize hardware 1520 */ 1521 mutex_enter(&e1000g_nvm_lock); 1522 result = e1000_init_hw(hw); 1523 mutex_exit(&e1000g_nvm_lock); 1524 1525 if (result < E1000_SUCCESS) { 1526 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1527 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1528 goto init_fail; 1529 } 1530 1531 /* 1532 * Restore LED settings to the default from EEPROM 1533 * to meet the standard for Sun platforms. 1534 */ 1535 (void) e1000_cleanup_led(hw); 1536 1537 /* Disable Smart Power Down */ 1538 phy_spd_state(hw, B_FALSE); 1539 1540 /* Make sure driver has control */ 1541 e1000g_get_driver_control(hw); 1542 1543 /* 1544 * Initialize unicast addresses. 1545 */ 1546 e1000g_init_unicst(Adapter); 1547 1548 /* 1549 * Setup and initialize the mctable structures. After this routine 1550 * completes Multicast table will be set 1551 */ 1552 e1000_update_mc_addr_list(hw, 1553 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 1554 msec_delay(5); 1555 1556 /* 1557 * Implement Adaptive IFS 1558 */ 1559 e1000_reset_adaptive(hw); 1560 1561 /* Setup Interrupt Throttling Register */ 1562 if (hw->mac.type >= e1000_82540) { 1563 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1564 } else 1565 Adapter->intr_adaptive = B_FALSE; 1566 1567 /* Start the timer for link setup */ 1568 if (hw->mac.autoneg) 1569 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1570 else 1571 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1572 1573 mutex_enter(&Adapter->link_lock); 1574 if (hw->phy.autoneg_wait_to_complete) { 1575 Adapter->link_complete = B_TRUE; 1576 } else { 1577 Adapter->link_complete = B_FALSE; 1578 Adapter->link_tid = timeout(e1000g_link_timer, 1579 (void *)Adapter, link_timeout); 1580 } 1581 mutex_exit(&Adapter->link_lock); 1582 1583 /* Save the state of the phy */ 1584 e1000g_get_phy_state(Adapter); 1585 1586 e1000g_param_sync(Adapter); 1587 1588 Adapter->init_count++; 1589 1590 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1591 goto init_fail; 1592 } 1593 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1594 goto init_fail; 1595 } 1596 1597 Adapter->poll_mode = e1000g_poll_mode; 1598 1599 return (DDI_SUCCESS); 1600 1601 init_fail: 1602 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1603 return (DDI_FAILURE); 1604 } 1605 1606 static int 1607 e1000g_alloc_rx_data(struct e1000g *Adapter) 1608 { 1609 e1000g_rx_ring_t *rx_ring; 1610 e1000g_rx_data_t *rx_data; 1611 1612 rx_ring = Adapter->rx_ring; 1613 1614 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP); 1615 1616 if (rx_data == NULL) 1617 return (DDI_FAILURE); 1618 1619 rx_data->priv_devi_node = Adapter->priv_devi_node; 1620 rx_data->rx_ring = rx_ring; 1621 1622 mutex_init(&rx_data->freelist_lock, NULL, 1623 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1624 mutex_init(&rx_data->recycle_lock, NULL, 1625 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1626 1627 rx_ring->rx_data = rx_data; 1628 1629 return (DDI_SUCCESS); 1630 } 1631 1632 void 1633 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data) 1634 { 1635 rx_sw_packet_t *packet, *next_packet; 1636 1637 if (rx_data == NULL) 1638 return; 1639 1640 packet = rx_data->packet_area; 1641 while (packet != NULL) { 1642 next_packet = packet->next; 1643 e1000g_free_rx_sw_packet(packet, B_TRUE); 1644 packet = next_packet; 1645 } 1646 rx_data->packet_area = NULL; 1647 } 1648 1649 void 1650 e1000g_free_rx_data(e1000g_rx_data_t *rx_data) 1651 { 1652 if (rx_data == NULL) 1653 return; 1654 1655 mutex_destroy(&rx_data->freelist_lock); 1656 mutex_destroy(&rx_data->recycle_lock); 1657 1658 kmem_free(rx_data, sizeof (e1000g_rx_data_t)); 1659 } 1660 1661 /* 1662 * Check if the link is up 1663 */ 1664 static boolean_t 1665 e1000g_link_up(struct e1000g *Adapter) 1666 { 1667 struct e1000_hw *hw = &Adapter->shared; 1668 boolean_t link_up = B_FALSE; 1669 1670 /* 1671 * get_link_status is set in the interrupt handler on link-status-change 1672 * or rx sequence error interrupt. get_link_status will stay 1673 * false until the e1000_check_for_link establishes link only 1674 * for copper adapters. 1675 */ 1676 switch (hw->phy.media_type) { 1677 case e1000_media_type_copper: 1678 if (hw->mac.get_link_status) { 1679 (void) e1000_check_for_link(hw); 1680 if ((E1000_READ_REG(hw, E1000_STATUS) & 1681 E1000_STATUS_LU)) { 1682 link_up = B_TRUE; 1683 } else { 1684 link_up = !hw->mac.get_link_status; 1685 } 1686 } else { 1687 link_up = B_TRUE; 1688 } 1689 break; 1690 case e1000_media_type_fiber: 1691 (void) e1000_check_for_link(hw); 1692 link_up = (E1000_READ_REG(hw, E1000_STATUS) & 1693 E1000_STATUS_LU); 1694 break; 1695 case e1000_media_type_internal_serdes: 1696 (void) e1000_check_for_link(hw); 1697 link_up = hw->mac.serdes_has_link; 1698 break; 1699 } 1700 1701 return (link_up); 1702 } 1703 1704 static void 1705 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1706 { 1707 struct iocblk *iocp; 1708 struct e1000g *e1000gp; 1709 enum ioc_reply status; 1710 1711 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1712 iocp->ioc_error = 0; 1713 e1000gp = (struct e1000g *)arg; 1714 1715 ASSERT(e1000gp); 1716 if (e1000gp == NULL) { 1717 miocnak(q, mp, 0, EINVAL); 1718 return; 1719 } 1720 1721 rw_enter(&e1000gp->chip_lock, RW_READER); 1722 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1723 rw_exit(&e1000gp->chip_lock); 1724 miocnak(q, mp, 0, EINVAL); 1725 return; 1726 } 1727 rw_exit(&e1000gp->chip_lock); 1728 1729 switch (iocp->ioc_cmd) { 1730 1731 case LB_GET_INFO_SIZE: 1732 case LB_GET_INFO: 1733 case LB_GET_MODE: 1734 case LB_SET_MODE: 1735 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1736 break; 1737 1738 1739 #ifdef E1000G_DEBUG 1740 case E1000G_IOC_REG_PEEK: 1741 case E1000G_IOC_REG_POKE: 1742 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1743 break; 1744 case E1000G_IOC_CHIP_RESET: 1745 e1000gp->reset_count++; 1746 if (e1000g_reset_adapter(e1000gp)) 1747 status = IOC_ACK; 1748 else 1749 status = IOC_INVAL; 1750 break; 1751 #endif 1752 default: 1753 status = IOC_INVAL; 1754 break; 1755 } 1756 1757 /* 1758 * Decide how to reply 1759 */ 1760 switch (status) { 1761 default: 1762 case IOC_INVAL: 1763 /* 1764 * Error, reply with a NAK and EINVAL or the specified error 1765 */ 1766 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1767 EINVAL : iocp->ioc_error); 1768 break; 1769 1770 case IOC_DONE: 1771 /* 1772 * OK, reply already sent 1773 */ 1774 break; 1775 1776 case IOC_ACK: 1777 /* 1778 * OK, reply with an ACK 1779 */ 1780 miocack(q, mp, 0, 0); 1781 break; 1782 1783 case IOC_REPLY: 1784 /* 1785 * OK, send prepared reply as ACK or NAK 1786 */ 1787 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1788 M_IOCACK : M_IOCNAK; 1789 qreply(q, mp); 1790 break; 1791 } 1792 } 1793 1794 /* 1795 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1796 * capable of supporting only one interrupt and we shouldn't disable 1797 * the physical interrupt. In this case we let the interrupt come and 1798 * we queue the packets in the rx ring itself in case we are in polling 1799 * mode (better latency but slightly lower performance and a very 1800 * high intrrupt count in mpstat which is harmless). 1801 * 1802 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1803 * which can be disabled in poll mode. This gives better overall 1804 * throughput (compared to the mode above), shows very low interrupt 1805 * count but has slightly higher latency since we pick the packets when 1806 * the poll thread does polling. 1807 * 1808 * Currently, this flag should be enabled only while doing performance 1809 * measurement or when it can be guaranteed that entire NIC going 1810 * in poll mode will not harm any traffic like cluster heartbeat etc. 1811 */ 1812 int e1000g_poll_mode = 0; 1813 1814 /* 1815 * Called from the upper layers when driver is in polling mode to 1816 * pick up any queued packets. Care should be taken to not block 1817 * this thread. 1818 */ 1819 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1820 { 1821 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1822 mblk_t *mp = NULL; 1823 mblk_t *tail; 1824 struct e1000g *adapter; 1825 1826 adapter = rx_ring->adapter; 1827 1828 rw_enter(&adapter->chip_lock, RW_READER); 1829 1830 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1831 rw_exit(&adapter->chip_lock); 1832 return (NULL); 1833 } 1834 1835 mutex_enter(&rx_ring->rx_lock); 1836 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1837 mutex_exit(&rx_ring->rx_lock); 1838 rw_exit(&adapter->chip_lock); 1839 return (mp); 1840 } 1841 1842 static int 1843 e1000g_m_start(void *arg) 1844 { 1845 struct e1000g *Adapter = (struct e1000g *)arg; 1846 1847 rw_enter(&Adapter->chip_lock, RW_WRITER); 1848 1849 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1850 rw_exit(&Adapter->chip_lock); 1851 return (ECANCELED); 1852 } 1853 1854 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1855 rw_exit(&Adapter->chip_lock); 1856 return (ENOTACTIVE); 1857 } 1858 1859 Adapter->e1000g_state |= E1000G_STARTED; 1860 1861 rw_exit(&Adapter->chip_lock); 1862 1863 /* Enable and start the watchdog timer */ 1864 enable_watchdog_timer(Adapter); 1865 1866 return (0); 1867 } 1868 1869 static int 1870 e1000g_start(struct e1000g *Adapter, boolean_t global) 1871 { 1872 e1000g_rx_data_t *rx_data; 1873 1874 if (global) { 1875 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) { 1876 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed"); 1877 goto start_fail; 1878 } 1879 1880 /* Allocate dma resources for descriptors and buffers */ 1881 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1882 e1000g_log(Adapter, CE_WARN, 1883 "Alloc DMA resources failed"); 1884 goto start_fail; 1885 } 1886 Adapter->rx_buffer_setup = B_FALSE; 1887 } 1888 1889 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1890 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1891 e1000g_log(Adapter, CE_WARN, 1892 "Adapter initialization failed"); 1893 goto start_fail; 1894 } 1895 } 1896 1897 /* Setup and initialize the transmit structures */ 1898 e1000g_tx_setup(Adapter); 1899 msec_delay(5); 1900 1901 /* Setup and initialize the receive structures */ 1902 e1000g_rx_setup(Adapter); 1903 msec_delay(5); 1904 1905 /* Restore the e1000g promiscuous mode */ 1906 e1000g_restore_promisc(Adapter); 1907 1908 e1000g_mask_interrupt(Adapter); 1909 1910 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1911 1912 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1913 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1914 goto start_fail; 1915 } 1916 1917 return (DDI_SUCCESS); 1918 1919 start_fail: 1920 rx_data = Adapter->rx_ring->rx_data; 1921 1922 if (global) { 1923 e1000g_release_dma_resources(Adapter); 1924 e1000g_free_rx_pending_buffers(rx_data); 1925 e1000g_free_rx_data(rx_data); 1926 } 1927 1928 mutex_enter(&e1000g_nvm_lock); 1929 (void) e1000_reset_hw(&Adapter->shared); 1930 mutex_exit(&e1000g_nvm_lock); 1931 1932 return (DDI_FAILURE); 1933 } 1934 1935 static void 1936 e1000g_m_stop(void *arg) 1937 { 1938 struct e1000g *Adapter = (struct e1000g *)arg; 1939 1940 /* Drain tx sessions */ 1941 (void) e1000g_tx_drain(Adapter); 1942 1943 rw_enter(&Adapter->chip_lock, RW_WRITER); 1944 1945 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1946 rw_exit(&Adapter->chip_lock); 1947 return; 1948 } 1949 Adapter->e1000g_state &= ~E1000G_STARTED; 1950 e1000g_stop(Adapter, B_TRUE); 1951 1952 rw_exit(&Adapter->chip_lock); 1953 1954 /* Disable and stop all the timers */ 1955 disable_watchdog_timer(Adapter); 1956 stop_link_timer(Adapter); 1957 stop_82547_timer(Adapter->tx_ring); 1958 } 1959 1960 static void 1961 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1962 { 1963 private_devi_list_t *devi_node; 1964 e1000g_rx_data_t *rx_data; 1965 int result; 1966 1967 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1968 1969 /* Stop the chip and release pending resources */ 1970 1971 /* Tell firmware driver is no longer in control */ 1972 e1000g_release_driver_control(&Adapter->shared); 1973 1974 e1000g_clear_all_interrupts(Adapter); 1975 1976 mutex_enter(&e1000g_nvm_lock); 1977 result = e1000_reset_hw(&Adapter->shared); 1978 mutex_exit(&e1000g_nvm_lock); 1979 1980 if (result != E1000_SUCCESS) { 1981 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1982 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1983 } 1984 1985 mutex_enter(&Adapter->link_lock); 1986 Adapter->link_complete = B_FALSE; 1987 mutex_exit(&Adapter->link_lock); 1988 1989 /* Release resources still held by the TX descriptors */ 1990 e1000g_tx_clean(Adapter); 1991 1992 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1993 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1994 1995 /* Clean the pending rx jumbo packet fragment */ 1996 e1000g_rx_clean(Adapter); 1997 1998 if (global) { 1999 e1000g_release_dma_resources(Adapter); 2000 2001 mutex_enter(&e1000g_rx_detach_lock); 2002 rx_data = Adapter->rx_ring->rx_data; 2003 rx_data->flag |= E1000G_RX_STOPPED; 2004 2005 if (rx_data->pending_count == 0) { 2006 e1000g_free_rx_pending_buffers(rx_data); 2007 e1000g_free_rx_data(rx_data); 2008 } else { 2009 devi_node = rx_data->priv_devi_node; 2010 if (devi_node != NULL) 2011 atomic_inc_32(&devi_node->pending_rx_count); 2012 else 2013 atomic_inc_32(&Adapter->pending_rx_count); 2014 } 2015 mutex_exit(&e1000g_rx_detach_lock); 2016 } 2017 2018 if (Adapter->link_state != LINK_STATE_UNKNOWN) { 2019 Adapter->link_state = LINK_STATE_UNKNOWN; 2020 if (!Adapter->reset_flag) 2021 mac_link_update(Adapter->mh, Adapter->link_state); 2022 } 2023 } 2024 2025 static void 2026 e1000g_rx_clean(struct e1000g *Adapter) 2027 { 2028 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data; 2029 2030 if (rx_data == NULL) 2031 return; 2032 2033 if (rx_data->rx_mblk != NULL) { 2034 freemsg(rx_data->rx_mblk); 2035 rx_data->rx_mblk = NULL; 2036 rx_data->rx_mblk_tail = NULL; 2037 rx_data->rx_mblk_len = 0; 2038 } 2039 } 2040 2041 static void 2042 e1000g_tx_clean(struct e1000g *Adapter) 2043 { 2044 e1000g_tx_ring_t *tx_ring; 2045 p_tx_sw_packet_t packet; 2046 mblk_t *mp; 2047 mblk_t *nmp; 2048 uint32_t packet_count; 2049 2050 tx_ring = Adapter->tx_ring; 2051 2052 /* 2053 * Here we don't need to protect the lists using 2054 * the usedlist_lock and freelist_lock, for they 2055 * have been protected by the chip_lock. 2056 */ 2057 mp = NULL; 2058 nmp = NULL; 2059 packet_count = 0; 2060 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 2061 while (packet != NULL) { 2062 if (packet->mp != NULL) { 2063 /* Assemble the message chain */ 2064 if (mp == NULL) { 2065 mp = packet->mp; 2066 nmp = packet->mp; 2067 } else { 2068 nmp->b_next = packet->mp; 2069 nmp = packet->mp; 2070 } 2071 /* Disconnect the message from the sw packet */ 2072 packet->mp = NULL; 2073 } 2074 2075 e1000g_free_tx_swpkt(packet); 2076 packet_count++; 2077 2078 packet = (p_tx_sw_packet_t) 2079 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 2080 } 2081 2082 if (mp != NULL) 2083 freemsgchain(mp); 2084 2085 if (packet_count > 0) { 2086 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 2087 QUEUE_INIT_LIST(&tx_ring->used_list); 2088 2089 /* Setup TX descriptor pointers */ 2090 tx_ring->tbd_next = tx_ring->tbd_first; 2091 tx_ring->tbd_oldest = tx_ring->tbd_first; 2092 2093 /* Setup our HW Tx Head & Tail descriptor pointers */ 2094 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 2095 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 2096 } 2097 } 2098 2099 static boolean_t 2100 e1000g_tx_drain(struct e1000g *Adapter) 2101 { 2102 int i; 2103 boolean_t done; 2104 e1000g_tx_ring_t *tx_ring; 2105 2106 tx_ring = Adapter->tx_ring; 2107 2108 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 2109 for (i = 0; i < TX_DRAIN_TIME; i++) { 2110 mutex_enter(&tx_ring->usedlist_lock); 2111 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 2112 mutex_exit(&tx_ring->usedlist_lock); 2113 2114 if (done) 2115 break; 2116 2117 msec_delay(1); 2118 } 2119 2120 return (done); 2121 } 2122 2123 static boolean_t 2124 e1000g_rx_drain(struct e1000g *Adapter) 2125 { 2126 int i; 2127 boolean_t done; 2128 2129 /* 2130 * Allow up to RX_DRAIN_TIME for pending received packets to complete. 2131 */ 2132 for (i = 0; i < RX_DRAIN_TIME; i++) { 2133 done = (Adapter->pending_rx_count == 0); 2134 2135 if (done) 2136 break; 2137 2138 msec_delay(1); 2139 } 2140 2141 return (done); 2142 } 2143 2144 static boolean_t 2145 e1000g_reset_adapter(struct e1000g *Adapter) 2146 { 2147 /* Disable and stop all the timers */ 2148 disable_watchdog_timer(Adapter); 2149 stop_link_timer(Adapter); 2150 stop_82547_timer(Adapter->tx_ring); 2151 2152 rw_enter(&Adapter->chip_lock, RW_WRITER); 2153 2154 if (Adapter->stall_flag) { 2155 Adapter->stall_flag = B_FALSE; 2156 Adapter->reset_flag = B_TRUE; 2157 } 2158 2159 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2160 rw_exit(&Adapter->chip_lock); 2161 return (B_TRUE); 2162 } 2163 2164 e1000g_stop(Adapter, B_FALSE); 2165 2166 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 2167 rw_exit(&Adapter->chip_lock); 2168 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2169 return (B_FALSE); 2170 } 2171 2172 rw_exit(&Adapter->chip_lock); 2173 2174 /* Enable and start the watchdog timer */ 2175 enable_watchdog_timer(Adapter); 2176 2177 return (B_TRUE); 2178 } 2179 2180 boolean_t 2181 e1000g_global_reset(struct e1000g *Adapter) 2182 { 2183 /* Disable and stop all the timers */ 2184 disable_watchdog_timer(Adapter); 2185 stop_link_timer(Adapter); 2186 stop_82547_timer(Adapter->tx_ring); 2187 2188 rw_enter(&Adapter->chip_lock, RW_WRITER); 2189 2190 e1000g_stop(Adapter, B_TRUE); 2191 2192 Adapter->init_count = 0; 2193 2194 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 2195 rw_exit(&Adapter->chip_lock); 2196 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2197 return (B_FALSE); 2198 } 2199 2200 rw_exit(&Adapter->chip_lock); 2201 2202 /* Enable and start the watchdog timer */ 2203 enable_watchdog_timer(Adapter); 2204 2205 return (B_TRUE); 2206 } 2207 2208 /* 2209 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2210 * 2211 * This interrupt service routine is for PCI-Express adapters. 2212 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2213 * bit is set. 2214 */ 2215 static uint_t 2216 e1000g_intr_pciexpress(caddr_t arg) 2217 { 2218 struct e1000g *Adapter; 2219 uint32_t icr; 2220 2221 Adapter = (struct e1000g *)(uintptr_t)arg; 2222 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2223 2224 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2225 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2226 return (DDI_INTR_CLAIMED); 2227 } 2228 2229 if (icr & E1000_ICR_INT_ASSERTED) { 2230 /* 2231 * E1000_ICR_INT_ASSERTED bit was set: 2232 * Read(Clear) the ICR, claim this interrupt, 2233 * look for work to do. 2234 */ 2235 e1000g_intr_work(Adapter, icr); 2236 return (DDI_INTR_CLAIMED); 2237 } else { 2238 /* 2239 * E1000_ICR_INT_ASSERTED bit was not set: 2240 * Don't claim this interrupt, return immediately. 2241 */ 2242 return (DDI_INTR_UNCLAIMED); 2243 } 2244 } 2245 2246 /* 2247 * e1000g_intr - ISR for PCI/PCI-X chipsets 2248 * 2249 * This interrupt service routine is for PCI/PCI-X adapters. 2250 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2251 * bit is set or not. 2252 */ 2253 static uint_t 2254 e1000g_intr(caddr_t arg) 2255 { 2256 struct e1000g *Adapter; 2257 uint32_t icr; 2258 2259 Adapter = (struct e1000g *)(uintptr_t)arg; 2260 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2261 2262 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2263 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2264 return (DDI_INTR_CLAIMED); 2265 } 2266 2267 if (icr) { 2268 /* 2269 * Any bit was set in ICR: 2270 * Read(Clear) the ICR, claim this interrupt, 2271 * look for work to do. 2272 */ 2273 e1000g_intr_work(Adapter, icr); 2274 return (DDI_INTR_CLAIMED); 2275 } else { 2276 /* 2277 * No bit was set in ICR: 2278 * Don't claim this interrupt, return immediately. 2279 */ 2280 return (DDI_INTR_UNCLAIMED); 2281 } 2282 } 2283 2284 /* 2285 * e1000g_intr_work - actual processing of ISR 2286 * 2287 * Read(clear) the ICR contents and call appropriate interrupt 2288 * processing routines. 2289 */ 2290 static void 2291 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2292 { 2293 struct e1000_hw *hw; 2294 hw = &Adapter->shared; 2295 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2296 2297 Adapter->rx_pkt_cnt = 0; 2298 Adapter->tx_pkt_cnt = 0; 2299 2300 rw_enter(&Adapter->chip_lock, RW_READER); 2301 2302 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2303 rw_exit(&Adapter->chip_lock); 2304 return; 2305 } 2306 /* 2307 * Here we need to check the "e1000g_state" flag within the chip_lock to 2308 * ensure the receive routine will not execute when the adapter is 2309 * being reset. 2310 */ 2311 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2312 rw_exit(&Adapter->chip_lock); 2313 return; 2314 } 2315 2316 if (icr & E1000_ICR_RXT0) { 2317 mblk_t *mp = NULL; 2318 mblk_t *tail = NULL; 2319 e1000g_rx_ring_t *rx_ring; 2320 2321 rx_ring = Adapter->rx_ring; 2322 mutex_enter(&rx_ring->rx_lock); 2323 /* 2324 * Sometimes with legacy interrupts, it possible that 2325 * there is a single interrupt for Rx/Tx. In which 2326 * case, if poll flag is set, we shouldn't really 2327 * be doing Rx processing. 2328 */ 2329 if (!rx_ring->poll_flag) 2330 mp = e1000g_receive(rx_ring, &tail, 2331 E1000G_CHAIN_NO_LIMIT); 2332 mutex_exit(&rx_ring->rx_lock); 2333 rw_exit(&Adapter->chip_lock); 2334 if (mp != NULL) 2335 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2336 mp, rx_ring->ring_gen_num); 2337 } else 2338 rw_exit(&Adapter->chip_lock); 2339 2340 if (icr & E1000_ICR_TXDW) { 2341 if (!Adapter->tx_intr_enable) 2342 e1000g_clear_tx_interrupt(Adapter); 2343 2344 /* Recycle the tx descriptors */ 2345 rw_enter(&Adapter->chip_lock, RW_READER); 2346 (void) e1000g_recycle(tx_ring); 2347 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2348 rw_exit(&Adapter->chip_lock); 2349 2350 if (tx_ring->resched_needed && 2351 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2352 tx_ring->resched_needed = B_FALSE; 2353 mac_tx_update(Adapter->mh); 2354 E1000G_STAT(tx_ring->stat_reschedule); 2355 } 2356 } 2357 2358 /* 2359 * The Receive Sequence errors RXSEQ and the link status change LSC 2360 * are checked to detect that the cable has been pulled out. For 2361 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2362 * are an indication that cable is not connected. 2363 */ 2364 if ((icr & E1000_ICR_RXSEQ) || 2365 (icr & E1000_ICR_LSC) || 2366 (icr & E1000_ICR_GPI_EN1)) { 2367 boolean_t link_changed; 2368 timeout_id_t tid = 0; 2369 2370 stop_watchdog_timer(Adapter); 2371 2372 rw_enter(&Adapter->chip_lock, RW_WRITER); 2373 2374 /* 2375 * Because we got a link-status-change interrupt, force 2376 * e1000_check_for_link() to look at phy 2377 */ 2378 Adapter->shared.mac.get_link_status = B_TRUE; 2379 2380 /* e1000g_link_check takes care of link status change */ 2381 link_changed = e1000g_link_check(Adapter); 2382 2383 /* Get new phy state */ 2384 e1000g_get_phy_state(Adapter); 2385 2386 /* 2387 * If the link timer has not timed out, we'll not notify 2388 * the upper layer with any link state until the link is up. 2389 */ 2390 if (link_changed && !Adapter->link_complete) { 2391 if (Adapter->link_state == LINK_STATE_UP) { 2392 mutex_enter(&Adapter->link_lock); 2393 Adapter->link_complete = B_TRUE; 2394 tid = Adapter->link_tid; 2395 Adapter->link_tid = 0; 2396 mutex_exit(&Adapter->link_lock); 2397 } else { 2398 link_changed = B_FALSE; 2399 } 2400 } 2401 rw_exit(&Adapter->chip_lock); 2402 2403 if (link_changed) { 2404 if (tid != 0) 2405 (void) untimeout(tid); 2406 2407 /* 2408 * Workaround for esb2. Data stuck in fifo on a link 2409 * down event. Stop receiver here and reset in watchdog. 2410 */ 2411 if ((Adapter->link_state == LINK_STATE_DOWN) && 2412 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2413 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2414 E1000_WRITE_REG(hw, E1000_RCTL, 2415 rctl & ~E1000_RCTL_EN); 2416 e1000g_log(Adapter, CE_WARN, 2417 "ESB2 receiver disabled"); 2418 Adapter->esb2_workaround = B_TRUE; 2419 } 2420 if (!Adapter->reset_flag) 2421 mac_link_update(Adapter->mh, 2422 Adapter->link_state); 2423 if (Adapter->link_state == LINK_STATE_UP) 2424 Adapter->reset_flag = B_FALSE; 2425 } 2426 2427 start_watchdog_timer(Adapter); 2428 } 2429 } 2430 2431 static void 2432 e1000g_init_unicst(struct e1000g *Adapter) 2433 { 2434 struct e1000_hw *hw; 2435 int slot; 2436 2437 hw = &Adapter->shared; 2438 2439 if (Adapter->init_count == 0) { 2440 /* Initialize the multiple unicast addresses */ 2441 Adapter->unicst_total = min(hw->mac.rar_entry_count, 2442 MAX_NUM_UNICAST_ADDRESSES); 2443 2444 /* Workaround for an erratum of 82571 chipst */ 2445 if ((hw->mac.type == e1000_82571) && 2446 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2447 Adapter->unicst_total--; 2448 2449 /* VMware doesn't support multiple mac addresses properly */ 2450 if (hw->subsystem_vendor_id == 0x15ad) 2451 Adapter->unicst_total = 1; 2452 2453 Adapter->unicst_avail = Adapter->unicst_total; 2454 2455 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2456 /* Clear both the flag and MAC address */ 2457 Adapter->unicst_addr[slot].reg.high = 0; 2458 Adapter->unicst_addr[slot].reg.low = 0; 2459 } 2460 } else { 2461 /* Workaround for an erratum of 82571 chipst */ 2462 if ((hw->mac.type == e1000_82571) && 2463 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2464 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2465 2466 /* Re-configure the RAR registers */ 2467 for (slot = 0; slot < Adapter->unicst_total; slot++) 2468 if (Adapter->unicst_addr[slot].mac.set == 1) 2469 e1000_rar_set(hw, 2470 Adapter->unicst_addr[slot].mac.addr, slot); 2471 } 2472 2473 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2474 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2475 } 2476 2477 static int 2478 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2479 int slot) 2480 { 2481 struct e1000_hw *hw; 2482 2483 hw = &Adapter->shared; 2484 2485 /* 2486 * The first revision of Wiseman silicon (rev 2.0) has an errata 2487 * that requires the receiver to be in reset when any of the 2488 * receive address registers (RAR regs) are accessed. The first 2489 * rev of Wiseman silicon also requires MWI to be disabled when 2490 * a global reset or a receive reset is issued. So before we 2491 * initialize the RARs, we check the rev of the Wiseman controller 2492 * and work around any necessary HW errata. 2493 */ 2494 if ((hw->mac.type == e1000_82542) && 2495 (hw->revision_id == E1000_REVISION_2)) { 2496 e1000_pci_clear_mwi(hw); 2497 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2498 msec_delay(5); 2499 } 2500 if (mac_addr == NULL) { 2501 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2502 E1000_WRITE_FLUSH(hw); 2503 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2504 E1000_WRITE_FLUSH(hw); 2505 /* Clear both the flag and MAC address */ 2506 Adapter->unicst_addr[slot].reg.high = 0; 2507 Adapter->unicst_addr[slot].reg.low = 0; 2508 } else { 2509 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2510 ETHERADDRL); 2511 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2512 Adapter->unicst_addr[slot].mac.set = 1; 2513 } 2514 2515 /* Workaround for an erratum of 82571 chipst */ 2516 if (slot == 0) { 2517 if ((hw->mac.type == e1000_82571) && 2518 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2519 if (mac_addr == NULL) { 2520 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2521 slot << 1, 0); 2522 E1000_WRITE_FLUSH(hw); 2523 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2524 (slot << 1) + 1, 0); 2525 E1000_WRITE_FLUSH(hw); 2526 } else { 2527 e1000_rar_set(hw, (uint8_t *)mac_addr, 2528 LAST_RAR_ENTRY); 2529 } 2530 } 2531 2532 /* 2533 * If we are using Wiseman rev 2.0 silicon, we will have previously 2534 * put the receive in reset, and disabled MWI, to work around some 2535 * HW errata. Now we should take the receiver out of reset, and 2536 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2537 */ 2538 if ((hw->mac.type == e1000_82542) && 2539 (hw->revision_id == E1000_REVISION_2)) { 2540 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2541 msec_delay(1); 2542 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2543 e1000_pci_set_mwi(hw); 2544 e1000g_rx_setup(Adapter); 2545 } 2546 2547 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2548 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2549 return (EIO); 2550 } 2551 2552 return (0); 2553 } 2554 2555 static int 2556 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2557 { 2558 struct e1000_hw *hw = &Adapter->shared; 2559 struct ether_addr *newtable; 2560 size_t new_len; 2561 size_t old_len; 2562 int res = 0; 2563 2564 if ((multiaddr[0] & 01) == 0) { 2565 res = EINVAL; 2566 e1000g_log(Adapter, CE_WARN, "Illegal multicast address"); 2567 goto done; 2568 } 2569 2570 if (Adapter->mcast_count >= Adapter->mcast_max_num) { 2571 res = ENOENT; 2572 e1000g_log(Adapter, CE_WARN, 2573 "Adapter requested more than %d mcast addresses", 2574 Adapter->mcast_max_num); 2575 goto done; 2576 } 2577 2578 2579 if (Adapter->mcast_count == Adapter->mcast_alloc_count) { 2580 old_len = Adapter->mcast_alloc_count * 2581 sizeof (struct ether_addr); 2582 new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) * 2583 sizeof (struct ether_addr); 2584 2585 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2586 if (newtable == NULL) { 2587 res = ENOMEM; 2588 e1000g_log(Adapter, CE_WARN, 2589 "Not enough memory to alloc mcast table"); 2590 goto done; 2591 } 2592 2593 if (Adapter->mcast_table != NULL) { 2594 bcopy(Adapter->mcast_table, newtable, old_len); 2595 kmem_free(Adapter->mcast_table, old_len); 2596 } 2597 Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE; 2598 Adapter->mcast_table = newtable; 2599 } 2600 2601 bcopy(multiaddr, 2602 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2603 Adapter->mcast_count++; 2604 2605 /* 2606 * Update the MC table in the hardware 2607 */ 2608 e1000g_clear_interrupt(Adapter); 2609 2610 e1000_update_mc_addr_list(hw, 2611 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2612 2613 e1000g_mask_interrupt(Adapter); 2614 2615 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2616 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2617 res = EIO; 2618 } 2619 2620 done: 2621 return (res); 2622 } 2623 2624 static int 2625 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2626 { 2627 struct e1000_hw *hw = &Adapter->shared; 2628 struct ether_addr *newtable; 2629 size_t new_len; 2630 size_t old_len; 2631 unsigned i; 2632 2633 for (i = 0; i < Adapter->mcast_count; i++) { 2634 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2635 ETHERADDRL) == 0) { 2636 for (i++; i < Adapter->mcast_count; i++) { 2637 Adapter->mcast_table[i - 1] = 2638 Adapter->mcast_table[i]; 2639 } 2640 Adapter->mcast_count--; 2641 break; 2642 } 2643 } 2644 2645 if ((Adapter->mcast_alloc_count - Adapter->mcast_count) > 2646 MCAST_ALLOC_SIZE) { 2647 old_len = Adapter->mcast_alloc_count * 2648 sizeof (struct ether_addr); 2649 new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) * 2650 sizeof (struct ether_addr); 2651 2652 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2653 if (newtable != NULL) { 2654 bcopy(Adapter->mcast_table, newtable, new_len); 2655 kmem_free(Adapter->mcast_table, old_len); 2656 2657 Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE; 2658 Adapter->mcast_table = newtable; 2659 } 2660 } 2661 2662 /* 2663 * Update the MC table in the hardware 2664 */ 2665 e1000g_clear_interrupt(Adapter); 2666 2667 e1000_update_mc_addr_list(hw, 2668 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2669 2670 e1000g_mask_interrupt(Adapter); 2671 2672 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2673 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2674 return (EIO); 2675 } 2676 2677 return (0); 2678 } 2679 2680 static void 2681 e1000g_release_multicast(struct e1000g *Adapter) 2682 { 2683 if (Adapter->mcast_table != NULL) { 2684 kmem_free(Adapter->mcast_table, 2685 Adapter->mcast_alloc_count * sizeof (struct ether_addr)); 2686 Adapter->mcast_table = NULL; 2687 } 2688 } 2689 2690 int 2691 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2692 { 2693 struct e1000g *Adapter = (struct e1000g *)arg; 2694 int result; 2695 2696 rw_enter(&Adapter->chip_lock, RW_WRITER); 2697 2698 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2699 result = ECANCELED; 2700 goto done; 2701 } 2702 2703 result = (add) ? multicst_add(Adapter, addr) 2704 : multicst_remove(Adapter, addr); 2705 2706 done: 2707 rw_exit(&Adapter->chip_lock); 2708 return (result); 2709 2710 } 2711 2712 int 2713 e1000g_m_promisc(void *arg, boolean_t on) 2714 { 2715 struct e1000g *Adapter = (struct e1000g *)arg; 2716 uint32_t rctl; 2717 2718 rw_enter(&Adapter->chip_lock, RW_WRITER); 2719 2720 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2721 rw_exit(&Adapter->chip_lock); 2722 return (ECANCELED); 2723 } 2724 2725 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2726 2727 if (on) 2728 rctl |= 2729 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2730 else 2731 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2732 2733 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2734 2735 Adapter->e1000g_promisc = on; 2736 2737 rw_exit(&Adapter->chip_lock); 2738 2739 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2740 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2741 return (EIO); 2742 } 2743 2744 return (0); 2745 } 2746 2747 /* 2748 * Entry points to enable and disable interrupts at the granularity of 2749 * a group. 2750 * Turns the poll_mode for the whole adapter on and off to enable or 2751 * override the ring level polling control over the hardware interrupts. 2752 */ 2753 static int 2754 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2755 { 2756 struct e1000g *adapter = (struct e1000g *)arg; 2757 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2758 2759 /* 2760 * Later interrupts at the granularity of the this ring will 2761 * invoke mac_rx() with NULL, indicating the need for another 2762 * software classification. 2763 * We have a single ring usable per adapter now, so we only need to 2764 * reset the rx handle for that one. 2765 * When more RX rings can be used, we should update each one of them. 2766 */ 2767 mutex_enter(&rx_ring->rx_lock); 2768 rx_ring->mrh = NULL; 2769 adapter->poll_mode = B_FALSE; 2770 mutex_exit(&rx_ring->rx_lock); 2771 return (0); 2772 } 2773 2774 static int 2775 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2776 { 2777 struct e1000g *adapter = (struct e1000g *)arg; 2778 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2779 2780 mutex_enter(&rx_ring->rx_lock); 2781 2782 /* 2783 * Later interrupts at the granularity of the this ring will 2784 * invoke mac_rx() with the handle for this ring; 2785 */ 2786 adapter->poll_mode = B_TRUE; 2787 rx_ring->mrh = rx_ring->mrh_init; 2788 mutex_exit(&rx_ring->rx_lock); 2789 return (0); 2790 } 2791 2792 /* 2793 * Entry points to enable and disable interrupts at the granularity of 2794 * a ring. 2795 * adapter poll_mode controls whether we actually proceed with hardware 2796 * interrupt toggling. 2797 */ 2798 static int 2799 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2800 { 2801 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2802 struct e1000g *adapter = rx_ring->adapter; 2803 struct e1000_hw *hw = &adapter->shared; 2804 uint32_t intr_mask; 2805 2806 rw_enter(&adapter->chip_lock, RW_READER); 2807 2808 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2809 rw_exit(&adapter->chip_lock); 2810 return (0); 2811 } 2812 2813 mutex_enter(&rx_ring->rx_lock); 2814 rx_ring->poll_flag = 0; 2815 mutex_exit(&rx_ring->rx_lock); 2816 2817 /* Rx interrupt enabling for MSI and legacy */ 2818 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2819 intr_mask |= E1000_IMS_RXT0; 2820 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2821 E1000_WRITE_FLUSH(hw); 2822 2823 /* Trigger a Rx interrupt to check Rx ring */ 2824 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2825 E1000_WRITE_FLUSH(hw); 2826 2827 rw_exit(&adapter->chip_lock); 2828 return (0); 2829 } 2830 2831 static int 2832 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2833 { 2834 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2835 struct e1000g *adapter = rx_ring->adapter; 2836 struct e1000_hw *hw = &adapter->shared; 2837 2838 rw_enter(&adapter->chip_lock, RW_READER); 2839 2840 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2841 rw_exit(&adapter->chip_lock); 2842 return (0); 2843 } 2844 mutex_enter(&rx_ring->rx_lock); 2845 rx_ring->poll_flag = 1; 2846 mutex_exit(&rx_ring->rx_lock); 2847 2848 /* Rx interrupt disabling for MSI and legacy */ 2849 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2850 E1000_WRITE_FLUSH(hw); 2851 2852 rw_exit(&adapter->chip_lock); 2853 return (0); 2854 } 2855 2856 /* 2857 * e1000g_unicst_find - Find the slot for the specified unicast address 2858 */ 2859 static int 2860 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2861 { 2862 int slot; 2863 2864 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2865 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2866 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2867 mac_addr, ETHERADDRL) == 0)) 2868 return (slot); 2869 } 2870 2871 return (-1); 2872 } 2873 2874 /* 2875 * Entry points to add and remove a MAC address to a ring group. 2876 * The caller takes care of adding and removing the MAC addresses 2877 * to the filter via these two routines. 2878 */ 2879 2880 static int 2881 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2882 { 2883 struct e1000g *Adapter = (struct e1000g *)arg; 2884 int slot, err; 2885 2886 rw_enter(&Adapter->chip_lock, RW_WRITER); 2887 2888 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2889 rw_exit(&Adapter->chip_lock); 2890 return (ECANCELED); 2891 } 2892 2893 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2894 /* The same address is already in slot */ 2895 rw_exit(&Adapter->chip_lock); 2896 return (0); 2897 } 2898 2899 if (Adapter->unicst_avail == 0) { 2900 /* no slots available */ 2901 rw_exit(&Adapter->chip_lock); 2902 return (ENOSPC); 2903 } 2904 2905 /* Search for a free slot */ 2906 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2907 if (Adapter->unicst_addr[slot].mac.set == 0) 2908 break; 2909 } 2910 ASSERT(slot < Adapter->unicst_total); 2911 2912 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2913 if (err == 0) 2914 Adapter->unicst_avail--; 2915 2916 rw_exit(&Adapter->chip_lock); 2917 2918 return (err); 2919 } 2920 2921 static int 2922 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2923 { 2924 struct e1000g *Adapter = (struct e1000g *)arg; 2925 int slot, err; 2926 2927 rw_enter(&Adapter->chip_lock, RW_WRITER); 2928 2929 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2930 rw_exit(&Adapter->chip_lock); 2931 return (ECANCELED); 2932 } 2933 2934 slot = e1000g_unicst_find(Adapter, mac_addr); 2935 if (slot == -1) { 2936 rw_exit(&Adapter->chip_lock); 2937 return (EINVAL); 2938 } 2939 2940 ASSERT(Adapter->unicst_addr[slot].mac.set); 2941 2942 /* Clear this slot */ 2943 err = e1000g_unicst_set(Adapter, NULL, slot); 2944 if (err == 0) 2945 Adapter->unicst_avail++; 2946 2947 rw_exit(&Adapter->chip_lock); 2948 2949 return (err); 2950 } 2951 2952 static int 2953 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2954 { 2955 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2956 2957 mutex_enter(&rx_ring->rx_lock); 2958 rx_ring->ring_gen_num = mr_gen_num; 2959 mutex_exit(&rx_ring->rx_lock); 2960 return (0); 2961 } 2962 2963 /* 2964 * Callback funtion for MAC layer to register all rings. 2965 * 2966 * The hardware supports a single group with currently only one ring 2967 * available. 2968 * Though not offering virtualization ability per se, exposing the 2969 * group/ring still enables the polling and interrupt toggling. 2970 */ 2971 /* ARGSUSED */ 2972 void 2973 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2974 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2975 { 2976 struct e1000g *Adapter = (struct e1000g *)arg; 2977 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2978 mac_intr_t *mintr; 2979 2980 /* 2981 * We advertised only RX group/rings, so the MAC framework shouldn't 2982 * ask for any thing else. 2983 */ 2984 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2985 2986 rx_ring->mrh = rx_ring->mrh_init = rh; 2987 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2988 infop->mri_start = e1000g_ring_start; 2989 infop->mri_stop = NULL; 2990 infop->mri_poll = e1000g_poll_ring; 2991 infop->mri_stat = e1000g_rx_ring_stat; 2992 2993 /* Ring level interrupts */ 2994 mintr = &infop->mri_intr; 2995 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2996 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2997 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2998 if (Adapter->msi_enable) 2999 mintr->mi_ddi_handle = Adapter->htable[0]; 3000 } 3001 3002 /* ARGSUSED */ 3003 static void 3004 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 3005 mac_group_info_t *infop, mac_group_handle_t gh) 3006 { 3007 struct e1000g *Adapter = (struct e1000g *)arg; 3008 mac_intr_t *mintr; 3009 3010 /* 3011 * We advertised a single RX ring. Getting a request for anything else 3012 * signifies a bug in the MAC framework. 3013 */ 3014 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 3015 3016 Adapter->rx_group = gh; 3017 3018 infop->mgi_driver = (mac_group_driver_t)Adapter; 3019 infop->mgi_start = NULL; 3020 infop->mgi_stop = NULL; 3021 infop->mgi_addmac = e1000g_addmac; 3022 infop->mgi_remmac = e1000g_remmac; 3023 infop->mgi_count = 1; 3024 3025 /* Group level interrupts */ 3026 mintr = &infop->mgi_intr; 3027 mintr->mi_handle = (mac_intr_handle_t)Adapter; 3028 mintr->mi_enable = e1000g_rx_group_intr_enable; 3029 mintr->mi_disable = e1000g_rx_group_intr_disable; 3030 } 3031 3032 static boolean_t 3033 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 3034 { 3035 struct e1000g *Adapter = (struct e1000g *)arg; 3036 3037 switch (cap) { 3038 case MAC_CAPAB_HCKSUM: { 3039 uint32_t *txflags = cap_data; 3040 3041 if (Adapter->tx_hcksum_enable) 3042 *txflags = HCKSUM_IPHDRCKSUM | 3043 HCKSUM_INET_PARTIAL; 3044 else 3045 return (B_FALSE); 3046 break; 3047 } 3048 3049 case MAC_CAPAB_LSO: { 3050 mac_capab_lso_t *cap_lso = cap_data; 3051 3052 if (Adapter->lso_enable) { 3053 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 3054 cap_lso->lso_basic_tcp_ipv4.lso_max = 3055 E1000_LSO_MAXLEN; 3056 } else 3057 return (B_FALSE); 3058 break; 3059 } 3060 case MAC_CAPAB_RINGS: { 3061 mac_capab_rings_t *cap_rings = cap_data; 3062 3063 /* No TX rings exposed yet */ 3064 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 3065 return (B_FALSE); 3066 3067 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 3068 cap_rings->mr_rnum = 1; 3069 cap_rings->mr_gnum = 1; 3070 cap_rings->mr_rget = e1000g_fill_ring; 3071 cap_rings->mr_gget = e1000g_fill_group; 3072 break; 3073 } 3074 default: 3075 return (B_FALSE); 3076 } 3077 return (B_TRUE); 3078 } 3079 3080 static boolean_t 3081 e1000g_param_locked(mac_prop_id_t pr_num) 3082 { 3083 /* 3084 * All en_* parameters are locked (read-only) while 3085 * the device is in any sort of loopback mode ... 3086 */ 3087 switch (pr_num) { 3088 case MAC_PROP_EN_1000FDX_CAP: 3089 case MAC_PROP_EN_1000HDX_CAP: 3090 case MAC_PROP_EN_100FDX_CAP: 3091 case MAC_PROP_EN_100HDX_CAP: 3092 case MAC_PROP_EN_10FDX_CAP: 3093 case MAC_PROP_EN_10HDX_CAP: 3094 case MAC_PROP_AUTONEG: 3095 case MAC_PROP_FLOWCTRL: 3096 return (B_TRUE); 3097 } 3098 return (B_FALSE); 3099 } 3100 3101 /* 3102 * callback function for set/get of properties 3103 */ 3104 static int 3105 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3106 uint_t pr_valsize, const void *pr_val) 3107 { 3108 struct e1000g *Adapter = arg; 3109 struct e1000_hw *hw = &Adapter->shared; 3110 struct e1000_fc_info *fc = &Adapter->shared.fc; 3111 int err = 0; 3112 link_flowctrl_t flowctrl; 3113 uint32_t cur_mtu, new_mtu; 3114 3115 rw_enter(&Adapter->chip_lock, RW_WRITER); 3116 3117 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 3118 rw_exit(&Adapter->chip_lock); 3119 return (ECANCELED); 3120 } 3121 3122 if (Adapter->loopback_mode != E1000G_LB_NONE && 3123 e1000g_param_locked(pr_num)) { 3124 /* 3125 * All en_* parameters are locked (read-only) 3126 * while the device is in any sort of loopback mode. 3127 */ 3128 rw_exit(&Adapter->chip_lock); 3129 return (EBUSY); 3130 } 3131 3132 switch (pr_num) { 3133 case MAC_PROP_EN_1000FDX_CAP: 3134 if (hw->phy.media_type != e1000_media_type_copper) { 3135 err = ENOTSUP; 3136 break; 3137 } 3138 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 3139 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 3140 goto reset; 3141 case MAC_PROP_EN_100FDX_CAP: 3142 if (hw->phy.media_type != e1000_media_type_copper) { 3143 err = ENOTSUP; 3144 break; 3145 } 3146 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 3147 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 3148 goto reset; 3149 case MAC_PROP_EN_100HDX_CAP: 3150 if (hw->phy.media_type != e1000_media_type_copper) { 3151 err = ENOTSUP; 3152 break; 3153 } 3154 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 3155 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 3156 goto reset; 3157 case MAC_PROP_EN_10FDX_CAP: 3158 if (hw->phy.media_type != e1000_media_type_copper) { 3159 err = ENOTSUP; 3160 break; 3161 } 3162 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 3163 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 3164 goto reset; 3165 case MAC_PROP_EN_10HDX_CAP: 3166 if (hw->phy.media_type != e1000_media_type_copper) { 3167 err = ENOTSUP; 3168 break; 3169 } 3170 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 3171 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 3172 goto reset; 3173 case MAC_PROP_AUTONEG: 3174 if (hw->phy.media_type != e1000_media_type_copper) { 3175 err = ENOTSUP; 3176 break; 3177 } 3178 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 3179 goto reset; 3180 case MAC_PROP_FLOWCTRL: 3181 fc->send_xon = B_TRUE; 3182 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 3183 3184 switch (flowctrl) { 3185 default: 3186 err = EINVAL; 3187 break; 3188 case LINK_FLOWCTRL_NONE: 3189 fc->requested_mode = e1000_fc_none; 3190 break; 3191 case LINK_FLOWCTRL_RX: 3192 fc->requested_mode = e1000_fc_rx_pause; 3193 break; 3194 case LINK_FLOWCTRL_TX: 3195 fc->requested_mode = e1000_fc_tx_pause; 3196 break; 3197 case LINK_FLOWCTRL_BI: 3198 fc->requested_mode = e1000_fc_full; 3199 break; 3200 } 3201 reset: 3202 if (err == 0) { 3203 /* check PCH limits & reset the link */ 3204 e1000g_pch_limits(Adapter); 3205 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3206 err = EINVAL; 3207 } 3208 break; 3209 case MAC_PROP_ADV_1000FDX_CAP: 3210 case MAC_PROP_ADV_1000HDX_CAP: 3211 case MAC_PROP_ADV_100FDX_CAP: 3212 case MAC_PROP_ADV_100HDX_CAP: 3213 case MAC_PROP_ADV_10FDX_CAP: 3214 case MAC_PROP_ADV_10HDX_CAP: 3215 case MAC_PROP_EN_1000HDX_CAP: 3216 case MAC_PROP_STATUS: 3217 case MAC_PROP_SPEED: 3218 case MAC_PROP_DUPLEX: 3219 err = ENOTSUP; /* read-only prop. Can't set this. */ 3220 break; 3221 case MAC_PROP_MTU: 3222 /* adapter must be stopped for an MTU change */ 3223 if (Adapter->e1000g_state & E1000G_STARTED) { 3224 err = EBUSY; 3225 break; 3226 } 3227 3228 cur_mtu = Adapter->default_mtu; 3229 3230 /* get new requested MTU */ 3231 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3232 if (new_mtu == cur_mtu) { 3233 err = 0; 3234 break; 3235 } 3236 3237 if ((new_mtu < DEFAULT_MTU) || 3238 (new_mtu > Adapter->max_mtu)) { 3239 err = EINVAL; 3240 break; 3241 } 3242 3243 /* inform MAC framework of new MTU */ 3244 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3245 3246 if (err == 0) { 3247 Adapter->default_mtu = new_mtu; 3248 Adapter->max_frame_size = 3249 e1000g_mtu2maxframe(new_mtu); 3250 3251 /* 3252 * check PCH limits & set buffer sizes to 3253 * match new MTU 3254 */ 3255 e1000g_pch_limits(Adapter); 3256 e1000g_set_bufsize(Adapter); 3257 3258 /* 3259 * decrease the number of descriptors and free 3260 * packets for jumbo frames to reduce tx/rx 3261 * resource consumption 3262 */ 3263 if (Adapter->max_frame_size >= 3264 (FRAME_SIZE_UPTO_4K)) { 3265 if (Adapter->tx_desc_num_flag == 0) 3266 Adapter->tx_desc_num = 3267 DEFAULT_JUMBO_NUM_TX_DESC; 3268 3269 if (Adapter->rx_desc_num_flag == 0) 3270 Adapter->rx_desc_num = 3271 DEFAULT_JUMBO_NUM_RX_DESC; 3272 3273 if (Adapter->tx_buf_num_flag == 0) 3274 Adapter->tx_freelist_num = 3275 DEFAULT_JUMBO_NUM_TX_BUF; 3276 3277 if (Adapter->rx_buf_num_flag == 0) 3278 Adapter->rx_freelist_limit = 3279 DEFAULT_JUMBO_NUM_RX_BUF; 3280 } else { 3281 if (Adapter->tx_desc_num_flag == 0) 3282 Adapter->tx_desc_num = 3283 DEFAULT_NUM_TX_DESCRIPTOR; 3284 3285 if (Adapter->rx_desc_num_flag == 0) 3286 Adapter->rx_desc_num = 3287 DEFAULT_NUM_RX_DESCRIPTOR; 3288 3289 if (Adapter->tx_buf_num_flag == 0) 3290 Adapter->tx_freelist_num = 3291 DEFAULT_NUM_TX_FREELIST; 3292 3293 if (Adapter->rx_buf_num_flag == 0) 3294 Adapter->rx_freelist_limit = 3295 DEFAULT_NUM_RX_FREELIST; 3296 } 3297 } 3298 break; 3299 case MAC_PROP_PRIVATE: 3300 err = e1000g_set_priv_prop(Adapter, pr_name, 3301 pr_valsize, pr_val); 3302 break; 3303 default: 3304 err = ENOTSUP; 3305 break; 3306 } 3307 rw_exit(&Adapter->chip_lock); 3308 return (err); 3309 } 3310 3311 static int 3312 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3313 uint_t pr_valsize, void *pr_val) 3314 { 3315 struct e1000g *Adapter = arg; 3316 struct e1000_fc_info *fc = &Adapter->shared.fc; 3317 int err = 0; 3318 link_flowctrl_t flowctrl; 3319 uint64_t tmp = 0; 3320 3321 switch (pr_num) { 3322 case MAC_PROP_DUPLEX: 3323 ASSERT(pr_valsize >= sizeof (link_duplex_t)); 3324 bcopy(&Adapter->link_duplex, pr_val, 3325 sizeof (link_duplex_t)); 3326 break; 3327 case MAC_PROP_SPEED: 3328 ASSERT(pr_valsize >= sizeof (uint64_t)); 3329 tmp = Adapter->link_speed * 1000000ull; 3330 bcopy(&tmp, pr_val, sizeof (tmp)); 3331 break; 3332 case MAC_PROP_AUTONEG: 3333 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3334 break; 3335 case MAC_PROP_FLOWCTRL: 3336 ASSERT(pr_valsize >= sizeof (link_flowctrl_t)); 3337 switch (fc->current_mode) { 3338 case e1000_fc_none: 3339 flowctrl = LINK_FLOWCTRL_NONE; 3340 break; 3341 case e1000_fc_rx_pause: 3342 flowctrl = LINK_FLOWCTRL_RX; 3343 break; 3344 case e1000_fc_tx_pause: 3345 flowctrl = LINK_FLOWCTRL_TX; 3346 break; 3347 case e1000_fc_full: 3348 flowctrl = LINK_FLOWCTRL_BI; 3349 break; 3350 } 3351 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3352 break; 3353 case MAC_PROP_ADV_1000FDX_CAP: 3354 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3355 break; 3356 case MAC_PROP_EN_1000FDX_CAP: 3357 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3358 break; 3359 case MAC_PROP_ADV_1000HDX_CAP: 3360 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3361 break; 3362 case MAC_PROP_EN_1000HDX_CAP: 3363 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3364 break; 3365 case MAC_PROP_ADV_100FDX_CAP: 3366 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3367 break; 3368 case MAC_PROP_EN_100FDX_CAP: 3369 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3370 break; 3371 case MAC_PROP_ADV_100HDX_CAP: 3372 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3373 break; 3374 case MAC_PROP_EN_100HDX_CAP: 3375 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3376 break; 3377 case MAC_PROP_ADV_10FDX_CAP: 3378 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3379 break; 3380 case MAC_PROP_EN_10FDX_CAP: 3381 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3382 break; 3383 case MAC_PROP_ADV_10HDX_CAP: 3384 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3385 break; 3386 case MAC_PROP_EN_10HDX_CAP: 3387 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3388 break; 3389 case MAC_PROP_ADV_100T4_CAP: 3390 case MAC_PROP_EN_100T4_CAP: 3391 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3392 break; 3393 case MAC_PROP_PRIVATE: 3394 err = e1000g_get_priv_prop(Adapter, pr_name, 3395 pr_valsize, pr_val); 3396 break; 3397 default: 3398 err = ENOTSUP; 3399 break; 3400 } 3401 3402 return (err); 3403 } 3404 3405 static void 3406 e1000g_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3407 mac_prop_info_handle_t prh) 3408 { 3409 struct e1000g *Adapter = arg; 3410 struct e1000_hw *hw = &Adapter->shared; 3411 3412 switch (pr_num) { 3413 case MAC_PROP_DUPLEX: 3414 case MAC_PROP_SPEED: 3415 case MAC_PROP_ADV_1000FDX_CAP: 3416 case MAC_PROP_ADV_1000HDX_CAP: 3417 case MAC_PROP_ADV_100FDX_CAP: 3418 case MAC_PROP_ADV_100HDX_CAP: 3419 case MAC_PROP_ADV_10FDX_CAP: 3420 case MAC_PROP_ADV_10HDX_CAP: 3421 case MAC_PROP_ADV_100T4_CAP: 3422 case MAC_PROP_EN_100T4_CAP: 3423 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3424 break; 3425 3426 case MAC_PROP_EN_1000FDX_CAP: 3427 if (hw->phy.media_type != e1000_media_type_copper) { 3428 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3429 } else { 3430 mac_prop_info_set_default_uint8(prh, 3431 ((Adapter->phy_ext_status & 3432 IEEE_ESR_1000T_FD_CAPS) || 3433 (Adapter->phy_ext_status & 3434 IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0); 3435 } 3436 break; 3437 3438 case MAC_PROP_EN_100FDX_CAP: 3439 if (hw->phy.media_type != e1000_media_type_copper) { 3440 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3441 } else { 3442 mac_prop_info_set_default_uint8(prh, 3443 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 3444 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 3445 ? 1 : 0); 3446 } 3447 break; 3448 3449 case MAC_PROP_EN_100HDX_CAP: 3450 if (hw->phy.media_type != e1000_media_type_copper) { 3451 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3452 } else { 3453 mac_prop_info_set_default_uint8(prh, 3454 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 3455 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) 3456 ? 1 : 0); 3457 } 3458 break; 3459 3460 case MAC_PROP_EN_10FDX_CAP: 3461 if (hw->phy.media_type != e1000_media_type_copper) { 3462 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3463 } else { 3464 mac_prop_info_set_default_uint8(prh, 3465 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0); 3466 } 3467 break; 3468 3469 case MAC_PROP_EN_10HDX_CAP: 3470 if (hw->phy.media_type != e1000_media_type_copper) { 3471 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3472 } else { 3473 mac_prop_info_set_default_uint8(prh, 3474 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0); 3475 } 3476 break; 3477 3478 case MAC_PROP_EN_1000HDX_CAP: 3479 if (hw->phy.media_type != e1000_media_type_copper) 3480 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3481 break; 3482 3483 case MAC_PROP_AUTONEG: 3484 if (hw->phy.media_type != e1000_media_type_copper) { 3485 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3486 } else { 3487 mac_prop_info_set_default_uint8(prh, 3488 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) 3489 ? 1 : 0); 3490 } 3491 break; 3492 3493 case MAC_PROP_FLOWCTRL: 3494 mac_prop_info_set_default_link_flowctrl(prh, LINK_FLOWCTRL_BI); 3495 break; 3496 3497 case MAC_PROP_MTU: { 3498 struct e1000_mac_info *mac = &Adapter->shared.mac; 3499 struct e1000_phy_info *phy = &Adapter->shared.phy; 3500 uint32_t max; 3501 3502 /* some MAC types do not support jumbo frames */ 3503 if ((mac->type == e1000_ich8lan) || 3504 ((mac->type == e1000_ich9lan) && (phy->type == 3505 e1000_phy_ife))) { 3506 max = DEFAULT_MTU; 3507 } else { 3508 max = Adapter->max_mtu; 3509 } 3510 3511 mac_prop_info_set_range_uint32(prh, DEFAULT_MTU, max); 3512 break; 3513 } 3514 case MAC_PROP_PRIVATE: { 3515 char valstr[64]; 3516 int value; 3517 3518 if (strcmp(pr_name, "_adv_pause_cap") == 0 || 3519 strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3520 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 3521 return; 3522 } else if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3523 value = DEFAULT_TX_BCOPY_THRESHOLD; 3524 } else if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3525 value = DEFAULT_TX_INTR_ENABLE; 3526 } else if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3527 value = DEFAULT_TX_INTR_DELAY; 3528 } else if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3529 value = DEFAULT_TX_INTR_ABS_DELAY; 3530 } else if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3531 value = DEFAULT_RX_BCOPY_THRESHOLD; 3532 } else if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3533 value = DEFAULT_RX_LIMIT_ON_INTR; 3534 } else if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3535 value = DEFAULT_RX_INTR_DELAY; 3536 } else if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3537 value = DEFAULT_RX_INTR_ABS_DELAY; 3538 } else if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3539 value = DEFAULT_INTR_THROTTLING; 3540 } else if (strcmp(pr_name, "_intr_adaptive") == 0) { 3541 value = 1; 3542 } else { 3543 return; 3544 } 3545 3546 (void) snprintf(valstr, sizeof (valstr), "%d", value); 3547 mac_prop_info_set_default_str(prh, valstr); 3548 break; 3549 } 3550 } 3551 } 3552 3553 /* ARGSUSED2 */ 3554 static int 3555 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3556 uint_t pr_valsize, const void *pr_val) 3557 { 3558 int err = 0; 3559 long result; 3560 struct e1000_hw *hw = &Adapter->shared; 3561 3562 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3563 if (pr_val == NULL) { 3564 err = EINVAL; 3565 return (err); 3566 } 3567 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3568 if (result < MIN_TX_BCOPY_THRESHOLD || 3569 result > MAX_TX_BCOPY_THRESHOLD) 3570 err = EINVAL; 3571 else { 3572 Adapter->tx_bcopy_thresh = (uint32_t)result; 3573 } 3574 return (err); 3575 } 3576 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3577 if (pr_val == NULL) { 3578 err = EINVAL; 3579 return (err); 3580 } 3581 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3582 if (result < 0 || result > 1) 3583 err = EINVAL; 3584 else { 3585 Adapter->tx_intr_enable = (result == 1) ? 3586 B_TRUE: B_FALSE; 3587 if (Adapter->tx_intr_enable) 3588 e1000g_mask_tx_interrupt(Adapter); 3589 else 3590 e1000g_clear_tx_interrupt(Adapter); 3591 if (e1000g_check_acc_handle( 3592 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3593 ddi_fm_service_impact(Adapter->dip, 3594 DDI_SERVICE_DEGRADED); 3595 err = EIO; 3596 } 3597 } 3598 return (err); 3599 } 3600 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3601 if (pr_val == NULL) { 3602 err = EINVAL; 3603 return (err); 3604 } 3605 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3606 if (result < MIN_TX_INTR_DELAY || 3607 result > MAX_TX_INTR_DELAY) 3608 err = EINVAL; 3609 else { 3610 Adapter->tx_intr_delay = (uint32_t)result; 3611 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3612 if (e1000g_check_acc_handle( 3613 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3614 ddi_fm_service_impact(Adapter->dip, 3615 DDI_SERVICE_DEGRADED); 3616 err = EIO; 3617 } 3618 } 3619 return (err); 3620 } 3621 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3622 if (pr_val == NULL) { 3623 err = EINVAL; 3624 return (err); 3625 } 3626 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3627 if (result < MIN_TX_INTR_ABS_DELAY || 3628 result > MAX_TX_INTR_ABS_DELAY) 3629 err = EINVAL; 3630 else { 3631 Adapter->tx_intr_abs_delay = (uint32_t)result; 3632 E1000_WRITE_REG(hw, E1000_TADV, 3633 Adapter->tx_intr_abs_delay); 3634 if (e1000g_check_acc_handle( 3635 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3636 ddi_fm_service_impact(Adapter->dip, 3637 DDI_SERVICE_DEGRADED); 3638 err = EIO; 3639 } 3640 } 3641 return (err); 3642 } 3643 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3644 if (pr_val == NULL) { 3645 err = EINVAL; 3646 return (err); 3647 } 3648 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3649 if (result < MIN_RX_BCOPY_THRESHOLD || 3650 result > MAX_RX_BCOPY_THRESHOLD) 3651 err = EINVAL; 3652 else 3653 Adapter->rx_bcopy_thresh = (uint32_t)result; 3654 return (err); 3655 } 3656 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3657 if (pr_val == NULL) { 3658 err = EINVAL; 3659 return (err); 3660 } 3661 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3662 if (result < MIN_RX_LIMIT_ON_INTR || 3663 result > MAX_RX_LIMIT_ON_INTR) 3664 err = EINVAL; 3665 else 3666 Adapter->rx_limit_onintr = (uint32_t)result; 3667 return (err); 3668 } 3669 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3670 if (pr_val == NULL) { 3671 err = EINVAL; 3672 return (err); 3673 } 3674 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3675 if (result < MIN_RX_INTR_DELAY || 3676 result > MAX_RX_INTR_DELAY) 3677 err = EINVAL; 3678 else { 3679 Adapter->rx_intr_delay = (uint32_t)result; 3680 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3681 if (e1000g_check_acc_handle( 3682 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3683 ddi_fm_service_impact(Adapter->dip, 3684 DDI_SERVICE_DEGRADED); 3685 err = EIO; 3686 } 3687 } 3688 return (err); 3689 } 3690 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3691 if (pr_val == NULL) { 3692 err = EINVAL; 3693 return (err); 3694 } 3695 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3696 if (result < MIN_RX_INTR_ABS_DELAY || 3697 result > MAX_RX_INTR_ABS_DELAY) 3698 err = EINVAL; 3699 else { 3700 Adapter->rx_intr_abs_delay = (uint32_t)result; 3701 E1000_WRITE_REG(hw, E1000_RADV, 3702 Adapter->rx_intr_abs_delay); 3703 if (e1000g_check_acc_handle( 3704 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3705 ddi_fm_service_impact(Adapter->dip, 3706 DDI_SERVICE_DEGRADED); 3707 err = EIO; 3708 } 3709 } 3710 return (err); 3711 } 3712 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3713 if (pr_val == NULL) { 3714 err = EINVAL; 3715 return (err); 3716 } 3717 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3718 if (result < MIN_INTR_THROTTLING || 3719 result > MAX_INTR_THROTTLING) 3720 err = EINVAL; 3721 else { 3722 if (hw->mac.type >= e1000_82540) { 3723 Adapter->intr_throttling_rate = 3724 (uint32_t)result; 3725 E1000_WRITE_REG(hw, E1000_ITR, 3726 Adapter->intr_throttling_rate); 3727 if (e1000g_check_acc_handle( 3728 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3729 ddi_fm_service_impact(Adapter->dip, 3730 DDI_SERVICE_DEGRADED); 3731 err = EIO; 3732 } 3733 } else 3734 err = EINVAL; 3735 } 3736 return (err); 3737 } 3738 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3739 if (pr_val == NULL) { 3740 err = EINVAL; 3741 return (err); 3742 } 3743 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3744 if (result < 0 || result > 1) 3745 err = EINVAL; 3746 else { 3747 if (hw->mac.type >= e1000_82540) { 3748 Adapter->intr_adaptive = (result == 1) ? 3749 B_TRUE : B_FALSE; 3750 } else { 3751 err = EINVAL; 3752 } 3753 } 3754 return (err); 3755 } 3756 return (ENOTSUP); 3757 } 3758 3759 static int 3760 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3761 uint_t pr_valsize, void *pr_val) 3762 { 3763 int err = ENOTSUP; 3764 int value; 3765 3766 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3767 value = Adapter->param_adv_pause; 3768 err = 0; 3769 goto done; 3770 } 3771 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3772 value = Adapter->param_adv_asym_pause; 3773 err = 0; 3774 goto done; 3775 } 3776 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3777 value = Adapter->tx_bcopy_thresh; 3778 err = 0; 3779 goto done; 3780 } 3781 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3782 value = Adapter->tx_intr_enable; 3783 err = 0; 3784 goto done; 3785 } 3786 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3787 value = Adapter->tx_intr_delay; 3788 err = 0; 3789 goto done; 3790 } 3791 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3792 value = Adapter->tx_intr_abs_delay; 3793 err = 0; 3794 goto done; 3795 } 3796 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3797 value = Adapter->rx_bcopy_thresh; 3798 err = 0; 3799 goto done; 3800 } 3801 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3802 value = Adapter->rx_limit_onintr; 3803 err = 0; 3804 goto done; 3805 } 3806 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3807 value = Adapter->rx_intr_delay; 3808 err = 0; 3809 goto done; 3810 } 3811 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3812 value = Adapter->rx_intr_abs_delay; 3813 err = 0; 3814 goto done; 3815 } 3816 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3817 value = Adapter->intr_throttling_rate; 3818 err = 0; 3819 goto done; 3820 } 3821 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3822 value = Adapter->intr_adaptive; 3823 err = 0; 3824 goto done; 3825 } 3826 done: 3827 if (err == 0) { 3828 (void) snprintf(pr_val, pr_valsize, "%d", value); 3829 } 3830 return (err); 3831 } 3832 3833 /* 3834 * e1000g_get_conf - get configurations set in e1000g.conf 3835 * This routine gets user-configured values out of the configuration 3836 * file e1000g.conf. 3837 * 3838 * For each configurable value, there is a minimum, a maximum, and a 3839 * default. 3840 * If user does not configure a value, use the default. 3841 * If user configures below the minimum, use the minumum. 3842 * If user configures above the maximum, use the maxumum. 3843 */ 3844 static void 3845 e1000g_get_conf(struct e1000g *Adapter) 3846 { 3847 struct e1000_hw *hw = &Adapter->shared; 3848 boolean_t tbi_compatibility = B_FALSE; 3849 boolean_t is_jumbo = B_FALSE; 3850 int propval; 3851 /* 3852 * decrease the number of descriptors and free packets 3853 * for jumbo frames to reduce tx/rx resource consumption 3854 */ 3855 if (Adapter->max_frame_size >= FRAME_SIZE_UPTO_4K) { 3856 is_jumbo = B_TRUE; 3857 } 3858 3859 /* 3860 * get each configurable property from e1000g.conf 3861 */ 3862 3863 /* 3864 * NumTxDescriptors 3865 */ 3866 Adapter->tx_desc_num_flag = 3867 e1000g_get_prop(Adapter, "NumTxDescriptors", 3868 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3869 is_jumbo ? DEFAULT_JUMBO_NUM_TX_DESC 3870 : DEFAULT_NUM_TX_DESCRIPTOR, &propval); 3871 Adapter->tx_desc_num = propval; 3872 3873 /* 3874 * NumRxDescriptors 3875 */ 3876 Adapter->rx_desc_num_flag = 3877 e1000g_get_prop(Adapter, "NumRxDescriptors", 3878 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3879 is_jumbo ? DEFAULT_JUMBO_NUM_RX_DESC 3880 : DEFAULT_NUM_RX_DESCRIPTOR, &propval); 3881 Adapter->rx_desc_num = propval; 3882 3883 /* 3884 * NumRxFreeList 3885 */ 3886 Adapter->rx_buf_num_flag = 3887 e1000g_get_prop(Adapter, "NumRxFreeList", 3888 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3889 is_jumbo ? DEFAULT_JUMBO_NUM_RX_BUF 3890 : DEFAULT_NUM_RX_FREELIST, &propval); 3891 Adapter->rx_freelist_limit = propval; 3892 3893 /* 3894 * NumTxPacketList 3895 */ 3896 Adapter->tx_buf_num_flag = 3897 e1000g_get_prop(Adapter, "NumTxPacketList", 3898 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3899 is_jumbo ? DEFAULT_JUMBO_NUM_TX_BUF 3900 : DEFAULT_NUM_TX_FREELIST, &propval); 3901 Adapter->tx_freelist_num = propval; 3902 3903 /* 3904 * FlowControl 3905 */ 3906 hw->fc.send_xon = B_TRUE; 3907 (void) e1000g_get_prop(Adapter, "FlowControl", 3908 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL, &propval); 3909 hw->fc.requested_mode = propval; 3910 /* 4 is the setting that says "let the eeprom decide" */ 3911 if (hw->fc.requested_mode == 4) 3912 hw->fc.requested_mode = e1000_fc_default; 3913 3914 /* 3915 * Max Num Receive Packets on Interrupt 3916 */ 3917 (void) e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3918 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3919 DEFAULT_RX_LIMIT_ON_INTR, &propval); 3920 Adapter->rx_limit_onintr = propval; 3921 3922 /* 3923 * PHY master slave setting 3924 */ 3925 (void) e1000g_get_prop(Adapter, "SetMasterSlave", 3926 e1000_ms_hw_default, e1000_ms_auto, 3927 e1000_ms_hw_default, &propval); 3928 hw->phy.ms_type = propval; 3929 3930 /* 3931 * Parameter which controls TBI mode workaround, which is only 3932 * needed on certain switches such as Cisco 6500/Foundry 3933 */ 3934 (void) e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3935 0, 1, DEFAULT_TBI_COMPAT_ENABLE, &propval); 3936 tbi_compatibility = (propval == 1); 3937 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3938 3939 /* 3940 * MSI Enable 3941 */ 3942 (void) e1000g_get_prop(Adapter, "MSIEnable", 3943 0, 1, DEFAULT_MSI_ENABLE, &propval); 3944 Adapter->msi_enable = (propval == 1); 3945 3946 /* 3947 * Interrupt Throttling Rate 3948 */ 3949 (void) e1000g_get_prop(Adapter, "intr_throttling_rate", 3950 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3951 DEFAULT_INTR_THROTTLING, &propval); 3952 Adapter->intr_throttling_rate = propval; 3953 3954 /* 3955 * Adaptive Interrupt Blanking Enable/Disable 3956 * It is enabled by default 3957 */ 3958 (void) e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1, 3959 &propval); 3960 Adapter->intr_adaptive = (propval == 1); 3961 3962 /* 3963 * Hardware checksum enable/disable parameter 3964 */ 3965 (void) e1000g_get_prop(Adapter, "tx_hcksum_enable", 3966 0, 1, DEFAULT_TX_HCKSUM_ENABLE, &propval); 3967 Adapter->tx_hcksum_enable = (propval == 1); 3968 /* 3969 * Checksum on/off selection via global parameters. 3970 * 3971 * If the chip is flagged as not capable of (correctly) 3972 * handling checksumming, we don't enable it on either 3973 * Rx or Tx side. Otherwise, we take this chip's settings 3974 * from the patchable global defaults. 3975 * 3976 * We advertise our capabilities only if TX offload is 3977 * enabled. On receive, the stack will accept checksummed 3978 * packets anyway, even if we haven't said we can deliver 3979 * them. 3980 */ 3981 switch (hw->mac.type) { 3982 case e1000_82540: 3983 case e1000_82544: 3984 case e1000_82545: 3985 case e1000_82545_rev_3: 3986 case e1000_82546: 3987 case e1000_82546_rev_3: 3988 case e1000_82571: 3989 case e1000_82572: 3990 case e1000_82573: 3991 case e1000_80003es2lan: 3992 break; 3993 /* 3994 * For the following Intel PRO/1000 chipsets, we have not 3995 * tested the hardware checksum offload capability, so we 3996 * disable the capability for them. 3997 * e1000_82542, 3998 * e1000_82543, 3999 * e1000_82541, 4000 * e1000_82541_rev_2, 4001 * e1000_82547, 4002 * e1000_82547_rev_2, 4003 */ 4004 default: 4005 Adapter->tx_hcksum_enable = B_FALSE; 4006 } 4007 4008 /* 4009 * Large Send Offloading(LSO) Enable/Disable 4010 * If the tx hardware checksum is not enabled, LSO should be 4011 * disabled. 4012 */ 4013 (void) e1000g_get_prop(Adapter, "lso_enable", 4014 0, 1, DEFAULT_LSO_ENABLE, &propval); 4015 Adapter->lso_enable = (propval == 1); 4016 4017 switch (hw->mac.type) { 4018 case e1000_82546: 4019 case e1000_82546_rev_3: 4020 if (Adapter->lso_enable) 4021 Adapter->lso_premature_issue = B_TRUE; 4022 /* FALLTHRU */ 4023 case e1000_82571: 4024 case e1000_82572: 4025 case e1000_82573: 4026 case e1000_80003es2lan: 4027 break; 4028 default: 4029 Adapter->lso_enable = B_FALSE; 4030 } 4031 4032 if (!Adapter->tx_hcksum_enable) { 4033 Adapter->lso_premature_issue = B_FALSE; 4034 Adapter->lso_enable = B_FALSE; 4035 } 4036 4037 /* 4038 * If mem_workaround_82546 is enabled, the rx buffer allocated by 4039 * e1000_82545, e1000_82546 and e1000_82546_rev_3 4040 * will not cross 64k boundary. 4041 */ 4042 (void) e1000g_get_prop(Adapter, "mem_workaround_82546", 4043 0, 1, DEFAULT_MEM_WORKAROUND_82546, &propval); 4044 Adapter->mem_workaround_82546 = (propval == 1); 4045 4046 /* 4047 * Max number of multicast addresses 4048 */ 4049 (void) e1000g_get_prop(Adapter, "mcast_max_num", 4050 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32, 4051 &propval); 4052 Adapter->mcast_max_num = propval; 4053 } 4054 4055 /* 4056 * e1000g_get_prop - routine to read properties 4057 * 4058 * Get a user-configure property value out of the configuration 4059 * file e1000g.conf. 4060 * 4061 * Caller provides name of the property, a default value, a minimum 4062 * value, a maximum value and a pointer to the returned property 4063 * value. 4064 * 4065 * Return B_TRUE if the configured value of the property is not a default 4066 * value, otherwise return B_FALSE. 4067 */ 4068 static boolean_t 4069 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 4070 char *propname, /* name of the property */ 4071 int minval, /* minimum acceptable value */ 4072 int maxval, /* maximim acceptable value */ 4073 int defval, /* default value */ 4074 int *propvalue) /* property value return to caller */ 4075 { 4076 int propval; /* value returned for requested property */ 4077 int *props; /* point to array of properties returned */ 4078 uint_t nprops; /* number of property value returned */ 4079 boolean_t ret = B_TRUE; 4080 4081 /* 4082 * get the array of properties from the config file 4083 */ 4084 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 4085 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 4086 /* got some properties, test if we got enough */ 4087 if (Adapter->instance < nprops) { 4088 propval = props[Adapter->instance]; 4089 } else { 4090 /* not enough properties configured */ 4091 propval = defval; 4092 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4093 "Not Enough %s values found in e1000g.conf" 4094 " - set to %d\n", 4095 propname, propval); 4096 ret = B_FALSE; 4097 } 4098 4099 /* free memory allocated for properties */ 4100 ddi_prop_free(props); 4101 4102 } else { 4103 propval = defval; 4104 ret = B_FALSE; 4105 } 4106 4107 /* 4108 * enforce limits 4109 */ 4110 if (propval > maxval) { 4111 propval = maxval; 4112 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4113 "Too High %s value in e1000g.conf - set to %d\n", 4114 propname, propval); 4115 } 4116 4117 if (propval < minval) { 4118 propval = minval; 4119 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4120 "Too Low %s value in e1000g.conf - set to %d\n", 4121 propname, propval); 4122 } 4123 4124 *propvalue = propval; 4125 return (ret); 4126 } 4127 4128 static boolean_t 4129 e1000g_link_check(struct e1000g *Adapter) 4130 { 4131 uint16_t speed, duplex, phydata; 4132 boolean_t link_changed = B_FALSE; 4133 struct e1000_hw *hw; 4134 uint32_t reg_tarc; 4135 4136 hw = &Adapter->shared; 4137 4138 if (e1000g_link_up(Adapter)) { 4139 /* 4140 * The Link is up, check whether it was marked as down earlier 4141 */ 4142 if (Adapter->link_state != LINK_STATE_UP) { 4143 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 4144 Adapter->link_speed = speed; 4145 Adapter->link_duplex = duplex; 4146 Adapter->link_state = LINK_STATE_UP; 4147 link_changed = B_TRUE; 4148 4149 if (Adapter->link_speed == SPEED_1000) 4150 Adapter->stall_threshold = TX_STALL_TIME_2S; 4151 else 4152 Adapter->stall_threshold = TX_STALL_TIME_8S; 4153 4154 Adapter->tx_link_down_timeout = 0; 4155 4156 if ((hw->mac.type == e1000_82571) || 4157 (hw->mac.type == e1000_82572)) { 4158 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 4159 if (speed == SPEED_1000) 4160 reg_tarc |= (1 << 21); 4161 else 4162 reg_tarc &= ~(1 << 21); 4163 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 4164 } 4165 } 4166 Adapter->smartspeed = 0; 4167 } else { 4168 if (Adapter->link_state != LINK_STATE_DOWN) { 4169 Adapter->link_speed = 0; 4170 Adapter->link_duplex = 0; 4171 Adapter->link_state = LINK_STATE_DOWN; 4172 link_changed = B_TRUE; 4173 4174 /* 4175 * SmartSpeed workaround for Tabor/TanaX, When the 4176 * driver loses link disable auto master/slave 4177 * resolution. 4178 */ 4179 if (hw->phy.type == e1000_phy_igp) { 4180 (void) e1000_read_phy_reg(hw, 4181 PHY_1000T_CTRL, &phydata); 4182 phydata |= CR_1000T_MS_ENABLE; 4183 (void) e1000_write_phy_reg(hw, 4184 PHY_1000T_CTRL, phydata); 4185 } 4186 } else { 4187 e1000g_smartspeed(Adapter); 4188 } 4189 4190 if (Adapter->e1000g_state & E1000G_STARTED) { 4191 if (Adapter->tx_link_down_timeout < 4192 MAX_TX_LINK_DOWN_TIMEOUT) { 4193 Adapter->tx_link_down_timeout++; 4194 } else if (Adapter->tx_link_down_timeout == 4195 MAX_TX_LINK_DOWN_TIMEOUT) { 4196 e1000g_tx_clean(Adapter); 4197 Adapter->tx_link_down_timeout++; 4198 } 4199 } 4200 } 4201 4202 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4203 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4204 4205 return (link_changed); 4206 } 4207 4208 /* 4209 * e1000g_reset_link - Using the link properties to setup the link 4210 */ 4211 int 4212 e1000g_reset_link(struct e1000g *Adapter) 4213 { 4214 struct e1000_mac_info *mac; 4215 struct e1000_phy_info *phy; 4216 struct e1000_hw *hw; 4217 boolean_t invalid; 4218 4219 mac = &Adapter->shared.mac; 4220 phy = &Adapter->shared.phy; 4221 hw = &Adapter->shared; 4222 invalid = B_FALSE; 4223 4224 if (hw->phy.media_type != e1000_media_type_copper) 4225 goto out; 4226 4227 if (Adapter->param_adv_autoneg == 1) { 4228 mac->autoneg = B_TRUE; 4229 phy->autoneg_advertised = 0; 4230 4231 /* 4232 * 1000hdx is not supported for autonegotiation 4233 */ 4234 if (Adapter->param_adv_1000fdx == 1) 4235 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 4236 4237 if (Adapter->param_adv_100fdx == 1) 4238 phy->autoneg_advertised |= ADVERTISE_100_FULL; 4239 4240 if (Adapter->param_adv_100hdx == 1) 4241 phy->autoneg_advertised |= ADVERTISE_100_HALF; 4242 4243 if (Adapter->param_adv_10fdx == 1) 4244 phy->autoneg_advertised |= ADVERTISE_10_FULL; 4245 4246 if (Adapter->param_adv_10hdx == 1) 4247 phy->autoneg_advertised |= ADVERTISE_10_HALF; 4248 4249 if (phy->autoneg_advertised == 0) 4250 invalid = B_TRUE; 4251 } else { 4252 mac->autoneg = B_FALSE; 4253 4254 /* 4255 * For Intel copper cards, 1000fdx and 1000hdx are not 4256 * supported for forced link 4257 */ 4258 if (Adapter->param_adv_100fdx == 1) 4259 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4260 else if (Adapter->param_adv_100hdx == 1) 4261 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4262 else if (Adapter->param_adv_10fdx == 1) 4263 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4264 else if (Adapter->param_adv_10hdx == 1) 4265 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4266 else 4267 invalid = B_TRUE; 4268 4269 } 4270 4271 if (invalid) { 4272 e1000g_log(Adapter, CE_WARN, 4273 "Invalid link settings. Setup link to " 4274 "support autonegotiation with all link capabilities."); 4275 mac->autoneg = B_TRUE; 4276 phy->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 4277 } 4278 4279 out: 4280 return (e1000_setup_link(&Adapter->shared)); 4281 } 4282 4283 static void 4284 e1000g_timer_tx_resched(struct e1000g *Adapter) 4285 { 4286 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 4287 4288 rw_enter(&Adapter->chip_lock, RW_READER); 4289 4290 if (tx_ring->resched_needed && 4291 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 4292 drv_usectohz(1000000)) && 4293 (Adapter->e1000g_state & E1000G_STARTED) && 4294 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 4295 tx_ring->resched_needed = B_FALSE; 4296 mac_tx_update(Adapter->mh); 4297 E1000G_STAT(tx_ring->stat_reschedule); 4298 E1000G_STAT(tx_ring->stat_timer_reschedule); 4299 } 4300 4301 rw_exit(&Adapter->chip_lock); 4302 } 4303 4304 static void 4305 e1000g_local_timer(void *ws) 4306 { 4307 struct e1000g *Adapter = (struct e1000g *)ws; 4308 struct e1000_hw *hw; 4309 e1000g_ether_addr_t ether_addr; 4310 boolean_t link_changed; 4311 4312 hw = &Adapter->shared; 4313 4314 if (Adapter->e1000g_state & E1000G_ERROR) { 4315 rw_enter(&Adapter->chip_lock, RW_WRITER); 4316 Adapter->e1000g_state &= ~E1000G_ERROR; 4317 rw_exit(&Adapter->chip_lock); 4318 4319 Adapter->reset_count++; 4320 if (e1000g_global_reset(Adapter)) { 4321 ddi_fm_service_impact(Adapter->dip, 4322 DDI_SERVICE_RESTORED); 4323 e1000g_timer_tx_resched(Adapter); 4324 } else 4325 ddi_fm_service_impact(Adapter->dip, 4326 DDI_SERVICE_LOST); 4327 return; 4328 } 4329 4330 if (e1000g_stall_check(Adapter)) { 4331 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4332 "Tx stall detected. Activate automatic recovery.\n"); 4333 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 4334 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 4335 Adapter->reset_count++; 4336 if (e1000g_reset_adapter(Adapter)) { 4337 ddi_fm_service_impact(Adapter->dip, 4338 DDI_SERVICE_RESTORED); 4339 e1000g_timer_tx_resched(Adapter); 4340 } 4341 return; 4342 } 4343 4344 link_changed = B_FALSE; 4345 rw_enter(&Adapter->chip_lock, RW_READER); 4346 if (Adapter->link_complete) 4347 link_changed = e1000g_link_check(Adapter); 4348 rw_exit(&Adapter->chip_lock); 4349 4350 if (link_changed) { 4351 if (!Adapter->reset_flag && 4352 (Adapter->e1000g_state & E1000G_STARTED) && 4353 !(Adapter->e1000g_state & E1000G_SUSPENDED)) 4354 mac_link_update(Adapter->mh, Adapter->link_state); 4355 if (Adapter->link_state == LINK_STATE_UP) 4356 Adapter->reset_flag = B_FALSE; 4357 } 4358 /* 4359 * Workaround for esb2. Data stuck in fifo on a link 4360 * down event. Reset the adapter to recover it. 4361 */ 4362 if (Adapter->esb2_workaround) { 4363 Adapter->esb2_workaround = B_FALSE; 4364 (void) e1000g_reset_adapter(Adapter); 4365 return; 4366 } 4367 4368 /* 4369 * With 82571 controllers, any locally administered address will 4370 * be overwritten when there is a reset on the other port. 4371 * Detect this circumstance and correct it. 4372 */ 4373 if ((hw->mac.type == e1000_82571) && 4374 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 4375 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 4376 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 4377 4378 ether_addr.reg.low = ntohl(ether_addr.reg.low); 4379 ether_addr.reg.high = ntohl(ether_addr.reg.high); 4380 4381 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 4382 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 4383 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 4384 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 4385 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 4386 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 4387 e1000_rar_set(hw, hw->mac.addr, 0); 4388 } 4389 } 4390 4391 /* 4392 * Long TTL workaround for 82541/82547 4393 */ 4394 (void) e1000_igp_ttl_workaround_82547(hw); 4395 4396 /* 4397 * Check for Adaptive IFS settings If there are lots of collisions 4398 * change the value in steps... 4399 * These properties should only be set for 10/100 4400 */ 4401 if ((hw->phy.media_type == e1000_media_type_copper) && 4402 ((Adapter->link_speed == SPEED_100) || 4403 (Adapter->link_speed == SPEED_10))) { 4404 e1000_update_adaptive(hw); 4405 } 4406 /* 4407 * Set Timer Interrupts 4408 */ 4409 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4410 4411 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4412 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4413 else 4414 e1000g_timer_tx_resched(Adapter); 4415 4416 restart_watchdog_timer(Adapter); 4417 } 4418 4419 /* 4420 * The function e1000g_link_timer() is called when the timer for link setup 4421 * is expired, which indicates the completion of the link setup. The link 4422 * state will not be updated until the link setup is completed. And the 4423 * link state will not be sent to the upper layer through mac_link_update() 4424 * in this function. It will be updated in the local timer routine or the 4425 * interrupt service routine after the interface is started (plumbed). 4426 */ 4427 static void 4428 e1000g_link_timer(void *arg) 4429 { 4430 struct e1000g *Adapter = (struct e1000g *)arg; 4431 4432 mutex_enter(&Adapter->link_lock); 4433 Adapter->link_complete = B_TRUE; 4434 Adapter->link_tid = 0; 4435 mutex_exit(&Adapter->link_lock); 4436 } 4437 4438 /* 4439 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4440 * 4441 * This function read the forced speed and duplex for 10/100 Mbps speeds 4442 * and also for 1000 Mbps speeds from the e1000g.conf file 4443 */ 4444 static void 4445 e1000g_force_speed_duplex(struct e1000g *Adapter) 4446 { 4447 int forced; 4448 int propval; 4449 struct e1000_mac_info *mac = &Adapter->shared.mac; 4450 struct e1000_phy_info *phy = &Adapter->shared.phy; 4451 4452 /* 4453 * get value out of config file 4454 */ 4455 (void) e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4456 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY, &forced); 4457 4458 switch (forced) { 4459 case GDIAG_10_HALF: 4460 /* 4461 * Disable Auto Negotiation 4462 */ 4463 mac->autoneg = B_FALSE; 4464 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4465 break; 4466 case GDIAG_10_FULL: 4467 /* 4468 * Disable Auto Negotiation 4469 */ 4470 mac->autoneg = B_FALSE; 4471 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4472 break; 4473 case GDIAG_100_HALF: 4474 /* 4475 * Disable Auto Negotiation 4476 */ 4477 mac->autoneg = B_FALSE; 4478 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4479 break; 4480 case GDIAG_100_FULL: 4481 /* 4482 * Disable Auto Negotiation 4483 */ 4484 mac->autoneg = B_FALSE; 4485 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4486 break; 4487 case GDIAG_1000_FULL: 4488 /* 4489 * The gigabit spec requires autonegotiation. Therefore, 4490 * when the user wants to force the speed to 1000Mbps, we 4491 * enable AutoNeg, but only allow the harware to advertise 4492 * 1000Mbps. This is different from 10/100 operation, where 4493 * we are allowed to link without any negotiation. 4494 */ 4495 mac->autoneg = B_TRUE; 4496 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4497 break; 4498 default: /* obey the setting of AutoNegAdvertised */ 4499 mac->autoneg = B_TRUE; 4500 (void) e1000g_get_prop(Adapter, "AutoNegAdvertised", 4501 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4502 AUTONEG_ADVERTISE_SPEED_DEFAULT, &propval); 4503 phy->autoneg_advertised = (uint16_t)propval; 4504 break; 4505 } /* switch */ 4506 } 4507 4508 /* 4509 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4510 * 4511 * This function reads MaxFrameSize from e1000g.conf 4512 */ 4513 static void 4514 e1000g_get_max_frame_size(struct e1000g *Adapter) 4515 { 4516 int max_frame; 4517 4518 /* 4519 * get value out of config file 4520 */ 4521 (void) e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0, 4522 &max_frame); 4523 4524 switch (max_frame) { 4525 case 0: 4526 Adapter->default_mtu = ETHERMTU; 4527 break; 4528 case 1: 4529 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4530 sizeof (struct ether_vlan_header) - ETHERFCSL; 4531 break; 4532 case 2: 4533 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4534 sizeof (struct ether_vlan_header) - ETHERFCSL; 4535 break; 4536 case 3: 4537 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4538 sizeof (struct ether_vlan_header) - ETHERFCSL; 4539 break; 4540 default: 4541 Adapter->default_mtu = ETHERMTU; 4542 break; 4543 } /* switch */ 4544 4545 /* 4546 * If the user configed MTU is larger than the deivce's maximum MTU, 4547 * the MTU is set to the deivce's maximum value. 4548 */ 4549 if (Adapter->default_mtu > Adapter->max_mtu) 4550 Adapter->default_mtu = Adapter->max_mtu; 4551 4552 Adapter->max_frame_size = e1000g_mtu2maxframe(Adapter->default_mtu); 4553 } 4554 4555 /* 4556 * e1000g_pch_limits - Apply limits of the PCH silicon type 4557 * 4558 * At any frame size larger than the ethernet default, 4559 * prevent linking at 10/100 speeds. 4560 */ 4561 static void 4562 e1000g_pch_limits(struct e1000g *Adapter) 4563 { 4564 struct e1000_hw *hw = &Adapter->shared; 4565 4566 /* only applies to PCH silicon type */ 4567 if (hw->mac.type != e1000_pchlan && hw->mac.type != e1000_pch2lan) 4568 return; 4569 4570 /* only applies to frames larger than ethernet default */ 4571 if (Adapter->max_frame_size > DEFAULT_FRAME_SIZE) { 4572 hw->mac.autoneg = B_TRUE; 4573 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL; 4574 4575 Adapter->param_adv_autoneg = 1; 4576 Adapter->param_adv_1000fdx = 1; 4577 4578 Adapter->param_adv_100fdx = 0; 4579 Adapter->param_adv_100hdx = 0; 4580 Adapter->param_adv_10fdx = 0; 4581 Adapter->param_adv_10hdx = 0; 4582 4583 e1000g_param_sync(Adapter); 4584 } 4585 } 4586 4587 /* 4588 * e1000g_mtu2maxframe - convert given MTU to maximum frame size 4589 */ 4590 static uint32_t 4591 e1000g_mtu2maxframe(uint32_t mtu) 4592 { 4593 uint32_t maxframe; 4594 4595 maxframe = mtu + sizeof (struct ether_vlan_header) + ETHERFCSL; 4596 4597 return (maxframe); 4598 } 4599 4600 static void 4601 arm_watchdog_timer(struct e1000g *Adapter) 4602 { 4603 Adapter->watchdog_tid = 4604 timeout(e1000g_local_timer, 4605 (void *)Adapter, 1 * drv_usectohz(1000000)); 4606 } 4607 #pragma inline(arm_watchdog_timer) 4608 4609 static void 4610 enable_watchdog_timer(struct e1000g *Adapter) 4611 { 4612 mutex_enter(&Adapter->watchdog_lock); 4613 4614 if (!Adapter->watchdog_timer_enabled) { 4615 Adapter->watchdog_timer_enabled = B_TRUE; 4616 Adapter->watchdog_timer_started = B_TRUE; 4617 arm_watchdog_timer(Adapter); 4618 } 4619 4620 mutex_exit(&Adapter->watchdog_lock); 4621 } 4622 4623 static void 4624 disable_watchdog_timer(struct e1000g *Adapter) 4625 { 4626 timeout_id_t tid; 4627 4628 mutex_enter(&Adapter->watchdog_lock); 4629 4630 Adapter->watchdog_timer_enabled = B_FALSE; 4631 Adapter->watchdog_timer_started = B_FALSE; 4632 tid = Adapter->watchdog_tid; 4633 Adapter->watchdog_tid = 0; 4634 4635 mutex_exit(&Adapter->watchdog_lock); 4636 4637 if (tid != 0) 4638 (void) untimeout(tid); 4639 } 4640 4641 static void 4642 start_watchdog_timer(struct e1000g *Adapter) 4643 { 4644 mutex_enter(&Adapter->watchdog_lock); 4645 4646 if (Adapter->watchdog_timer_enabled) { 4647 if (!Adapter->watchdog_timer_started) { 4648 Adapter->watchdog_timer_started = B_TRUE; 4649 arm_watchdog_timer(Adapter); 4650 } 4651 } 4652 4653 mutex_exit(&Adapter->watchdog_lock); 4654 } 4655 4656 static void 4657 restart_watchdog_timer(struct e1000g *Adapter) 4658 { 4659 mutex_enter(&Adapter->watchdog_lock); 4660 4661 if (Adapter->watchdog_timer_started) 4662 arm_watchdog_timer(Adapter); 4663 4664 mutex_exit(&Adapter->watchdog_lock); 4665 } 4666 4667 static void 4668 stop_watchdog_timer(struct e1000g *Adapter) 4669 { 4670 timeout_id_t tid; 4671 4672 mutex_enter(&Adapter->watchdog_lock); 4673 4674 Adapter->watchdog_timer_started = B_FALSE; 4675 tid = Adapter->watchdog_tid; 4676 Adapter->watchdog_tid = 0; 4677 4678 mutex_exit(&Adapter->watchdog_lock); 4679 4680 if (tid != 0) 4681 (void) untimeout(tid); 4682 } 4683 4684 static void 4685 stop_link_timer(struct e1000g *Adapter) 4686 { 4687 timeout_id_t tid; 4688 4689 /* Disable the link timer */ 4690 mutex_enter(&Adapter->link_lock); 4691 4692 tid = Adapter->link_tid; 4693 Adapter->link_tid = 0; 4694 4695 mutex_exit(&Adapter->link_lock); 4696 4697 if (tid != 0) 4698 (void) untimeout(tid); 4699 } 4700 4701 static void 4702 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4703 { 4704 timeout_id_t tid; 4705 4706 /* Disable the tx timer for 82547 chipset */ 4707 mutex_enter(&tx_ring->tx_lock); 4708 4709 tx_ring->timer_enable_82547 = B_FALSE; 4710 tid = tx_ring->timer_id_82547; 4711 tx_ring->timer_id_82547 = 0; 4712 4713 mutex_exit(&tx_ring->tx_lock); 4714 4715 if (tid != 0) 4716 (void) untimeout(tid); 4717 } 4718 4719 void 4720 e1000g_clear_interrupt(struct e1000g *Adapter) 4721 { 4722 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4723 0xffffffff & ~E1000_IMS_RXSEQ); 4724 } 4725 4726 void 4727 e1000g_mask_interrupt(struct e1000g *Adapter) 4728 { 4729 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4730 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4731 4732 if (Adapter->tx_intr_enable) 4733 e1000g_mask_tx_interrupt(Adapter); 4734 } 4735 4736 /* 4737 * This routine is called by e1000g_quiesce(), therefore must not block. 4738 */ 4739 void 4740 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4741 { 4742 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4743 } 4744 4745 void 4746 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4747 { 4748 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4749 } 4750 4751 void 4752 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4753 { 4754 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4755 } 4756 4757 static void 4758 e1000g_smartspeed(struct e1000g *Adapter) 4759 { 4760 struct e1000_hw *hw = &Adapter->shared; 4761 uint16_t phy_status; 4762 uint16_t phy_ctrl; 4763 4764 /* 4765 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4766 * advertising 1000Full, we don't even use the workaround 4767 */ 4768 if ((hw->phy.type != e1000_phy_igp) || 4769 !hw->mac.autoneg || 4770 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4771 return; 4772 4773 /* 4774 * True if this is the first call of this function or after every 4775 * 30 seconds of not having link 4776 */ 4777 if (Adapter->smartspeed == 0) { 4778 /* 4779 * If Master/Slave config fault is asserted twice, we 4780 * assume back-to-back 4781 */ 4782 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4783 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4784 return; 4785 4786 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4787 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4788 return; 4789 /* 4790 * We're assuming back-2-back because our status register 4791 * insists! there's a fault in the master/slave 4792 * relationship that was "negotiated" 4793 */ 4794 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4795 /* 4796 * Is the phy configured for manual configuration of 4797 * master/slave? 4798 */ 4799 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4800 /* 4801 * Yes. Then disable manual configuration (enable 4802 * auto configuration) of master/slave 4803 */ 4804 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4805 (void) e1000_write_phy_reg(hw, 4806 PHY_1000T_CTRL, phy_ctrl); 4807 /* 4808 * Effectively starting the clock 4809 */ 4810 Adapter->smartspeed++; 4811 /* 4812 * Restart autonegotiation 4813 */ 4814 if (!e1000_phy_setup_autoneg(hw) && 4815 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4816 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4817 MII_CR_RESTART_AUTO_NEG); 4818 (void) e1000_write_phy_reg(hw, 4819 PHY_CONTROL, phy_ctrl); 4820 } 4821 } 4822 return; 4823 /* 4824 * Has 6 seconds transpired still without link? Remember, 4825 * you should reset the smartspeed counter once you obtain 4826 * link 4827 */ 4828 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4829 /* 4830 * Yes. Remember, we did at the start determine that 4831 * there's a master/slave configuration fault, so we're 4832 * still assuming there's someone on the other end, but we 4833 * just haven't yet been able to talk to it. We then 4834 * re-enable auto configuration of master/slave to see if 4835 * we're running 2/3 pair cables. 4836 */ 4837 /* 4838 * If still no link, perhaps using 2/3 pair cable 4839 */ 4840 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4841 phy_ctrl |= CR_1000T_MS_ENABLE; 4842 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4843 /* 4844 * Restart autoneg with phy enabled for manual 4845 * configuration of master/slave 4846 */ 4847 if (!e1000_phy_setup_autoneg(hw) && 4848 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4849 phy_ctrl |= 4850 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4851 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4852 } 4853 /* 4854 * Hopefully, there are no more faults and we've obtained 4855 * link as a result. 4856 */ 4857 } 4858 /* 4859 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4860 * seconds) 4861 */ 4862 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4863 Adapter->smartspeed = 0; 4864 } 4865 4866 static boolean_t 4867 is_valid_mac_addr(uint8_t *mac_addr) 4868 { 4869 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4870 const uint8_t addr_test2[6] = 4871 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4872 4873 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4874 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4875 return (B_FALSE); 4876 4877 return (B_TRUE); 4878 } 4879 4880 /* 4881 * e1000g_stall_check - check for tx stall 4882 * 4883 * This function checks if the adapter is stalled (in transmit). 4884 * 4885 * It is called each time the watchdog timeout is invoked. 4886 * If the transmit descriptor reclaim continuously fails, 4887 * the watchdog value will increment by 1. If the watchdog 4888 * value exceeds the threshold, the adapter is assumed to 4889 * have stalled and need to be reset. 4890 */ 4891 static boolean_t 4892 e1000g_stall_check(struct e1000g *Adapter) 4893 { 4894 e1000g_tx_ring_t *tx_ring; 4895 4896 tx_ring = Adapter->tx_ring; 4897 4898 if (Adapter->link_state != LINK_STATE_UP) 4899 return (B_FALSE); 4900 4901 (void) e1000g_recycle(tx_ring); 4902 4903 if (Adapter->stall_flag) 4904 return (B_TRUE); 4905 4906 return (B_FALSE); 4907 } 4908 4909 #ifdef E1000G_DEBUG 4910 static enum ioc_reply 4911 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4912 { 4913 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4914 e1000g_peekpoke_t *ppd; 4915 uint64_t mem_va; 4916 uint64_t maxoff; 4917 boolean_t peek; 4918 4919 switch (iocp->ioc_cmd) { 4920 4921 case E1000G_IOC_REG_PEEK: 4922 peek = B_TRUE; 4923 break; 4924 4925 case E1000G_IOC_REG_POKE: 4926 peek = B_FALSE; 4927 break; 4928 4929 deault: 4930 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4931 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4932 iocp->ioc_cmd); 4933 return (IOC_INVAL); 4934 } 4935 4936 /* 4937 * Validate format of ioctl 4938 */ 4939 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4940 return (IOC_INVAL); 4941 if (mp->b_cont == NULL) 4942 return (IOC_INVAL); 4943 4944 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4945 4946 /* 4947 * Validate request parameters 4948 */ 4949 switch (ppd->pp_acc_space) { 4950 4951 default: 4952 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4953 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4954 ppd->pp_acc_space); 4955 return (IOC_INVAL); 4956 4957 case E1000G_PP_SPACE_REG: 4958 /* 4959 * Memory-mapped I/O space 4960 */ 4961 ASSERT(ppd->pp_acc_size == 4); 4962 if (ppd->pp_acc_size != 4) 4963 return (IOC_INVAL); 4964 4965 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4966 return (IOC_INVAL); 4967 4968 mem_va = 0; 4969 maxoff = 0x10000; 4970 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4971 break; 4972 4973 case E1000G_PP_SPACE_E1000G: 4974 /* 4975 * E1000g data structure! 4976 */ 4977 mem_va = (uintptr_t)e1000gp; 4978 maxoff = sizeof (struct e1000g); 4979 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4980 break; 4981 4982 } 4983 4984 if (ppd->pp_acc_offset >= maxoff) 4985 return (IOC_INVAL); 4986 4987 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4988 return (IOC_INVAL); 4989 4990 /* 4991 * All OK - go! 4992 */ 4993 ppd->pp_acc_offset += mem_va; 4994 (*ppfn)(e1000gp, ppd); 4995 return (peek ? IOC_REPLY : IOC_ACK); 4996 } 4997 4998 static void 4999 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5000 { 5001 ddi_acc_handle_t handle; 5002 uint32_t *regaddr; 5003 5004 handle = e1000gp->osdep.reg_handle; 5005 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 5006 (uintptr_t)ppd->pp_acc_offset); 5007 5008 ppd->pp_acc_data = ddi_get32(handle, regaddr); 5009 } 5010 5011 static void 5012 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5013 { 5014 ddi_acc_handle_t handle; 5015 uint32_t *regaddr; 5016 uint32_t value; 5017 5018 handle = e1000gp->osdep.reg_handle; 5019 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 5020 (uintptr_t)ppd->pp_acc_offset); 5021 value = (uint32_t)ppd->pp_acc_data; 5022 5023 ddi_put32(handle, regaddr, value); 5024 } 5025 5026 static void 5027 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5028 { 5029 uint64_t value; 5030 void *vaddr; 5031 5032 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5033 5034 switch (ppd->pp_acc_size) { 5035 case 1: 5036 value = *(uint8_t *)vaddr; 5037 break; 5038 5039 case 2: 5040 value = *(uint16_t *)vaddr; 5041 break; 5042 5043 case 4: 5044 value = *(uint32_t *)vaddr; 5045 break; 5046 5047 case 8: 5048 value = *(uint64_t *)vaddr; 5049 break; 5050 } 5051 5052 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 5053 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 5054 (void *)e1000gp, (void *)ppd, value, vaddr); 5055 5056 ppd->pp_acc_data = value; 5057 } 5058 5059 static void 5060 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 5061 { 5062 uint64_t value; 5063 void *vaddr; 5064 5065 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5066 value = ppd->pp_acc_data; 5067 5068 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 5069 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 5070 (void *)e1000gp, (void *)ppd, value, vaddr); 5071 5072 switch (ppd->pp_acc_size) { 5073 case 1: 5074 *(uint8_t *)vaddr = (uint8_t)value; 5075 break; 5076 5077 case 2: 5078 *(uint16_t *)vaddr = (uint16_t)value; 5079 break; 5080 5081 case 4: 5082 *(uint32_t *)vaddr = (uint32_t)value; 5083 break; 5084 5085 case 8: 5086 *(uint64_t *)vaddr = (uint64_t)value; 5087 break; 5088 } 5089 } 5090 #endif 5091 5092 /* 5093 * Loopback Support 5094 */ 5095 static lb_property_t lb_normal = 5096 { normal, "normal", E1000G_LB_NONE }; 5097 static lb_property_t lb_external1000 = 5098 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 5099 static lb_property_t lb_external100 = 5100 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 5101 static lb_property_t lb_external10 = 5102 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 5103 static lb_property_t lb_phy = 5104 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 5105 5106 static enum ioc_reply 5107 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 5108 { 5109 lb_info_sz_t *lbsp; 5110 lb_property_t *lbpp; 5111 struct e1000_hw *hw; 5112 uint32_t *lbmp; 5113 uint32_t size; 5114 uint32_t value; 5115 5116 hw = &Adapter->shared; 5117 5118 if (mp->b_cont == NULL) 5119 return (IOC_INVAL); 5120 5121 if (!e1000g_check_loopback_support(hw)) { 5122 e1000g_log(NULL, CE_WARN, 5123 "Loopback is not supported on e1000g%d", Adapter->instance); 5124 return (IOC_INVAL); 5125 } 5126 5127 switch (iocp->ioc_cmd) { 5128 default: 5129 return (IOC_INVAL); 5130 5131 case LB_GET_INFO_SIZE: 5132 size = sizeof (lb_info_sz_t); 5133 if (iocp->ioc_count != size) 5134 return (IOC_INVAL); 5135 5136 rw_enter(&Adapter->chip_lock, RW_WRITER); 5137 e1000g_get_phy_state(Adapter); 5138 5139 /* 5140 * Workaround for hardware faults. In order to get a stable 5141 * state of phy, we will wait for a specific interval and 5142 * try again. The time delay is an experiential value based 5143 * on our testing. 5144 */ 5145 msec_delay(100); 5146 e1000g_get_phy_state(Adapter); 5147 rw_exit(&Adapter->chip_lock); 5148 5149 value = sizeof (lb_normal); 5150 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5151 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5152 (hw->phy.media_type == e1000_media_type_fiber) || 5153 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5154 value += sizeof (lb_phy); 5155 switch (hw->mac.type) { 5156 case e1000_82571: 5157 case e1000_82572: 5158 case e1000_80003es2lan: 5159 value += sizeof (lb_external1000); 5160 break; 5161 } 5162 } 5163 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5164 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5165 value += sizeof (lb_external100); 5166 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5167 value += sizeof (lb_external10); 5168 5169 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 5170 *lbsp = value; 5171 break; 5172 5173 case LB_GET_INFO: 5174 value = sizeof (lb_normal); 5175 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5176 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5177 (hw->phy.media_type == e1000_media_type_fiber) || 5178 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5179 value += sizeof (lb_phy); 5180 switch (hw->mac.type) { 5181 case e1000_82571: 5182 case e1000_82572: 5183 case e1000_80003es2lan: 5184 value += sizeof (lb_external1000); 5185 break; 5186 } 5187 } 5188 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5189 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5190 value += sizeof (lb_external100); 5191 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5192 value += sizeof (lb_external10); 5193 5194 size = value; 5195 if (iocp->ioc_count != size) 5196 return (IOC_INVAL); 5197 5198 value = 0; 5199 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 5200 lbpp[value++] = lb_normal; 5201 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5202 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5203 (hw->phy.media_type == e1000_media_type_fiber) || 5204 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5205 lbpp[value++] = lb_phy; 5206 switch (hw->mac.type) { 5207 case e1000_82571: 5208 case e1000_82572: 5209 case e1000_80003es2lan: 5210 lbpp[value++] = lb_external1000; 5211 break; 5212 } 5213 } 5214 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5215 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5216 lbpp[value++] = lb_external100; 5217 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5218 lbpp[value++] = lb_external10; 5219 break; 5220 5221 case LB_GET_MODE: 5222 size = sizeof (uint32_t); 5223 if (iocp->ioc_count != size) 5224 return (IOC_INVAL); 5225 5226 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5227 *lbmp = Adapter->loopback_mode; 5228 break; 5229 5230 case LB_SET_MODE: 5231 size = 0; 5232 if (iocp->ioc_count != sizeof (uint32_t)) 5233 return (IOC_INVAL); 5234 5235 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5236 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 5237 return (IOC_INVAL); 5238 break; 5239 } 5240 5241 iocp->ioc_count = size; 5242 iocp->ioc_error = 0; 5243 5244 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 5245 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 5246 return (IOC_INVAL); 5247 } 5248 5249 return (IOC_REPLY); 5250 } 5251 5252 static boolean_t 5253 e1000g_check_loopback_support(struct e1000_hw *hw) 5254 { 5255 switch (hw->mac.type) { 5256 case e1000_82540: 5257 case e1000_82545: 5258 case e1000_82545_rev_3: 5259 case e1000_82546: 5260 case e1000_82546_rev_3: 5261 case e1000_82541: 5262 case e1000_82541_rev_2: 5263 case e1000_82547: 5264 case e1000_82547_rev_2: 5265 case e1000_82571: 5266 case e1000_82572: 5267 case e1000_82573: 5268 case e1000_82574: 5269 case e1000_80003es2lan: 5270 case e1000_ich9lan: 5271 case e1000_ich10lan: 5272 return (B_TRUE); 5273 } 5274 return (B_FALSE); 5275 } 5276 5277 static boolean_t 5278 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 5279 { 5280 struct e1000_hw *hw; 5281 int i, times; 5282 boolean_t link_up; 5283 5284 if (mode == Adapter->loopback_mode) 5285 return (B_TRUE); 5286 5287 hw = &Adapter->shared; 5288 times = 0; 5289 5290 Adapter->loopback_mode = mode; 5291 5292 if (mode == E1000G_LB_NONE) { 5293 /* Reset the chip */ 5294 hw->phy.autoneg_wait_to_complete = B_TRUE; 5295 (void) e1000g_reset_adapter(Adapter); 5296 hw->phy.autoneg_wait_to_complete = B_FALSE; 5297 return (B_TRUE); 5298 } 5299 5300 again: 5301 5302 rw_enter(&Adapter->chip_lock, RW_WRITER); 5303 5304 switch (mode) { 5305 default: 5306 rw_exit(&Adapter->chip_lock); 5307 return (B_FALSE); 5308 5309 case E1000G_LB_EXTERNAL_1000: 5310 e1000g_set_external_loopback_1000(Adapter); 5311 break; 5312 5313 case E1000G_LB_EXTERNAL_100: 5314 e1000g_set_external_loopback_100(Adapter); 5315 break; 5316 5317 case E1000G_LB_EXTERNAL_10: 5318 e1000g_set_external_loopback_10(Adapter); 5319 break; 5320 5321 case E1000G_LB_INTERNAL_PHY: 5322 e1000g_set_internal_loopback(Adapter); 5323 break; 5324 } 5325 5326 times++; 5327 5328 rw_exit(&Adapter->chip_lock); 5329 5330 /* Wait for link up */ 5331 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 5332 msec_delay(100); 5333 5334 rw_enter(&Adapter->chip_lock, RW_WRITER); 5335 5336 link_up = e1000g_link_up(Adapter); 5337 5338 rw_exit(&Adapter->chip_lock); 5339 5340 if (!link_up) { 5341 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5342 "Failed to get the link up"); 5343 if (times < 2) { 5344 /* Reset the link */ 5345 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5346 "Reset the link ..."); 5347 (void) e1000g_reset_adapter(Adapter); 5348 goto again; 5349 } 5350 5351 /* 5352 * Reset driver to loopback none when set loopback failed 5353 * for the second time. 5354 */ 5355 Adapter->loopback_mode = E1000G_LB_NONE; 5356 5357 /* Reset the chip */ 5358 hw->phy.autoneg_wait_to_complete = B_TRUE; 5359 (void) e1000g_reset_adapter(Adapter); 5360 hw->phy.autoneg_wait_to_complete = B_FALSE; 5361 5362 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5363 "Set loopback mode failed, reset to loopback none"); 5364 5365 return (B_FALSE); 5366 } 5367 5368 return (B_TRUE); 5369 } 5370 5371 /* 5372 * The following loopback settings are from Intel's technical 5373 * document - "How To Loopback". All the register settings and 5374 * time delay values are directly inherited from the document 5375 * without more explanations available. 5376 */ 5377 static void 5378 e1000g_set_internal_loopback(struct e1000g *Adapter) 5379 { 5380 struct e1000_hw *hw; 5381 uint32_t ctrl; 5382 uint32_t status; 5383 uint16_t phy_ctrl; 5384 uint16_t phy_reg; 5385 uint32_t txcw; 5386 5387 hw = &Adapter->shared; 5388 5389 /* Disable Smart Power Down */ 5390 phy_spd_state(hw, B_FALSE); 5391 5392 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5393 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 5394 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 5395 5396 switch (hw->mac.type) { 5397 case e1000_82540: 5398 case e1000_82545: 5399 case e1000_82545_rev_3: 5400 case e1000_82546: 5401 case e1000_82546_rev_3: 5402 case e1000_82573: 5403 /* Auto-MDI/MDIX off */ 5404 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 5405 /* Reset PHY to update Auto-MDI/MDIX */ 5406 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5407 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 5408 /* Reset PHY to auto-neg off and force 1000 */ 5409 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5410 phy_ctrl | MII_CR_RESET); 5411 /* 5412 * Disable PHY receiver for 82540/545/546 and 82573 Family. 5413 * See comments above e1000g_set_internal_loopback() for the 5414 * background. 5415 */ 5416 (void) e1000_write_phy_reg(hw, 29, 0x001F); 5417 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 5418 (void) e1000_write_phy_reg(hw, 29, 0x001A); 5419 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 5420 break; 5421 case e1000_80003es2lan: 5422 /* Force Link Up */ 5423 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 5424 0x1CC); 5425 /* Sets PCS loopback at 1Gbs */ 5426 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5427 0x1046); 5428 break; 5429 } 5430 5431 /* 5432 * The following registers should be set for e1000_phy_bm phy type. 5433 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5434 * For others, we do not need to set these registers. 5435 */ 5436 if (hw->phy.type == e1000_phy_bm) { 5437 /* Set Default MAC Interface speed to 1GB */ 5438 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5439 phy_reg &= ~0x0007; 5440 phy_reg |= 0x006; 5441 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5442 /* Assert SW reset for above settings to take effect */ 5443 (void) e1000_phy_commit(hw); 5444 msec_delay(1); 5445 /* Force Full Duplex */ 5446 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5447 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5448 phy_reg | 0x000C); 5449 /* Set Link Up (in force link) */ 5450 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5451 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5452 phy_reg | 0x0040); 5453 /* Force Link */ 5454 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5455 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5456 phy_reg | 0x0040); 5457 /* Set Early Link Enable */ 5458 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5459 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20), 5460 phy_reg | 0x0400); 5461 } 5462 5463 /* Set loopback */ 5464 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5465 5466 msec_delay(250); 5467 5468 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5469 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5470 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5471 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5472 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5473 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5474 E1000_CTRL_FD); /* Force Duplex to FULL */ 5475 5476 switch (hw->mac.type) { 5477 case e1000_82540: 5478 case e1000_82545: 5479 case e1000_82545_rev_3: 5480 case e1000_82546: 5481 case e1000_82546_rev_3: 5482 /* 5483 * For some serdes we'll need to commit the writes now 5484 * so that the status is updated on link 5485 */ 5486 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5487 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5488 msec_delay(100); 5489 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5490 } 5491 5492 if (hw->phy.media_type == e1000_media_type_copper) { 5493 /* Invert Loss of Signal */ 5494 ctrl |= E1000_CTRL_ILOS; 5495 } else { 5496 /* Set ILOS on fiber nic if half duplex is detected */ 5497 status = E1000_READ_REG(hw, E1000_STATUS); 5498 if ((status & E1000_STATUS_FD) == 0) 5499 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5500 } 5501 break; 5502 5503 case e1000_82571: 5504 case e1000_82572: 5505 /* 5506 * The fiber/SerDes versions of this adapter do not contain an 5507 * accessible PHY. Therefore, loopback beyond MAC must be done 5508 * using SerDes analog loopback. 5509 */ 5510 if (hw->phy.media_type != e1000_media_type_copper) { 5511 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5512 txcw = E1000_READ_REG(hw, E1000_TXCW); 5513 txcw &= ~((uint32_t)1 << 31); 5514 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5515 5516 /* 5517 * Write 0x410 to Serdes Control register 5518 * to enable Serdes analog loopback 5519 */ 5520 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5521 msec_delay(10); 5522 } 5523 5524 status = E1000_READ_REG(hw, E1000_STATUS); 5525 /* Set ILOS on fiber nic if half duplex is detected */ 5526 if ((hw->phy.media_type == e1000_media_type_fiber) && 5527 ((status & E1000_STATUS_FD) == 0 || 5528 (status & E1000_STATUS_LU) == 0)) 5529 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5530 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5531 ctrl |= E1000_CTRL_SLU; 5532 break; 5533 5534 case e1000_82573: 5535 ctrl |= E1000_CTRL_ILOS; 5536 break; 5537 case e1000_ich9lan: 5538 case e1000_ich10lan: 5539 ctrl |= E1000_CTRL_SLU; 5540 break; 5541 } 5542 if (hw->phy.type == e1000_phy_bm) 5543 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5544 5545 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5546 } 5547 5548 static void 5549 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5550 { 5551 struct e1000_hw *hw; 5552 uint32_t rctl; 5553 uint32_t ctrl_ext; 5554 uint32_t ctrl; 5555 uint32_t status; 5556 uint32_t txcw; 5557 uint16_t phydata; 5558 5559 hw = &Adapter->shared; 5560 5561 /* Disable Smart Power Down */ 5562 phy_spd_state(hw, B_FALSE); 5563 5564 switch (hw->mac.type) { 5565 case e1000_82571: 5566 case e1000_82572: 5567 switch (hw->phy.media_type) { 5568 case e1000_media_type_copper: 5569 /* Force link up (Must be done before the PHY writes) */ 5570 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5571 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5572 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5573 5574 rctl = E1000_READ_REG(hw, E1000_RCTL); 5575 rctl |= (E1000_RCTL_EN | 5576 E1000_RCTL_SBP | 5577 E1000_RCTL_UPE | 5578 E1000_RCTL_MPE | 5579 E1000_RCTL_LPE | 5580 E1000_RCTL_BAM); /* 0x803E */ 5581 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5582 5583 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5584 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5585 E1000_CTRL_EXT_SDP6_DATA | 5586 E1000_CTRL_EXT_SDP3_DATA | 5587 E1000_CTRL_EXT_SDP4_DIR | 5588 E1000_CTRL_EXT_SDP6_DIR | 5589 E1000_CTRL_EXT_SDP3_DIR); /* 0x0DD0 */ 5590 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5591 5592 /* 5593 * This sequence tunes the PHY's SDP and no customer 5594 * settable values. For background, see comments above 5595 * e1000g_set_internal_loopback(). 5596 */ 5597 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5598 msec_delay(10); 5599 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5600 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5601 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5602 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5603 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5604 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5605 5606 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5607 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5608 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5609 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5610 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5611 5612 msec_delay(50); 5613 break; 5614 case e1000_media_type_fiber: 5615 case e1000_media_type_internal_serdes: 5616 status = E1000_READ_REG(hw, E1000_STATUS); 5617 if (((status & E1000_STATUS_LU) == 0) || 5618 (hw->phy.media_type == 5619 e1000_media_type_internal_serdes)) { 5620 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5621 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5622 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5623 } 5624 5625 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5626 txcw = E1000_READ_REG(hw, E1000_TXCW); 5627 txcw &= ~((uint32_t)1 << 31); 5628 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5629 5630 /* 5631 * Write 0x410 to Serdes Control register 5632 * to enable Serdes analog loopback 5633 */ 5634 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5635 msec_delay(10); 5636 break; 5637 default: 5638 break; 5639 } 5640 break; 5641 case e1000_82574: 5642 case e1000_80003es2lan: 5643 case e1000_ich9lan: 5644 case e1000_ich10lan: 5645 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5646 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5647 phydata | (1 << 5)); 5648 Adapter->param_adv_autoneg = 1; 5649 Adapter->param_adv_1000fdx = 1; 5650 (void) e1000g_reset_link(Adapter); 5651 break; 5652 } 5653 } 5654 5655 static void 5656 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5657 { 5658 struct e1000_hw *hw; 5659 uint32_t ctrl; 5660 uint16_t phy_ctrl; 5661 5662 hw = &Adapter->shared; 5663 5664 /* Disable Smart Power Down */ 5665 phy_spd_state(hw, B_FALSE); 5666 5667 phy_ctrl = (MII_CR_FULL_DUPLEX | 5668 MII_CR_SPEED_100); 5669 5670 /* Force 100/FD, reset PHY */ 5671 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5672 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5673 msec_delay(10); 5674 5675 /* Force 100/FD */ 5676 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5677 phy_ctrl); /* 0x2100 */ 5678 msec_delay(10); 5679 5680 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5681 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5682 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5683 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5684 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5685 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5686 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5687 E1000_CTRL_FD); /* Force Duplex to FULL */ 5688 5689 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5690 } 5691 5692 static void 5693 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5694 { 5695 struct e1000_hw *hw; 5696 uint32_t ctrl; 5697 uint16_t phy_ctrl; 5698 5699 hw = &Adapter->shared; 5700 5701 /* Disable Smart Power Down */ 5702 phy_spd_state(hw, B_FALSE); 5703 5704 phy_ctrl = (MII_CR_FULL_DUPLEX | 5705 MII_CR_SPEED_10); 5706 5707 /* Force 10/FD, reset PHY */ 5708 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5709 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5710 msec_delay(10); 5711 5712 /* Force 10/FD */ 5713 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5714 phy_ctrl); /* 0x0100 */ 5715 msec_delay(10); 5716 5717 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5718 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5719 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5720 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5721 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5722 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5723 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5724 E1000_CTRL_FD); /* Force Duplex to FULL */ 5725 5726 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5727 } 5728 5729 #ifdef __sparc 5730 static boolean_t 5731 e1000g_find_mac_address(struct e1000g *Adapter) 5732 { 5733 struct e1000_hw *hw = &Adapter->shared; 5734 uchar_t *bytes; 5735 struct ether_addr sysaddr; 5736 uint_t nelts; 5737 int err; 5738 boolean_t found = B_FALSE; 5739 5740 /* 5741 * The "vendor's factory-set address" may already have 5742 * been extracted from the chip, but if the property 5743 * "local-mac-address" is set we use that instead. 5744 * 5745 * We check whether it looks like an array of 6 5746 * bytes (which it should, if OBP set it). If we can't 5747 * make sense of it this way, we'll ignore it. 5748 */ 5749 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5750 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5751 if (err == DDI_PROP_SUCCESS) { 5752 if (nelts == ETHERADDRL) { 5753 while (nelts--) 5754 hw->mac.addr[nelts] = bytes[nelts]; 5755 found = B_TRUE; 5756 } 5757 ddi_prop_free(bytes); 5758 } 5759 5760 /* 5761 * Look up the OBP property "local-mac-address?". If the user has set 5762 * 'local-mac-address? = false', use "the system address" instead. 5763 */ 5764 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5765 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5766 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5767 if (localetheraddr(NULL, &sysaddr) != 0) { 5768 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5769 found = B_TRUE; 5770 } 5771 } 5772 ddi_prop_free(bytes); 5773 } 5774 5775 /* 5776 * Finally(!), if there's a valid "mac-address" property (created 5777 * if we netbooted from this interface), we must use this instead 5778 * of any of the above to ensure that the NFS/install server doesn't 5779 * get confused by the address changing as Solaris takes over! 5780 */ 5781 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5782 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5783 if (err == DDI_PROP_SUCCESS) { 5784 if (nelts == ETHERADDRL) { 5785 while (nelts--) 5786 hw->mac.addr[nelts] = bytes[nelts]; 5787 found = B_TRUE; 5788 } 5789 ddi_prop_free(bytes); 5790 } 5791 5792 if (found) { 5793 bcopy(hw->mac.addr, hw->mac.perm_addr, 5794 ETHERADDRL); 5795 } 5796 5797 return (found); 5798 } 5799 #endif 5800 5801 static int 5802 e1000g_add_intrs(struct e1000g *Adapter) 5803 { 5804 dev_info_t *devinfo; 5805 int intr_types; 5806 int rc; 5807 5808 devinfo = Adapter->dip; 5809 5810 /* Get supported interrupt types */ 5811 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5812 5813 if (rc != DDI_SUCCESS) { 5814 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5815 "Get supported interrupt types failed: %d\n", rc); 5816 return (DDI_FAILURE); 5817 } 5818 5819 /* 5820 * Based on Intel Technical Advisory document (TA-160), there are some 5821 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5822 * that it supports MSI, but in fact has problems. 5823 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5824 * PCI/PCI-X NICs. 5825 */ 5826 if (Adapter->shared.mac.type < e1000_82571) 5827 Adapter->msi_enable = B_FALSE; 5828 5829 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5830 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5831 5832 if (rc != DDI_SUCCESS) { 5833 /* EMPTY */ 5834 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5835 "Add MSI failed, trying Legacy interrupts\n"); 5836 } else { 5837 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5838 } 5839 } 5840 5841 if ((Adapter->intr_type == 0) && 5842 (intr_types & DDI_INTR_TYPE_FIXED)) { 5843 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5844 5845 if (rc != DDI_SUCCESS) { 5846 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5847 "Add Legacy interrupts failed\n"); 5848 return (DDI_FAILURE); 5849 } 5850 5851 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5852 } 5853 5854 if (Adapter->intr_type == 0) { 5855 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5856 "No interrupts registered\n"); 5857 return (DDI_FAILURE); 5858 } 5859 5860 return (DDI_SUCCESS); 5861 } 5862 5863 /* 5864 * e1000g_intr_add() handles MSI/Legacy interrupts 5865 */ 5866 static int 5867 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5868 { 5869 dev_info_t *devinfo; 5870 int count, avail, actual; 5871 int x, y, rc, inum = 0; 5872 int flag; 5873 ddi_intr_handler_t *intr_handler; 5874 5875 devinfo = Adapter->dip; 5876 5877 /* get number of interrupts */ 5878 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5879 if ((rc != DDI_SUCCESS) || (count == 0)) { 5880 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5881 "Get interrupt number failed. Return: %d, count: %d\n", 5882 rc, count); 5883 return (DDI_FAILURE); 5884 } 5885 5886 /* get number of available interrupts */ 5887 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5888 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5889 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5890 "Get interrupt available number failed. " 5891 "Return: %d, available: %d\n", rc, avail); 5892 return (DDI_FAILURE); 5893 } 5894 5895 if (avail < count) { 5896 /* EMPTY */ 5897 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5898 "Interrupts count: %d, available: %d\n", 5899 count, avail); 5900 } 5901 5902 /* Allocate an array of interrupt handles */ 5903 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5904 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5905 5906 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5907 flag = DDI_INTR_ALLOC_NORMAL; 5908 5909 /* call ddi_intr_alloc() */ 5910 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5911 count, &actual, flag); 5912 5913 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5914 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5915 "Allocate interrupts failed: %d\n", rc); 5916 5917 kmem_free(Adapter->htable, Adapter->intr_size); 5918 return (DDI_FAILURE); 5919 } 5920 5921 if (actual < count) { 5922 /* EMPTY */ 5923 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5924 "Interrupts requested: %d, received: %d\n", 5925 count, actual); 5926 } 5927 5928 Adapter->intr_cnt = actual; 5929 5930 /* Get priority for first msi, assume remaining are all the same */ 5931 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5932 5933 if (rc != DDI_SUCCESS) { 5934 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5935 "Get interrupt priority failed: %d\n", rc); 5936 5937 /* Free already allocated intr */ 5938 for (y = 0; y < actual; y++) 5939 (void) ddi_intr_free(Adapter->htable[y]); 5940 5941 kmem_free(Adapter->htable, Adapter->intr_size); 5942 return (DDI_FAILURE); 5943 } 5944 5945 /* 5946 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5947 * use the interrupt service routine e1000g_intr_pciexpress() 5948 * to avoid interrupt stealing when sharing interrupt with other 5949 * devices. 5950 */ 5951 if (Adapter->shared.mac.type < e1000_82571) 5952 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5953 else 5954 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5955 5956 /* Call ddi_intr_add_handler() */ 5957 for (x = 0; x < actual; x++) { 5958 rc = ddi_intr_add_handler(Adapter->htable[x], 5959 intr_handler, (caddr_t)Adapter, NULL); 5960 5961 if (rc != DDI_SUCCESS) { 5962 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5963 "Add interrupt handler failed: %d\n", rc); 5964 5965 /* Remove already added handler */ 5966 for (y = 0; y < x; y++) 5967 (void) ddi_intr_remove_handler( 5968 Adapter->htable[y]); 5969 5970 /* Free already allocated intr */ 5971 for (y = 0; y < actual; y++) 5972 (void) ddi_intr_free(Adapter->htable[y]); 5973 5974 kmem_free(Adapter->htable, Adapter->intr_size); 5975 return (DDI_FAILURE); 5976 } 5977 } 5978 5979 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5980 5981 if (rc != DDI_SUCCESS) { 5982 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5983 "Get interrupt cap failed: %d\n", rc); 5984 5985 /* Free already allocated intr */ 5986 for (y = 0; y < actual; y++) { 5987 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5988 (void) ddi_intr_free(Adapter->htable[y]); 5989 } 5990 5991 kmem_free(Adapter->htable, Adapter->intr_size); 5992 return (DDI_FAILURE); 5993 } 5994 5995 return (DDI_SUCCESS); 5996 } 5997 5998 static int 5999 e1000g_rem_intrs(struct e1000g *Adapter) 6000 { 6001 int x; 6002 int rc; 6003 6004 for (x = 0; x < Adapter->intr_cnt; x++) { 6005 rc = ddi_intr_remove_handler(Adapter->htable[x]); 6006 if (rc != DDI_SUCCESS) { 6007 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6008 "Remove intr handler failed: %d\n", rc); 6009 return (DDI_FAILURE); 6010 } 6011 6012 rc = ddi_intr_free(Adapter->htable[x]); 6013 if (rc != DDI_SUCCESS) { 6014 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6015 "Free intr failed: %d\n", rc); 6016 return (DDI_FAILURE); 6017 } 6018 } 6019 6020 kmem_free(Adapter->htable, Adapter->intr_size); 6021 6022 return (DDI_SUCCESS); 6023 } 6024 6025 static int 6026 e1000g_enable_intrs(struct e1000g *Adapter) 6027 { 6028 int x; 6029 int rc; 6030 6031 /* Enable interrupts */ 6032 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 6033 /* Call ddi_intr_block_enable() for MSI */ 6034 rc = ddi_intr_block_enable(Adapter->htable, 6035 Adapter->intr_cnt); 6036 if (rc != DDI_SUCCESS) { 6037 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6038 "Enable block intr failed: %d\n", rc); 6039 return (DDI_FAILURE); 6040 } 6041 } else { 6042 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 6043 for (x = 0; x < Adapter->intr_cnt; x++) { 6044 rc = ddi_intr_enable(Adapter->htable[x]); 6045 if (rc != DDI_SUCCESS) { 6046 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6047 "Enable intr failed: %d\n", rc); 6048 return (DDI_FAILURE); 6049 } 6050 } 6051 } 6052 6053 return (DDI_SUCCESS); 6054 } 6055 6056 static int 6057 e1000g_disable_intrs(struct e1000g *Adapter) 6058 { 6059 int x; 6060 int rc; 6061 6062 /* Disable all interrupts */ 6063 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 6064 rc = ddi_intr_block_disable(Adapter->htable, 6065 Adapter->intr_cnt); 6066 if (rc != DDI_SUCCESS) { 6067 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6068 "Disable block intr failed: %d\n", rc); 6069 return (DDI_FAILURE); 6070 } 6071 } else { 6072 for (x = 0; x < Adapter->intr_cnt; x++) { 6073 rc = ddi_intr_disable(Adapter->htable[x]); 6074 if (rc != DDI_SUCCESS) { 6075 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 6076 "Disable intr failed: %d\n", rc); 6077 return (DDI_FAILURE); 6078 } 6079 } 6080 } 6081 6082 return (DDI_SUCCESS); 6083 } 6084 6085 /* 6086 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 6087 */ 6088 static void 6089 e1000g_get_phy_state(struct e1000g *Adapter) 6090 { 6091 struct e1000_hw *hw = &Adapter->shared; 6092 6093 if (hw->phy.media_type == e1000_media_type_copper) { 6094 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 6095 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 6096 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 6097 &Adapter->phy_an_adv); 6098 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, 6099 &Adapter->phy_an_exp); 6100 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, 6101 &Adapter->phy_ext_status); 6102 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, 6103 &Adapter->phy_1000t_ctrl); 6104 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 6105 &Adapter->phy_1000t_status); 6106 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, 6107 &Adapter->phy_lp_able); 6108 6109 Adapter->param_autoneg_cap = 6110 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 6111 Adapter->param_pause_cap = 6112 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 6113 Adapter->param_asym_pause_cap = 6114 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 6115 Adapter->param_1000fdx_cap = 6116 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 6117 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 6118 Adapter->param_1000hdx_cap = 6119 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 6120 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 6121 Adapter->param_100t4_cap = 6122 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 6123 Adapter->param_100fdx_cap = 6124 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6125 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 6126 Adapter->param_100hdx_cap = 6127 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6128 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 6129 Adapter->param_10fdx_cap = 6130 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6131 Adapter->param_10hdx_cap = 6132 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6133 6134 Adapter->param_adv_autoneg = hw->mac.autoneg; 6135 Adapter->param_adv_pause = 6136 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 6137 Adapter->param_adv_asym_pause = 6138 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 6139 Adapter->param_adv_1000hdx = 6140 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 6141 Adapter->param_adv_100t4 = 6142 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 6143 if (Adapter->param_adv_autoneg == 1) { 6144 Adapter->param_adv_1000fdx = 6145 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) 6146 ? 1 : 0; 6147 Adapter->param_adv_100fdx = 6148 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) 6149 ? 1 : 0; 6150 Adapter->param_adv_100hdx = 6151 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) 6152 ? 1 : 0; 6153 Adapter->param_adv_10fdx = 6154 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 6155 Adapter->param_adv_10hdx = 6156 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 6157 } 6158 6159 Adapter->param_lp_autoneg = 6160 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 6161 Adapter->param_lp_pause = 6162 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 6163 Adapter->param_lp_asym_pause = 6164 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 6165 Adapter->param_lp_1000fdx = 6166 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 6167 Adapter->param_lp_1000hdx = 6168 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 6169 Adapter->param_lp_100t4 = 6170 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 6171 Adapter->param_lp_100fdx = 6172 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 6173 Adapter->param_lp_100hdx = 6174 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 6175 Adapter->param_lp_10fdx = 6176 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 6177 Adapter->param_lp_10hdx = 6178 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 6179 } else { 6180 /* 6181 * 1Gig Fiber adapter only offers 1Gig Full Duplex. Meaning, 6182 * it can only work with 1Gig Full Duplex Link Partner. 6183 */ 6184 Adapter->param_autoneg_cap = 0; 6185 Adapter->param_pause_cap = 1; 6186 Adapter->param_asym_pause_cap = 1; 6187 Adapter->param_1000fdx_cap = 1; 6188 Adapter->param_1000hdx_cap = 0; 6189 Adapter->param_100t4_cap = 0; 6190 Adapter->param_100fdx_cap = 0; 6191 Adapter->param_100hdx_cap = 0; 6192 Adapter->param_10fdx_cap = 0; 6193 Adapter->param_10hdx_cap = 0; 6194 6195 Adapter->param_adv_autoneg = 0; 6196 Adapter->param_adv_pause = 1; 6197 Adapter->param_adv_asym_pause = 1; 6198 Adapter->param_adv_1000fdx = 1; 6199 Adapter->param_adv_1000hdx = 0; 6200 Adapter->param_adv_100t4 = 0; 6201 Adapter->param_adv_100fdx = 0; 6202 Adapter->param_adv_100hdx = 0; 6203 Adapter->param_adv_10fdx = 0; 6204 Adapter->param_adv_10hdx = 0; 6205 6206 Adapter->param_lp_autoneg = 0; 6207 Adapter->param_lp_pause = 0; 6208 Adapter->param_lp_asym_pause = 0; 6209 Adapter->param_lp_1000fdx = 0; 6210 Adapter->param_lp_1000hdx = 0; 6211 Adapter->param_lp_100t4 = 0; 6212 Adapter->param_lp_100fdx = 0; 6213 Adapter->param_lp_100hdx = 0; 6214 Adapter->param_lp_10fdx = 0; 6215 Adapter->param_lp_10hdx = 0; 6216 } 6217 } 6218 6219 /* 6220 * FMA support 6221 */ 6222 6223 int 6224 e1000g_check_acc_handle(ddi_acc_handle_t handle) 6225 { 6226 ddi_fm_error_t de; 6227 6228 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 6229 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 6230 return (de.fme_status); 6231 } 6232 6233 int 6234 e1000g_check_dma_handle(ddi_dma_handle_t handle) 6235 { 6236 ddi_fm_error_t de; 6237 6238 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 6239 return (de.fme_status); 6240 } 6241 6242 /* 6243 * The IO fault service error handling callback function 6244 */ 6245 /* ARGSUSED2 */ 6246 static int 6247 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 6248 { 6249 /* 6250 * as the driver can always deal with an error in any dma or 6251 * access handle, we can just return the fme_status value. 6252 */ 6253 pci_ereport_post(dip, err, NULL); 6254 return (err->fme_status); 6255 } 6256 6257 static void 6258 e1000g_fm_init(struct e1000g *Adapter) 6259 { 6260 ddi_iblock_cookie_t iblk; 6261 int fma_dma_flag; 6262 6263 /* Only register with IO Fault Services if we have some capability */ 6264 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 6265 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 6266 } else { 6267 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 6268 } 6269 6270 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 6271 fma_dma_flag = 1; 6272 } else { 6273 fma_dma_flag = 0; 6274 } 6275 6276 (void) e1000g_set_fma_flags(fma_dma_flag); 6277 6278 if (Adapter->fm_capabilities) { 6279 6280 /* Register capabilities with IO Fault Services */ 6281 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 6282 6283 /* 6284 * Initialize pci ereport capabilities if ereport capable 6285 */ 6286 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6287 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6288 pci_ereport_setup(Adapter->dip); 6289 6290 /* 6291 * Register error callback if error callback capable 6292 */ 6293 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6294 ddi_fm_handler_register(Adapter->dip, 6295 e1000g_fm_error_cb, (void*) Adapter); 6296 } 6297 } 6298 6299 static void 6300 e1000g_fm_fini(struct e1000g *Adapter) 6301 { 6302 /* Only unregister FMA capabilities if we registered some */ 6303 if (Adapter->fm_capabilities) { 6304 6305 /* 6306 * Release any resources allocated by pci_ereport_setup() 6307 */ 6308 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6309 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6310 pci_ereport_teardown(Adapter->dip); 6311 6312 /* 6313 * Un-register error callback if error callback capable 6314 */ 6315 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6316 ddi_fm_handler_unregister(Adapter->dip); 6317 6318 /* Unregister from IO Fault Services */ 6319 mutex_enter(&e1000g_rx_detach_lock); 6320 ddi_fm_fini(Adapter->dip); 6321 if (Adapter->priv_dip != NULL) { 6322 DEVI(Adapter->priv_dip)->devi_fmhdl = NULL; 6323 } 6324 mutex_exit(&e1000g_rx_detach_lock); 6325 } 6326 } 6327 6328 void 6329 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 6330 { 6331 uint64_t ena; 6332 char buf[FM_MAX_CLASS]; 6333 6334 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 6335 ena = fm_ena_generate(0, FM_ENA_FMT1); 6336 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 6337 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 6338 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 6339 } 6340 } 6341 6342 /* 6343 * quiesce(9E) entry point. 6344 * 6345 * This function is called when the system is single-threaded at high 6346 * PIL with preemption disabled. Therefore, this function must not be 6347 * blocked. 6348 * 6349 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6350 * DDI_FAILURE indicates an error condition and should almost never happen. 6351 */ 6352 static int 6353 e1000g_quiesce(dev_info_t *devinfo) 6354 { 6355 struct e1000g *Adapter; 6356 6357 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 6358 6359 if (Adapter == NULL) 6360 return (DDI_FAILURE); 6361 6362 e1000g_clear_all_interrupts(Adapter); 6363 6364 (void) e1000_reset_hw(&Adapter->shared); 6365 6366 /* Setup our HW Tx Head & Tail descriptor pointers */ 6367 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 6368 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 6369 6370 /* Setup our HW Rx Head & Tail descriptor pointers */ 6371 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 6372 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 6373 6374 return (DDI_SUCCESS); 6375 } 6376 6377 /* 6378 * synchronize the adv* and en* parameters. 6379 * 6380 * See comments in <sys/dld.h> for details of the *_en_* 6381 * parameters. The usage of ndd for setting adv parameters will 6382 * synchronize all the en parameters with the e1000g parameters, 6383 * implicitly disabling any settings made via dladm. 6384 */ 6385 static void 6386 e1000g_param_sync(struct e1000g *Adapter) 6387 { 6388 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 6389 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 6390 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 6391 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 6392 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 6393 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 6394 } 6395 6396 /* 6397 * e1000g_get_driver_control - tell manageability firmware that the driver 6398 * has control. 6399 */ 6400 static void 6401 e1000g_get_driver_control(struct e1000_hw *hw) 6402 { 6403 uint32_t ctrl_ext; 6404 uint32_t swsm; 6405 6406 /* tell manageability firmware the driver has taken over */ 6407 switch (hw->mac.type) { 6408 case e1000_82573: 6409 swsm = E1000_READ_REG(hw, E1000_SWSM); 6410 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 6411 break; 6412 case e1000_82571: 6413 case e1000_82572: 6414 case e1000_82574: 6415 case e1000_80003es2lan: 6416 case e1000_ich8lan: 6417 case e1000_ich9lan: 6418 case e1000_ich10lan: 6419 case e1000_pchlan: 6420 case e1000_pch2lan: 6421 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6422 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6423 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6424 break; 6425 default: 6426 /* no manageability firmware: do nothing */ 6427 break; 6428 } 6429 } 6430 6431 /* 6432 * e1000g_release_driver_control - tell manageability firmware that the driver 6433 * has released control. 6434 */ 6435 static void 6436 e1000g_release_driver_control(struct e1000_hw *hw) 6437 { 6438 uint32_t ctrl_ext; 6439 uint32_t swsm; 6440 6441 /* tell manageability firmware the driver has released control */ 6442 switch (hw->mac.type) { 6443 case e1000_82573: 6444 swsm = E1000_READ_REG(hw, E1000_SWSM); 6445 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6446 break; 6447 case e1000_82571: 6448 case e1000_82572: 6449 case e1000_82574: 6450 case e1000_80003es2lan: 6451 case e1000_ich8lan: 6452 case e1000_ich9lan: 6453 case e1000_ich10lan: 6454 case e1000_pchlan: 6455 case e1000_pch2lan: 6456 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6457 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6458 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6459 break; 6460 default: 6461 /* no manageability firmware: do nothing */ 6462 break; 6463 } 6464 } 6465 6466 /* 6467 * Restore e1000g promiscuous mode. 6468 */ 6469 static void 6470 e1000g_restore_promisc(struct e1000g *Adapter) 6471 { 6472 if (Adapter->e1000g_promisc) { 6473 uint32_t rctl; 6474 6475 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6476 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6477 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6478 } 6479 } 6480