1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #ifndef _E1000_OSDEP_H 27 #define _E1000_OSDEP_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <sys/types.h> 34 #include <sys/conf.h> 35 #include <sys/debug.h> 36 #include <sys/stropts.h> 37 #include <sys/stream.h> 38 #include <sys/strlog.h> 39 #include <sys/kmem.h> 40 #include <sys/stat.h> 41 #include <sys/kstat.h> 42 #include <sys/modctl.h> 43 #include <sys/errno.h> 44 #include <sys/ddi.h> 45 #include <sys/sunddi.h> 46 #include <sys/pci.h> 47 #include <sys/atomic.h> 48 #include <sys/note.h> 49 #include "e1000g_debug.h" 50 51 /* 52 * === BEGIN CONTENT FORMERLY IN FXHW.H === 53 */ 54 #define usec_delay(x) drv_usecwait(x) 55 #define msec_delay(x) drv_usecwait(x * 1000) 56 57 #ifdef E1000G_DEBUG 58 #define DEBUGOUT(S) \ 59 E1000G_DEBUGLOG_0(NULL, E1000G_INFO_LEVEL, S) 60 #define DEBUGOUT1(S, A) \ 61 E1000G_DEBUGLOG_1(NULL, E1000G_INFO_LEVEL, S, A) 62 #define DEBUGOUT2(S, A, B) \ 63 E1000G_DEBUGLOG_2(NULL, E1000G_INFO_LEVEL, S, A, B) 64 #define DEBUGOUT3(S, A, B, C) \ 65 E1000G_DEBUGLOG_3(NULL, E1000G_INFO_LEVEL, S, A, B, C) 66 #define DEBUGFUNC(F) \ 67 E1000G_DEBUGLOG_0(NULL, E1000G_TRACE_LEVEL, F) 68 #else 69 #define DEBUGOUT(S) 70 #define DEBUGOUT1(S, A) 71 #define DEBUGOUT2(S, A, B) 72 #define DEBUGOUT3(S, A, B, C) 73 #define DEBUGFUNC(F) 74 #endif 75 76 #define OS_DEP(hw) ((struct e1000g_osdep *)((hw)->back)) 77 78 #define FALSE 0 79 #define TRUE 1 80 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 81 #define PCI_COMMAND_REGISTER 0x04 82 #define PCI_EX_CONF_CAP 0xE0 83 #define ICH_FLASH_REG_SET 2 /* solaris mapping of flash memory */ 84 85 #define RECEIVE_BUFFER_ALIGN_SIZE 256 86 #define E1000_MDALIGN 4096 87 #define E1000_ERT_2048 0x100 88 89 #define E1000_DEV_ID_ICH10D_BM_LM 0x10DE 90 91 /* PHY Extended Status Register */ 92 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 93 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 94 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 95 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 96 97 /* 98 * required by shared code 99 */ 100 #define E1000_WRITE_FLUSH(a) (void)E1000_READ_REG(a, E1000_STATUS) 101 102 #define E1000_WRITE_REG(hw, reg, value) \ 103 {\ 104 if ((hw)->mac.type != e1000_82542) \ 105 ddi_put32((OS_DEP(hw))->reg_handle, \ 106 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg), \ 107 value); \ 108 else \ 109 ddi_put32((OS_DEP(hw))->reg_handle, \ 110 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 111 e1000_translate_register_82542(reg)), \ 112 value); \ 113 } 114 115 #define E1000_READ_REG(hw, reg) (\ 116 ((hw)->mac.type != e1000_82542) ? \ 117 ddi_get32((OS_DEP(hw))->reg_handle, \ 118 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg)) : \ 119 ddi_get32((OS_DEP(hw))->reg_handle, \ 120 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 121 e1000_translate_register_82542(reg)))) 122 123 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ 124 {\ 125 if ((hw)->mac.type != e1000_82542) \ 126 ddi_put32((OS_DEP(hw))->reg_handle, \ 127 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 128 reg + ((offset) << 2)),\ 129 value); \ 130 else \ 131 ddi_put32((OS_DEP(hw))->reg_handle, \ 132 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 133 e1000_translate_register_82542(reg) + \ 134 ((offset) << 2)), value); \ 135 } 136 137 #define E1000_READ_REG_ARRAY(hw, reg, offset) (\ 138 ((hw)->mac.type != e1000_82542) ? \ 139 ddi_get32((OS_DEP(hw))->reg_handle, \ 140 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + \ 141 ((offset) << 2))) : \ 142 ddi_get32((OS_DEP(hw))->reg_handle, \ 143 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 144 e1000_translate_register_82542(reg) + \ 145 ((offset) << 2)))) 146 147 148 #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) \ 149 E1000_WRITE_REG_ARRAY(a, reg, offset, value) 150 #define E1000_READ_REG_ARRAY_DWORD(a, reg, offset) \ 151 E1000_READ_REG_ARRAY(a, reg, offset) 152 153 154 #define E1000_READ_FLASH_REG(hw, reg) \ 155 ddi_get32((OS_DEP(hw))->ich_flash_handle, \ 156 (uint32_t *)((uintptr_t)(hw)->flash_address + (reg))) 157 158 #define E1000_READ_FLASH_REG16(hw, reg) \ 159 ddi_get16((OS_DEP(hw))->ich_flash_handle, \ 160 (uint16_t *)((uintptr_t)(hw)->flash_address + (reg))) 161 162 #define E1000_WRITE_FLASH_REG(hw, reg, value) \ 163 ddi_put32((OS_DEP(hw))->ich_flash_handle, \ 164 (uint32_t *)((uintptr_t)(hw)->flash_address + (reg)), (value)) 165 166 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \ 167 ddi_put16((OS_DEP(hw))->ich_flash_handle, \ 168 (uint16_t *)((uintptr_t)(hw)->flash_address + (reg)), (value)) 169 170 /* 171 * === END CONTENT FORMERLY IN FXHW.H === 172 */ 173 174 #define msec_delay_irq msec_delay 175 176 #define UNREFERENCED_1PARAMETER(_p) _NOTE(ARGUNUSED(_p)) 177 #define UNREFERENCED_2PARAMETER(_p, _q) _NOTE(ARGUNUSED(_p, _q)) 178 #define UNREFERENCED_3PARAMETER(_p, _q, _r) _NOTE(ARGUNUSED(_p, _q, _r)) 179 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) _NOTE(ARGUNUSED(_p, _q, _r, _s)) 180 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) \ 181 _NOTE(ARGUNUSED(_p, _q, _r, _s, _t)) 182 183 typedef int8_t s8; 184 typedef int16_t s16; 185 typedef int32_t s32; 186 typedef int64_t s64; 187 typedef uint8_t u8; 188 typedef uint16_t u16; 189 typedef uint32_t u32; 190 typedef uint64_t u64; 191 192 typedef uint8_t UCHAR; /* 8-bit unsigned */ 193 typedef UCHAR UINT8; /* 8-bit unsigned */ 194 typedef uint16_t USHORT; /* 16-bit unsigned */ 195 typedef uint16_t UINT16; /* 16-bit unsigned */ 196 typedef uint32_t ULONG; /* 32-bit unsigned */ 197 typedef uint32_t UINT32; 198 typedef uint32_t UINT; /* 32-bit unsigned */ 199 typedef UCHAR BOOLEAN; 200 typedef BOOLEAN bool; 201 typedef UCHAR *PUCHAR; 202 typedef UINT *PUINT; 203 typedef ULONG *PLONG; 204 typedef ULONG NDIS_STATUS; 205 typedef USHORT *PUSHORT; 206 typedef PUSHORT PUINT16; /* 16-bit unsigned pointer */ 207 typedef ULONG E1000_32_BIT_PHYSICAL_ADDRESS, 208 *PFX_32_BIT_PHYSICAL_ADDRESS; 209 typedef uint64_t E1000_64_BIT_PHYSICAL_ADDRESS, 210 *PFX_64_BIT_PHYSICAL_ADDRESS; 211 212 struct e1000g_osdep { 213 ddi_acc_handle_t reg_handle; 214 ddi_acc_handle_t cfg_handle; 215 ddi_acc_handle_t ich_flash_handle; 216 struct e1000g *adapter; 217 }; 218 219 #ifdef __sparc /* on SPARC, use only memory-mapped routines */ 220 #define E1000_WRITE_REG_IO E1000_WRITE_REG 221 #else /* on x86, use port io routines */ 222 #define E1000_WRITE_REG_IO(a, reg, val) { \ 223 outl(((a)->io_base), reg); \ 224 outl(((a)->io_base + 4), val); } 225 #endif /* __sparc */ 226 227 #ifdef __cplusplus 228 } 229 #endif 230 231 #endif /* _E1000_OSDEP_H */ 232