1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "bge_impl.h" 30 31 /* 32 * Bit test macros, returning boolean_t values 33 */ 34 #define BIS(w, b) (((w) & (b)) ? B_TRUE : B_FALSE) 35 #define BIC(w, b) (((w) & (b)) ? B_FALSE : B_TRUE) 36 #define UPORDOWN(x) ((x) ? "up" : "down") 37 38 /* 39 * ========== Copper (PHY) support ========== 40 */ 41 42 #define BGE_DBG BGE_DBG_PHY /* debug flag for this code */ 43 44 /* 45 * #defines: 46 * BGE_COPPER_WIRESPEED controls whether the Broadcom WireSpeed(tm) 47 * feature is enabled. We need to recheck whether this can be 48 * enabled; at one time it seemed to interact unpleasantly with the 49 * loopback modes. 50 * 51 * BGE_COPPER_IDLEOFF controls whether the (copper) PHY power is 52 * turned off when the PHY is idled i.e. during driver suspend(). 53 * For now this is disabled because the chip doesn't seem to 54 * resume cleanly if the PHY power is turned off. 55 */ 56 #define BGE_COPPER_WIRESPEED B_TRUE 57 #define BGE_COPPER_IDLEOFF B_FALSE 58 59 /* 60 * The arrays below can be indexed by the MODE bits from the Auxiliary 61 * Status register to determine the current speed/duplex settings. 62 */ 63 static const int16_t bge_copper_link_speed[] = { 64 0, /* MII_AUX_STATUS_MODE_NONE */ 65 10, /* MII_AUX_STATUS_MODE_10_H */ 66 10, /* MII_AUX_STATUS_MODE_10_F */ 67 100, /* MII_AUX_STATUS_MODE_100_H */ 68 0, /* MII_AUX_STATUS_MODE_100_4 */ 69 100, /* MII_AUX_STATUS_MODE_100_F */ 70 1000, /* MII_AUX_STATUS_MODE_1000_H */ 71 1000 /* MII_AUX_STATUS_MODE_1000_F */ 72 }; 73 74 static const int8_t bge_copper_link_duplex[] = { 75 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_NONE */ 76 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_10_H */ 77 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_10_F */ 78 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_100_H */ 79 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_100_4 */ 80 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_100_F */ 81 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_1000_H */ 82 LINK_DUPLEX_FULL /* MII_AUX_STATUS_MODE_1000_F */ 83 }; 84 85 static const char * const bge_copper_link_text[] = { 86 "down", /* MII_AUX_STATUS_MODE_NONE */ 87 "up 10Mbps Half-Duplex", /* MII_AUX_STATUS_MODE_10_H */ 88 "up 10Mbps Full-Duplex", /* MII_AUX_STATUS_MODE_10_F */ 89 "up 100Mbps Half-Duplex", /* MII_AUX_STATUS_MODE_100_H */ 90 "down", /* MII_AUX_STATUS_MODE_100_4 */ 91 "up 100Mbps Full-Duplex", /* MII_AUX_STATUS_MODE_100_F */ 92 "up 1000Mbps Half-Duplex", /* MII_AUX_STATUS_MODE_1000_H */ 93 "up 1000Mbps Full-Duplex" /* MII_AUX_STATUS_MODE_1000_F */ 94 }; 95 96 #if BGE_DEBUGGING 97 98 static void 99 bge_phydump(bge_t *bgep, uint16_t mii_status, uint16_t aux) 100 { 101 uint16_t regs[32]; 102 int i; 103 104 ASSERT(mutex_owned(bgep->genlock)); 105 106 for (i = 0; i < 32; ++i) 107 switch (i) { 108 default: 109 regs[i] = bge_mii_get16(bgep, i); 110 break; 111 112 case MII_STATUS: 113 regs[i] = mii_status; 114 break; 115 116 case MII_AUX_STATUS: 117 regs[i] = aux; 118 break; 119 120 case 0x0b: case 0x0c: case 0x0d: case 0x0e: 121 case 0x15: case 0x16: case 0x17: 122 case 0x1c: 123 case 0x1f: 124 /* reserved registers -- don't read these */ 125 regs[i] = 0; 126 break; 127 } 128 129 for (i = 0; i < 32; i += 8) 130 BGE_DEBUG(("bge_phydump: " 131 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 132 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 133 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 134 } 135 136 #endif /* BGE_DEBUGGING */ 137 138 /* 139 * Basic low-level function to probe for a PHY 140 * 141 * Returns TRUE if the PHY responds with valid data, FALSE otherwise 142 */ 143 static boolean_t 144 bge_phy_probe(bge_t *bgep) 145 { 146 uint16_t phy_status; 147 148 BGE_TRACE(("bge_phy_probe($%p)", (void *)bgep)); 149 150 ASSERT(mutex_owned(bgep->genlock)); 151 152 /* 153 * Read the MII_STATUS register twice, in 154 * order to clear any sticky bits (but they should 155 * have been cleared by the RESET, I think). 156 */ 157 phy_status = bge_mii_get16(bgep, MII_STATUS); 158 phy_status = bge_mii_get16(bgep, MII_STATUS); 159 BGE_DEBUG(("bge_phy_probe: status 0x%x", phy_status)); 160 161 /* 162 * Now check the value read; it should have at least one bit set 163 * (for the device capabilities) and at least one clear (one of 164 * the error bits). So if we see all 0s or all 1s, there's a 165 * problem. In particular, bge_mii_get16() returns all 1s if 166 * communications fails ... 167 */ 168 switch (phy_status) { 169 case 0x0000: 170 case 0xffff: 171 return (B_FALSE); 172 173 default : 174 return (B_TRUE); 175 } 176 } 177 178 /* 179 * Basic low-level function to reset the PHY. 180 * Doesn't incorporate any special-case workarounds. 181 * 182 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 183 */ 184 static boolean_t 185 bge_phy_reset(bge_t *bgep) 186 { 187 uint16_t control; 188 uint_t count; 189 190 BGE_TRACE(("bge_phy_reset($%p)", (void *)bgep)); 191 192 ASSERT(mutex_owned(bgep->genlock)); 193 194 /* 195 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 196 */ 197 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_RESET); 198 for (count = 0; ++count < 1000; ) { 199 drv_usecwait(5); 200 control = bge_mii_get16(bgep, MII_CONTROL); 201 if (BIC(control, MII_CONTROL_RESET)) 202 return (B_TRUE); 203 } 204 205 BGE_DEBUG(("bge_phy_reset: FAILED, control now 0x%x", control)); 206 207 return (B_FALSE); 208 } 209 210 /* 211 * Basic low-level function to powerdown the PHY, if supported 212 * If powerdown support is compiled out, this function does nothing. 213 */ 214 static void 215 bge_phy_powerdown(bge_t *bgep) 216 { 217 BGE_TRACE(("bge_phy_powerdown")); 218 #if BGE_COPPER_IDLEOFF 219 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_PWRDN); 220 #endif /* BGE_COPPER_IDLEOFF */ 221 } 222 223 /* 224 * The following functions are based on sample code provided by 225 * Broadcom (20-June-2003), and implement workarounds said to be 226 * required on the early revisions of the BCM5703/4C. 227 * 228 * The registers and values used are mostly UNDOCUMENTED, and 229 * therefore don't have symbolic names ;-( 230 * 231 * Many of the comments are straight out of the Broadcom code: 232 * even where the code has been restructured, the original 233 * comments have been preserved in order to explain what these 234 * undocumented registers & values are all about ... 235 */ 236 237 static void 238 bge_phy_macro_wait(bge_t *bgep) 239 { 240 uint_t count; 241 242 for (count = 100; --count; ) 243 if ((bge_mii_get16(bgep, 0x16) & 0x1000) == 0) 244 break; 245 } 246 247 /* 248 * PHY test data pattern: 249 * 250 * For 5703/04, each DFE TAP has 21-bits (low word 15, hi word 6) 251 * For 5705, each DFE TAP has 19-bits (low word 15, hi word 4) 252 * For simplicity, we check only 19-bits, so we don't have to 253 * distinguish which chip it is. 254 * the LO word contains 15 bits, make sure pattern data is < 0x7fff 255 * the HI word contains 6 bits, make sure pattern data is < 0x003f 256 */ 257 #define N_CHANNELS 4 258 #define N_TAPS 3 259 260 static struct { 261 uint16_t lo; 262 uint16_t hi; 263 } tap_data[N_CHANNELS][N_TAPS] = { 264 { 265 { 0x5555, 0x0005 }, /* ch0, TAP 0, LO/HI pattern */ 266 { 0x2aaa, 0x000a }, /* ch0, TAP 1, LO/HI pattern */ 267 { 0x3456, 0x0003 } /* ch0, TAP 2, LO/HI pattern */ 268 }, 269 { 270 { 0x2aaa, 0x000a }, /* ch1, TAP 0, LO/HI pattern */ 271 { 0x3333, 0x0003 }, /* ch1, TAP 1, LO/HI pattern */ 272 { 0x789a, 0x0005 } /* ch1, TAP 2, LO/HI pattern */ 273 }, 274 { 275 { 0x5a5a, 0x0005 }, /* ch2, TAP 0, LO/HI pattern */ 276 { 0x2a6a, 0x000a }, /* ch2, TAP 1, LO/HI pattern */ 277 { 0x1bcd, 0x0003 } /* ch2, TAP 2, LO/HI pattern */ 278 }, 279 { 280 { 0x2a5a, 0x000a }, /* ch3, TAP 0, LO/HI pattern */ 281 { 0x33c3, 0x0003 }, /* ch3, TAP 1, LO/HI pattern */ 282 { 0x2ef1, 0x0005 } /* ch3, TAP 2, LO/HI pattern */ 283 } 284 }; 285 286 /* 287 * Check whether the PHY has locked up after a RESET. 288 * 289 * Returns TRUE if it did, FALSE is it's OK ;-) 290 */ 291 static boolean_t 292 bge_phy_locked_up(bge_t *bgep) 293 { 294 uint16_t dataLo; 295 uint16_t dataHi; 296 uint_t chan; 297 uint_t tap; 298 299 /* 300 * Check TAPs for all 4 channels, as soon as we see a lockup 301 * we'll stop checking. 302 */ 303 for (chan = 0; chan < N_CHANNELS; ++chan) { 304 /* Select channel and set TAP index to 0 */ 305 bge_mii_put16(bgep, 0x17, (chan << 13) | 0x0200); 306 /* Freeze filter again just to be safe */ 307 bge_mii_put16(bgep, 0x16, 0x0002); 308 309 /* 310 * Write fixed pattern to the RAM, 3 TAPs for 311 * each channel, each TAP have 2 WORDs (LO/HI) 312 */ 313 for (tap = 0; tap < N_TAPS; ++tap) { 314 bge_mii_put16(bgep, 0x15, tap_data[chan][tap].lo); 315 bge_mii_put16(bgep, 0x15, tap_data[chan][tap].hi); 316 } 317 318 /* 319 * Active PHY's Macro operation to write DFE 320 * TAP from RAM, and wait for Macro to complete. 321 */ 322 bge_mii_put16(bgep, 0x16, 0x0202); 323 bge_phy_macro_wait(bgep); 324 325 /* 326 * Done with write phase, now begin read phase. 327 */ 328 329 /* Select channel and set TAP index to 0 */ 330 bge_mii_put16(bgep, 0x17, (chan << 13) | 0x0200); 331 332 /* 333 * Active PHY's Macro operation to load DFE 334 * TAP to RAM, and wait for Macro to complete 335 */ 336 bge_mii_put16(bgep, 0x16, 0x0082); 337 bge_phy_macro_wait(bgep); 338 339 /* Enable "pre-fetch" */ 340 bge_mii_put16(bgep, 0x16, 0x0802); 341 bge_phy_macro_wait(bgep); 342 343 /* 344 * Read back the TAP values. 3 TAPs for each 345 * channel, each TAP have 2 WORDs (LO/HI) 346 */ 347 for (tap = 0; tap < N_TAPS; ++tap) { 348 /* 349 * Read Lo/Hi then wait for 'done' is faster. 350 * For DFE TAP, the HI word contains 6 bits, 351 * LO word contains 15 bits 352 */ 353 dataLo = bge_mii_get16(bgep, 0x15) & 0x7fff; 354 dataHi = bge_mii_get16(bgep, 0x15) & 0x003f; 355 bge_phy_macro_wait(bgep); 356 357 /* 358 * Check if what we wrote is what we read back. 359 * If failed, then the PHY is locked up, we need 360 * to do PHY reset again 361 */ 362 if (dataLo != tap_data[chan][tap].lo) 363 return (B_TRUE); /* wedged! */ 364 365 if (dataHi != tap_data[chan][tap].hi) 366 return (B_TRUE); /* wedged! */ 367 } 368 } 369 370 /* 371 * The PHY isn't locked up ;-) 372 */ 373 return (B_FALSE); 374 } 375 376 /* 377 * Special-case code to reset the PHY on the 5702/5703/5704C/5705/5782. 378 * Tries up to 5 times to recover from failure to reset or PHY lockup. 379 * 380 * Returns TRUE on success, FALSE if there's an unrecoverable problem 381 */ 382 static boolean_t 383 bge_phy_reset_and_check(bge_t *bgep) 384 { 385 boolean_t reset_success; 386 boolean_t phy_locked; 387 uint16_t extctrl; 388 uint_t retries; 389 390 for (retries = 0; retries < 5; ++retries) { 391 /* Issue a phy reset, and wait for reset to complete */ 392 /* Assuming reset is successful first */ 393 reset_success = bge_phy_reset(bgep); 394 395 /* 396 * Now go check the DFE TAPs to see if locked up, but 397 * first, we need to set up PHY so we can read DFE 398 * TAPs. 399 */ 400 401 /* 402 * Disable Transmitter and Interrupt, while we play 403 * with the PHY registers, so the link partner won't 404 * see any strange data and the Driver won't see any 405 * interrupts. 406 */ 407 extctrl = bge_mii_get16(bgep, 0x10); 408 bge_mii_put16(bgep, 0x10, extctrl | 0x3000); 409 410 /* Setup Full-Duplex, 1000 mbps */ 411 bge_mii_put16(bgep, 0x0, 0x0140); 412 413 /* Set to Master mode */ 414 bge_mii_put16(bgep, 0x9, 0x1800); 415 416 /* Enable SM_DSP_CLOCK & 6dB */ 417 bge_mii_put16(bgep, 0x18, 0x0c00); /* "the ADC fix" */ 418 419 /* Work-arounds */ 420 bge_mii_put16(bgep, 0x17, 0x201f); 421 bge_mii_put16(bgep, 0x15, 0x2aaa); 422 423 /* More workarounds */ 424 bge_mii_put16(bgep, 0x17, 0x000a); 425 bge_mii_put16(bgep, 0x15, 0x0323); /* "the Gamma fix" */ 426 427 /* Blocks the PHY control access */ 428 bge_mii_put16(bgep, 0x17, 0x8005); 429 bge_mii_put16(bgep, 0x15, 0x0800); 430 431 /* Test whether PHY locked up ;-( */ 432 phy_locked = bge_phy_locked_up(bgep); 433 if (reset_success && !phy_locked) 434 break; 435 436 /* 437 * Some problem here ... log it & retry 438 */ 439 if (!reset_success) 440 BGE_REPORT((bgep, "PHY didn't reset!")); 441 if (phy_locked) 442 BGE_REPORT((bgep, "PHY locked up!")); 443 } 444 445 /* Remove block phy control */ 446 bge_mii_put16(bgep, 0x17, 0x8005); 447 bge_mii_put16(bgep, 0x15, 0x0000); 448 449 /* Unfreeze DFE TAP filter for all channels */ 450 bge_mii_put16(bgep, 0x17, 0x8200); 451 bge_mii_put16(bgep, 0x16, 0x0000); 452 453 /* Restore PHY back to operating state */ 454 bge_mii_put16(bgep, 0x18, 0x0400); 455 456 /* Enable transmitter and interrupt */ 457 extctrl = bge_mii_get16(bgep, 0x10); 458 bge_mii_put16(bgep, 0x10, extctrl & ~0x3000); 459 460 if (!reset_success) 461 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 462 else if (phy_locked) 463 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 464 return (reset_success && !phy_locked); 465 } 466 467 static void 468 bge_phy_tweak_gmii(bge_t *bgep) 469 { 470 /* Tweak GMII timing */ 471 bge_mii_put16(bgep, 0x1c, 0x8d68); 472 bge_mii_put16(bgep, 0x1c, 0x8d68); 473 } 474 475 /* Bit Error Rate reduction fix */ 476 static void 477 bge_phy_bit_err_fix(bge_t *bgep) 478 { 479 bge_mii_put16(bgep, 0x18, 0x0c00); 480 bge_mii_put16(bgep, 0x17, 0x000a); 481 bge_mii_put16(bgep, 0x15, 0x310b); 482 bge_mii_put16(bgep, 0x17, 0x201f); 483 bge_mii_put16(bgep, 0x15, 0x9506); 484 bge_mii_put16(bgep, 0x17, 0x401f); 485 bge_mii_put16(bgep, 0x15, 0x14e2); 486 bge_mii_put16(bgep, 0x18, 0x0400); 487 } 488 489 /* 490 * End of Broadcom-derived workaround code * 491 */ 492 493 static int 494 bge_restart_copper(bge_t *bgep, boolean_t powerdown) 495 { 496 uint16_t phy_status; 497 boolean_t reset_ok; 498 499 BGE_TRACE(("bge_restart_copper($%p, %d)", (void *)bgep, powerdown)); 500 501 ASSERT(mutex_owned(bgep->genlock)); 502 503 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 504 default: 505 /* 506 * Shouldn't happen; it means we don't recognise this chip. 507 * It's probably a new one, so we'll try our best anyway ... 508 */ 509 case MHCR_CHIP_ASIC_REV_5703: 510 case MHCR_CHIP_ASIC_REV_5704: 511 case MHCR_CHIP_ASIC_REV_5705: 512 case MHCR_CHIP_ASIC_REV_5721_5751: 513 case MHCR_CHIP_ASIC_REV_5752: 514 case MHCR_CHIP_ASIC_REV_5714: 515 case MHCR_CHIP_ASIC_REV_5715: 516 reset_ok = bge_phy_reset_and_check(bgep); 517 break; 518 519 case MHCR_CHIP_ASIC_REV_5700: 520 case MHCR_CHIP_ASIC_REV_5701: 521 /* 522 * Just a plain reset; the "check" code breaks these chips 523 */ 524 reset_ok = bge_phy_reset(bgep); 525 if (!reset_ok) 526 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 527 break; 528 } 529 if (!reset_ok) { 530 BGE_REPORT((bgep, "PHY failed to reset correctly")); 531 return (DDI_FAILURE); 532 } 533 534 /* 535 * Step 5: disable WOL (not required after RESET) 536 * 537 * Step 6: refer to errata 538 */ 539 switch (bgep->chipid.asic_rev) { 540 default: 541 break; 542 543 case MHCR_CHIP_REV_5704_A0: 544 bge_phy_tweak_gmii(bgep); 545 break; 546 } 547 548 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 549 case MHCR_CHIP_ASIC_REV_5705: 550 case MHCR_CHIP_ASIC_REV_5721_5751: 551 bge_phy_bit_err_fix(bgep); 552 break; 553 } 554 555 /* 556 * Step 7: read the MII_INTR_STATUS register twice, 557 * in order to clear any sticky bits (but they should 558 * have been cleared by the RESET, I think), and we're 559 * not using PHY interrupts anyway. 560 * 561 * Step 8: enable the PHY to interrupt on link status 562 * change (not required) 563 * 564 * Step 9: configure PHY LED Mode - not applicable? 565 * 566 * Step 10: read the MII_STATUS register twice, in 567 * order to clear any sticky bits (but they should 568 * have been cleared by the RESET, I think). 569 */ 570 phy_status = bge_mii_get16(bgep, MII_STATUS); 571 phy_status = bge_mii_get16(bgep, MII_STATUS); 572 BGE_DEBUG(("bge_restart_copper: status 0x%x", phy_status)); 573 574 /* 575 * Finally, shut down the PHY, if required 576 */ 577 if (powerdown) 578 bge_phy_powerdown(bgep); 579 return (DDI_SUCCESS); 580 } 581 582 /* 583 * Synchronise the (copper) PHY's speed/duplex/autonegotiation capabilities 584 * and advertisements with the required settings as specified by the various 585 * param_* variables that can be poked via the NDD interface. 586 * 587 * We always reset the PHY and reprogram *all* the relevant registers, 588 * not just those changed. This should cause the link to go down, and then 589 * back up again once the link is stable and autonegotiation (if enabled) 590 * is complete. We should get a link state change interrupt somewhere along 591 * the way ... 592 * 593 * NOTE: <genlock> must already be held by the caller 594 */ 595 static int 596 bge_update_copper(bge_t *bgep) 597 { 598 boolean_t adv_autoneg; 599 boolean_t adv_pause; 600 boolean_t adv_asym_pause; 601 boolean_t adv_1000fdx; 602 boolean_t adv_1000hdx; 603 boolean_t adv_100fdx; 604 boolean_t adv_100hdx; 605 boolean_t adv_10fdx; 606 boolean_t adv_10hdx; 607 608 uint16_t control; 609 uint16_t gigctrl; 610 uint16_t auxctrl; 611 uint16_t anar; 612 613 BGE_TRACE(("bge_update_copper($%p)", (void *)bgep)); 614 615 ASSERT(mutex_owned(bgep->genlock)); 616 617 BGE_DEBUG(("bge_update_copper: autoneg %d " 618 "pause %d asym_pause %d " 619 "1000fdx %d 1000hdx %d " 620 "100fdx %d 100hdx %d " 621 "10fdx %d 10hdx %d ", 622 bgep->param_adv_autoneg, 623 bgep->param_adv_pause, bgep->param_adv_asym_pause, 624 bgep->param_adv_1000fdx, bgep->param_adv_1000hdx, 625 bgep->param_adv_100fdx, bgep->param_adv_100hdx, 626 bgep->param_adv_10fdx, bgep->param_adv_10hdx)); 627 628 control = gigctrl = auxctrl = anar = 0; 629 630 /* 631 * PHY settings are normally based on the param_* variables, 632 * but if any loopback mode is in effect, that takes precedence. 633 * 634 * BGE supports MAC-internal loopback, PHY-internal loopback, 635 * and External loopback at a variety of speeds (with a special 636 * cable). In all cases, autoneg is turned OFF, full-duplex 637 * is turned ON, and the speed/mastership is forced. 638 */ 639 switch (bgep->param_loop_mode) { 640 case BGE_LOOP_NONE: 641 default: 642 adv_autoneg = bgep->param_adv_autoneg; 643 adv_pause = bgep->param_adv_pause; 644 adv_asym_pause = bgep->param_adv_asym_pause; 645 adv_1000fdx = bgep->param_adv_1000fdx; 646 adv_1000hdx = bgep->param_adv_1000hdx; 647 adv_100fdx = bgep->param_adv_100fdx; 648 adv_100hdx = bgep->param_adv_100hdx; 649 adv_10fdx = bgep->param_adv_10fdx; 650 adv_10hdx = bgep->param_adv_10hdx; 651 break; 652 653 case BGE_LOOP_EXTERNAL_1000: 654 case BGE_LOOP_EXTERNAL_100: 655 case BGE_LOOP_EXTERNAL_10: 656 case BGE_LOOP_INTERNAL_PHY: 657 case BGE_LOOP_INTERNAL_MAC: 658 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 659 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 660 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 661 bgep->param_link_duplex = LINK_DUPLEX_FULL; 662 663 switch (bgep->param_loop_mode) { 664 case BGE_LOOP_EXTERNAL_1000: 665 bgep->param_link_speed = 1000; 666 adv_1000fdx = B_TRUE; 667 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 668 gigctrl |= MII_1000BT_CTL_MASTER_CFG; 669 gigctrl |= MII_1000BT_CTL_MASTER_SEL; 670 break; 671 672 case BGE_LOOP_EXTERNAL_100: 673 bgep->param_link_speed = 100; 674 adv_100fdx = B_TRUE; 675 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 676 break; 677 678 case BGE_LOOP_EXTERNAL_10: 679 bgep->param_link_speed = 10; 680 adv_10fdx = B_TRUE; 681 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 682 break; 683 684 case BGE_LOOP_INTERNAL_PHY: 685 bgep->param_link_speed = 1000; 686 adv_1000fdx = B_TRUE; 687 control = MII_CONTROL_LOOPBACK; 688 break; 689 690 case BGE_LOOP_INTERNAL_MAC: 691 bgep->param_link_speed = 1000; 692 adv_1000fdx = B_TRUE; 693 break; 694 } 695 } 696 697 BGE_DEBUG(("bge_update_copper: autoneg %d " 698 "pause %d asym_pause %d " 699 "1000fdx %d 1000hdx %d " 700 "100fdx %d 100hdx %d " 701 "10fdx %d 10hdx %d ", 702 adv_autoneg, 703 adv_pause, adv_asym_pause, 704 adv_1000fdx, adv_1000hdx, 705 adv_100fdx, adv_100hdx, 706 adv_10fdx, adv_10hdx)); 707 708 /* 709 * We should have at least one technology capability set; 710 * if not, we select a default of 1000Mb/s full-duplex 711 */ 712 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 713 !adv_1000hdx && !adv_100hdx && !adv_10hdx) 714 adv_1000fdx = B_TRUE; 715 716 /* 717 * Now transform the adv_* variables into the proper settings 718 * of the PHY registers ... 719 * 720 * If autonegotiation is (now) enabled, we want to trigger 721 * a new autonegotiation cycle once the PHY has been 722 * programmed with the capabilities to be advertised. 723 */ 724 if (adv_autoneg) 725 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 726 727 if (adv_1000fdx) 728 control |= MII_CONTROL_1000MB|MII_CONTROL_FDUPLEX; 729 else if (adv_1000hdx) 730 control |= MII_CONTROL_1000MB; 731 else if (adv_100fdx) 732 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 733 else if (adv_100hdx) 734 control |= MII_CONTROL_100MB; 735 else if (adv_10fdx) 736 control |= MII_CONTROL_FDUPLEX; 737 else if (adv_10hdx) 738 control |= 0; 739 else 740 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 741 742 if (adv_1000fdx) 743 gigctrl |= MII_1000BT_CTL_ADV_FDX; 744 if (adv_1000hdx) 745 gigctrl |= MII_1000BT_CTL_ADV_HDX; 746 747 if (adv_100fdx) 748 anar |= MII_ABILITY_100BASE_TX_FD; 749 if (adv_100hdx) 750 anar |= MII_ABILITY_100BASE_TX; 751 if (adv_10fdx) 752 anar |= MII_ABILITY_10BASE_T_FD; 753 if (adv_10hdx) 754 anar |= MII_ABILITY_10BASE_T; 755 756 if (adv_pause) 757 anar |= MII_ABILITY_PAUSE; 758 if (adv_asym_pause) 759 anar |= MII_ABILITY_ASYM_PAUSE; 760 761 /* 762 * Munge in any other fixed bits we require ... 763 */ 764 anar |= MII_AN_SELECTOR_8023; 765 auxctrl |= MII_AUX_CTRL_NORM_TX_MODE; 766 auxctrl |= MII_AUX_CTRL_NORMAL; 767 768 /* 769 * Restart the PHY and write the new values. Note the 770 * time, so that we can say whether subsequent link state 771 * changes can be attributed to our reprogramming the PHY 772 */ 773 bgep->phys_write_time = gethrtime(); 774 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) == DDI_FAILURE) 775 return (DDI_FAILURE); 776 bge_mii_put16(bgep, MII_AN_ADVERT, anar); 777 bge_mii_put16(bgep, MII_CONTROL, control); 778 bge_mii_put16(bgep, MII_AUX_CONTROL, auxctrl); 779 bge_mii_put16(bgep, MII_1000BASE_T_CONTROL, gigctrl); 780 781 BGE_DEBUG(("bge_update_copper: anar <- 0x%x", anar)); 782 BGE_DEBUG(("bge_update_copper: control <- 0x%x", control)); 783 BGE_DEBUG(("bge_update_copper: auxctrl <- 0x%x", auxctrl)); 784 BGE_DEBUG(("bge_update_copper: gigctrl <- 0x%x", gigctrl)); 785 786 #if BGE_COPPER_WIRESPEED 787 /* 788 * Enable the 'wire-speed' feature, if the chip supports it 789 * and we haven't got (any) loopback mode selected. 790 */ 791 switch (bgep->chipid.device) { 792 case DEVICE_ID_5700: 793 case DEVICE_ID_5700x: 794 case DEVICE_ID_5705C: 795 case DEVICE_ID_5782: 796 /* 797 * These chips are known or assumed not to support it 798 */ 799 break; 800 801 default: 802 /* 803 * All other Broadcom chips are expected to support it. 804 */ 805 if (bgep->param_loop_mode == BGE_LOOP_NONE) 806 bge_mii_put16(bgep, MII_AUX_CONTROL, 807 MII_AUX_CTRL_MISC_WRITE_ENABLE | 808 MII_AUX_CTRL_MISC_WIRE_SPEED | 809 MII_AUX_CTRL_MISC); 810 break; 811 } 812 #endif /* BGE_COPPER_WIRESPEED */ 813 return (DDI_SUCCESS); 814 } 815 816 static boolean_t 817 bge_check_copper(bge_t *bgep, boolean_t recheck) 818 { 819 uint32_t emac_status; 820 uint16_t mii_status; 821 uint16_t aux; 822 uint_t mode; 823 boolean_t linkup; 824 825 /* 826 * Step 10: read the status from the PHY (which is self-clearing 827 * on read!); also read & clear the main (Ethernet) MAC status 828 * (the relevant bits of this are write-one-to-clear). 829 */ 830 mii_status = bge_mii_get16(bgep, MII_STATUS); 831 emac_status = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG); 832 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, emac_status); 833 834 BGE_DEBUG(("bge_check_copper: link %d/%s, MII status 0x%x " 835 "(was 0x%x), Ethernet MAC status 0x%x", 836 bgep->link_state, UPORDOWN(bgep->param_link_up), mii_status, 837 bgep->phy_gen_status, emac_status)); 838 839 /* 840 * If the PHY status hasn't changed since last we looked, and 841 * we not forcing a recheck (i.e. the link state was already 842 * known), there's nothing to do. 843 */ 844 if (mii_status == bgep->phy_gen_status && !recheck) 845 return (B_FALSE); 846 847 do { 848 /* 849 * If the PHY status changed, record the time 850 */ 851 if (mii_status != bgep->phy_gen_status) 852 bgep->phys_event_time = gethrtime(); 853 854 /* 855 * Step 11: read AUX STATUS register to find speed/duplex 856 */ 857 aux = bge_mii_get16(bgep, MII_AUX_STATUS); 858 BGE_CDB(bge_phydump, (bgep, mii_status, aux)); 859 860 /* 861 * We will only consider the link UP if all the readings 862 * are consistent and give meaningful results ... 863 */ 864 mode = aux & MII_AUX_STATUS_MODE_MASK; 865 mode >>= MII_AUX_STATUS_MODE_SHIFT; 866 linkup = bge_copper_link_speed[mode] > 0; 867 linkup &= bge_copper_link_duplex[mode] != LINK_DUPLEX_UNKNOWN; 868 linkup &= BIS(aux, MII_AUX_STATUS_LINKUP); 869 linkup &= BIS(mii_status, MII_STATUS_LINKUP); 870 871 BGE_DEBUG(("bge_check_copper: MII status 0x%x aux 0x%x " 872 "=> mode %d (%s)", 873 mii_status, aux, 874 mode, UPORDOWN(linkup))); 875 876 /* 877 * Record current register values, then reread status 878 * register & loop until it stabilises ... 879 */ 880 bgep->phy_aux_status = aux; 881 bgep->phy_gen_status = mii_status; 882 mii_status = bge_mii_get16(bgep, MII_STATUS); 883 } while (mii_status != bgep->phy_gen_status); 884 885 /* 886 * Assume very little ... 887 */ 888 bgep->param_lp_autoneg = B_FALSE; 889 bgep->param_lp_1000fdx = B_FALSE; 890 bgep->param_lp_1000hdx = B_FALSE; 891 bgep->param_lp_100fdx = B_FALSE; 892 bgep->param_lp_100hdx = B_FALSE; 893 bgep->param_lp_10fdx = B_FALSE; 894 bgep->param_lp_10hdx = B_FALSE; 895 bgep->param_lp_pause = B_FALSE; 896 bgep->param_lp_asym_pause = B_FALSE; 897 bgep->param_link_autoneg = B_FALSE; 898 bgep->param_link_tx_pause = B_FALSE; 899 if (bgep->param_adv_autoneg) 900 bgep->param_link_rx_pause = B_FALSE; 901 else 902 bgep->param_link_rx_pause = bgep->param_adv_pause; 903 904 /* 905 * Discover all the link partner's abilities. 906 * These are scattered through various registers ... 907 */ 908 if (BIS(aux, MII_AUX_STATUS_LP_ANEG_ABLE)) { 909 bgep->param_lp_autoneg = B_TRUE; 910 bgep->param_link_autoneg = B_TRUE; 911 bgep->param_link_tx_pause = BIS(aux, MII_AUX_STATUS_TX_PAUSE); 912 bgep->param_link_rx_pause = BIS(aux, MII_AUX_STATUS_RX_PAUSE); 913 914 aux = bge_mii_get16(bgep, MII_1000BASE_T_STATUS); 915 bgep->param_lp_1000fdx = BIS(aux, MII_1000BT_STAT_LP_FDX_CAP); 916 bgep->param_lp_1000hdx = BIS(aux, MII_1000BT_STAT_LP_HDX_CAP); 917 918 aux = bge_mii_get16(bgep, MII_AN_LPABLE); 919 bgep->param_lp_100fdx = BIS(aux, MII_ABILITY_100BASE_TX_FD); 920 bgep->param_lp_100hdx = BIS(aux, MII_ABILITY_100BASE_TX); 921 bgep->param_lp_10fdx = BIS(aux, MII_ABILITY_10BASE_T_FD); 922 bgep->param_lp_10hdx = BIS(aux, MII_ABILITY_10BASE_T); 923 bgep->param_lp_pause = BIS(aux, MII_ABILITY_PAUSE); 924 bgep->param_lp_asym_pause = BIS(aux, MII_ABILITY_ASYM_PAUSE); 925 } 926 927 /* 928 * Step 12: update ndd-visible state parameters, BUT! 929 * we don't transfer the new state to <link_state> just yet; 930 * instead we mark the <link_state> as UNKNOWN, and our caller 931 * will resolve it once the status has stopped changing and 932 * been stable for several seconds. 933 */ 934 BGE_DEBUG(("bge_check_copper: link was %s speed %d duplex %d", 935 UPORDOWN(bgep->param_link_up), 936 bgep->param_link_speed, 937 bgep->param_link_duplex)); 938 939 if (!linkup) 940 mode = MII_AUX_STATUS_MODE_NONE; 941 bgep->param_link_up = linkup; 942 bgep->param_link_speed = bge_copper_link_speed[mode]; 943 bgep->param_link_duplex = bge_copper_link_duplex[mode]; 944 bgep->link_mode_msg = bge_copper_link_text[mode]; 945 bgep->link_state = LINK_STATE_UNKNOWN; 946 947 BGE_DEBUG(("bge_check_copper: link now %s speed %d duplex %d", 948 UPORDOWN(bgep->param_link_up), 949 bgep->param_link_speed, 950 bgep->param_link_duplex)); 951 952 return (B_TRUE); 953 } 954 955 static const phys_ops_t copper_ops = { 956 bge_restart_copper, 957 bge_update_copper, 958 bge_check_copper 959 }; 960 961 962 /* 963 * ========== SerDes support ========== 964 */ 965 966 #undef BGE_DBG 967 #define BGE_DBG BGE_DBG_SERDES /* debug flag for this code */ 968 969 /* 970 * Reinitialise the SerDes interface. Note that it normally powers 971 * up in the disabled state, so we need to explicitly activate it. 972 */ 973 static int 974 bge_restart_serdes(bge_t *bgep, boolean_t powerdown) 975 { 976 uint32_t macmode; 977 978 BGE_TRACE(("bge_restart_serdes($%p, %d)", (void *)bgep, powerdown)); 979 980 ASSERT(mutex_owned(bgep->genlock)); 981 982 /* 983 * Ensure that the main Ethernet MAC mode register is programmed 984 * appropriately for the SerDes interface ... 985 */ 986 macmode = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 987 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 988 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 989 macmode |= ETHERNET_MODE_PORTMODE_TBI; 990 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 991 992 /* 993 * Ensure that loopback is OFF and comma detection is enabled. Then 994 * disable the SerDes output (the first time through, it may/will 995 * already be disabled). If we're shutting down, leave it disabled. 996 */ 997 bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TBI_LOOPBACK); 998 bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_COMMA_DETECT); 999 bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE); 1000 if (powerdown) 1001 return (DDI_SUCCESS); 1002 1003 /* 1004 * Otherwise, pause, (re-)enable the SerDes output, and send 1005 * all-zero config words in order to force autoneg restart. 1006 * Invalidate the saved "link partners received configs", as 1007 * we're starting over ... 1008 */ 1009 drv_usecwait(10000); 1010 bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE); 1011 bge_reg_put32(bgep, TX_1000BASEX_AUTONEG_REG, 0); 1012 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS); 1013 drv_usecwait(10); 1014 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS); 1015 bgep->serdes_lpadv = AUTONEG_CODE_FAULT_ANEG_ERR; 1016 bgep->serdes_status = ~0U; 1017 return (DDI_SUCCESS); 1018 } 1019 1020 /* 1021 * Synchronise the SerDes speed/duplex/autonegotiation capabilities and 1022 * advertisements with the required settings as specified by the various 1023 * param_* variables that can be poked via the NDD interface. 1024 * 1025 * We always reinitalise the SerDes; this should cause the link to go down, 1026 * and then back up again once the link is stable and autonegotiation 1027 * (if enabled) is complete. We should get a link state change interrupt 1028 * somewhere along the way ... 1029 * 1030 * NOTE: SerDes only supports 1000FDX/HDX (with or without pause) so the 1031 * param_* variables relating to lower speeds are ignored. 1032 * 1033 * NOTE: <genlock> must already be held by the caller 1034 */ 1035 static int 1036 bge_update_serdes(bge_t *bgep) 1037 { 1038 boolean_t adv_autoneg; 1039 boolean_t adv_pause; 1040 boolean_t adv_asym_pause; 1041 boolean_t adv_1000fdx; 1042 boolean_t adv_1000hdx; 1043 1044 uint32_t serdes; 1045 uint32_t advert; 1046 1047 BGE_TRACE(("bge_update_serdes($%p)", (void *)bgep)); 1048 1049 ASSERT(mutex_owned(bgep->genlock)); 1050 1051 BGE_DEBUG(("bge_update_serdes: autoneg %d " 1052 "pause %d asym_pause %d " 1053 "1000fdx %d 1000hdx %d " 1054 "100fdx %d 100hdx %d " 1055 "10fdx %d 10hdx %d ", 1056 bgep->param_adv_autoneg, 1057 bgep->param_adv_pause, bgep->param_adv_asym_pause, 1058 bgep->param_adv_1000fdx, bgep->param_adv_1000hdx, 1059 bgep->param_adv_100fdx, bgep->param_adv_100hdx, 1060 bgep->param_adv_10fdx, bgep->param_adv_10hdx)); 1061 1062 serdes = advert = 0; 1063 1064 /* 1065 * SerDes settings are normally based on the param_* variables, 1066 * but if any loopback mode is in effect, that takes precedence. 1067 * 1068 * BGE supports MAC-internal loopback, PHY-internal loopback, 1069 * and External loopback at a variety of speeds (with a special 1070 * cable). In all cases, autoneg is turned OFF, full-duplex 1071 * is turned ON, and the speed/mastership is forced. 1072 * 1073 * Note: for the SerDes interface, "PHY" internal loopback is 1074 * interpreted as SerDes internal loopback, and all external 1075 * loopback modes are treated equivalently, as 1Gb/external. 1076 */ 1077 switch (bgep->param_loop_mode) { 1078 case BGE_LOOP_NONE: 1079 default: 1080 adv_autoneg = bgep->param_adv_autoneg; 1081 adv_pause = bgep->param_adv_pause; 1082 adv_asym_pause = bgep->param_adv_asym_pause; 1083 adv_1000fdx = bgep->param_adv_1000fdx; 1084 adv_1000hdx = bgep->param_adv_1000hdx; 1085 break; 1086 1087 case BGE_LOOP_INTERNAL_PHY: 1088 serdes |= SERDES_CONTROL_TBI_LOOPBACK; 1089 /* FALLTHRU */ 1090 case BGE_LOOP_INTERNAL_MAC: 1091 case BGE_LOOP_EXTERNAL_1000: 1092 case BGE_LOOP_EXTERNAL_100: 1093 case BGE_LOOP_EXTERNAL_10: 1094 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 1095 adv_1000fdx = B_TRUE; 1096 adv_1000hdx = B_FALSE; 1097 break; 1098 } 1099 1100 BGE_DEBUG(("bge_update_serdes: autoneg %d " 1101 "pause %d asym_pause %d " 1102 "1000fdx %d 1000hdx %d ", 1103 adv_autoneg, 1104 adv_pause, adv_asym_pause, 1105 adv_1000fdx, adv_1000hdx)); 1106 1107 /* 1108 * We should have at least one gigabit technology capability 1109 * set; if not, we select a default of 1000Mb/s full-duplex 1110 */ 1111 if (!adv_1000fdx && !adv_1000hdx) 1112 adv_1000fdx = B_TRUE; 1113 1114 /* 1115 * Now transform the adv_* variables into the proper settings 1116 * of the SerDes registers ... 1117 * 1118 * If autonegotiation is (now) not enabled, pretend it's been 1119 * done and failed ... 1120 */ 1121 if (!adv_autoneg) 1122 advert |= AUTONEG_CODE_FAULT_ANEG_ERR; 1123 1124 if (adv_1000fdx) { 1125 advert |= AUTONEG_CODE_FULL_DUPLEX; 1126 bgep->param_adv_1000fdx = adv_1000fdx; 1127 bgep->param_link_duplex = LINK_DUPLEX_FULL; 1128 bgep->param_link_speed = 1000; 1129 } 1130 if (adv_1000hdx) { 1131 advert |= AUTONEG_CODE_HALF_DUPLEX; 1132 bgep->param_adv_1000hdx = adv_1000hdx; 1133 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1134 bgep->param_link_speed = 1000; 1135 } 1136 1137 if (adv_pause) 1138 advert |= AUTONEG_CODE_PAUSE; 1139 if (adv_asym_pause) 1140 advert |= AUTONEG_CODE_ASYM_PAUSE; 1141 1142 /* 1143 * Restart the SerDes and write the new values. Note the 1144 * time, so that we can say whether subsequent link state 1145 * changes can be attributed to our reprogramming the SerDes 1146 */ 1147 bgep->serdes_advert = advert; 1148 bgep->phys_write_time = gethrtime(); 1149 (void) bge_restart_serdes(bgep, B_FALSE); 1150 bge_reg_set32(bgep, SERDES_CONTROL_REG, serdes); 1151 1152 BGE_DEBUG(("bge_update_serdes: serdes |= 0x%x, advert 0x%x", 1153 serdes, advert)); 1154 return (DDI_SUCCESS); 1155 } 1156 1157 /* 1158 * Bare-minimum autoneg protocol 1159 * 1160 * This code is only called when the link is up and we're receiving config 1161 * words, which implies that the link partner wants to autonegotiate 1162 * (otherwise, we wouldn't see configs and wouldn't reach this code). 1163 */ 1164 static void 1165 bge_autoneg_serdes(bge_t *bgep) 1166 { 1167 boolean_t ack; 1168 1169 bgep->serdes_lpadv = bge_reg_get32(bgep, RX_1000BASEX_AUTONEG_REG); 1170 ack = BIS(bgep->serdes_lpadv, AUTONEG_CODE_ACKNOWLEDGE); 1171 1172 if (!ack) { 1173 /* 1174 * Phase 1: after SerDes reset, we send a few zero configs 1175 * but then stop. Here the partner is sending configs, but 1176 * not ACKing ours; we assume that's 'cos we're not sending 1177 * any. So here we send ours, with ACK already set. 1178 */ 1179 bge_reg_put32(bgep, TX_1000BASEX_AUTONEG_REG, 1180 bgep->serdes_advert | AUTONEG_CODE_ACKNOWLEDGE); 1181 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 1182 ETHERNET_MODE_SEND_CFGS); 1183 } else { 1184 /* 1185 * Phase 2: partner has ACKed our configs, so now we can 1186 * stop sending; once our partner also stops sending, we 1187 * can resolve the Tx/Rx configs. 1188 */ 1189 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, 1190 ETHERNET_MODE_SEND_CFGS); 1191 } 1192 1193 BGE_DEBUG(("bge_autoneg_serdes: Rx 0x%x %s Tx 0x%x", 1194 bgep->serdes_lpadv, 1195 ack ? "stop" : "send", 1196 bgep->serdes_advert)); 1197 } 1198 1199 static boolean_t 1200 bge_check_serdes(bge_t *bgep, boolean_t recheck) 1201 { 1202 uint32_t emac_status; 1203 uint32_t lpadv; 1204 boolean_t linkup; 1205 1206 for (;;) { 1207 /* 1208 * Step 10: read & clear the main (Ethernet) MAC status 1209 * (the relevant bits of this are write-one-to-clear). 1210 */ 1211 emac_status = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG); 1212 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, emac_status); 1213 1214 BGE_DEBUG(("bge_check_serdes: link %d/%s, " 1215 "MAC status 0x%x (was 0x%x)", 1216 bgep->link_state, UPORDOWN(bgep->param_link_up), 1217 emac_status, bgep->serdes_status)); 1218 1219 /* 1220 * We will only consider the link UP if all the readings 1221 * are consistent and give meaningful results ... 1222 */ 1223 bgep->serdes_status = emac_status; 1224 linkup = BIS(emac_status, ETHERNET_STATUS_SIGNAL_DETECT); 1225 linkup &= BIS(emac_status, ETHERNET_STATUS_PCS_SYNCHED); 1226 1227 /* 1228 * Now some fiddling with the interpretation: 1229 * if there's been an error at the PCS level, treat 1230 * it as a link change (the h/w doesn't do this) 1231 * 1232 * if there's been a change, but it's only a PCS sync 1233 * change (not a config change), AND the link already 1234 * was & is still UP, then ignore the change 1235 */ 1236 if (BIS(emac_status, ETHERNET_STATUS_PCS_ERROR)) 1237 emac_status |= ETHERNET_STATUS_LINK_CHANGED; 1238 else if (BIC(emac_status, ETHERNET_STATUS_CFG_CHANGED)) 1239 if (bgep->param_link_up && linkup) 1240 emac_status &= ~ETHERNET_STATUS_LINK_CHANGED; 1241 1242 BGE_DEBUG(("bge_check_serdes: status 0x%x => 0x%x %s", 1243 bgep->serdes_status, emac_status, UPORDOWN(linkup))); 1244 1245 /* 1246 * If we're receiving configs, run the autoneg protocol 1247 */ 1248 if (linkup && BIS(emac_status, ETHERNET_STATUS_RECEIVING_CFG)) 1249 bge_autoneg_serdes(bgep); 1250 1251 /* 1252 * If the SerDes status hasn't changed, we're done ... 1253 */ 1254 if (BIC(emac_status, ETHERNET_STATUS_LINK_CHANGED)) 1255 break; 1256 1257 /* 1258 * Record when the SerDes status changed, then go 1259 * round again until we no longer see a change ... 1260 */ 1261 bgep->phys_event_time = gethrtime(); 1262 recheck = B_TRUE; 1263 } 1264 1265 /* 1266 * If we're not forcing a recheck (i.e. the link state was already 1267 * known), and we didn't see the hardware flag a change, there's 1268 * no more to do (and we tell the caller nothing happened). 1269 */ 1270 if (!recheck) 1271 return (B_FALSE); 1272 1273 /* 1274 * Don't resolve autoneg until we're no longer receiving configs 1275 */ 1276 if (linkup && BIS(emac_status, ETHERNET_STATUS_RECEIVING_CFG)) 1277 return (B_FALSE); 1278 1279 /* 1280 * Assume very little ... 1281 */ 1282 bgep->param_lp_autoneg = B_FALSE; 1283 bgep->param_lp_1000fdx = B_FALSE; 1284 bgep->param_lp_1000hdx = B_FALSE; 1285 bgep->param_lp_100fdx = B_FALSE; 1286 bgep->param_lp_100hdx = B_FALSE; 1287 bgep->param_lp_10fdx = B_FALSE; 1288 bgep->param_lp_10hdx = B_FALSE; 1289 bgep->param_lp_pause = B_FALSE; 1290 bgep->param_lp_asym_pause = B_FALSE; 1291 bgep->param_link_autoneg = B_FALSE; 1292 bgep->param_link_tx_pause = B_FALSE; 1293 if (bgep->param_adv_autoneg) 1294 bgep->param_link_rx_pause = B_FALSE; 1295 else 1296 bgep->param_link_rx_pause = bgep->param_adv_pause; 1297 1298 /* 1299 * Discover all the link partner's abilities. 1300 */ 1301 lpadv = bgep->serdes_lpadv; 1302 if (lpadv != 0 && BIC(lpadv, AUTONEG_CODE_FAULT_MASK)) { 1303 /* 1304 * No fault, so derive partner's capabilities 1305 */ 1306 bgep->param_lp_autoneg = B_TRUE; 1307 bgep->param_lp_1000fdx = BIS(lpadv, AUTONEG_CODE_FULL_DUPLEX); 1308 bgep->param_lp_1000hdx = BIS(lpadv, AUTONEG_CODE_HALF_DUPLEX); 1309 bgep->param_lp_pause = BIS(lpadv, AUTONEG_CODE_PAUSE); 1310 bgep->param_lp_asym_pause = BIS(lpadv, AUTONEG_CODE_ASYM_PAUSE); 1311 1312 /* 1313 * Pause direction resolution 1314 */ 1315 bgep->param_link_autoneg = B_TRUE; 1316 if (bgep->param_adv_pause && 1317 bgep->param_lp_pause) { 1318 bgep->param_link_tx_pause = B_TRUE; 1319 bgep->param_link_rx_pause = B_TRUE; 1320 } 1321 if (bgep->param_adv_asym_pause && 1322 bgep->param_lp_asym_pause) { 1323 if (bgep->param_adv_pause) 1324 bgep->param_link_rx_pause = B_TRUE; 1325 if (bgep->param_lp_pause) 1326 bgep->param_link_tx_pause = B_TRUE; 1327 } 1328 } 1329 1330 /* 1331 * Step 12: update ndd-visible state parameters, BUT! 1332 * we don't transfer the new state to <link_state> just yet; 1333 * instead we mark the <link_state> as UNKNOWN, and our caller 1334 * will resolve it once the status has stopped changing and 1335 * been stable for several seconds. 1336 */ 1337 BGE_DEBUG(("bge_check_serdes: link was %s speed %d duplex %d", 1338 UPORDOWN(bgep->param_link_up), 1339 bgep->param_link_speed, 1340 bgep->param_link_duplex)); 1341 1342 if (linkup) { 1343 bgep->param_link_up = B_TRUE; 1344 bgep->param_link_speed = 1000; 1345 if (bgep->param_adv_1000fdx) 1346 bgep->param_link_duplex = LINK_DUPLEX_FULL; 1347 else 1348 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1349 if (bgep->param_lp_autoneg && !bgep->param_lp_1000fdx) 1350 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1351 } else { 1352 bgep->param_link_up = B_FALSE; 1353 bgep->param_link_speed = 0; 1354 bgep->param_link_duplex = LINK_DUPLEX_UNKNOWN; 1355 } 1356 switch (bgep->param_link_duplex) { 1357 default: 1358 case LINK_DUPLEX_UNKNOWN: 1359 bgep->link_mode_msg = "down"; 1360 break; 1361 1362 case LINK_DUPLEX_HALF: 1363 bgep->link_mode_msg = "up 1000Mbps Half-Duplex"; 1364 break; 1365 1366 case LINK_DUPLEX_FULL: 1367 bgep->link_mode_msg = "up 1000Mbps Full-Duplex"; 1368 break; 1369 } 1370 bgep->link_state = LINK_STATE_UNKNOWN; 1371 1372 BGE_DEBUG(("bge_check_serdes: link now %s speed %d duplex %d", 1373 UPORDOWN(bgep->param_link_up), 1374 bgep->param_link_speed, 1375 bgep->param_link_duplex)); 1376 1377 return (B_TRUE); 1378 } 1379 1380 static const phys_ops_t serdes_ops = { 1381 bge_restart_serdes, 1382 bge_update_serdes, 1383 bge_check_serdes 1384 }; 1385 1386 /* 1387 * ========== Exported physical layer control routines ========== 1388 */ 1389 1390 #undef BGE_DBG 1391 #define BGE_DBG BGE_DBG_PHYS /* debug flag for this code */ 1392 1393 /* 1394 * Here we have to determine which media we're using (copper or serdes). 1395 * Once that's done, we can initialise the physical layer appropriately. 1396 */ 1397 int 1398 bge_phys_init(bge_t *bgep) 1399 { 1400 BGE_TRACE(("bge_phys_init($%p)", (void *)bgep)); 1401 1402 mutex_enter(bgep->genlock); 1403 1404 /* 1405 * Probe for the (internal) PHY. If it's not there, we'll assume 1406 * that this is a 5703/4S, with a SerDes interface rather than 1407 * a PHY. BCM5714S/BCM5715S are not supported.It are based on 1408 * BCM800x PHY. 1409 */ 1410 bgep->phy_mii_addr = 1; 1411 if (bge_phy_probe(bgep)) { 1412 bgep->chipid.flags &= ~CHIP_FLAG_SERDES; 1413 bgep->phys_delta_time = BGE_PHY_STABLE_TIME; 1414 bgep->physops = &copper_ops; 1415 } else { 1416 bgep->chipid.flags |= CHIP_FLAG_SERDES; 1417 bgep->phys_delta_time = BGE_SERDES_STABLE_TIME; 1418 bgep->physops = &serdes_ops; 1419 } 1420 1421 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) != DDI_SUCCESS) { 1422 mutex_exit(bgep->genlock); 1423 return (EIO); 1424 } 1425 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 1426 mutex_exit(bgep->genlock); 1427 return (EIO); 1428 } 1429 mutex_exit(bgep->genlock); 1430 return (0); 1431 } 1432 1433 /* 1434 * Reset the physical layer 1435 */ 1436 void 1437 bge_phys_reset(bge_t *bgep) 1438 { 1439 BGE_TRACE(("bge_phys_reset($%p)", (void *)bgep)); 1440 1441 mutex_enter(bgep->genlock); 1442 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) != DDI_SUCCESS) 1443 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 1444 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 1445 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 1446 mutex_exit(bgep->genlock); 1447 } 1448 1449 /* 1450 * Reset and power off the physical layer. 1451 * 1452 * Another RESET should get it back to working, but it may take a few 1453 * seconds it may take a few moments to return to normal operation ... 1454 */ 1455 int 1456 bge_phys_idle(bge_t *bgep) 1457 { 1458 BGE_TRACE(("bge_phys_idle($%p)", (void *)bgep)); 1459 1460 ASSERT(mutex_owned(bgep->genlock)); 1461 return ((*bgep->physops->phys_restart)(bgep, B_TRUE)); 1462 } 1463 1464 /* 1465 * Synchronise the PHYSICAL layer's speed/duplex/autonegotiation capabilities 1466 * and advertisements with the required settings as specified by the various 1467 * param_* variables that can be poked via the NDD interface. 1468 * 1469 * We always reset the PHYSICAL layer and reprogram *all* relevant registers. 1470 * This is expected to cause the link to go down, and then back up again once 1471 * the link is stable and autonegotiation (if enabled) is complete. We should 1472 * get a link state change interrupt somewhere along the way ... 1473 * 1474 * NOTE: <genlock> must already be held by the caller 1475 */ 1476 int 1477 bge_phys_update(bge_t *bgep) 1478 { 1479 BGE_TRACE(("bge_phys_update($%p)", (void *)bgep)); 1480 1481 ASSERT(mutex_owned(bgep->genlock)); 1482 return ((*bgep->physops->phys_update)(bgep)); 1483 } 1484 1485 #undef BGE_DBG 1486 #define BGE_DBG BGE_DBG_LINK /* debug flag for this code */ 1487 1488 /* 1489 * Read the link status and determine whether anything's changed ... 1490 * 1491 * This routine should be called whenever the chip flags a change 1492 * in the hardware link state. 1493 * 1494 * This routine returns B_FALSE if the link state has not changed, 1495 * returns B_TRUE when the change to the new state should be accepted. 1496 * In such a case, the param_* variables give the new hardware state, 1497 * which the caller should use to update link_state etc. 1498 * 1499 * The caller must already hold <genlock> 1500 */ 1501 boolean_t 1502 bge_phys_check(bge_t *bgep) 1503 { 1504 int32_t orig_state; 1505 boolean_t recheck; 1506 1507 BGE_TRACE(("bge_phys_check($%p)", (void *)bgep)); 1508 1509 ASSERT(mutex_owned(bgep->genlock)); 1510 1511 orig_state = bgep->link_state; 1512 recheck = orig_state == LINK_STATE_UNKNOWN; 1513 recheck = (*bgep->physops->phys_check)(bgep, recheck); 1514 if (!recheck) 1515 return (B_FALSE); 1516 1517 return (B_TRUE); 1518 } 1519