1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 #ifndef _BGE_HW_H 27 #define _BGE_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <sys/types.h> 34 35 36 /* 37 * First section: 38 * Identification of the various Broadcom chips 39 * 40 * Note: the various ID values are *not* all unique ;-( 41 * 42 * Note: the presence of an ID here does *not* imply that the chip is 43 * supported. At this time, only the 5703C, 5704C, and 5704S devices 44 * used on the motherboards of certain Sun products are supported. 45 * 46 * Note: the revision-id values in the PCI revision ID register are 47 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 48 */ 49 50 #define VENDOR_ID_BROADCOM 0x14e4 51 #define VENDOR_ID_SUN 0x108e 52 53 #define DEVICE_ID_5700 0x1644 54 #define DEVICE_ID_5700x 0x0003 55 #define DEVICE_ID_5701 0x1645 56 #define DEVICE_ID_5702 0x16a6 57 #define DEVICE_ID_5702fe 0x164d 58 #define DEVICE_ID_5703C 0x16a7 59 #define DEVICE_ID_5703S 0x1647 60 #define DEVICE_ID_5703 0x16c7 61 #define DEVICE_ID_5704C 0x1648 62 #define DEVICE_ID_5704S 0x16a8 63 #define DEVICE_ID_5704 0x1649 64 #define DEVICE_ID_5705C 0x1653 65 #define DEVICE_ID_5705_2 0x1654 66 #define DEVICE_ID_5717 0x1655 67 #define DEVICE_ID_5718 0x1656 68 #define DEVICE_ID_5724 0x165c 69 #define DEVICE_ID_5705M 0x165d 70 #define DEVICE_ID_5705MA3 0x165e 71 #define DEVICE_ID_5705F 0x166e 72 #define DEVICE_ID_5780 0x166a 73 #define DEVICE_ID_5782 0x1696 74 #define DEVICE_ID_5785 0x1699 75 #define DEVICE_ID_5787 0x169b 76 #define DEVICE_ID_5787M 0x1693 77 #define DEVICE_ID_5788 0x169c 78 #define DEVICE_ID_5789 0x169d 79 #define DEVICE_ID_5751 0x1677 80 #define DEVICE_ID_5751M 0x167d 81 #define DEVICE_ID_5752 0x1600 82 #define DEVICE_ID_5752M 0x1601 83 #define DEVICE_ID_5753 0x16fd 84 #define DEVICE_ID_5754 0x167a 85 #define DEVICE_ID_5755 0x167b 86 #define DEVICE_ID_5755M 0x1673 87 #define DEVICE_ID_5756M 0x1674 88 #define DEVICE_ID_5721 0x1659 89 #define DEVICE_ID_5722 0x165a 90 #define DEVICE_ID_5723 0x165b 91 #define DEVICE_ID_5714C 0x1668 92 #define DEVICE_ID_5714S 0x1669 93 #define DEVICE_ID_5715C 0x1678 94 #define DEVICE_ID_5715S 0x1679 95 #define DEVICE_ID_5761E 0x1680 96 #define DEVICE_ID_5761 0x1681 97 #define DEVICE_ID_5764 0x1684 98 #define DEVICE_ID_5906 0x1712 99 #define DEVICE_ID_5906M 0x1713 100 #define DEVICE_ID_57780 0x1692 101 102 #define REVISION_ID_5700_B0 0x10 103 #define REVISION_ID_5700_B2 0x12 104 #define REVISION_ID_5700_B3 0x13 105 #define REVISION_ID_5700_C0 0x20 106 #define REVISION_ID_5700_C1 0x21 107 #define REVISION_ID_5700_C2 0x22 108 109 #define REVISION_ID_5701_A0 0x08 110 #define REVISION_ID_5701_A2 0x12 111 #define REVISION_ID_5701_A3 0x15 112 113 #define REVISION_ID_5702_A0 0x00 114 115 #define REVISION_ID_5703_A0 0x00 116 #define REVISION_ID_5703_A1 0x01 117 #define REVISION_ID_5703_A2 0x02 118 119 #define REVISION_ID_5704_A0 0x00 120 #define REVISION_ID_5704_A1 0x01 121 #define REVISION_ID_5704_A2 0x02 122 #define REVISION_ID_5704_A3 0x03 123 #define REVISION_ID_5704_B0 0x10 124 125 #define REVISION_ID_5705_A0 0x00 126 #define REVISION_ID_5705_A1 0x01 127 #define REVISION_ID_5705_A2 0x02 128 #define REVISION_ID_5705_A3 0x03 129 130 #define REVISION_ID_5721_A0 0x00 131 #define REVISION_ID_5721_A1 0x01 132 133 #define REVISION_ID_5751_A0 0x00 134 #define REVISION_ID_5751_A1 0x01 135 136 #define REVISION_ID_5714_A0 0x00 137 #define REVISION_ID_5714_A1 0x01 138 #define REVISION_ID_5714_A2 0xA2 139 #define REVISION_ID_5714_A3 0xA3 140 141 #define REVISION_ID_5715_A0 0x00 142 #define REVISION_ID_5715_A1 0x01 143 #define REVISION_ID_5715_A2 0xA2 144 145 #define REVISION_ID_5715S_A0 0x00 146 #define REVISION_ID_5715S_A1 0x01 147 148 #define REVISION_ID_5754_A0 0x00 149 #define REVISION_ID_5754_A1 0x01 150 151 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 152 ((bgep->chipid.device == DEVICE_ID_5700) ||\ 153 (bgep->chipid.device == DEVICE_ID_5701) ||\ 154 (bgep->chipid.device == DEVICE_ID_5702) ||\ 155 (bgep->chipid.device == DEVICE_ID_5702fe)||\ 156 (bgep->chipid.device == DEVICE_ID_5703C) ||\ 157 (bgep->chipid.device == DEVICE_ID_5703S) ||\ 158 (bgep->chipid.device == DEVICE_ID_5703) ||\ 159 (bgep->chipid.device == DEVICE_ID_5704C) ||\ 160 (bgep->chipid.device == DEVICE_ID_5704S) ||\ 161 (bgep->chipid.device == DEVICE_ID_5704)) 162 163 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 164 ((bgep->chipid.device == DEVICE_ID_5702) ||\ 165 (bgep->chipid.device == DEVICE_ID_5702fe)) 166 167 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 168 ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 169 (bgep->chipid.device == DEVICE_ID_5705M) ||\ 170 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 171 (bgep->chipid.device == DEVICE_ID_5705F) ||\ 172 (bgep->chipid.device == DEVICE_ID_5780) ||\ 173 (bgep->chipid.device == DEVICE_ID_5782) ||\ 174 (bgep->chipid.device == DEVICE_ID_5788) ||\ 175 (bgep->chipid.device == DEVICE_ID_5705_2) ||\ 176 (bgep->chipid.device == DEVICE_ID_5754) ||\ 177 (bgep->chipid.device == DEVICE_ID_5755) ||\ 178 (bgep->chipid.device == DEVICE_ID_5756M) ||\ 179 (bgep->chipid.device == DEVICE_ID_5753)) 180 181 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 182 ((bgep->chipid.device == DEVICE_ID_5721) ||\ 183 (bgep->chipid.device == DEVICE_ID_5751) ||\ 184 (bgep->chipid.device == DEVICE_ID_5751M) ||\ 185 (bgep->chipid.device == DEVICE_ID_5752) ||\ 186 (bgep->chipid.device == DEVICE_ID_5752M) ||\ 187 (bgep->chipid.device == DEVICE_ID_5789)) 188 189 #define DEVICE_5717_SERIES_CHIPSETS(bgep) \ 190 (bgep->chipid.device == DEVICE_ID_5717) ||\ 191 (bgep->chipid.device == DEVICE_ID_5718) ||\ 192 (bgep->chipid.device == DEVICE_ID_5724) 193 194 #define DEVICE_5723_SERIES_CHIPSETS(bgep) \ 195 ((bgep->chipid.device == DEVICE_ID_5723) ||\ 196 (bgep->chipid.device == DEVICE_ID_5761) ||\ 197 (bgep->chipid.device == DEVICE_ID_5761E) ||\ 198 (bgep->chipid.device == DEVICE_ID_5764) ||\ 199 (bgep->chipid.device == DEVICE_ID_5785) ||\ 200 (bgep->chipid.device == DEVICE_ID_57780)) 201 202 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 203 ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 204 (bgep->chipid.device == DEVICE_ID_5714S) ||\ 205 (bgep->chipid.device == DEVICE_ID_5715C) ||\ 206 (bgep->chipid.device == DEVICE_ID_5715S)) 207 208 #define DEVICE_5906_SERIES_CHIPSETS(bgep) \ 209 ((bgep->chipid.device == DEVICE_ID_5906) ||\ 210 (bgep->chipid.device == DEVICE_ID_5906M)) 211 212 /* 213 * Second section: 214 * Offsets of important registers & definitions for bits therein 215 */ 216 217 /* 218 * PCI-X registers & bits 219 */ 220 #define PCIX_CONF_COMM 0x42 221 #define PCIX_COMM_RELAXED 0x0002 222 223 /* 224 * Miscellaneous Host Control Register, in PCI config space 225 */ 226 #define PCI_CONF_BGE_MHCR 0x68 227 #define MHCR_CHIP_REV_MASK 0xffff0000 228 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 229 #define MHCR_MASK_INTERRUPT_MODE 0x00000100 230 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 231 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 232 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 233 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010 234 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 235 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 236 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 237 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 238 239 #define MHCR_CHIP_REV_5700_B0 0x71000000 240 #define MHCR_CHIP_REV_5700_B2 0x71020000 241 #define MHCR_CHIP_REV_5700_B3 0x71030000 242 #define MHCR_CHIP_REV_5700_C0 0x72000000 243 #define MHCR_CHIP_REV_5700_C1 0x72010000 244 #define MHCR_CHIP_REV_5700_C2 0x72020000 245 246 #define MHCR_CHIP_REV_5701_A0 0x00000000 247 #define MHCR_CHIP_REV_5701_A2 0x00020000 248 #define MHCR_CHIP_REV_5701_A3 0x00030000 249 #define MHCR_CHIP_REV_5701_A5 0x01050000 250 251 #define MHCR_CHIP_REV_5702_A0 0x10000000 252 #define MHCR_CHIP_REV_5702_A1 0x10010000 253 #define MHCR_CHIP_REV_5702_A2 0x10020000 254 255 #define MHCR_CHIP_REV_5703_A0 0x10000000 256 #define MHCR_CHIP_REV_5703_A1 0x10010000 257 #define MHCR_CHIP_REV_5703_A2 0x10020000 258 #define MHCR_CHIP_REV_5703_B0 0x11000000 259 #define MHCR_CHIP_REV_5703_B1 0x11010000 260 261 #define MHCR_CHIP_REV_5704_A0 0x20000000 262 #define MHCR_CHIP_REV_5704_A1 0x20010000 263 #define MHCR_CHIP_REV_5704_A2 0x20020000 264 #define MHCR_CHIP_REV_5704_A3 0x20030000 265 #define MHCR_CHIP_REV_5704_B0 0x21000000 266 267 #define MHCR_CHIP_REV_5705_A0 0x30000000 268 #define MHCR_CHIP_REV_5705_A1 0x30010000 269 #define MHCR_CHIP_REV_5705_A2 0x30020000 270 #define MHCR_CHIP_REV_5705_A3 0x30030000 271 #define MHCR_CHIP_REV_5705_A5 0x30050000 272 273 #define MHCR_CHIP_REV_5782_A0 0x30030000 274 #define MHCR_CHIP_REV_5782_A1 0x30030088 275 276 #define MHCR_CHIP_REV_5788_A1 0x30050000 277 278 #define MHCR_CHIP_REV_5751_A0 0x40000000 279 #define MHCR_CHIP_REV_5751_A1 0x40010000 280 281 #define MHCR_CHIP_REV_5721_A0 0x41000000 282 #define MHCR_CHIP_REV_5721_A1 0x41010000 283 284 #define MHCR_CHIP_REV_5714_A0 0x50000000 285 #define MHCR_CHIP_REV_5714_A1 0x90010000 286 287 #define MHCR_CHIP_REV_5715_A0 0x50000000 288 #define MHCR_CHIP_REV_5715_A1 0x90010000 289 290 #define MHCR_CHIP_REV_5715S_A0 0x50000000 291 #define MHCR_CHIP_REV_5715S_A1 0x90010000 292 293 #define MHCR_CHIP_REV_5754_A0 0xb0000000 294 #define MHCR_CHIP_REV_5754_A1 0xb0010000 295 296 #define MHCR_CHIP_REV_5787_A0 0xb0000000 297 #define MHCR_CHIP_REV_5787_A1 0xb0010000 298 #define MHCR_CHIP_REV_5787_A2 0xb0020000 299 300 #define MHCR_CHIP_REV_5755_A0 0xa0000000 301 #define MHCR_CHIP_REV_5755_A1 0xa0010000 302 303 #define MHCR_CHIP_REV_5906_A0 0xc0000000 304 #define MHCR_CHIP_REV_5906_A1 0xc0010000 305 #define MHCR_CHIP_REV_5906_A2 0xc0020000 306 307 #define MHCR_CHIP_REV_5723_A0 0xf0000000 308 #define MHCR_CHIP_REV_5723_A1 0xf0010000 309 #define MHCR_CHIP_REV_5723_A2 0xf0020000 310 #define MHCR_CHIP_REV_5723_B0 0xf1000000 311 312 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000) 313 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 314 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 315 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 316 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 317 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 318 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 319 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 320 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 321 #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28) 322 #define MHCR_CHIP_ASIC_REV_5787 ((uint32_t)0xb << 28) 323 #define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28) 324 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 325 #define MHCR_CHIP_ASIC_REV_5906 ((uint32_t)0xc << 28) 326 #define MHCR_CHIP_ASIC_REV_5723 ((uint32_t)0xf << 28) 327 328 329 /* 330 * PCI DMA read/write Control Register, in PCI config space 331 * 332 * Note that several fields previously defined here have been deleted 333 * as they are not implemented in the 5703/4. 334 * 335 * Note: the value of this register is critical. It is possible to 336 * cause various unpleasant effects (DTOs, transaction deadlock, etc) 337 * by programming the wrong value. The value #defined below has been 338 * tested and shown to avoid all known problems. If it is to be changed, 339 * correct operation must be reverified on all supported platforms. 340 * 341 * In particular, we set both watermark fields to 2xCacheLineSize (128) 342 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 343 * with Tomatillo's internal pipelines, that otherwise result in stalls, 344 * repeated retries, and DTOs. 345 */ 346 #define PCI_CONF_BGE_PDRWCR 0x6c 347 #define PDRWCR_RWCMD_MASK 0xFF000000 348 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 349 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 350 #define PDRWCR_READ_WATERMARK_MASK 0x00070000 351 #define PDRWCR_CONCURRENCY_MASK 0x0000c000 352 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 353 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 354 #define PDRWCR_MIN_BEAT_MASK 0x000000ff 355 356 /* 357 * These are the actual values to be put into the fields shown above 358 */ 359 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 360 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 361 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 362 #define PDRWCR_MIN_BEATS 0x00000000 363 364 #define PDRWCR_VAR_DEFAULT 0x761b0000 365 #define PDRWCR_VAR_5721 0x76180000 366 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 367 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 368 #define PDRWCR_VAR_5717 0x00380000 369 370 /* 371 * PCI State Register, in PCI config space 372 * 373 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 374 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 375 */ 376 #define PCI_CONF_BGE_PCISTATE 0x70 377 #define PCISTATE_RETRY_SAME_DMA 0x00002000 378 #define PCISTATE_FLAT_VIEW 0x00000100 379 #define PCISTATE_EXT_ROM_RETRY 0x00000040 380 #define PCISTATE_EXT_ROM_ENABLE 0x00000020 381 #define PCISTATE_BUS_IS_32_BIT 0x00000010 382 #define PCISTATE_BUS_IS_FAST 0x00000008 383 #define PCISTATE_BUS_IS_PCI 0x00000004 384 #define PCISTATE_INTA_STATE 0x00000002 385 #define PCISTATE_FORCE_RESET 0x00000001 386 387 /* 388 * PCI Clock Control Register, in PCI config space 389 */ 390 #define PCI_CONF_BGE_CLKCTL 0x74 391 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 392 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 393 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 394 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 395 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 396 #define CLKCTL_PCIE_A0_FIX 0x00101000 397 398 /* 399 * Dual MAC Control Register, in PCI config space 400 */ 401 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 402 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 403 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 404 405 /* 406 * Register Indirect Access Address Register, 0x78 in PCI config 407 * space. Once this is set, accesses to the Register Indirect 408 * Access Data Register (0x80) refer to the register whose address 409 * is given by *this* register. This allows access to all the 410 * operating registers, while using only config space accesses. 411 * 412 * Note that the address written to the RIIAR should lie in one 413 * of the following ranges: 414 * 0x00000000 <= address < 0x00008000 (regular registers) 415 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 416 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 417 * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 418 */ 419 #define PCI_CONF_BGE_RIAAR 0x78 420 #define PCI_CONF_BGE_RIADR 0x80 421 422 #define RIAAR_REGISTER_MIN 0x00000000 423 #define RIAAR_REGISTER_MAX 0x00008000 424 #define RIAAR_RX_SCRATCH_MIN 0x00030000 425 #define RIAAR_RX_SCRATCH_MAX 0x00034000 426 #define RIAAR_TX_SCRATCH_MIN 0x00034000 427 #define RIAAR_TX_SCRATCH_MAX 0x00038000 428 #define RIAAR_RXROM_MIN 0x00038000 429 #define RIAAR_RXROM_MAX 0x00038800 430 431 /* 432 * Memory Window Base Address Register, 0x7c in PCI config space 433 * Once this is set, accesses to the Memory Window Data Access Register 434 * (0x84) refer to the word of NIC-local memory whose address is given 435 * by this register. When used in this way, the whole of the address 436 * written to this register is significant. 437 * 438 * This register also provides the 32K-aligned base address for a 32K 439 * region of NIC-local memory that the host can directly address in 440 * the upper 32K of the 64K of PCI memory space allocated to the chip. 441 * In this case, the bottom 15 bits of the register are ignored. 442 * 443 * Note that the address written to the MWBAR should lie in the range 444 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 445 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 446 * memory were present, but it's only supported on the 5700, not the 447 * 5701/5703/5704. 448 */ 449 #define PCI_CONF_BGE_MWBAR 0x7c 450 #define PCI_CONF_BGE_MWDAR 0x84 451 #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 452 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 453 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 454 455 /* 456 * The PCI express device control register and device status register 457 * which are only applicable on BCM5751 and BCM5721. 458 */ 459 #define PCI_CONF_DEV_CTRL 0xd8 460 #define PCI_CONF_DEV_CTRL_5723 0xd4 461 #define READ_REQ_SIZE_MAX 0x5000 462 #define DEV_CTRL_NO_SNOOP 0x0800 463 #define DEV_CTRL_RELAXED 0x0010 464 465 #define PCI_CONF_DEV_STUS 0xda 466 #define PCI_CONF_DEV_STUS_5723 0xd6 467 #define DEVICE_ERROR_STUS 0xf 468 469 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 470 471 /* 472 * Where to find things in NIC-local (on-chip) memory 473 */ 474 #define NIC_MEM_SEND_RINGS 0x0100 475 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 476 #define NIC_MEM_RECV_RINGS 0x0200 477 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 478 #define NIC_MEM_STATISTICS 0x0300 479 #define NIC_MEM_STATISTICS_SIZE 0x0800 480 #define NIC_MEM_STATUS_BLOCK 0x0b00 481 #define NIC_MEM_STATUS_SIZE 0x0050 482 #define NIC_MEM_GENCOMM 0x0b50 483 484 485 /* 486 * Note: the (non-bogus) values below are appropriate for systems 487 * without external memory. They would be different on a 5700 with 488 * external memory. 489 * 490 * Note: The higher send ring addresses and the mini ring shadow 491 * buffer address are dummies - systems without external memory 492 * are limited to 4 send rings and no mini receive ring. 493 */ 494 #define NIC_MEM_SHADOW_DMA 0x2000 495 #define NIC_MEM_SHADOW_SEND_1_4 0x4000 496 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 497 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 498 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 499 #define NIC_MEM_SHADOW_BUFF_STD 0x6000 500 #define NIC_MEM_SHADOW_BUFF_STD_5717 0x40000 501 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 502 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 503 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 504 505 /* 506 * Put this in the GENCOMM port to tell the firmware not to run PXE 507 */ 508 #define T3_MAGIC_NUMBER 0x4b657654u 509 510 /* 511 * The remaining registers appear in the low 32K of regular 512 * PCI Memory Address Space 513 */ 514 515 /* 516 * All the state machine control registers below have at least a 517 * <RESET> bit and an <ENABLE> bit as defined below. Some also 518 * have an <ATTN_ENABLE> bit. 519 */ 520 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 521 #define STATE_MACHINE_ENABLE_BIT 0x00000002 522 #define STATE_MACHINE_RESET_BIT 0x00000001 523 524 #define TRANSMIT_MAC_MODE_REG 0x045c 525 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 526 #define SEND_DATA_COMPLETION_MODE_REG 0x1000 527 #define SEND_BD_SELECTOR_MODE_REG 0x1400 528 #define SEND_BD_INITIATOR_MODE_REG 0x1800 529 #define SEND_BD_COMPLETION_MODE_REG 0x1c00 530 531 #define RECEIVE_MAC_MODE_REG 0x0468 532 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 533 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 534 #define RCV_DATA_COMPLETION_MODE_REG 0x2800 535 #define RCV_BD_INITIATOR_MODE_REG 0x2c00 536 #define RCV_BD_COMPLETION_MODE_REG 0x3000 537 #define RCV_LIST_SELECTOR_MODE_REG 0x3400 538 539 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 540 #define HOST_COALESCE_MODE_REG 0x3c00 541 #define MEMORY_ARBITER_MODE_REG 0x4000 542 #define BUFFER_MANAGER_MODE_REG 0x4400 543 #define READ_DMA_MODE_REG 0x4800 544 #define WRITE_DMA_MODE_REG 0x4c00 545 #define DMA_COMPLETION_MODE_REG 0x6400 546 547 /* 548 * Other bits in some of the above state machine control registers 549 */ 550 551 /* 552 * Transmit MAC Mode Register 553 * (TRANSMIT_MAC_MODE_REG, 0x045c) 554 */ 555 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 556 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 557 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 558 559 /* 560 * Receive MAC Mode Register 561 * (RECEIVE_MAC_MODE_REG, 0x0468) 562 */ 563 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 564 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 565 #define RECEIVE_MODE_PROMISCUOUS 0x00000100 566 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 567 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 568 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 569 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 570 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 571 572 /* 573 * Receive BD Initiator Mode Register 574 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 575 * 576 * Each of these bits controls whether ATTN is asserted 577 * on a particular condition 578 */ 579 #define RCV_BD_DISABLED_RING_ATTN 0x00000004 580 581 /* 582 * Receive Data & Receive BD Initiator Mode Register 583 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 584 * 585 * Each of these bits controls whether ATTN is asserted 586 * on a particular condition 587 */ 588 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 589 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 590 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 591 592 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 593 594 /* 595 * Host Coalescing Mode Control Register 596 * (HOST_COALESCE_MODE_REG, 0x3c00) 597 */ 598 #define COALESCE_64_BYTE_RINGS 12 599 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 600 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 601 #define COALESCE_CLR_TICKS_TX 0x00000400 602 #define COALESCE_CLR_TICKS_RX 0x00000200 603 #define COALESCE_32_BYTE_STATUS 0x00000100 604 #define COALESCE_64_BYTE_STATUS 0x00000080 605 #define COALESCE_NOW 0x00000008 606 607 /* 608 * Memory Arbiter Mode Register 609 * (MEMORY_ARBITER_MODE_REG, 0x4000) 610 */ 611 #define MEMORY_ARBITER_ENABLE 0x00000002 612 613 /* 614 * Buffer Manager Mode Register 615 * (BUFFER_MANAGER_MODE_REG, 0x4400) 616 * 617 * In addition to the usual error-attn common to most state machines 618 * this register has a separate bit for attn on running-low-on-mbufs 619 */ 620 #define BUFF_MGR_TEST_MODE 0x00000008 621 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 622 623 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 624 625 /* 626 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 627 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 628 * 629 * These registers each contain a 2-bit priority field, which controls 630 * the relative priority of that type of DMA (read vs. write vs. MSI), 631 * and a set of bits that control whether ATTN is asserted on each 632 * particular condition 633 */ 634 #define DMA_PRIORITY_MASK 0xc0000000 635 #define DMA_PRIORITY_SHIFT 30 636 #define ALL_DMA_ATTN_BITS 0x000003fc 637 638 /* 639 * BCM5755, 5755M, 5906, 5906M only 640 * 1 - Enable Fix. Device will send out the status block before 641 * the interrupt message 642 * 0 - Disable fix. Device will send out the interrupt message 643 * before the status block 644 */ 645 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000 646 647 /* 648 * End of state machine control register definitions 649 */ 650 651 652 /* 653 * High priority mailbox registers. 654 * Mailbox Registers (8 bytes each, but high half unused) 655 */ 656 #define INTERRUPT_MBOX_0_REG 0x0200 657 #define INTERRUPT_MBOX_1_REG 0x0208 658 #define INTERRUPT_MBOX_2_REG 0x0210 659 #define INTERRUPT_MBOX_3_REG 0x0218 660 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 661 662 /* 663 * Low priority mailbox registers, for BCM5906, BCM5906M. 664 */ 665 #define INTERRUPT_LP_MBOX_0_REG 0x5800 666 667 /* 668 * Ring Producer/Consumer Index (Mailbox) Registers 669 */ 670 #define RECV_STD_PROD_INDEX_REG 0x0268 671 #define RECV_JUMBO_PROD_INDEX_REG 0x0270 672 #define RECV_MINI_PROD_INDEX_REG 0x0278 673 #define RECV_RING_CONS_INDEX_REGS 0x0280 674 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 675 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 676 677 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 678 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 679 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 680 681 /* 682 * Ethernet MAC Mode Register 683 */ 684 #define ETHERNET_MAC_MODE_REG 0x0400 685 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 686 #define ETHERNET_MODE_ENABLE_RDE 0x00400000 687 #define ETHERNET_MODE_ENABLE_TDE 0x00200000 688 #define ETHERNET_MODE_ENABLE_MIP 0x00100000 689 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 690 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 691 #define ETHERNET_MODE_SEND_CFGS 0x00020000 692 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 693 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 694 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 695 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 696 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 697 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 698 #define ETHERNET_MODE_LINK_POLARITY 0x00000400 699 #define ETHERNET_MODE_MAX_DEFER 0x00000200 700 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 701 #define ETHERNET_MODE_TAGGED_MODE 0x00000080 702 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 703 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 704 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 705 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 706 #define ETHERNET_MODE_PORTMODE_MII 0x00000004 707 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 708 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 709 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 710 711 /* 712 * Ethernet MAC Status & Event Registers 713 */ 714 #define ETHERNET_MAC_STATUS_REG 0x0404 715 #define ETHERNET_STATUS_MI_INT 0x00800000 716 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 717 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 718 #define ETHERNET_STATUS_PCS_ERROR 0x00000400 719 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 720 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 721 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 722 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 723 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 724 725 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 726 #define ETHERNET_EVENT_MI_INT 0x00800000 727 #define ETHERNET_EVENT_LINK_INT 0x00001000 728 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 729 730 /* 731 * Ethernet MAC LED Control Register 732 * 733 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 734 * the external LED driver circuitry is wired up to assume that this mode 735 * will always be selected. Software must not change it! 736 */ 737 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 738 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 739 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 740 #define LED_CONTROL_LED_MODE_MASK 0x00001800 741 #define LED_CONTROL_LED_MODE_5700 0x00000000 742 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 743 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 744 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 745 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 746 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 747 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 748 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 749 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 750 #define LED_CONTROL_TRAFFIC_LED 0x00000020 751 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 752 #define LED_CONTROL_10MBPS_LED 0x00000008 753 #define LED_CONTROL_100MBPS_LED 0x00000004 754 #define LED_CONTROL_1000MBPS_LED 0x00000002 755 #define LED_CONTROL_OVERRIDE_LINK 0x00000001 756 #define LED_CONTROL_DEFAULT 0x02000800 757 758 /* 759 * MAC Address registers 760 * 761 * These four eight-byte registers each hold one unicast address 762 * (six bytes), right justified & zero-filled on the left. 763 * They will normally all be set to the same value, as a station 764 * usually only has one h/w address. The value in register 0 is 765 * used for pause packets; any of the four can be specified for 766 * substitution into other transmitted packets if required. 767 */ 768 #define MAC_ADDRESS_0_REG 0x0410 769 #define MAC_ADDRESS_1_REG 0x0418 770 #define MAC_ADDRESS_2_REG 0x0420 771 #define MAC_ADDRESS_3_REG 0x0428 772 773 #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 774 #define MAC_ADDRESS_REGS_MAX 4 775 776 /* 777 * More MAC Registers ... 778 */ 779 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 780 #define MAC_RX_MTU_SIZE_REG 0x043c 781 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 782 #define MAC_TX_LENGTHS_REG 0x0464 783 #define MAC_TX_LENGTHS_DEFAULT 0x00002620 784 785 /* 786 * MII access registers 787 */ 788 #define MI_COMMS_REG 0x044c 789 #define MI_COMMS_START 0x20000000 790 #define MI_COMMS_READ_FAILED 0x10000000 791 #define MI_COMMS_COMMAND_MASK 0x0c000000 792 #define MI_COMMS_COMMAND_READ 0x08000000 793 #define MI_COMMS_COMMAND_WRITE 0x04000000 794 #define MI_COMMS_ADDRESS_MASK 0x03e00000 795 #define MI_COMMS_ADDRESS_SHIFT 21 796 #define MI_COMMS_REGISTER_MASK 0x001f0000 797 #define MI_COMMS_REGISTER_SHIFT 16 798 #define MI_COMMS_DATA_MASK 0x0000ffff 799 #define MI_COMMS_DATA_SHIFT 0 800 801 #define MI_STATUS_REG 0x0450 802 #define MI_STATUS_10MBPS 0x00000002 803 #define MI_STATUS_LINK 0x00000001 804 805 #define MI_MODE_REG 0x0454 806 #define MI_MODE_CLOCK_MASK 0x001f0000 807 #define MI_MODE_AUTOPOLL 0x00000010 808 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 809 #define MI_MODE_DEFAULT 0x000c0000 810 811 #define MI_AUTOPOLL_STATUS_REG 0x0458 812 #define MI_AUTOPOLL_ERROR 0x00000001 813 814 #define TRANSMIT_MAC_STATUS_REG 0x0460 815 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 816 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 817 #define TRANSMIT_STATUS_LINK_UP 0x00000008 818 #define TRANSMIT_STATUS_SENT_XON 0x00000004 819 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 820 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 821 822 #define RECEIVE_MAC_STATUS_REG 0x046c 823 #define RECEIVE_STATUS_RCVD_XON 0x00000004 824 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 825 #define RECEIVE_STATUS_SENT_XOFF 0x00000001 826 827 /* 828 * These four-byte registers constitute a hash table for deciding 829 * whether to accept incoming multicast packets. The bits are 830 * numbered in big-endian fashion, from hash 0 => the MSB of 831 * register 0 to hash 127 => the LSB of the highest-numbered 832 * register. 833 * 834 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 835 * enabled by setting the appropriate bit in the Rx MAC mode 836 * register. Otherwise, and on all earlier chips, the table 837 * is only 128 bits (registers 0-3). 838 */ 839 #define MAC_HASH_0_REG 0x0470 840 #define MAC_HASH_1_REG 0x0474 841 #define MAC_HASH_2_REG 0x0478 842 #define MAC_HASH_3_REG 0x047c 843 #define MAC_HASH_4_REG 0x???? 844 #define MAC_HASH_5_REG 0x???? 845 #define MAC_HASH_6_REG 0x???? 846 #define MAC_HASH_7_REG 0x???? 847 #define MAC_HASH_REG(n) (0x470+4*(n)) 848 849 /* 850 * Receive Rules Registers: 16 pairs of control+mask/value pairs 851 */ 852 #define RCV_RULES_CONTROL_0_REG 0x0480 853 #define RCV_RULES_MASK_0_REG 0x0484 854 #define RCV_RULES_CONTROL_15_REG 0x04f8 855 #define RCV_RULES_MASK_15_REG 0x04fc 856 #define RCV_RULES_CONFIG_REG 0x0500 857 #define RCV_RULES_CONFIG_DEFAULT 0x00000008 858 859 #define RECV_RULES_NUM_MAX 16 860 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 861 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 862 863 #define RECV_RULE_CTL_ENABLE 0x80000000 864 #define RECV_RULE_CTL_AND 0x40000000 865 #define RECV_RULE_CTL_P1 0x20000000 866 #define RECV_RULE_CTL_P2 0x10000000 867 #define RECV_RULE_CTL_P3 0x08000000 868 #define RECV_RULE_CTL_MASK 0x04000000 869 #define RECV_RULE_CTL_DISCARD 0x02000000 870 #define RECV_RULE_CTL_MAP 0x01000000 871 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 872 #define RECV_RULE_CTL_OP 0x00030000 873 #define RECV_RULE_CTL_OP_EQ 0x00000000 874 #define RECV_RULE_CTL_OP_NEQ 0x00010000 875 #define RECV_RULE_CTL_OP_GREAT 0x00020000 876 #define RECV_RULE_CTL_OP_LESS 0x00030000 877 #define RECV_RULE_CTL_HEADER 0x0000e000 878 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 879 #define RECV_RULE_CTL_HEADER_IP 0x00002000 880 #define RECV_RULE_CTL_HEADER_TCP 0x00004000 881 #define RECV_RULE_CTL_HEADER_UDP 0x00006000 882 #define RECV_RULE_CTL_HEADER_DATA 0x00008000 883 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 884 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 885 RECV_RULE_CTL_CLASS_BITS) 886 #define RECV_RULE_CTL_OFFSET 0x000000ff 887 888 /* 889 * Receive Rules definition 890 */ 891 #define ETHERHEADER_DEST_OFFSET 0x00 892 #define IPHEADER_PROTO_OFFSET 0x08 893 #define IPHEADER_SIP_OFFSET 0x0c 894 #define IPHEADER_DIP_OFFSET 0x10 895 #define TCPHEADER_SPORT_OFFSET 0x00 896 #define TCPHEADER_DPORT_OFFSET 0x02 897 #define UDPHEADER_SPORT_OFFSET 0x00 898 #define UDPHEADER_DPORT_OFFSET 0x02 899 900 #define RULE_MATCH(ring) (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 901 RECV_RULE_CTL_CLASS((ring))) 902 903 #define RULE_MATCH_MASK(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_MASK) 904 905 #define RULE_DEST_MAC_1(ring) (RULE_MATCH(ring) | \ 906 RECV_RULE_CTL_HEADER_FRAME | \ 907 ETHERHEADER_DEST_OFFSET) 908 909 #define RULE_DEST_MAC_2(ring) (RULE_MATCH_MASK(ring) | \ 910 RECV_RULE_CTL_HEADER_FRAME | \ 911 ETHERHEADER_DEST_OFFSET + 4) 912 913 #define RULE_LOCAL_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 914 IPHEADER_DIP_OFFSET) 915 916 #define RULE_REMOTE_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 917 IPHEADER_SIP_OFFSET) 918 919 #define RULE_IP_PROTO(ring) (RULE_MATCH_MASK(ring) | \ 920 RECV_RULE_CTL_HEADER_IP | \ 921 IPHEADER_PROTO_OFFSET) 922 923 #define RULE_TCP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 924 RECV_RULE_CTL_HEADER_TCP | \ 925 TCPHEADER_SPORT_OFFSET) 926 927 #define RULE_TCP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 928 RECV_RULE_CTL_HEADER_TCP | \ 929 TCPHEADER_DPORT_OFFSET) 930 931 #define RULE_UDP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 932 RECV_RULE_CTL_HEADER_UDP | \ 933 UDPHEADER_SPORT_OFFSET) 934 935 #define RULE_UDP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 936 RECV_RULE_CTL_HEADER_UDP | \ 937 UDPHEADER_DPORT_OFFSET) 938 939 /* 940 * 1000BaseX low-level access registers 941 */ 942 #define MAC_GIGABIT_PCS_TEST_REG 0x0440 943 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 944 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 945 #define TX_1000BASEX_AUTONEG_REG 0x0444 946 #define RX_1000BASEX_AUTONEG_REG 0x0448 947 948 /* 949 * Autoneg code bits for the 1000BASE-X AUTONEG registers 950 */ 951 #define AUTONEG_CODE_PAUSE 0x00008000 952 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 953 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 954 #define AUTONEG_CODE_NEXT_PAGE 0x00000080 955 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 956 #define AUTONEG_CODE_FAULT_MASK 0x00000030 957 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 958 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 959 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 960 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 961 962 /* 963 * SerDes Registers (5703S/5704S only) 964 */ 965 #define SERDES_CONTROL_REG 0x0590 966 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 967 #define SERDES_CONTROL_COMMA_DETECT 0x00010000 968 #define SERDES_CONTROL_TX_DISABLE 0x00004000 969 #define SERDES_STATUS_REG 0x0594 970 #define SERDES_STATUS_COMMA_DETECTED 0x00000100 971 #define SERDES_STATUS_RXSTAT 0x000000ff 972 973 /* 974 * SGMII Status Register (5717/5718 only) 975 */ 976 #define SGMII_STATUS_REG 0x5B4 977 #define MEDIA_SELECTION_MODE 0x00000100 978 979 /* 980 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 981 */ 982 #define STAT_IFHCOUT_OCTETS_REG 0x0800 983 #define STAT_ETHER_COLLIS_REG 0x0808 984 #define STAT_OUTXON_SENT_REG 0x080c 985 #define STAT_OUTXOFF_SENT_REG 0x0810 986 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 987 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 988 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 989 #define STAT_DOT3_DEFERED_TX_REG 0x0824 990 #define STAT_DOT3_EXCE_COLLI_REG 0x082c 991 #define STAT_DOT3_LATE_COLLI_REG 0x0830 992 #define STAT_IFHCOUT_UPKGS_REG 0x086c 993 #define STAT_IFHCOUT_MPKGS_REG 0x0870 994 #define STAT_IFHCOUT_BPKGS_REG 0x0874 995 996 #define STAT_IFHCIN_OCTETS_REG 0x0880 997 #define STAT_ETHER_FRAGMENT_REG 0x0888 998 #define STAT_IFHCIN_UPKGS_REG 0x088c 999 #define STAT_IFHCIN_MPKGS_REG 0x0890 1000 #define STAT_IFHCIN_BPKGS_REG 0x0894 1001 1002 #define STAT_DOT3_FCS_ERR_REG 0x0898 1003 #define STAT_DOT3_ALIGN_ERR_REG 0x089c 1004 #define STAT_XON_PAUSE_RX_REG 0x08a0 1005 #define STAT_XOFF_PAUSE_RX_REG 0x08a4 1006 #define STAT_MAC_CTRL_RX_REG 0x08a8 1007 #define STAT_XOFF_STATE_ENTER_REG 0x08ac 1008 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 1009 #define STAT_ETHER_JABBERS_REG 0x08b4 1010 #define STAT_ETHER_UNDERSIZE_REG 0x08b8 1011 #define SIZE_OF_STATISTIC_REG 0x1B 1012 /* 1013 * Send Data Initiator Registers 1014 */ 1015 #define SEND_INIT_STATS_CONTROL_REG 0x0c08 1016 #define SEND_INIT_STATS_ZERO 0x00000010 1017 #define SEND_INIT_STATS_FLUSH 0x00000008 1018 #define SEND_INIT_STATS_CLEAR 0x00000004 1019 #define SEND_INIT_STATS_FASTER 0x00000002 1020 #define SEND_INIT_STATS_ENABLE 0x00000001 1021 1022 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 1023 1024 /* 1025 * Send Buffer Descriptor Selector Control Registers 1026 */ 1027 #define SEND_BD_SELECTOR_STATUS_REG 0x1404 1028 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 1029 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 1030 1031 /* 1032 * Receive List Placement Registers 1033 */ 1034 #define RCV_LP_CONFIG_REG 0x2010 1035 #define RCV_LP_CONFIG_DEFAULT 0x00000009 1036 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 1037 1038 #define RCV_LP_STATS_CONTROL_REG 0x2014 1039 #define RCV_LP_STATS_ZERO 0x00000010 1040 #define RCV_LP_STATS_FLUSH 0x00000008 1041 #define RCV_LP_STATS_CLEAR 0x00000004 1042 #define RCV_LP_STATS_FASTER 0x00000002 1043 #define RCV_LP_STATS_ENABLE 0x00000001 1044 1045 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 1046 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000 1047 1048 /* 1049 * Receive Data & BD Initiator Registers 1050 */ 1051 #define RCV_INITIATOR_STATUS_REG 0x2404 1052 1053 /* 1054 * Receive Buffer Descriptor Ring Control Block Registers 1055 * NB: sixteen bytes (128 bits) each 1056 */ 1057 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 1058 #define STD_RCV_BD_RING_RCB_REG 0x2450 1059 #define MINI_RCV_BD_RING_RCB_REG 0x2460 1060 1061 /* 1062 * Receive Buffer Descriptor Ring Replenish Threshold Registers 1063 */ 1064 #define MINI_RCV_BD_REPLENISH_REG 0x2c14 1065 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 1066 #define STD_RCV_BD_REPLENISH_REG 0x2c18 1067 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 1068 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 1069 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 1070 1071 /* 1072 * CPMU registers (5717/5718 only) 1073 */ 1074 #define CPMU_STATUS_REG 0x362c 1075 #define CPMU_STATUS_FUN_NUM 0x20000000 1076 1077 /* 1078 * Host Coalescing Engine Control Registers 1079 */ 1080 #define RCV_COALESCE_TICKS_REG 0x3c08 1081 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1082 #define SEND_COALESCE_TICKS_REG 0x3c0c 1083 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1084 #define RCV_COALESCE_MAX_BD_REG 0x3c10 1085 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1086 #define SEND_COALESCE_MAX_BD_REG 0x3c14 1087 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1088 #define RCV_COALESCE_INT_TICKS_REG 0x3c18 1089 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1090 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 1091 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1092 #define RCV_COALESCE_INT_BD_REG 0x3c20 1093 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1094 #define SEND_COALESCE_INT_BD_REG 0x3c24 1095 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1096 #define STATISTICS_TICKS_REG 0x3c28 1097 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 1098 #define STATISTICS_HOST_ADDR_REG 0x3c30 1099 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 1100 #define STATISTICS_BASE_ADDR_REG 0x3c40 1101 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 1102 #define FLOW_ATTN_REG 0x3c48 1103 1104 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 1105 #define NIC_STD_RECV_INDEX_REG 0x3c54 1106 #define NIC_MINI_RECV_INDEX_REG 0x3c58 1107 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 1108 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 1109 1110 /* 1111 * Mbuf Pool Initialisation & Watermark Registers 1112 * 1113 * There are some conflicts in the PRM; compare the recommendations 1114 * on pp. 115, 236, and 339. The values here were recommended by 1115 * dkim@broadcom.com (and the PRM should be corrected soon ;-) 1116 */ 1117 #define BUFFER_MANAGER_STATUS_REG 0x4404 1118 #define MBUF_POOL_BASE_REG 0x4408 1119 #define MBUF_POOL_BASE_DEFAULT 0x00008000 1120 #define MBUF_POOL_BASE_5721 0x00010000 1121 #define MBUF_POOL_BASE_5704 0x00010000 1122 #define MBUF_POOL_BASE_5705 0x00010000 1123 #define MBUF_POOL_LENGTH_REG 0x440c 1124 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 1125 #define MBUF_POOL_LENGTH_5704 0x00010000 1126 #define MBUF_POOL_LENGTH_5705 0x00008000 1127 #define MBUF_POOL_LENGTH_5721 0x00008000 1128 #define RDMA_MBUF_LOWAT_REG 0x4410 1129 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 1130 #define RDMA_MBUF_LOWAT_5705 0x00000000 1131 #define RDMA_MBUF_LOWAT_5906 0x00000000 1132 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 1133 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 1134 #define MAC_RX_MBUF_LOWAT_REG 0x4414 1135 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 1136 #define MAC_RX_MBUF_LOWAT_5705 0x00000010 1137 #define MAC_RX_MBUF_LOWAT_5906 0x00000004 1138 #define MAC_RX_MBUF_LOWAT_5717 0x0000002a 1139 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 1140 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 1141 #define MBUF_HIWAT_REG 0x4418 1142 #define MBUF_HIWAT_DEFAULT 0x00000060 1143 #define MBUF_HIWAT_5705 0x00000060 1144 #define MBUF_HIWAT_5906 0x00000010 1145 #define MBUF_HIWAT_5717 0x000000a0 1146 #define MBUF_HIWAT_JUMBO 0x0000017c 1147 #define MBUF_HIWAT_5714_JUMBO 0x00000096 1148 1149 /* 1150 * DMA Descriptor Pool Initialisation & Watermark Registers 1151 */ 1152 #define DMAD_POOL_BASE_REG 0x442c 1153 #define DMAD_POOL_BASE_DEFAULT 0x00002000 1154 #define DMAD_POOL_LENGTH_REG 0x4430 1155 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 1156 #define DMAD_POOL_LOWAT_REG 0x4434 1157 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 1158 #define DMAD_POOL_HIWAT_REG 0x4438 1159 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 1160 1161 /* 1162 * More threshold/watermark registers ... 1163 */ 1164 #define RECV_FLOW_THRESHOLD_REG 0x4458 1165 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 1166 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 1167 1168 /* 1169 * Read/Write DMA Status Registers 1170 */ 1171 #define READ_DMA_STATUS_REG 0x4804 1172 #define WRITE_DMA_STATUS_REG 0x4c04 1173 1174 /* 1175 * RX/TX RISC Registers 1176 */ 1177 #define RX_RISC_MODE_REG 0x5000 1178 #define RX_RISC_STATE_REG 0x5004 1179 #define RX_RISC_PC_REG 0x501c 1180 #define TX_RISC_MODE_REG 0x5400 1181 #define TX_RISC_STATE_REG 0x5404 1182 #define TX_RISC_PC_REG 0x541c 1183 1184 /* 1185 * V? RISC Registerss 1186 */ 1187 #define VCPU_STATUS_REG 0x5100 1188 #define VCPU_INIT_DONE 0x04000000 1189 #define VCPU_DRV_RESET 0x08000000 1190 1191 #define VCPU_EXT_CTL 0x6890 1192 #define VCPU_EXT_CTL_HALF 0x00400000 1193 1194 #define FTQ_RESET_REG 0x5c00 1195 1196 #define MSI_MODE_REG 0x6000 1197 #define MSI_PRI_HIGHEST 0xc0000000 1198 #define MSI_MSI_ENABLE 0x00000002 1199 #define MSI_ERROR_ATTENTION 0x0000001c 1200 1201 #define MSI_STATUS_REG 0x6004 1202 1203 #define MODE_CONTROL_REG 0x6800 1204 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 1205 #define MODE_4X_NIC_SEND_RINGS 0x20000000 1206 #define MODE_INT_ON_FLOW_ATTN 0x10000000 1207 #define MODE_INT_ON_DMA_ATTN 0x08000000 1208 #define MODE_INT_ON_MAC_ATTN 0x04000000 1209 #define MODE_INT_ON_RXRISC_ATTN 0x02000000 1210 #define MODE_INT_ON_TXRISC_ATTN 0x01000000 1211 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 1212 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 1213 #define MODE_HOST_SEND_BDS 0x00020000 1214 #define MODE_HOST_STACK_UP 0x00010000 1215 #define MODE_FORCE_32_BIT_PCI 0x00008000 1216 #define MODE_NO_INT_ON_RECV 0x00004000 1217 #define MODE_NO_INT_ON_SEND 0x00002000 1218 #define MODE_ALLOW_BAD_FRAMES 0x00000800 1219 #define MODE_NO_CRC 0x00000400 1220 #define MODE_NO_FRAME_CRACKING 0x00000200 1221 #define MODE_WORD_SWAP_FRAME 0x00000020 1222 #define MODE_BYTE_SWAP_FRAME 0x00000010 1223 #define MODE_WORD_SWAP_NONFRAME 0x00000004 1224 #define MODE_BYTE_SWAP_NONFRAME 0x00000002 1225 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 1226 1227 /* 1228 * Miscellaneous Configuration Register 1229 * 1230 * This contains various bits relating to power control (which differ 1231 * among different members of the chip family), but the important bits 1232 * for our purposes are the RESET bit and the Timer Prescaler field. 1233 * 1234 * The RESET bit in this register serves to reset the whole chip, even 1235 * including the PCI interface(!) Once it's set, the chip will not 1236 * respond to ANY accesses -- not even CONFIG space -- until the reset 1237 * completes internally. According to the PRM, this should take less 1238 * than 100us. Any access during this period will get a bus error. 1239 * 1240 * The Timer Prescaler field must be programmed so that the timer period 1241 * is as near as possible to 1us. The value in this field should be 1242 * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 1243 * the Core Clock should always be 66MHz (independently of the bus speed, 1244 * at least for PCI rather than PCI-X), so this register must be set to 1245 * the value 0x82 ((66-1) << 1). 1246 */ 1247 #define CORE_CLOCK_MHZ 66 1248 #define MISC_CONFIG_REG 0x6804 1249 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 1250 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 1251 #define MISC_CONFIG_POWERDOWN 0x00100000 1252 #define MISC_CONFIG_POWER_STATE 0x00060000 1253 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 1254 #define MISC_CONFIG_RESET_BIT 0x00000001 1255 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 1256 #define MISC_CONFIG_EPHY_IDDQ 0x00200000 1257 1258 /* 1259 * Miscellaneous Local Control Register (MLCR) 1260 */ 1261 #define MISC_LOCAL_CONTROL_REG 0x6808 1262 #define MLCR_PCI_CTRL_SELECT 0x10000000 1263 #define MLCR_LEGACY_PCI_MODE 0x08000000 1264 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 1265 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 1266 #define MLCR_SSRAM_TYPE 0x00400000 1267 #define MLCR_BANK_SELECT 0x00200000 1268 #define MLCR_SRAM_SIZE_MASK 0x001c0000 1269 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 1270 1271 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1272 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 1273 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 1274 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 1275 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1276 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 1277 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 1278 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 1279 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 1280 1281 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 1282 #define MLCR_SET_INT 0x00000004 /* W/O */ 1283 #define MLCR_CLR_INT 0x00000002 /* W/O */ 1284 #define MLCR_INTA_STATE 0x00000001 /* R/O */ 1285 1286 /* 1287 * This value defines all GPIO bits as INPUTS, but sets their default 1288 * values as outputs to HIGH, on the assumption that external circuits 1289 * (if any) will probably be active-LOW with passive pullups. 1290 * 1291 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 1292 * just this fashion. It has to be set as an OUTPUT and driven LOW to 1293 * enable writing. Otherwise, the SEEPROM is protected. 1294 */ 1295 #define MLCR_DEFAULT 0x0101c000 1296 #define MLCR_DEFAULT_5714 0x1901c000 1297 #define MLCR_DEFAULT_5717 0x01000000 1298 1299 /* 1300 * Serial EEPROM Data/Address Registers (auto-access mode) 1301 */ 1302 #define SERIAL_EEPROM_DATA_REG 0x683c 1303 #define SERIAL_EEPROM_ADDRESS_REG 0x6838 1304 #define SEEPROM_ACCESS_READ 0x80000000 1305 #define SEEPROM_ACCESS_WRITE 0x00000000 1306 #define SEEPROM_ACCESS_COMPLETE 0x40000000 1307 #define SEEPROM_ACCESS_RESET 0x20000000 1308 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 1309 #define SEEPROM_ACCESS_START 0x02000000 1310 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 1311 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 1312 1313 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 1314 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 1315 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 1316 1317 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 1318 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 1319 1320 /* 1321 * "Linearised" address mask, treating multiple devices as consecutive 1322 */ 1323 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 1324 1325 /* 1326 * Non-Volatile Memory Interface Registers 1327 * Note: on chips that support the flash interface (5702+), flash is the 1328 * default and the legacy seeprom interface must be explicitly enabled 1329 * if required. On older chips (5700/01), SEEPROM is the default (and 1330 * only) non-volatile memory available, and these registers don't exist! 1331 */ 1332 #define NVM_FLASH_CMD_REG 0x7000 1333 #define NVM_FLASH_CMD_LAST 0x00000100 1334 #define NVM_FLASH_CMD_FIRST 0x00000080 1335 #define NVM_FLASH_CMD_RD 0x00000000 1336 #define NVM_FLASH_CMD_WR 0x00000020 1337 #define NVM_FLASH_CMD_DOIT 0x00000010 1338 #define NVM_FLASH_CMD_DONE 0x00000008 1339 1340 #define NVM_FLASH_WRITE_REG 0x7008 1341 #define NVM_FLASH_READ_REG 0x7010 1342 1343 #define NVM_FLASH_ADDR_REG 0x700c 1344 #define NVM_FLASH_ADDR_MASK 0x00fffffc 1345 1346 #define NVM_CONFIG1_REG 0x7014 1347 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 1348 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 1349 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 1350 #define NVM_CFG1_BUFFERED_MODE 0x00000002 1351 #define NVM_CFG1_FLASH_MODE 0x00000001 1352 1353 #define NVM_SW_ARBITRATION_REG 0x7020 1354 #define NVM_READ_REQ3 0X00008000 1355 #define NVM_READ_REQ2 0X00004000 1356 #define NVM_READ_REQ1 0X00002000 1357 #define NVM_READ_REQ0 0X00001000 1358 #define NVM_WON_REQ3 0X00000800 1359 #define NVM_WON_REQ2 0X00000400 1360 #define NVM_WON_REQ1 0X00000200 1361 #define NVM_WON_REQ0 0X00000100 1362 #define NVM_RESET_REQ3 0X00000080 1363 #define NVM_RESET_REQ2 0X00000040 1364 #define NVM_RESET_REQ1 0X00000020 1365 #define NVM_RESET_REQ0 0X00000010 1366 #define NVM_SET_REQ3 0X00000008 1367 #define NVM_SET_REQ2 0X00000004 1368 #define NVM_SET_REQ1 0X00000002 1369 #define NVM_SET_REQ0 0X00000001 1370 1371 /* 1372 * NVM access register 1373 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714 1374 * and BCM5715 only. 1375 */ 1376 #define NVM_ACCESS_REG 0X7024 1377 #define NVM_WRITE_ENABLE 0X00000002 1378 #define NVM_ACCESS_ENABLE 0X00000001 1379 1380 /* 1381 * TLP Control Register 1382 * Applicable to BCM5721 and BCM5751 only 1383 */ 1384 #define TLP_CONTROL_REG 0x7c00 1385 #define TLP_DATA_FIFO_PROTECT 0x02000000 1386 1387 /* 1388 * PHY Test Control Register 1389 * Applicable to BCM5721 and BCM5751 only 1390 */ 1391 #define PHY_TEST_CTRL_REG 0x7e2c 1392 #define PHY_PCIE_SCRAM_MODE 0x20 1393 #define PHY_PCIE_LTASS_MODE 0x40 1394 1395 /* 1396 * The internal firmware expects a certain layout of the non-volatile 1397 * memory (if fitted), and will check for it during startup, and use the 1398 * contents to initialise various internal parameters if it looks good. 1399 * 1400 * The offsets and field definitions below refer to where to find some 1401 * important values, and how to interpret them ... 1402 */ 1403 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 1404 #define NVMEM_DATA_MAC_ADDRESS_5906 0x0010 /* 8 bytes */ 1405 1406 /* 1407 * Vendor-specific MII registers 1408 */ 1409 #define MII_EXT_CONTROL MII_VENDOR(0) 1410 #define MII_EXT_STATUS MII_VENDOR(1) 1411 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 1412 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 1413 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 1414 #define MII_AUX_CONTROL MII_VENDOR(8) 1415 #define MII_AUX_STATUS MII_VENDOR(9) 1416 #define MII_INTR_STATUS MII_VENDOR(10) 1417 #define MII_INTR_MASK MII_VENDOR(11) 1418 #define MII_HCD_STATUS MII_VENDOR(13) 1419 1420 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 1421 1422 /* 1423 * Bits in the MII_EXT_CONTROL register 1424 */ 1425 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 1426 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 1427 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 1428 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 1429 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 1430 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 1431 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 1432 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 1433 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 1434 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 1435 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 1436 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 1437 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 1438 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 1439 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 1440 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 1441 1442 /* 1443 * Bits in the MII_EXT_STATUS register 1444 */ 1445 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 1446 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 1447 #define MII_EXT_STAT_MDIX_STATE 0x2000 1448 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 1449 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 1450 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 1451 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 1452 #define MII_EXT_STAT_LINK_STATUS 0x0100 1453 #define MII_EXT_STAT_CRC_ERROR 0x0080 1454 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 1455 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 1456 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 1457 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 1458 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 1459 #define MII_EXT_STAT_LOCK_ERROR 0x0002 1460 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 1461 1462 /* 1463 * The AUX CONTROL register is seriously weird! 1464 * 1465 * It hides (up to) eight 'shadow' registers. When writing, which one 1466 * of them is written is determined by the low-order bits of the data 1467 * written(!), but when reading, which one is read is determined by the 1468 * value previously written to (part of) one of the shadow registers!!! 1469 */ 1470 1471 /* 1472 * Shadow register numbers 1473 */ 1474 #define MII_AUX_CTRL_NORMAL 0 1475 #define MII_AUX_CTRL_10BASE_T 1 1476 #define MII_AUX_CTRL_POWER 2 1477 #define MII_AUX_CTRL_TEST_1 4 1478 #define MII_AUX_CTRL_MISC 7 1479 1480 /* 1481 * Selected bits in some of the shadow registers ... 1482 */ 1483 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 1484 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 1485 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 1486 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 1487 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 1488 1489 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 1490 1491 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 1492 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 1493 1494 /* 1495 * Write this value to the AUX control register 1496 * to select which shadow register will be read 1497 */ 1498 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 1499 1500 /* 1501 * Bits in the MII_AUX_STATUS register 1502 */ 1503 #define MII_AUX_STATUS_MODE_MASK 0x0700 1504 #define MII_AUX_STATUS_MODE_1000_F 0x0700 1505 #define MII_AUX_STATUS_MODE_1000_H 0x0600 1506 #define MII_AUX_STATUS_MODE_100_F 0x0500 1507 #define MII_AUX_STATUS_MODE_100_4 0x0400 1508 #define MII_AUX_STATUS_MODE_100_H 0x0300 1509 #define MII_AUX_STATUS_MODE_10_F 0x0200 1510 #define MII_AUX_STATUS_MODE_10_H 0x0100 1511 #define MII_AUX_STATUS_MODE_NONE 0x0000 1512 #define MII_AUX_STATUS_MODE_SHIFT 8 1513 1514 #define MII_AUX_STATUS_PAR_FAULT 0x0080 1515 #define MII_AUX_STATUS_REM_FAULT 0x0040 1516 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 1517 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 1518 1519 #define MII_AUX_STATUS_LINKUP 0x0004 1520 #define MII_AUX_STATUS_RX_PAUSE 0x0002 1521 #define MII_AUX_STATUS_TX_PAUSE 0x0001 1522 1523 #define MII_AUX_STATUS_SPEED_IND_5906 0x0008 1524 #define MII_AUX_STATUS_NEG_ENABLED_5906 0x0002 1525 #define MII_AUX_STATUS_DUPLEX_IND_5906 0x0001 1526 1527 /* 1528 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 1529 */ 1530 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 1531 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 1532 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 1533 #define MII_INTR_LINK_SPEED_CHANGE 0x0004 1534 #define MII_INTR_LINK_STATUS_CHANGE 0x0002 1535 1536 1537 /* 1538 * Third section: 1539 * Hardware-defined data structures 1540 * 1541 * Note that the chip is naturally BIG-endian, so, for a big-endian 1542 * host, the structures defined below match those described in the PRM. 1543 * For little-endian hosts, some structures have to be swapped around. 1544 */ 1545 1546 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 1547 #error Host endianness not defined 1548 #endif 1549 1550 /* 1551 * Architectural constants: absolute maximum numbers of each type of ring 1552 */ 1553 #ifdef BGE_EXT_MEM 1554 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 1555 #else 1556 #define BGE_SEND_RINGS_MAX 4 1557 #endif 1558 #define BGE_SEND_RINGS_MAX_5705 1 1559 #define BGE_RECV_RINGS_MAX 16 1560 #define BGE_RECV_RINGS_MAX_5705 1 1561 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 1562 /* only with ext mem) */ 1563 1564 #define BGE_SEND_SLOTS_MAX 512 1565 #define BGE_STD_SLOTS_MAX 512 1566 #define BGE_JUMBO_SLOTS_MAX 256 1567 #define BGE_MINI_SLOTS_MAX 1024 1568 #define BGE_RECV_SLOTS_MAX 2048 1569 #define BGE_RECV_SLOTS_5705 512 1570 #define BGE_RECV_SLOTS_5782 512 1571 #define BGE_RECV_SLOTS_5721 512 1572 1573 /* 1574 * Hardware-defined Ring Control Block 1575 */ 1576 typedef struct { 1577 uint64_t host_ring_addr; 1578 #ifdef _BIG_ENDIAN 1579 uint16_t max_len; 1580 uint16_t flags; 1581 uint32_t nic_ring_addr; 1582 #else 1583 uint32_t nic_ring_addr; 1584 uint16_t flags; 1585 uint16_t max_len; 1586 #endif /* _BIG_ENDIAN */ 1587 } bge_rcb_t; 1588 1589 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 1590 #define RCB_FLAG_RING_DISABLED 0x0002 1591 1592 /* 1593 * Hardware-defined Send Buffer Descriptor 1594 */ 1595 typedef struct { 1596 uint64_t host_buf_addr; 1597 #ifdef _BIG_ENDIAN 1598 uint16_t len; 1599 uint16_t flags; 1600 uint16_t reserved; 1601 uint16_t vlan_tci; 1602 #else 1603 uint16_t vlan_tci; 1604 uint16_t reserved; 1605 uint16_t flags; 1606 uint16_t len; 1607 #endif /* _BIG_ENDIAN */ 1608 } bge_sbd_t; 1609 1610 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 1611 #define SBD_FLAG_IP_CKSUM 0x0002 1612 #define SBD_FLAG_PACKET_END 0x0004 1613 #define SBD_FLAG_IP_FRAG 0x0008 1614 #define SBD_FLAG_IP_FRAG_END 0x0010 1615 1616 #define SBD_FLAG_VLAN_TAG 0x0040 1617 #define SBD_FLAG_COAL_NOW 0x0080 1618 #define SBD_FLAG_CPU_PRE_DMA 0x0100 1619 #define SBD_FLAG_CPU_POST_DMA 0x0200 1620 1621 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 1622 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 1623 #define SBD_FLAG_DONT_GEN_CRC 0x8000 1624 1625 /* 1626 * Hardware-defined Receive Buffer Descriptor 1627 */ 1628 typedef struct { 1629 uint64_t host_buf_addr; 1630 #ifdef _BIG_ENDIAN 1631 uint16_t index; 1632 uint16_t len; 1633 uint16_t type; 1634 uint16_t flags; 1635 uint16_t ip_cksum; 1636 uint16_t tcp_udp_cksum; 1637 uint16_t error_flag; 1638 uint16_t vlan_tci; 1639 uint32_t reserved; 1640 uint32_t opaque; 1641 #else 1642 uint16_t flags; 1643 uint16_t type; 1644 uint16_t len; 1645 uint16_t index; 1646 uint16_t vlan_tci; 1647 uint16_t error_flag; 1648 uint16_t tcp_udp_cksum; 1649 uint16_t ip_cksum; 1650 uint32_t opaque; 1651 uint32_t reserved; 1652 #endif /* _BIG_ENDIAN */ 1653 } bge_rbd_t; 1654 1655 #define RBD_FLAG_STD_RING 0x0000 1656 #define RBD_FLAG_PACKET_END 0x0004 1657 1658 #define RBD_FLAG_JUMBO_RING 0x0020 1659 #define RBD_FLAG_VLAN_TAG 0x0040 1660 1661 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 1662 #define RBD_FLAG_MINI_RING 0x0800 1663 #define RBD_FLAG_IP_CHECKSUM 0x1000 1664 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 1665 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 1666 1667 #define RBD_FLAG_DEFAULT 0x0000 1668 1669 #define RBD_ERROR_BAD_CRC 0x00010000 1670 #define RBD_ERROR_COLL_DETECT 0x00020000 1671 #define RBD_ERROR_LINK_LOST 0x00040000 1672 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 1673 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 1674 #define RBD_ERROR_MAC_ABORT 0x00200000 1675 #define RBD_ERROR_LEN_LESS_64 0x00400000 1676 #define RBD_ERROR_TRUNC_NO_RES 0x00800000 1677 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 1678 1679 /* 1680 * Hardware-defined Status Block,Size of status block 1681 * is actually 0x50 bytes.Use 0x80 bytes for cache line 1682 * alignment.For BCM5705/5788/5721/5751/5752/5714 1683 * and 5715,there is only 1 recv and send ring index,but 1684 * driver defined 16 indexs here,please pay attention only 1685 * one ring is enabled in these chipsets. 1686 */ 1687 typedef struct { 1688 uint64_t flags_n_tag; 1689 uint16_t buff_cons_index[4]; 1690 struct { 1691 #ifdef _BIG_ENDIAN 1692 uint16_t send_cons_index; 1693 uint16_t recv_prod_index; 1694 #else 1695 uint16_t recv_prod_index; 1696 uint16_t send_cons_index; 1697 #endif /* _BIG_ENDIAN */ 1698 } index[16]; 1699 } bge_status_t; 1700 1701 /* 1702 * Hardware-defined Receive BD Rule 1703 */ 1704 typedef struct { 1705 uint32_t control; 1706 uint32_t mask_value; 1707 } bge_recv_rule_t; 1708 1709 /* 1710 * This describes which sub-rule slots are used by a particular rule. 1711 */ 1712 typedef struct { 1713 int start; 1714 int count; 1715 } bge_rule_info_t; 1716 1717 /* 1718 * Indexes into the <buff_cons_index> array 1719 */ 1720 #ifdef _BIG_ENDIAN 1721 #define STATUS_STD_BUFF_CONS_INDEX 0 1722 #define STATUS_JUMBO_BUFF_CONS_INDEX 1 1723 #define STATUS_MINI_BUFF_CONS_INDEX 3 1724 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 1725 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 1726 #else 1727 #define STATUS_STD_BUFF_CONS_INDEX 3 1728 #define STATUS_JUMBO_BUFF_CONS_INDEX 2 1729 #define STATUS_MINI_BUFF_CONS_INDEX 0 1730 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 1731 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 1732 #endif /* _BIG_ENDIAN */ 1733 1734 /* 1735 * Bits in the <flags_n_tag> word 1736 */ 1737 #define STATUS_FLAG_UPDATED 0x0000000100000000ull 1738 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 1739 #define STATUS_FLAG_ERROR 0x0000000400000000ull 1740 #define STATUS_TAG_MASK 0x00000000000000FFull 1741 1742 /* 1743 * The tag from the status block is fed back to Interrupt Mailbox 0 1744 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 1745 * lets the chip know what updates have been processed, so it can 1746 * reassert its interrupt if more updates have occurred since. 1747 * 1748 * These macros extract the tag from the <flags_n_tag> word, shift 1749 * it to the proper position in the Mailbox register, and provide 1750 * the complete values to write to INTERRUPT_MBOX_0_REG to disable 1751 * or enable interrupts 1752 */ 1753 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 1754 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 1755 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 1756 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 1757 1758 /* 1759 * Hardware-defined Statistics Block Offsets 1760 * 1761 * These are given in the manual as addresses in NIC memory, starting 1762 * from the NIC statistics area base address of 0x300; but here we 1763 * convert them into indexes into an array of (uint64_t)s, so we can 1764 * use them directly for accessing the copy of the statistics block 1765 * that the chip DMAs into main memory ... 1766 */ 1767 1768 #define KS_BASE 0x300 1769 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 1770 1771 typedef enum { 1772 KS_ifHCInOctets = KS_ADDR(0x400), 1773 KS_etherStatsFragments = KS_ADDR(0x410), 1774 KS_ifHCInUcastPkts, 1775 KS_ifHCInMulticastPkts, 1776 KS_ifHCInBroadcastPkts, 1777 KS_dot3StatsFCSErrors, 1778 KS_dot3StatsAlignmentErrors, 1779 KS_xonPauseFramesReceived, 1780 KS_xoffPauseFramesReceived, 1781 KS_macControlFramesReceived, 1782 KS_xoffStateEntered, 1783 KS_dot3StatsFrameTooLongs, 1784 KS_etherStatsJabbers, 1785 KS_etherStatsUndersizePkts, 1786 KS_inRangeLengthError, 1787 KS_outRangeLengthError, 1788 KS_etherStatsPkts64Octets, 1789 KS_etherStatsPkts65to127Octets, 1790 KS_etherStatsPkts128to255Octets, 1791 KS_etherStatsPkts256to511Octets, 1792 KS_etherStatsPkts512to1023Octets, 1793 KS_etherStatsPkts1024to1518Octets, 1794 KS_etherStatsPkts1519to2047Octets, 1795 KS_etherStatsPkts2048to4095Octets, 1796 KS_etherStatsPkts4096to8191Octets, 1797 KS_etherStatsPkts8192to9022Octets, 1798 1799 KS_ifHCOutOctets = KS_ADDR(0x600), 1800 KS_etherStatsCollisions = KS_ADDR(0x610), 1801 KS_outXonSent, 1802 KS_outXoffSent, 1803 KS_flowControlDone, 1804 KS_dot3StatsInternalMacTransmitErrors, 1805 KS_dot3StatsSingleCollisionFrames, 1806 KS_dot3StatsMultipleCollisionFrames, 1807 KS_dot3StatsDeferredTransmissions, 1808 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 1809 KS_dot3StatsLateCollisions, 1810 KS_dot3Collided2Times, 1811 KS_dot3Collided3Times, 1812 KS_dot3Collided4Times, 1813 KS_dot3Collided5Times, 1814 KS_dot3Collided6Times, 1815 KS_dot3Collided7Times, 1816 KS_dot3Collided8Times, 1817 KS_dot3Collided9Times, 1818 KS_dot3Collided10Times, 1819 KS_dot3Collided11Times, 1820 KS_dot3Collided12Times, 1821 KS_dot3Collided13Times, 1822 KS_dot3Collided14Times, 1823 KS_dot3Collided15Times, 1824 KS_ifHCOutUcastPkts, 1825 KS_ifHCOutMulticastPkts, 1826 KS_ifHCOutBroadcastPkts, 1827 KS_dot3StatsCarrierSenseErrors, 1828 KS_ifOutDiscards, 1829 KS_ifOutErrors, 1830 1831 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 1832 KS_COSIfHCInPkts_2, 1833 KS_COSIfHCInPkts_3, 1834 KS_COSIfHCInPkts_4, 1835 KS_COSIfHCInPkts_5, 1836 KS_COSIfHCInPkts_6, 1837 KS_COSIfHCInPkts_7, 1838 KS_COSIfHCInPkts_8, 1839 KS_COSIfHCInPkts_9, 1840 KS_COSIfHCInPkts_10, 1841 KS_COSIfHCInPkts_11, 1842 KS_COSIfHCInPkts_12, 1843 KS_COSIfHCInPkts_13, 1844 KS_COSIfHCInPkts_14, 1845 KS_COSIfHCInPkts_15, 1846 KS_COSIfHCInPkts_16, 1847 KS_COSFramesDroppedDueToFilters, 1848 KS_nicDmaWriteQueueFull, 1849 KS_nicDmaWriteHighPriQueueFull, 1850 KS_nicNoMoreRxBDs, 1851 KS_ifInDiscards, 1852 KS_ifInErrors, 1853 KS_nicRecvThresholdHit, 1854 1855 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 1856 KS_COSIfHCOutPkts_2, 1857 KS_COSIfHCOutPkts_3, 1858 KS_COSIfHCOutPkts_4, 1859 KS_COSIfHCOutPkts_5, 1860 KS_COSIfHCOutPkts_6, 1861 KS_COSIfHCOutPkts_7, 1862 KS_COSIfHCOutPkts_8, 1863 KS_COSIfHCOutPkts_9, 1864 KS_COSIfHCOutPkts_10, 1865 KS_COSIfHCOutPkts_11, 1866 KS_COSIfHCOutPkts_12, 1867 KS_COSIfHCOutPkts_13, 1868 KS_COSIfHCOutPkts_14, 1869 KS_COSIfHCOutPkts_15, 1870 KS_COSIfHCOutPkts_16, 1871 KS_nicDmaReadQueueFull, 1872 KS_nicDmaReadHighPriQueueFull, 1873 KS_nicSendDataCompQueueFull, 1874 KS_nicRingSetSendProdIndex, 1875 KS_nicRingStatusUpdate, 1876 KS_nicInterrupts, 1877 KS_nicAvoidedInterrupts, 1878 KS_nicSendThresholdHit, 1879 1880 KS_STATS_SIZE = KS_ADDR(0xb00) 1881 } bge_stats_offset_t; 1882 1883 /* 1884 * Hardware-defined Statistics Block 1885 * 1886 * Another view of the statistic block, as a array and a structure ... 1887 */ 1888 1889 typedef union { 1890 uint64_t a[KS_STATS_SIZE]; 1891 struct { 1892 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 1893 1894 uint64_t ifHCInOctets; /* 0x0400 */ 1895 uint64_t spare2[1]; 1896 uint64_t etherStatsFragments; 1897 uint64_t ifHCInUcastPkts; 1898 uint64_t ifHCInMulticastPkts; 1899 uint64_t ifHCInBroadcastPkts; 1900 uint64_t dot3StatsFCSErrors; 1901 uint64_t dot3StatsAlignmentErrors; 1902 uint64_t xonPauseFramesReceived; 1903 uint64_t xoffPauseFramesReceived; 1904 uint64_t macControlFramesReceived; 1905 uint64_t xoffStateEntered; 1906 uint64_t dot3StatsFrameTooLongs; 1907 uint64_t etherStatsJabbers; 1908 uint64_t etherStatsUndersizePkts; 1909 uint64_t inRangeLengthError; 1910 uint64_t outRangeLengthError; 1911 uint64_t etherStatsPkts64Octets; 1912 uint64_t etherStatsPkts65to127Octets; 1913 uint64_t etherStatsPkts128to255Octets; 1914 uint64_t etherStatsPkts256to511Octets; 1915 uint64_t etherStatsPkts512to1023Octets; 1916 uint64_t etherStatsPkts1024to1518Octets; 1917 uint64_t etherStatsPkts1519to2047Octets; 1918 uint64_t etherStatsPkts2048to4095Octets; 1919 uint64_t etherStatsPkts4096to8191Octets; 1920 uint64_t etherStatsPkts8192to9022Octets; 1921 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 1922 1923 uint64_t ifHCOutOctets; /* 0x0600 */ 1924 uint64_t spare4[1]; 1925 uint64_t etherStatsCollisions; 1926 uint64_t outXonSent; 1927 uint64_t outXoffSent; 1928 uint64_t flowControlDone; 1929 uint64_t dot3StatsInternalMacTransmitErrors; 1930 uint64_t dot3StatsSingleCollisionFrames; 1931 uint64_t dot3StatsMultipleCollisionFrames; 1932 uint64_t dot3StatsDeferredTransmissions; 1933 uint64_t spare5[1]; 1934 uint64_t dot3StatsExcessiveCollisions; 1935 uint64_t dot3StatsLateCollisions; 1936 uint64_t dot3Collided2Times; 1937 uint64_t dot3Collided3Times; 1938 uint64_t dot3Collided4Times; 1939 uint64_t dot3Collided5Times; 1940 uint64_t dot3Collided6Times; 1941 uint64_t dot3Collided7Times; 1942 uint64_t dot3Collided8Times; 1943 uint64_t dot3Collided9Times; 1944 uint64_t dot3Collided10Times; 1945 uint64_t dot3Collided11Times; 1946 uint64_t dot3Collided12Times; 1947 uint64_t dot3Collided13Times; 1948 uint64_t dot3Collided14Times; 1949 uint64_t dot3Collided15Times; 1950 uint64_t ifHCOutUcastPkts; 1951 uint64_t ifHCOutMulticastPkts; 1952 uint64_t ifHCOutBroadcastPkts; 1953 uint64_t dot3StatsCarrierSenseErrors; 1954 uint64_t ifOutDiscards; 1955 uint64_t ifOutErrors; 1956 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 1957 1958 uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 1959 uint64_t COSFramesDroppedDueToFilters; 1960 uint64_t nicDmaWriteQueueFull; 1961 uint64_t nicDmaWriteHighPriQueueFull; 1962 uint64_t nicNoMoreRxBDs; 1963 uint64_t ifInDiscards; 1964 uint64_t ifInErrors; 1965 uint64_t nicRecvThresholdHit; 1966 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 1967 1968 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 1969 uint64_t nicDmaReadQueueFull; 1970 uint64_t nicDmaReadHighPriQueueFull; 1971 uint64_t nicSendDataCompQueueFull; 1972 uint64_t nicRingSetSendProdIndex; 1973 uint64_t nicRingStatusUpdate; 1974 uint64_t nicInterrupts; 1975 uint64_t nicAvoidedInterrupts; 1976 uint64_t nicSendThresholdHit; 1977 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 1978 } s; 1979 } bge_statistics_t; 1980 1981 #define KS_STAT_REG_SIZE (0x1B) 1982 #define KS_STAT_REG_BASE (0x800) 1983 1984 typedef struct { 1985 uint32_t ifHCOutOctets; 1986 uint32_t etherStatsCollisions; 1987 uint32_t outXonSent; 1988 uint32_t outXoffSent; 1989 uint32_t dot3StatsInternalMacTransmitErrors; 1990 uint32_t dot3StatsSingleCollisionFrames; 1991 uint32_t dot3StatsMultipleCollisionFrames; 1992 uint32_t dot3StatsDeferredTransmissions; 1993 uint32_t dot3StatsExcessiveCollisions; 1994 uint32_t dot3StatsLateCollisions; 1995 uint32_t ifHCOutUcastPkts; 1996 uint32_t ifHCOutMulticastPkts; 1997 uint32_t ifHCOutBroadcastPkts; 1998 uint32_t ifHCInOctets; 1999 uint32_t etherStatsFragments; 2000 uint32_t ifHCInUcastPkts; 2001 uint32_t ifHCInMulticastPkts; 2002 uint32_t ifHCInBroadcastPkts; 2003 uint32_t dot3StatsFCSErrors; 2004 uint32_t dot3StatsAlignmentErrors; 2005 uint32_t xonPauseFramesReceived; 2006 uint32_t xoffPauseFramesReceived; 2007 uint32_t macControlFramesReceived; 2008 uint32_t xoffStateEntered; 2009 uint32_t dot3StatsFrameTooLongs; 2010 uint32_t etherStatsJabbers; 2011 uint32_t etherStatsUndersizePkts; 2012 } bge_statistics_reg_t; 2013 2014 2015 #ifdef BGE_IPMI_ASF 2016 2017 /* 2018 * Device internal memory entries 2019 */ 2020 2021 #define BGE_FIRMWARE_MAILBOX 0x0b50 2022 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 2023 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 2024 2025 2026 #define BGE_NIC_DATA_SIG_ADDR 0x0b54 2027 #define BGE_NIC_DATA_SIG 0x4b657654 2028 2029 2030 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 2031 2032 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 2033 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 2034 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 2035 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 2036 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 2037 2038 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 2039 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 2040 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 2041 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 2042 2043 #define BGE_NIC_CFG_ENABLE_WOL 0x000040 2044 #define BGE_NIC_CFG_ENABLE_ASF 0x000080 2045 #define BGE_NIC_CFG_EEPROM_WP 0x000100 2046 #define BGE_NIC_CFG_POWER_SAVING 0x000200 2047 #define BGE_NIC_CFG_SWAP_PORT 0x000800 2048 #define BGE_NIC_CFG_MINI_PCI 0x001000 2049 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 2050 #define BGE_NIC_CFG_5753_12x12 0x100000 2051 2052 2053 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 2054 2055 2056 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 2057 #define BGE_NIC_PHY_ID1_MASK 0xffff0000 2058 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 2059 2060 2061 #define BGE_CMD_MAILBOX 0x0b78 2062 #define BGE_CMD_NICDRV_ALIVE 0x00000001 2063 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 2064 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 2065 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 2066 2067 2068 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 2069 #define BGE_CMD_DATA_MAILBOX 0x0b80 2070 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 2071 2072 #define BGE_DRV_STATE_MAILBOX 0x0c04 2073 #define BGE_DRV_STATE_START 0x00000001 2074 #define BGE_DRV_STATE_START_DONE 0x80000001 2075 #define BGE_DRV_STATE_UNLOAD 0x00000002 2076 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 2077 #define BGE_DRV_STATE_WOL 0x00000003 2078 #define BGE_DRV_STATE_SUSPEND 0x00000004 2079 2080 2081 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 2082 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 2083 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 2084 2085 2086 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 2087 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 2088 2089 2090 /* 2091 * RX-RISC event register 2092 */ 2093 #define RX_RISC_EVENT_REG 0x6810 2094 #define RRER_ASF_EVENT 0x4000 2095 2096 #endif /* BGE_IPMI_ASF */ 2097 2098 #ifdef __cplusplus 2099 } 2100 #endif 2101 2102 #endif /* _BGE_HW_H */ 2103