1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _BGE_HW_H 28 #define _BGE_HW_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 38 39 /* 40 * First section: 41 * Identification of the various Broadcom chips 42 * 43 * Note: the various ID values are *not* all unique ;-( 44 * 45 * Note: the presence of an ID here does *not* imply that the chip is 46 * supported. At this time, only the 5703C, 5704C, and 5704S devices 47 * used on the motherboards of certain Sun products are supported. 48 * 49 * Note: the revision-id values in the PCI revision ID register are 50 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 51 */ 52 53 #define VENDOR_ID_BROADCOM 0x14e4 54 #define VENDOR_ID_SUN 0x108e 55 56 #define DEVICE_ID_5700 0x1644 57 #define DEVICE_ID_5700x 0x0003 58 #define DEVICE_ID_5701 0x1645 59 #define DEVICE_ID_5702 0x16a6 60 #define DEVICE_ID_5702fe 0x164d 61 #define DEVICE_ID_5703C 0x1647 62 #define DEVICE_ID_5703S 0x16a7 63 #define DEVICE_ID_5703 0x16c7 64 #define DEVICE_ID_5704C 0x1648 65 #define DEVICE_ID_5704S 0x16a8 66 #define DEVICE_ID_5704 0x1649 67 #define DEVICE_ID_5705C 0x1653 68 #define DEVICE_ID_5705_2 0x1654 69 #define DEVICE_ID_5705M 0x165d 70 #define DEVICE_ID_5705MA3 0x165e 71 #define DEVICE_ID_5705F 0x166e 72 #define DEVICE_ID_5706 0x164a 73 #define DEVICE_ID_5782 0x1696 74 #define DEVICE_ID_5788 0x169c 75 #define DEVICE_ID_5789 0x169d 76 #define DEVICE_ID_5751 0x1677 77 #define DEVICE_ID_5751M 0x167d 78 #define DEVICE_ID_5752 0x1600 79 #define DEVICE_ID_5752M 0x1601 80 #define DEVICE_ID_5753 0x16fd 81 #define DEVICE_ID_5754 0x167a 82 #define DEVICE_ID_5755 0x167b 83 #define DEVICE_ID_5721 0x1659 84 #define DEVICE_ID_5714C 0x1668 85 #define DEVICE_ID_5714S 0x1669 86 #define DEVICE_ID_5715C 0x1678 87 #define DEVICE_ID_5715S 0x1679 88 89 #define REVISION_ID_5700_B0 0x10 90 #define REVISION_ID_5700_B2 0x12 91 #define REVISION_ID_5700_B3 0x13 92 #define REVISION_ID_5700_C0 0x20 93 #define REVISION_ID_5700_C1 0x21 94 #define REVISION_ID_5700_C2 0x22 95 96 #define REVISION_ID_5701_A0 0x08 97 #define REVISION_ID_5701_A2 0x12 98 #define REVISION_ID_5701_A3 0x15 99 100 #define REVISION_ID_5702_A0 0x00 101 102 #define REVISION_ID_5703_A0 0x00 103 #define REVISION_ID_5703_A1 0x01 104 #define REVISION_ID_5703_A2 0x02 105 106 #define REVISION_ID_5704_A0 0x00 107 #define REVISION_ID_5704_A1 0x01 108 #define REVISION_ID_5704_A2 0x02 109 #define REVISION_ID_5704_A3 0x03 110 #define REVISION_ID_5704_B0 0x10 111 112 #define REVISION_ID_5705_A0 0x00 113 #define REVISION_ID_5705_A1 0x01 114 #define REVISION_ID_5705_A2 0x02 115 #define REVISION_ID_5705_A3 0x03 116 117 #define REVISION_ID_5721_A0 0x00 118 #define REVISION_ID_5721_A1 0x01 119 120 #define REVISION_ID_5751_A0 0x00 121 #define REVISION_ID_5751_A1 0x01 122 123 #define REVISION_ID_5714_A0 0x00 124 #define REVISION_ID_5714_A1 0x01 125 #define REVISION_ID_5714_A2 0xA2 126 #define REVISION_ID_5714_A3 0xA3 127 128 #define REVISION_ID_5715_A0 0x00 129 #define REVISION_ID_5715_A1 0x01 130 #define REVISION_ID_5715_A2 0xA2 131 132 #define REVISION_ID_5715S_A0 0x00 133 #define REVISION_ID_5715S_A1 0x01 134 135 #define REVISION_ID_5754_A0 0x00 136 #define REVISION_ID_5754_A1 0x01 137 138 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 139 ((bgep->chipid.device == DEVICE_ID_5700) ||\ 140 (bgep->chipid.device == DEVICE_ID_5701) ||\ 141 (bgep->chipid.device == DEVICE_ID_5702) ||\ 142 (bgep->chipid.device == DEVICE_ID_5702fe)||\ 143 (bgep->chipid.device == DEVICE_ID_5703C) ||\ 144 (bgep->chipid.device == DEVICE_ID_5703S) ||\ 145 (bgep->chipid.device == DEVICE_ID_5703) ||\ 146 (bgep->chipid.device == DEVICE_ID_5704C) ||\ 147 (bgep->chipid.device == DEVICE_ID_5704S) ||\ 148 (bgep->chipid.device == DEVICE_ID_5704)) 149 150 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 151 ((bgep->chipid.device == DEVICE_ID_5702) ||\ 152 (bgep->chipid.device == DEVICE_ID_5702fe)) 153 154 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 155 ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 156 (bgep->chipid.device == DEVICE_ID_5705M) ||\ 157 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 158 (bgep->chipid.device == DEVICE_ID_5705F) ||\ 159 (bgep->chipid.device == DEVICE_ID_5782) ||\ 160 (bgep->chipid.device == DEVICE_ID_5788) ||\ 161 (bgep->chipid.device == DEVICE_ID_5705_2) ||\ 162 (bgep->chipid.device == DEVICE_ID_5754) ||\ 163 (bgep->chipid.device == DEVICE_ID_5755) ||\ 164 (bgep->chipid.device == DEVICE_ID_5753)) 165 166 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 167 ((bgep->chipid.device == DEVICE_ID_5721) ||\ 168 (bgep->chipid.device == DEVICE_ID_5751) ||\ 169 (bgep->chipid.device == DEVICE_ID_5751M) ||\ 170 (bgep->chipid.device == DEVICE_ID_5752) ||\ 171 (bgep->chipid.device == DEVICE_ID_5752M) ||\ 172 (bgep->chipid.device == DEVICE_ID_5789)) 173 174 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 175 ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 176 (bgep->chipid.device == DEVICE_ID_5714S) ||\ 177 (bgep->chipid.device == DEVICE_ID_5715C) ||\ 178 (bgep->chipid.device == DEVICE_ID_5715S)) 179 180 /* 181 * Second section: 182 * Offsets of important registers & definitions for bits therein 183 */ 184 185 /* 186 * PCI-X registers & bits 187 */ 188 #define PCIX_CONF_COMM 0x42 189 #define PCIX_COMM_RELAXED 0x0002 190 191 /* 192 * Miscellaneous Host Control Register, in PCI config space 193 */ 194 #define PCI_CONF_BGE_MHCR 0x68 195 #define MHCR_CHIP_REV_MASK 0xffff0000 196 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 197 #define MHCR_MASK_INTERRUPT_MODE 0x00000100 198 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 199 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 200 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 201 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010 202 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 203 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 204 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 205 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 206 207 #define MHCR_CHIP_REV_5700_B0 0x71000000 208 #define MHCR_CHIP_REV_5700_B2 0x71020000 209 #define MHCR_CHIP_REV_5700_B3 0x71030000 210 #define MHCR_CHIP_REV_5700_C0 0x72000000 211 #define MHCR_CHIP_REV_5700_C1 0x72010000 212 #define MHCR_CHIP_REV_5700_C2 0x72020000 213 214 #define MHCR_CHIP_REV_5701_A0 0x00000000 215 #define MHCR_CHIP_REV_5701_A2 0x00020000 216 #define MHCR_CHIP_REV_5701_A3 0x00030000 217 #define MHCR_CHIP_REV_5701_A5 0x01050000 218 219 #define MHCR_CHIP_REV_5702_A0 0x10000000 220 #define MHCR_CHIP_REV_5702_A1 0x10010000 221 #define MHCR_CHIP_REV_5702_A2 0x10020000 222 223 #define MHCR_CHIP_REV_5703_A0 0x10000000 224 #define MHCR_CHIP_REV_5703_A1 0x10010000 225 #define MHCR_CHIP_REV_5703_A2 0x10020000 226 #define MHCR_CHIP_REV_5703_B0 0x11000000 227 #define MHCR_CHIP_REV_5703_B1 0x11010000 228 229 #define MHCR_CHIP_REV_5704_A0 0x20000000 230 #define MHCR_CHIP_REV_5704_A1 0x20010000 231 #define MHCR_CHIP_REV_5704_A2 0x20020000 232 #define MHCR_CHIP_REV_5704_A3 0x20030000 233 #define MHCR_CHIP_REV_5704_B0 0x21000000 234 235 #define MHCR_CHIP_REV_5705_A0 0x30000000 236 #define MHCR_CHIP_REV_5705_A1 0x30010000 237 #define MHCR_CHIP_REV_5705_A2 0x30020000 238 #define MHCR_CHIP_REV_5705_A3 0x30030000 239 #define MHCR_CHIP_REV_5705_A5 0x30050000 240 241 #define MHCR_CHIP_REV_5782_A0 0x30030000 242 #define MHCR_CHIP_REV_5782_A1 0x30030088 243 244 #define MHCR_CHIP_REV_5788_A1 0x30050000 245 246 #define MHCR_CHIP_REV_5751_A0 0x40000000 247 #define MHCR_CHIP_REV_5751_A1 0x40010000 248 249 #define MHCR_CHIP_REV_5721_A0 0x41000000 250 #define MHCR_CHIP_REV_5721_A1 0x41010000 251 252 #define MHCR_CHIP_REV_5714_A0 0x50000000 253 #define MHCR_CHIP_REV_5714_A1 0x90010000 254 255 #define MHCR_CHIP_REV_5715_A0 0x50000000 256 #define MHCR_CHIP_REV_5715_A1 0x90010000 257 258 #define MHCR_CHIP_REV_5715S_A0 0x50000000 259 #define MHCR_CHIP_REV_5715S_A1 0x90010000 260 261 #define MHCR_CHIP_REV_5754_A0 0xb0000000 262 #define MHCR_CHIP_REV_5754_A1 0xb0010000 263 264 #define MHCR_CHIP_REV_5755_A0 0xa0000000 265 #define MHCR_CHIP_REV_5755_A1 0xa0010000 266 267 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000) 268 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 269 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 270 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 271 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 272 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 273 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 274 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 275 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 276 #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28) 277 #define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28) 278 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 279 280 281 /* 282 * PCI DMA read/write Control Register, in PCI config space 283 * 284 * Note that several fields previously defined here have been deleted 285 * as they are not implemented in the 5703/4. 286 * 287 * Note: the value of this register is critical. It is possible to 288 * cause various unpleasant effects (DTOs, transaction deadlock, etc) 289 * by programming the wrong value. The value #defined below has been 290 * tested and shown to avoid all known problems. If it is to be changed, 291 * correct operation must be reverified on all supported platforms. 292 * 293 * In particular, we set both watermark fields to 2xCacheLineSize (128) 294 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 295 * with Tomatillo's internal pipelines, that otherwise result in stalls, 296 * repeated retries, and DTOs. 297 */ 298 #define PCI_CONF_BGE_PDRWCR 0x6c 299 #define PDRWCR_RWCMD_MASK 0xFF000000 300 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 301 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 302 #define PDRWCR_READ_WATERMARK_MASK 0x00070000 303 #define PDRWCR_CONCURRENCY_MASK 0x0000c000 304 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 305 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 306 #define PDRWCR_MIN_BEAT_MASK 0x000000ff 307 308 /* 309 * These are the actual values to be put into the fields shown above 310 */ 311 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 312 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 313 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 314 #define PDRWCR_MIN_BEATS 0x00000000 315 316 #define PDRWCR_VAR_DEFAULT 0x761b0000 317 #define PDRWCR_VAR_5721 0x76180000 318 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 319 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 320 321 /* 322 * PCI State Register, in PCI config space 323 * 324 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 325 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 326 */ 327 #define PCI_CONF_BGE_PCISTATE 0x70 328 #define PCISTATE_RETRY_SAME_DMA 0x00002000 329 #define PCISTATE_FLAT_VIEW 0x00000100 330 #define PCISTATE_EXT_ROM_RETRY 0x00000040 331 #define PCISTATE_EXT_ROM_ENABLE 0x00000020 332 #define PCISTATE_BUS_IS_32_BIT 0x00000010 333 #define PCISTATE_BUS_IS_FAST 0x00000008 334 #define PCISTATE_BUS_IS_PCI 0x00000004 335 #define PCISTATE_INTA_STATE 0x00000002 336 #define PCISTATE_FORCE_RESET 0x00000001 337 338 /* 339 * PCI Clock Control Register, in PCI config space 340 */ 341 #define PCI_CONF_BGE_CLKCTL 0x74 342 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 343 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 344 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 345 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 346 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 347 #define CLKCTL_PCIE_A0_FIX 0x00101000 348 349 /* 350 * Dual MAC Control Register, in PCI config space 351 */ 352 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 353 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 354 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 355 356 /* 357 * Register Indirect Access Address Register, 0x78 in PCI config 358 * space. Once this is set, accesses to the Register Indirect 359 * Access Data Register (0x80) refer to the register whose address 360 * is given by *this* register. This allows access to all the 361 * operating registers, while using only config space accesses. 362 * 363 * Note that the address written to the RIIAR should lie in one 364 * of the following ranges: 365 * 0x00000000 <= address < 0x00008000 (regular registers) 366 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 367 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 368 * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 369 */ 370 #define PCI_CONF_BGE_RIAAR 0x78 371 #define PCI_CONF_BGE_RIADR 0x80 372 373 #define RIAAR_REGISTER_MIN 0x00000000 374 #define RIAAR_REGISTER_MAX 0x00008000 375 #define RIAAR_RX_SCRATCH_MIN 0x00030000 376 #define RIAAR_RX_SCRATCH_MAX 0x00034000 377 #define RIAAR_TX_SCRATCH_MIN 0x00034000 378 #define RIAAR_TX_SCRATCH_MAX 0x00038000 379 #define RIAAR_RXROM_MIN 0x00038000 380 #define RIAAR_RXROM_MAX 0x00038800 381 382 /* 383 * Memory Window Base Address Register, 0x7c in PCI config space 384 * Once this is set, accesses to the Memory Window Data Access Register 385 * (0x84) refer to the word of NIC-local memory whose address is given 386 * by this register. When used in this way, the whole of the address 387 * written to this register is significant. 388 * 389 * This register also provides the 32K-aligned base address for a 32K 390 * region of NIC-local memory that the host can directly address in 391 * the upper 32K of the 64K of PCI memory space allocated to the chip. 392 * In this case, the bottom 15 bits of the register are ignored. 393 * 394 * Note that the address written to the MWBAR should lie in the range 395 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 396 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 397 * memory were present, but it's only supported on the 5700, not the 398 * 5701/5703/5704. 399 */ 400 #define PCI_CONF_BGE_MWBAR 0x7c 401 #define PCI_CONF_BGE_MWDAR 0x84 402 #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 403 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 404 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 405 406 /* 407 * The PCI express device control register and device status register 408 * which are only applicable on BCM5751 and BCM5721. 409 */ 410 #define PCI_CONF_DEV_CTRL 0xd8 411 #define READ_REQ_SIZE_MAX 0x5000 412 #define DEV_CTRL_NO_SNOOP 0x0800 413 #define DEV_CTRL_RELAXED 0x0010 414 415 #define PCI_CONF_DEV_STUS 0xda 416 #define DEVICE_ERROR_STUS 0xf 417 418 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 419 420 /* 421 * Where to find things in NIC-local (on-chip) memory 422 */ 423 #define NIC_MEM_SEND_RINGS 0x0100 424 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 425 #define NIC_MEM_RECV_RINGS 0x0200 426 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 427 #define NIC_MEM_STATISTICS 0x0300 428 #define NIC_MEM_STATISTICS_SIZE 0x0800 429 #define NIC_MEM_STATUS_BLOCK 0x0b00 430 #define NIC_MEM_STATUS_SIZE 0x0050 431 #define NIC_MEM_GENCOMM 0x0b50 432 433 434 /* 435 * Note: the (non-bogus) values below are appropriate for systems 436 * without external memory. They would be different on a 5700 with 437 * external memory. 438 * 439 * Note: The higher send ring addresses and the mini ring shadow 440 * buffer address are dummies - systems without external memory 441 * are limited to 4 send rings and no mini receive ring. 442 */ 443 #define NIC_MEM_SHADOW_DMA 0x2000 444 #define NIC_MEM_SHADOW_SEND_1_4 0x4000 445 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 446 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 447 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 448 #define NIC_MEM_SHADOW_BUFF_STD 0x6000 449 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 450 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 451 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 452 453 /* 454 * Put this in the GENCOMM port to tell the firmware not to run PXE 455 */ 456 #define T3_MAGIC_NUMBER 0x4b657654u 457 458 /* 459 * The remaining registers appear in the low 32K of regular 460 * PCI Memory Address Space 461 */ 462 463 /* 464 * All the state machine control registers below have at least a 465 * <RESET> bit and an <ENABLE> bit as defined below. Some also 466 * have an <ATTN_ENABLE> bit. 467 */ 468 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 469 #define STATE_MACHINE_ENABLE_BIT 0x00000002 470 #define STATE_MACHINE_RESET_BIT 0x00000001 471 472 #define TRANSMIT_MAC_MODE_REG 0x045c 473 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 474 #define SEND_DATA_COMPLETION_MODE_REG 0x1000 475 #define SEND_BD_SELECTOR_MODE_REG 0x1400 476 #define SEND_BD_INITIATOR_MODE_REG 0x1800 477 #define SEND_BD_COMPLETION_MODE_REG 0x1c00 478 479 #define RECEIVE_MAC_MODE_REG 0x0468 480 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 481 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 482 #define RCV_DATA_COMPLETION_MODE_REG 0x2800 483 #define RCV_BD_INITIATOR_MODE_REG 0x2c00 484 #define RCV_BD_COMPLETION_MODE_REG 0x3000 485 #define RCV_LIST_SELECTOR_MODE_REG 0x3400 486 487 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 488 #define HOST_COALESCE_MODE_REG 0x3c00 489 #define MEMORY_ARBITER_MODE_REG 0x4000 490 #define BUFFER_MANAGER_MODE_REG 0x4400 491 #define READ_DMA_MODE_REG 0x4800 492 #define WRITE_DMA_MODE_REG 0x4c00 493 #define DMA_COMPLETION_MODE_REG 0x6400 494 495 /* 496 * Other bits in some of the above state machine control registers 497 */ 498 499 /* 500 * Transmit MAC Mode Register 501 * (TRANSMIT_MAC_MODE_REG, 0x045c) 502 */ 503 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 504 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 505 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 506 507 /* 508 * Receive MAC Mode Register 509 * (RECEIVE_MAC_MODE_REG, 0x0468) 510 */ 511 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 512 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 513 #define RECEIVE_MODE_PROMISCUOUS 0x00000100 514 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 515 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 516 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 517 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 518 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 519 520 /* 521 * Receive BD Initiator Mode Register 522 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 523 * 524 * Each of these bits controls whether ATTN is asserted 525 * on a particular condition 526 */ 527 #define RCV_BD_DISABLED_RING_ATTN 0x00000004 528 529 /* 530 * Receive Data & Receive BD Initiator Mode Register 531 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 532 * 533 * Each of these bits controls whether ATTN is asserted 534 * on a particular condition 535 */ 536 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 537 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 538 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 539 540 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 541 542 /* 543 * Host Coalescing Mode Control Register 544 * (HOST_COALESCE_MODE_REG, 0x3c00) 545 */ 546 #define COALESCE_64_BYTE_RINGS 12 547 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 548 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 549 #define COALESCE_CLR_TICKS_TX 0x00000400 550 #define COALESCE_CLR_TICKS_RX 0x00000200 551 #define COALESCE_32_BYTE_STATUS 0x00000100 552 #define COALESCE_64_BYTE_STATUS 0x00000080 553 #define COALESCE_NOW 0x00000008 554 555 /* 556 * Memory Arbiter Mode Register 557 * (MEMORY_ARBITER_MODE_REG, 0x4000) 558 */ 559 #define MEMORY_ARBITER_ENABLE 0x00000002 560 561 /* 562 * Buffer Manager Mode Register 563 * (BUFFER_MANAGER_MODE_REG, 0x4400) 564 * 565 * In addition to the usual error-attn common to most state machines 566 * this register has a separate bit for attn on running-low-on-mbufs 567 */ 568 #define BUFF_MGR_TEST_MODE 0x00000008 569 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 570 571 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 572 573 /* 574 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 575 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 576 * 577 * These registers each contain a 2-bit priority field, which controls 578 * the relative priority of that type of DMA (read vs. write vs. MSI), 579 * and a set of bits that control whether ATTN is asserted on each 580 * particular condition 581 */ 582 #define DMA_PRIORITY_MASK 0xc0000000 583 #define DMA_PRIORITY_SHIFT 30 584 #define ALL_DMA_ATTN_BITS 0x000003fc 585 586 /* 587 * BCM5755, 5755M, 5906, 5906M only 588 * 1 - Enable Fix. Device will send out the status block before 589 * the interrupt message 590 * 0 - Disable fix. Device will send out the interrupt message 591 * before the status block 592 */ 593 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000 594 595 /* 596 * End of state machine control register definitions 597 */ 598 599 600 /* 601 * Mailbox Registers (8 bytes each, but high half unused) 602 */ 603 #define INTERRUPT_MBOX_0_REG 0x0200 604 #define INTERRUPT_MBOX_1_REG 0x0208 605 #define INTERRUPT_MBOX_2_REG 0x0210 606 #define INTERRUPT_MBOX_3_REG 0x0218 607 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 608 609 /* 610 * Ring Producer/Consumer Index (Mailbox) Registers 611 */ 612 #define RECV_STD_PROD_INDEX_REG 0x0268 613 #define RECV_JUMBO_PROD_INDEX_REG 0x0270 614 #define RECV_MINI_PROD_INDEX_REG 0x0278 615 #define RECV_RING_CONS_INDEX_REGS 0x0280 616 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 617 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 618 619 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 620 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 621 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 622 623 /* 624 * Ethernet MAC Mode Register 625 */ 626 #define ETHERNET_MAC_MODE_REG 0x0400 627 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 628 #define ETHERNET_MODE_ENABLE_RDE 0x00400000 629 #define ETHERNET_MODE_ENABLE_TDE 0x00200000 630 #define ETHERNET_MODE_ENABLE_MIP 0x00100000 631 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 632 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 633 #define ETHERNET_MODE_SEND_CFGS 0x00020000 634 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 635 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 636 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 637 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 638 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 639 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 640 #define ETHERNET_MODE_LINK_POLARITY 0x00000400 641 #define ETHERNET_MODE_MAX_DEFER 0x00000200 642 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 643 #define ETHERNET_MODE_TAGGED_MODE 0x00000080 644 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 645 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 646 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 647 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 648 #define ETHERNET_MODE_PORTMODE_MII 0x00000004 649 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 650 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 651 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 652 653 /* 654 * Ethernet MAC Status & Event Registers 655 */ 656 #define ETHERNET_MAC_STATUS_REG 0x0404 657 #define ETHERNET_STATUS_MI_INT 0x00800000 658 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 659 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 660 #define ETHERNET_STATUS_PCS_ERROR 0x00000400 661 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 662 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 663 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 664 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 665 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 666 667 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 668 #define ETHERNET_EVENT_MI_INT 0x00800000 669 #define ETHERNET_EVENT_LINK_INT 0x00001000 670 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 671 672 /* 673 * Ethernet MAC LED Control Register 674 * 675 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 676 * the external LED driver circuitry is wired up to assume that this mode 677 * will always be selected. Software must not change it! 678 */ 679 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 680 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 681 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 682 #define LED_CONTROL_LED_MODE_MASK 0x00001800 683 #define LED_CONTROL_LED_MODE_5700 0x00000000 684 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 685 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 686 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 687 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 688 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 689 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 690 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 691 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 692 #define LED_CONTROL_TRAFFIC_LED 0x00000020 693 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 694 #define LED_CONTROL_10MBPS_LED 0x00000008 695 #define LED_CONTROL_100MBPS_LED 0x00000004 696 #define LED_CONTROL_1000MBPS_LED 0x00000002 697 #define LED_CONTROL_OVERRIDE_LINK 0x00000001 698 #define LED_CONTROL_DEFAULT 0x02000800 699 700 /* 701 * MAC Address registers 702 * 703 * These four eight-byte registers each hold one unicast address 704 * (six bytes), right justified & zero-filled on the left. 705 * They will normally all be set to the same value, as a station 706 * usually only has one h/w address. The value in register 0 is 707 * used for pause packets; any of the four can be specified for 708 * substitution into other transmitted packets if required. 709 */ 710 #define MAC_ADDRESS_0_REG 0x0410 711 #define MAC_ADDRESS_1_REG 0x0418 712 #define MAC_ADDRESS_2_REG 0x0420 713 #define MAC_ADDRESS_3_REG 0x0428 714 715 #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 716 #define MAC_ADDRESS_REGS_MAX 4 717 718 /* 719 * More MAC Registers ... 720 */ 721 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 722 #define MAC_RX_MTU_SIZE_REG 0x043c 723 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 724 #define MAC_TX_LENGTHS_REG 0x0464 725 #define MAC_TX_LENGTHS_DEFAULT 0x00002620 726 727 /* 728 * MII access registers 729 */ 730 #define MI_COMMS_REG 0x044c 731 #define MI_COMMS_START 0x20000000 732 #define MI_COMMS_READ_FAILED 0x10000000 733 #define MI_COMMS_COMMAND_MASK 0x0c000000 734 #define MI_COMMS_COMMAND_READ 0x08000000 735 #define MI_COMMS_COMMAND_WRITE 0x04000000 736 #define MI_COMMS_ADDRESS_MASK 0x03e00000 737 #define MI_COMMS_ADDRESS_SHIFT 21 738 #define MI_COMMS_REGISTER_MASK 0x001f0000 739 #define MI_COMMS_REGISTER_SHIFT 16 740 #define MI_COMMS_DATA_MASK 0x0000ffff 741 #define MI_COMMS_DATA_SHIFT 0 742 743 #define MI_STATUS_REG 0x0450 744 #define MI_STATUS_10MBPS 0x00000002 745 #define MI_STATUS_LINK 0x00000001 746 747 #define MI_MODE_REG 0x0454 748 #define MI_MODE_CLOCK_MASK 0x001f0000 749 #define MI_MODE_AUTOPOLL 0x00000010 750 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 751 #define MI_MODE_DEFAULT 0x000c0000 752 753 #define MI_AUTOPOLL_STATUS_REG 0x0458 754 #define MI_AUTOPOLL_ERROR 0x00000001 755 756 #define TRANSMIT_MAC_STATUS_REG 0x0460 757 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 758 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 759 #define TRANSMIT_STATUS_LINK_UP 0x00000008 760 #define TRANSMIT_STATUS_SENT_XON 0x00000004 761 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 762 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 763 764 #define RECEIVE_MAC_STATUS_REG 0x046c 765 #define RECEIVE_STATUS_RCVD_XON 0x00000004 766 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 767 #define RECEIVE_STATUS_SENT_XOFF 0x00000001 768 769 /* 770 * These four-byte registers constitute a hash table for deciding 771 * whether to accept incoming multicast packets. The bits are 772 * numbered in big-endian fashion, from hash 0 => the MSB of 773 * register 0 to hash 127 => the LSB of the highest-numbered 774 * register. 775 * 776 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 777 * enabled by setting the appropriate bit in the Rx MAC mode 778 * register. Otherwise, and on all earlier chips, the table 779 * is only 128 bits (registers 0-3). 780 */ 781 #define MAC_HASH_0_REG 0x0470 782 #define MAC_HASH_1_REG 0x0474 783 #define MAC_HASH_2_REG 0x0478 784 #define MAC_HASH_3_REG 0x047c 785 #define MAC_HASH_4_REG 0x???? 786 #define MAC_HASH_5_REG 0x???? 787 #define MAC_HASH_6_REG 0x???? 788 #define MAC_HASH_7_REG 0x???? 789 #define MAC_HASH_REG(n) (0x470+4*(n)) 790 791 /* 792 * Receive Rules Registers: 16 pairs of control+mask/value pairs 793 */ 794 #define RCV_RULES_CONTROL_0_REG 0x0480 795 #define RCV_RULES_MASK_0_REG 0x0484 796 #define RCV_RULES_CONTROL_15_REG 0x04f8 797 #define RCV_RULES_MASK_15_REG 0x04fc 798 #define RCV_RULES_CONFIG_REG 0x0500 799 #define RCV_RULES_CONFIG_DEFAULT 0x00000008 800 801 #define RECV_RULES_NUM_MAX 16 802 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 803 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 804 805 #define RECV_RULE_CTL_ENABLE 0x80000000 806 #define RECV_RULE_CTL_AND 0x40000000 807 #define RECV_RULE_CTL_P1 0x20000000 808 #define RECV_RULE_CTL_P2 0x10000000 809 #define RECV_RULE_CTL_P3 0x08000000 810 #define RECV_RULE_CTL_MASK 0x04000000 811 #define RECV_RULE_CTL_DISCARD 0x02000000 812 #define RECV_RULE_CTL_MAP 0x01000000 813 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 814 #define RECV_RULE_CTL_OP 0x00030000 815 #define RECV_RULE_CTL_OP_EQ 0x00000000 816 #define RECV_RULE_CTL_OP_NEQ 0x00010000 817 #define RECV_RULE_CTL_OP_GREAT 0x00020000 818 #define RECV_RULE_CTL_OP_LESS 0x00030000 819 #define RECV_RULE_CTL_HEADER 0x0000e000 820 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 821 #define RECV_RULE_CTL_HEADER_IP 0x00002000 822 #define RECV_RULE_CTL_HEADER_TCP 0x00004000 823 #define RECV_RULE_CTL_HEADER_UDP 0x00006000 824 #define RECV_RULE_CTL_HEADER_DATA 0x00008000 825 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 826 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 827 RECV_RULE_CTL_CLASS_BITS) 828 #define RECV_RULE_CTL_OFFSET 0x000000ff 829 830 /* 831 * Receive Rules definition 832 */ 833 #define RULE_MATCH_TO_RING 2 834 /* ring that traffic will go into when recv rule matches. */ 835 /* value is between 1 and 16, not 0 and 15 */ 836 837 #define IPHEADER_PROTO_OFFSET 0x08 838 #define IPHEADER_SIP_OFFSET 0x0c 839 840 #define RULE_PROTO_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_MASK | \ 841 RECV_RULE_CTL_OP_EQ | \ 842 RECV_RULE_CTL_HEADER_IP | \ 843 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 844 IPHEADER_PROTO_OFFSET) 845 #define RULE_TCP_MASK_VALUE 0x00ff0006 846 #define RULE_UDP_MASK_VALUE 0x00ff0011 847 #define RULE_ICMP_MASK_VALUE 0x00ff0001 848 849 #define RULE_SIP_ADDR 0x0a000001 850 /* ip address in 32-bit integer,such as, 0x0a000001 is "10.0.0.1" */ 851 852 #define RULE_SIP_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 853 RECV_RULE_CTL_HEADER_IP | \ 854 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 855 IPHEADER_SIP_OFFSET) 856 #define RULE_SIP_MASK_VALUE RULE_SIP_ADDR 857 858 /* 859 * 1000BaseX low-level access registers 860 */ 861 #define MAC_GIGABIT_PCS_TEST_REG 0x0440 862 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 863 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 864 #define TX_1000BASEX_AUTONEG_REG 0x0444 865 #define RX_1000BASEX_AUTONEG_REG 0x0448 866 867 /* 868 * Autoneg code bits for the 1000BASE-X AUTONEG registers 869 */ 870 #define AUTONEG_CODE_PAUSE 0x00008000 871 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 872 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 873 #define AUTONEG_CODE_NEXT_PAGE 0x00000080 874 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 875 #define AUTONEG_CODE_FAULT_MASK 0x00000030 876 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 877 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 878 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 879 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 880 881 /* 882 * SerDes Registers (5703S/5704S only) 883 */ 884 #define SERDES_CONTROL_REG 0x0590 885 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 886 #define SERDES_CONTROL_COMMA_DETECT 0x00010000 887 #define SERDES_CONTROL_TX_DISABLE 0x00004000 888 #define SERDES_STATUS_REG 0x0594 889 #define SERDES_STATUS_COMMA_DETECTED 0x00000100 890 #define SERDES_STATUS_RXSTAT 0x000000ff 891 892 /* 893 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 894 */ 895 #define STAT_IFHCOUT_OCTETS_REG 0x0800 896 #define STAT_ETHER_COLLIS_REG 0x0808 897 #define STAT_OUTXON_SENT_REG 0x080c 898 #define STAT_OUTXOFF_SENT_REG 0x0810 899 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 900 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 901 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 902 #define STAT_DOT3_DEFERED_TX_REG 0x0824 903 #define STAT_DOT3_EXCE_COLLI_REG 0x082c 904 #define STAT_DOT3_LATE_COLLI_REG 0x0830 905 #define STAT_IFHCOUT_UPKGS_REG 0x086c 906 #define STAT_IFHCOUT_MPKGS_REG 0x0870 907 #define STAT_IFHCOUT_BPKGS_REG 0x0874 908 909 #define STAT_IFHCIN_OCTETS_REG 0x0880 910 #define STAT_ETHER_FRAGMENT_REG 0x0888 911 #define STAT_IFHCIN_UPKGS_REG 0x088c 912 #define STAT_IFHCIN_MPKGS_REG 0x0890 913 #define STAT_IFHCIN_BPKGS_REG 0x0894 914 915 #define STAT_DOT3_FCS_ERR_REG 0x0898 916 #define STAT_DOT3_ALIGN_ERR_REG 0x089c 917 #define STAT_XON_PAUSE_RX_REG 0x08a0 918 #define STAT_XOFF_PAUSE_RX_REG 0x08a4 919 #define STAT_MAC_CTRL_RX_REG 0x08a8 920 #define STAT_XOFF_STATE_ENTER_REG 0x08ac 921 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 922 #define STAT_ETHER_JABBERS_REG 0x08b4 923 #define STAT_ETHER_UNDERSIZE_REG 0x08b8 924 #define SIZE_OF_STATISTIC_REG 0x1B 925 /* 926 * Send Data Initiator Registers 927 */ 928 #define SEND_INIT_STATS_CONTROL_REG 0x0c08 929 #define SEND_INIT_STATS_ZERO 0x00000010 930 #define SEND_INIT_STATS_FLUSH 0x00000008 931 #define SEND_INIT_STATS_CLEAR 0x00000004 932 #define SEND_INIT_STATS_FASTER 0x00000002 933 #define SEND_INIT_STATS_ENABLE 0x00000001 934 935 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 936 937 /* 938 * Send Buffer Descriptor Selector Control Registers 939 */ 940 #define SEND_BD_SELECTOR_STATUS_REG 0x1404 941 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 942 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 943 944 /* 945 * Receive List Placement Registers 946 */ 947 #define RCV_LP_CONFIG_REG 0x2010 948 #define RCV_LP_CONFIG_DEFAULT 0x00000009 949 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 950 951 #define RCV_LP_STATS_CONTROL_REG 0x2014 952 #define RCV_LP_STATS_ZERO 0x00000010 953 #define RCV_LP_STATS_FLUSH 0x00000008 954 #define RCV_LP_STATS_CLEAR 0x00000004 955 #define RCV_LP_STATS_FASTER 0x00000002 956 #define RCV_LP_STATS_ENABLE 0x00000001 957 958 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 959 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000 960 961 /* 962 * Receive Data & BD Initiator Registers 963 */ 964 #define RCV_INITIATOR_STATUS_REG 0x2404 965 966 /* 967 * Receive Buffer Descriptor Ring Control Block Registers 968 * NB: sixteen bytes (128 bits) each 969 */ 970 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 971 #define STD_RCV_BD_RING_RCB_REG 0x2450 972 #define MINI_RCV_BD_RING_RCB_REG 0x2460 973 974 /* 975 * Receive Buffer Descriptor Ring Replenish Threshold Registers 976 */ 977 #define MINI_RCV_BD_REPLENISH_REG 0x2c14 978 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 979 #define STD_RCV_BD_REPLENISH_REG 0x2c18 980 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 981 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 982 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 983 984 /* 985 * Host Coalescing Engine Control Registers 986 */ 987 #define RCV_COALESCE_TICKS_REG 0x3c08 988 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 989 #define SEND_COALESCE_TICKS_REG 0x3c0c 990 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 991 #define RCV_COALESCE_MAX_BD_REG 0x3c10 992 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 993 #define SEND_COALESCE_MAX_BD_REG 0x3c14 994 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 995 #define RCV_COALESCE_INT_TICKS_REG 0x3c18 996 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 997 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 998 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 999 #define RCV_COALESCE_INT_BD_REG 0x3c20 1000 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1001 #define SEND_COALESCE_INT_BD_REG 0x3c24 1002 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1003 #define STATISTICS_TICKS_REG 0x3c28 1004 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 1005 #define STATISTICS_HOST_ADDR_REG 0x3c30 1006 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 1007 #define STATISTICS_BASE_ADDR_REG 0x3c40 1008 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 1009 #define FLOW_ATTN_REG 0x3c48 1010 1011 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 1012 #define NIC_STD_RECV_INDEX_REG 0x3c54 1013 #define NIC_MINI_RECV_INDEX_REG 0x3c58 1014 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 1015 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 1016 1017 /* 1018 * Mbuf Pool Initialisation & Watermark Registers 1019 * 1020 * There are some conflicts in the PRM; compare the recommendations 1021 * on pp. 115, 236, and 339. The values here were recommended by 1022 * dkim@broadcom.com (and the PRM should be corrected soon ;-) 1023 */ 1024 #define BUFFER_MANAGER_STATUS_REG 0x4404 1025 #define MBUF_POOL_BASE_REG 0x4408 1026 #define MBUF_POOL_BASE_DEFAULT 0x00008000 1027 #define MBUF_POOL_BASE_5721 0x00010000 1028 #define MBUF_POOL_BASE_5704 0x00010000 1029 #define MBUF_POOL_BASE_5705 0x00010000 1030 #define MBUF_POOL_LENGTH_REG 0x440c 1031 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 1032 #define MBUF_POOL_LENGTH_5704 0x00010000 1033 #define MBUF_POOL_LENGTH_5705 0x00008000 1034 #define MBUF_POOL_LENGTH_5721 0x00008000 1035 #define RDMA_MBUF_LOWAT_REG 0x4410 1036 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 1037 #define RDMA_MBUF_LOWAT_5705 0x00000000 1038 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 1039 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 1040 #define MAC_RX_MBUF_LOWAT_REG 0x4414 1041 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 1042 #define MAC_RX_MBUF_LOWAT_5705 0x00000010 1043 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 1044 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 1045 #define MBUF_HIWAT_REG 0x4418 1046 #define MBUF_HIWAT_DEFAULT 0x00000060 1047 #define MBUF_HIWAT_5705 0x00000060 1048 #define MBUF_HIWAT_JUMBO 0x0000017c 1049 #define MBUF_HIWAT_5714_JUMBO 0x00000096 1050 1051 /* 1052 * DMA Descriptor Pool Initialisation & Watermark Registers 1053 */ 1054 #define DMAD_POOL_BASE_REG 0x442c 1055 #define DMAD_POOL_BASE_DEFAULT 0x00002000 1056 #define DMAD_POOL_LENGTH_REG 0x4430 1057 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 1058 #define DMAD_POOL_LOWAT_REG 0x4434 1059 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 1060 #define DMAD_POOL_HIWAT_REG 0x4438 1061 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 1062 1063 /* 1064 * More threshold/watermark registers ... 1065 */ 1066 #define RECV_FLOW_THRESHOLD_REG 0x4458 1067 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 1068 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 1069 1070 /* 1071 * Read/Write DMA Status Registers 1072 */ 1073 #define READ_DMA_STATUS_REG 0x4804 1074 #define WRITE_DMA_STATUS_REG 0x4c04 1075 1076 /* 1077 * RX/TX RISC Registers 1078 */ 1079 #define RX_RISC_MODE_REG 0x5000 1080 #define RX_RISC_STATE_REG 0x5004 1081 #define RX_RISC_PC_REG 0x501c 1082 #define TX_RISC_MODE_REG 0x5400 1083 #define TX_RISC_STATE_REG 0x5404 1084 #define TX_RISC_PC_REG 0x541c 1085 1086 #define FTQ_RESET_REG 0x5c00 1087 1088 #define MSI_MODE_REG 0x6000 1089 #define MSI_PRI_HIGHEST 0xc0000000 1090 #define MSI_MSI_ENABLE 0x00000002 1091 #define MSI_ERROR_ATTENTION 0x0000001c 1092 1093 #define MSI_STATUS_REG 0x6004 1094 1095 #define MODE_CONTROL_REG 0x6800 1096 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 1097 #define MODE_4X_NIC_SEND_RINGS 0x20000000 1098 #define MODE_INT_ON_FLOW_ATTN 0x10000000 1099 #define MODE_INT_ON_DMA_ATTN 0x08000000 1100 #define MODE_INT_ON_MAC_ATTN 0x04000000 1101 #define MODE_INT_ON_RXRISC_ATTN 0x02000000 1102 #define MODE_INT_ON_TXRISC_ATTN 0x01000000 1103 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 1104 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 1105 #define MODE_HOST_SEND_BDS 0x00020000 1106 #define MODE_HOST_STACK_UP 0x00010000 1107 #define MODE_FORCE_32_BIT_PCI 0x00008000 1108 #define MODE_NO_INT_ON_RECV 0x00004000 1109 #define MODE_NO_INT_ON_SEND 0x00002000 1110 #define MODE_ALLOW_BAD_FRAMES 0x00000800 1111 #define MODE_NO_CRC 0x00000400 1112 #define MODE_NO_FRAME_CRACKING 0x00000200 1113 #define MODE_WORD_SWAP_FRAME 0x00000020 1114 #define MODE_BYTE_SWAP_FRAME 0x00000010 1115 #define MODE_WORD_SWAP_NONFRAME 0x00000004 1116 #define MODE_BYTE_SWAP_NONFRAME 0x00000002 1117 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 1118 1119 /* 1120 * Miscellaneous Configuration Register 1121 * 1122 * This contains various bits relating to power control (which differ 1123 * among different members of the chip family), but the important bits 1124 * for our purposes are the RESET bit and the Timer Prescaler field. 1125 * 1126 * The RESET bit in this register serves to reset the whole chip, even 1127 * including the PCI interface(!) Once it's set, the chip will not 1128 * respond to ANY accesses -- not even CONFIG space -- until the reset 1129 * completes internally. According to the PRM, this should take less 1130 * than 100us. Any access during this period will get a bus error. 1131 * 1132 * The Timer Prescaler field must be programmed so that the timer period 1133 * is as near as possible to 1us. The value in this field should be 1134 * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 1135 * the Core Clock should always be 66MHz (independently of the bus speed, 1136 * at least for PCI rather than PCI-X), so this register must be set to 1137 * the value 0x82 ((66-1) << 1). 1138 */ 1139 #define CORE_CLOCK_MHZ 66 1140 #define MISC_CONFIG_REG 0x6804 1141 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 1142 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 1143 #define MISC_CONFIG_POWERDOWN 0x00100000 1144 #define MISC_CONFIG_POWER_STATE 0x00060000 1145 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 1146 #define MISC_CONFIG_RESET_BIT 0x00000001 1147 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 1148 1149 /* 1150 * Miscellaneous Local Control Register (MLCR) 1151 */ 1152 #define MISC_LOCAL_CONTROL_REG 0x6808 1153 #define MLCR_PCI_CTRL_SELECT 0x10000000 1154 #define MLCR_LEGACY_PCI_MODE 0x08000000 1155 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 1156 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 1157 #define MLCR_SSRAM_TYPE 0x00400000 1158 #define MLCR_BANK_SELECT 0x00200000 1159 #define MLCR_SRAM_SIZE_MASK 0x001c0000 1160 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 1161 1162 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1163 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 1164 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 1165 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 1166 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1167 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 1168 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 1169 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 1170 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 1171 1172 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 1173 #define MLCR_SET_INT 0x00000004 /* W/O */ 1174 #define MLCR_CLR_INT 0x00000002 /* W/O */ 1175 #define MLCR_INTA_STATE 0x00000001 /* R/O */ 1176 1177 /* 1178 * This value defines all GPIO bits as INPUTS, but sets their default 1179 * values as outputs to HIGH, on the assumption that external circuits 1180 * (if any) will probably be active-LOW with passive pullups. 1181 * 1182 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 1183 * just this fashion. It has to be set as an OUTPUT and driven LOW to 1184 * enable writing. Otherwise, the SEEPROM is protected. 1185 */ 1186 #define MLCR_DEFAULT 0x0101c000 1187 #define MLCR_DEFAULT_5714 0x1901c000 1188 1189 /* 1190 * Serial EEPROM Data/Address Registers (auto-access mode) 1191 */ 1192 #define SERIAL_EEPROM_DATA_REG 0x683c 1193 #define SERIAL_EEPROM_ADDRESS_REG 0x6838 1194 #define SEEPROM_ACCESS_READ 0x80000000 1195 #define SEEPROM_ACCESS_WRITE 0x00000000 1196 #define SEEPROM_ACCESS_COMPLETE 0x40000000 1197 #define SEEPROM_ACCESS_RESET 0x20000000 1198 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 1199 #define SEEPROM_ACCESS_START 0x02000000 1200 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 1201 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 1202 1203 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 1204 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 1205 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 1206 1207 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 1208 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 1209 1210 /* 1211 * "Linearised" address mask, treating multiple devices as consecutive 1212 */ 1213 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 1214 1215 /* 1216 * Non-Volatile Memory Interface Registers 1217 * Note: on chips that support the flash interface (5702+), flash is the 1218 * default and the legacy seeprom interface must be explicitly enabled 1219 * if required. On older chips (5700/01), SEEPROM is the default (and 1220 * only) non-volatile memory available, and these registers don't exist! 1221 */ 1222 #define NVM_FLASH_CMD_REG 0x7000 1223 #define NVM_FLASH_CMD_LAST 0x00000100 1224 #define NVM_FLASH_CMD_FIRST 0x00000080 1225 #define NVM_FLASH_CMD_RD 0x00000000 1226 #define NVM_FLASH_CMD_WR 0x00000020 1227 #define NVM_FLASH_CMD_DOIT 0x00000010 1228 #define NVM_FLASH_CMD_DONE 0x00000008 1229 1230 #define NVM_FLASH_WRITE_REG 0x7008 1231 #define NVM_FLASH_READ_REG 0x7010 1232 1233 #define NVM_FLASH_ADDR_REG 0x700c 1234 #define NVM_FLASH_ADDR_MASK 0x00fffffc 1235 1236 #define NVM_CONFIG1_REG 0x7014 1237 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 1238 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 1239 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 1240 #define NVM_CFG1_BUFFERED_MODE 0x00000002 1241 #define NVM_CFG1_FLASH_MODE 0x00000001 1242 1243 #define NVM_SW_ARBITRATION_REG 0x7020 1244 #define NVM_READ_REQ3 0X00008000 1245 #define NVM_READ_REQ2 0X00004000 1246 #define NVM_READ_REQ1 0X00002000 1247 #define NVM_READ_REQ0 0X00001000 1248 #define NVM_WON_REQ3 0X00000800 1249 #define NVM_WON_REQ2 0X00000400 1250 #define NVM_WON_REQ1 0X00000200 1251 #define NVM_WON_REQ0 0X00000100 1252 #define NVM_RESET_REQ3 0X00000080 1253 #define NVM_RESET_REQ2 0X00000040 1254 #define NVM_RESET_REQ1 0X00000020 1255 #define NVM_RESET_REQ0 0X00000010 1256 #define NVM_SET_REQ3 0X00000008 1257 #define NVM_SET_REQ2 0X00000004 1258 #define NVM_SET_REQ1 0X00000002 1259 #define NVM_SET_REQ0 0X00000001 1260 1261 /* 1262 * NVM access register 1263 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714 1264 * and BCM5715 only. 1265 */ 1266 #define NVM_ACCESS_REG 0X7024 1267 #define NVM_WRITE_ENABLE 0X00000002 1268 #define NVM_ACCESS_ENABLE 0X00000001 1269 1270 /* 1271 * TLP Control Register 1272 * Applicable to BCM5721 and BCM5751 only 1273 */ 1274 #define TLP_CONTROL_REG 0x7c00 1275 #define TLP_DATA_FIFO_PROTECT 0x02000000 1276 1277 /* 1278 * PHY Test Control Register 1279 * Applicable to BCM5721 and BCM5751 only 1280 */ 1281 #define PHY_TEST_CTRL_REG 0x7e2c 1282 #define PHY_PCIE_SCRAM_MODE 0x20 1283 #define PHY_PCIE_LTASS_MODE 0x40 1284 1285 /* 1286 * The internal firmware expects a certain layout of the non-volatile 1287 * memory (if fitted), and will check for it during startup, and use the 1288 * contents to initialise various internal parameters if it looks good. 1289 * 1290 * The offsets and field definitions below refer to where to find some 1291 * important values, and how to interpret them ... 1292 */ 1293 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 1294 1295 /* 1296 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 1297 */ 1298 1299 #define MII_AN_LPNXTPG 8 1300 #define MII_1000BASE_T_CONTROL 9 1301 #define MII_1000BASE_T_STATUS 10 1302 #define MII_IEEE_EXT_STATUS 15 1303 1304 /* 1305 * New bits in the MII_CONTROL register 1306 */ 1307 #define MII_CONTROL_1000MB 0x0040 1308 1309 /* 1310 * New bits in the MII_AN_ADVERT register 1311 */ 1312 #define MII_ABILITY_ASYM_PAUSE 0x0800 1313 #define MII_ABILITY_PAUSE 0x0400 1314 1315 /* 1316 * Values for the <selector> field of the MII_AN_ADVERT register 1317 */ 1318 #define MII_AN_SELECTOR_8023 0x0001 1319 1320 /* 1321 * Bits in the MII_1000BASE_T_CONTROL register 1322 * 1323 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 1324 * (otherwise, roles are automatically negotiated). When this bit is set, 1325 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 1326 */ 1327 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 1328 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 1329 #define MII_1000BT_CTL_ADV_FDX 0x0200 1330 #define MII_1000BT_CTL_ADV_HDX 0x0100 1331 1332 /* 1333 * Bits in the MII_1000BASE_T_STATUS register 1334 */ 1335 #define MII_1000BT_STAT_MASTER_FAULT 0x8000 1336 #define MII_1000BT_STAT_MASTER_MODE 0x4000 /* shows role selected */ 1337 #define MII_1000BT_STAT_LCL_RCV_OK 0x2000 1338 #define MII_1000BT_STAT_RMT_RCV_OK 0x1000 1339 #define MII_1000BT_STAT_LP_FDX_CAP 0x0800 1340 #define MII_1000BT_STAT_LP_HDX_CAP 0x0400 1341 1342 /* 1343 * Vendor-specific MII registers 1344 */ 1345 #define MII_EXT_CONTROL MII_VENDOR(0) 1346 #define MII_EXT_STATUS MII_VENDOR(1) 1347 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 1348 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 1349 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 1350 #define MII_AUX_CONTROL MII_VENDOR(8) 1351 #define MII_AUX_STATUS MII_VENDOR(9) 1352 #define MII_INTR_STATUS MII_VENDOR(10) 1353 #define MII_INTR_MASK MII_VENDOR(11) 1354 #define MII_HCD_STATUS MII_VENDOR(13) 1355 1356 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 1357 1358 /* 1359 * Bits in the MII_EXT_CONTROL register 1360 */ 1361 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 1362 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 1363 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 1364 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 1365 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 1366 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 1367 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 1368 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 1369 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 1370 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 1371 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 1372 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 1373 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 1374 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 1375 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 1376 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 1377 1378 /* 1379 * Bits in the MII_EXT_STATUS register 1380 */ 1381 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 1382 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 1383 #define MII_EXT_STAT_MDIX_STATE 0x2000 1384 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 1385 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 1386 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 1387 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 1388 #define MII_EXT_STAT_LINK_STATUS 0x0100 1389 #define MII_EXT_STAT_CRC_ERROR 0x0080 1390 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 1391 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 1392 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 1393 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 1394 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 1395 #define MII_EXT_STAT_LOCK_ERROR 0x0002 1396 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 1397 1398 /* 1399 * The AUX CONTROL register is seriously weird! 1400 * 1401 * It hides (up to) eight 'shadow' registers. When writing, which one 1402 * of them is written is determined by the low-order bits of the data 1403 * written(!), but when reading, which one is read is determined by the 1404 * value previously written to (part of) one of the shadow registers!!! 1405 */ 1406 1407 /* 1408 * Shadow register numbers 1409 */ 1410 #define MII_AUX_CTRL_NORMAL 0 1411 #define MII_AUX_CTRL_10BASE_T 1 1412 #define MII_AUX_CTRL_POWER 2 1413 #define MII_AUX_CTRL_TEST_1 4 1414 #define MII_AUX_CTRL_MISC 7 1415 1416 /* 1417 * Selected bits in some of the shadow registers ... 1418 */ 1419 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 1420 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 1421 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 1422 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 1423 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 1424 1425 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 1426 1427 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 1428 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 1429 1430 /* 1431 * Write this value to the AUX control register 1432 * to select which shadow register will be read 1433 */ 1434 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 1435 1436 /* 1437 * Bits in the MII_AUX_STATUS register 1438 */ 1439 #define MII_AUX_STATUS_MODE_MASK 0x0700 1440 #define MII_AUX_STATUS_MODE_1000_F 0x0700 1441 #define MII_AUX_STATUS_MODE_1000_H 0x0600 1442 #define MII_AUX_STATUS_MODE_100_F 0x0500 1443 #define MII_AUX_STATUS_MODE_100_4 0x0400 1444 #define MII_AUX_STATUS_MODE_100_H 0x0300 1445 #define MII_AUX_STATUS_MODE_10_F 0x0200 1446 #define MII_AUX_STATUS_MODE_10_H 0x0100 1447 #define MII_AUX_STATUS_MODE_NONE 0x0000 1448 #define MII_AUX_STATUS_MODE_SHIFT 8 1449 1450 #define MII_AUX_STATUS_PAR_FAULT 0x0080 1451 #define MII_AUX_STATUS_REM_FAULT 0x0040 1452 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 1453 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 1454 1455 #define MII_AUX_STATUS_LINKUP 0x0004 1456 #define MII_AUX_STATUS_RX_PAUSE 0x0002 1457 #define MII_AUX_STATUS_TX_PAUSE 0x0001 1458 1459 /* 1460 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 1461 */ 1462 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 1463 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 1464 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 1465 #define MII_INTR_LINK_SPEED_CHANGE 0x0004 1466 #define MII_INTR_LINK_STATUS_CHANGE 0x0002 1467 1468 1469 /* 1470 * Third section: 1471 * Hardware-defined data structures 1472 * 1473 * Note that the chip is naturally BIG-endian, so, for a big-endian 1474 * host, the structures defined below match those described in the PRM. 1475 * For little-endian hosts, some structures have to be swapped around. 1476 */ 1477 1478 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 1479 #error Host endianness not defined 1480 #endif 1481 1482 /* 1483 * Architectural constants: absolute maximum numbers of each type of ring 1484 */ 1485 #ifdef BGE_EXT_MEM 1486 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 1487 #else 1488 #define BGE_SEND_RINGS_MAX 4 1489 #endif 1490 #define BGE_SEND_RINGS_MAX_5705 1 1491 #define BGE_RECV_RINGS_MAX 16 1492 #define BGE_RECV_RINGS_MAX_5705 1 1493 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 1494 /* only with ext mem) */ 1495 1496 #define BGE_SEND_SLOTS_MAX 512 1497 #define BGE_STD_SLOTS_MAX 512 1498 #define BGE_JUMBO_SLOTS_MAX 256 1499 #define BGE_MINI_SLOTS_MAX 1024 1500 #define BGE_RECV_SLOTS_MAX 2048 1501 #define BGE_RECV_SLOTS_5705 512 1502 #define BGE_RECV_SLOTS_5782 512 1503 #define BGE_RECV_SLOTS_5721 512 1504 1505 /* 1506 * Hardware-defined Ring Control Block 1507 */ 1508 typedef struct { 1509 uint64_t host_ring_addr; 1510 #ifdef _BIG_ENDIAN 1511 uint16_t max_len; 1512 uint16_t flags; 1513 uint32_t nic_ring_addr; 1514 #else 1515 uint32_t nic_ring_addr; 1516 uint16_t flags; 1517 uint16_t max_len; 1518 #endif /* _BIG_ENDIAN */ 1519 } bge_rcb_t; 1520 1521 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 1522 #define RCB_FLAG_RING_DISABLED 0x0002 1523 1524 /* 1525 * Hardware-defined Send Buffer Descriptor 1526 */ 1527 typedef struct { 1528 uint64_t host_buf_addr; 1529 #ifdef _BIG_ENDIAN 1530 uint16_t len; 1531 uint16_t flags; 1532 uint16_t reserved; 1533 uint16_t vlan_tci; 1534 #else 1535 uint16_t vlan_tci; 1536 uint16_t reserved; 1537 uint16_t flags; 1538 uint16_t len; 1539 #endif /* _BIG_ENDIAN */ 1540 } bge_sbd_t; 1541 1542 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 1543 #define SBD_FLAG_IP_CKSUM 0x0002 1544 #define SBD_FLAG_PACKET_END 0x0004 1545 #define SBD_FLAG_IP_FRAG 0x0008 1546 #define SBD_FLAG_IP_FRAG_END 0x0010 1547 1548 #define SBD_FLAG_VLAN_TAG 0x0040 1549 #define SBD_FLAG_COAL_NOW 0x0080 1550 #define SBD_FLAG_CPU_PRE_DMA 0x0100 1551 #define SBD_FLAG_CPU_POST_DMA 0x0200 1552 1553 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 1554 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 1555 #define SBD_FLAG_DONT_GEN_CRC 0x8000 1556 1557 /* 1558 * Hardware-defined Receive Buffer Descriptor 1559 */ 1560 typedef struct { 1561 uint64_t host_buf_addr; 1562 #ifdef _BIG_ENDIAN 1563 uint16_t index; 1564 uint16_t len; 1565 uint16_t type; 1566 uint16_t flags; 1567 uint16_t ip_cksum; 1568 uint16_t tcp_udp_cksum; 1569 uint16_t error_flag; 1570 uint16_t vlan_tci; 1571 uint32_t reserved; 1572 uint32_t opaque; 1573 #else 1574 uint16_t flags; 1575 uint16_t type; 1576 uint16_t len; 1577 uint16_t index; 1578 uint16_t vlan_tci; 1579 uint16_t error_flag; 1580 uint16_t tcp_udp_cksum; 1581 uint16_t ip_cksum; 1582 uint32_t opaque; 1583 uint32_t reserved; 1584 #endif /* _BIG_ENDIAN */ 1585 } bge_rbd_t; 1586 1587 #define RBD_FLAG_STD_RING 0x0000 1588 #define RBD_FLAG_PACKET_END 0x0004 1589 1590 #define RBD_FLAG_JUMBO_RING 0x0020 1591 #define RBD_FLAG_VLAN_TAG 0x0040 1592 1593 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 1594 #define RBD_FLAG_MINI_RING 0x0800 1595 #define RBD_FLAG_IP_CHECKSUM 0x1000 1596 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 1597 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 1598 1599 #define RBD_FLAG_DEFAULT 0x0000 1600 1601 #define RBD_ERROR_BAD_CRC 0x00010000 1602 #define RBD_ERROR_COLL_DETECT 0x00020000 1603 #define RBD_ERROR_LINK_LOST 0x00040000 1604 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 1605 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 1606 #define RBD_ERROR_MAC_ABORT 0x00200000 1607 #define RBD_ERROR_LEN_LESS_64 0x00400000 1608 #define RBD_ERROR_TRUNC_NO_RES 0x00800000 1609 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 1610 1611 /* 1612 * Hardware-defined Status Block,Size of status block 1613 * is actually 0x50 bytes.Use 0x80 bytes for cache line 1614 * alignment.For BCM5705/5788/5721/5751/5752/5714 1615 * and 5715,there is only 1 recv and send ring index,but 1616 * driver defined 16 indexs here,please pay attention only 1617 * one ring is enabled in these chipsets. 1618 */ 1619 typedef struct { 1620 uint64_t flags_n_tag; 1621 uint16_t buff_cons_index[4]; 1622 struct { 1623 #ifdef _BIG_ENDIAN 1624 uint16_t send_cons_index; 1625 uint16_t recv_prod_index; 1626 #else 1627 uint16_t recv_prod_index; 1628 uint16_t send_cons_index; 1629 #endif /* _BIG_ENDIAN */ 1630 } index[16]; 1631 } bge_status_t; 1632 1633 /* 1634 * Hardware-defined Receive BD Rule 1635 */ 1636 typedef struct { 1637 uint32_t control; 1638 uint32_t mask_value; 1639 } bge_recv_rule_t; 1640 1641 /* 1642 * Indexes into the <buff_cons_index> array 1643 */ 1644 #ifdef _BIG_ENDIAN 1645 #define STATUS_STD_BUFF_CONS_INDEX 0 1646 #define STATUS_JUMBO_BUFF_CONS_INDEX 1 1647 #define STATUS_MINI_BUFF_CONS_INDEX 3 1648 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 1649 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 1650 #else 1651 #define STATUS_STD_BUFF_CONS_INDEX 3 1652 #define STATUS_JUMBO_BUFF_CONS_INDEX 2 1653 #define STATUS_MINI_BUFF_CONS_INDEX 0 1654 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 1655 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 1656 #endif /* _BIG_ENDIAN */ 1657 1658 /* 1659 * Bits in the <flags_n_tag> word 1660 */ 1661 #define STATUS_FLAG_UPDATED 0x0000000100000000ull 1662 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 1663 #define STATUS_FLAG_ERROR 0x0000000400000000ull 1664 #define STATUS_TAG_MASK 0x00000000000000FFull 1665 1666 /* 1667 * The tag from the status block is fed back to Interrupt Mailbox 0 1668 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 1669 * lets the chip know what updates have been processed, so it can 1670 * reassert its interrupt if more updates have occurred since. 1671 * 1672 * These macros extract the tag from the <flags_n_tag> word, shift 1673 * it to the proper position in the Mailbox register, and provide 1674 * the complete values to write to INTERRUPT_MBOX_0_REG to disable 1675 * or enable interrupts 1676 */ 1677 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 1678 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 1679 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 1680 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 1681 1682 /* 1683 * Hardware-defined Statistics Block Offsets 1684 * 1685 * These are given in the manual as addresses in NIC memory, starting 1686 * from the NIC statistics area base address of 0x300; but here we 1687 * convert them into indexes into an array of (uint64_t)s, so we can 1688 * use them directly for accessing the copy of the statistics block 1689 * that the chip DMAs into main memory ... 1690 */ 1691 1692 #define KS_BASE 0x300 1693 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 1694 1695 typedef enum { 1696 KS_ifHCInOctets = KS_ADDR(0x400), 1697 KS_etherStatsFragments = KS_ADDR(0x410), 1698 KS_ifHCInUcastPkts, 1699 KS_ifHCInMulticastPkts, 1700 KS_ifHCInBroadcastPkts, 1701 KS_dot3StatsFCSErrors, 1702 KS_dot3StatsAlignmentErrors, 1703 KS_xonPauseFramesReceived, 1704 KS_xoffPauseFramesReceived, 1705 KS_macControlFramesReceived, 1706 KS_xoffStateEntered, 1707 KS_dot3StatsFrameTooLongs, 1708 KS_etherStatsJabbers, 1709 KS_etherStatsUndersizePkts, 1710 KS_inRangeLengthError, 1711 KS_outRangeLengthError, 1712 KS_etherStatsPkts64Octets, 1713 KS_etherStatsPkts65to127Octets, 1714 KS_etherStatsPkts128to255Octets, 1715 KS_etherStatsPkts256to511Octets, 1716 KS_etherStatsPkts512to1023Octets, 1717 KS_etherStatsPkts1024to1518Octets, 1718 KS_etherStatsPkts1519to2047Octets, 1719 KS_etherStatsPkts2048to4095Octets, 1720 KS_etherStatsPkts4096to8191Octets, 1721 KS_etherStatsPkts8192to9022Octets, 1722 1723 KS_ifHCOutOctets = KS_ADDR(0x600), 1724 KS_etherStatsCollisions = KS_ADDR(0x610), 1725 KS_outXonSent, 1726 KS_outXoffSent, 1727 KS_flowControlDone, 1728 KS_dot3StatsInternalMacTransmitErrors, 1729 KS_dot3StatsSingleCollisionFrames, 1730 KS_dot3StatsMultipleCollisionFrames, 1731 KS_dot3StatsDeferredTransmissions, 1732 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 1733 KS_dot3StatsLateCollisions, 1734 KS_dot3Collided2Times, 1735 KS_dot3Collided3Times, 1736 KS_dot3Collided4Times, 1737 KS_dot3Collided5Times, 1738 KS_dot3Collided6Times, 1739 KS_dot3Collided7Times, 1740 KS_dot3Collided8Times, 1741 KS_dot3Collided9Times, 1742 KS_dot3Collided10Times, 1743 KS_dot3Collided11Times, 1744 KS_dot3Collided12Times, 1745 KS_dot3Collided13Times, 1746 KS_dot3Collided14Times, 1747 KS_dot3Collided15Times, 1748 KS_ifHCOutUcastPkts, 1749 KS_ifHCOutMulticastPkts, 1750 KS_ifHCOutBroadcastPkts, 1751 KS_dot3StatsCarrierSenseErrors, 1752 KS_ifOutDiscards, 1753 KS_ifOutErrors, 1754 1755 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 1756 KS_COSIfHCInPkts_2, 1757 KS_COSIfHCInPkts_3, 1758 KS_COSIfHCInPkts_4, 1759 KS_COSIfHCInPkts_5, 1760 KS_COSIfHCInPkts_6, 1761 KS_COSIfHCInPkts_7, 1762 KS_COSIfHCInPkts_8, 1763 KS_COSIfHCInPkts_9, 1764 KS_COSIfHCInPkts_10, 1765 KS_COSIfHCInPkts_11, 1766 KS_COSIfHCInPkts_12, 1767 KS_COSIfHCInPkts_13, 1768 KS_COSIfHCInPkts_14, 1769 KS_COSIfHCInPkts_15, 1770 KS_COSIfHCInPkts_16, 1771 KS_COSFramesDroppedDueToFilters, 1772 KS_nicDmaWriteQueueFull, 1773 KS_nicDmaWriteHighPriQueueFull, 1774 KS_nicNoMoreRxBDs, 1775 KS_ifInDiscards, 1776 KS_ifInErrors, 1777 KS_nicRecvThresholdHit, 1778 1779 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 1780 KS_COSIfHCOutPkts_2, 1781 KS_COSIfHCOutPkts_3, 1782 KS_COSIfHCOutPkts_4, 1783 KS_COSIfHCOutPkts_5, 1784 KS_COSIfHCOutPkts_6, 1785 KS_COSIfHCOutPkts_7, 1786 KS_COSIfHCOutPkts_8, 1787 KS_COSIfHCOutPkts_9, 1788 KS_COSIfHCOutPkts_10, 1789 KS_COSIfHCOutPkts_11, 1790 KS_COSIfHCOutPkts_12, 1791 KS_COSIfHCOutPkts_13, 1792 KS_COSIfHCOutPkts_14, 1793 KS_COSIfHCOutPkts_15, 1794 KS_COSIfHCOutPkts_16, 1795 KS_nicDmaReadQueueFull, 1796 KS_nicDmaReadHighPriQueueFull, 1797 KS_nicSendDataCompQueueFull, 1798 KS_nicRingSetSendProdIndex, 1799 KS_nicRingStatusUpdate, 1800 KS_nicInterrupts, 1801 KS_nicAvoidedInterrupts, 1802 KS_nicSendThresholdHit, 1803 1804 KS_STATS_SIZE = KS_ADDR(0xb00) 1805 } bge_stats_offset_t; 1806 1807 /* 1808 * Hardware-defined Statistics Block 1809 * 1810 * Another view of the statistic block, as a array and a structure ... 1811 */ 1812 1813 typedef union { 1814 uint64_t a[KS_STATS_SIZE]; 1815 struct { 1816 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 1817 1818 uint64_t ifHCInOctets; /* 0x0400 */ 1819 uint64_t spare2[1]; 1820 uint64_t etherStatsFragments; 1821 uint64_t ifHCInUcastPkts; 1822 uint64_t ifHCInMulticastPkts; 1823 uint64_t ifHCInBroadcastPkts; 1824 uint64_t dot3StatsFCSErrors; 1825 uint64_t dot3StatsAlignmentErrors; 1826 uint64_t xonPauseFramesReceived; 1827 uint64_t xoffPauseFramesReceived; 1828 uint64_t macControlFramesReceived; 1829 uint64_t xoffStateEntered; 1830 uint64_t dot3StatsFrameTooLongs; 1831 uint64_t etherStatsJabbers; 1832 uint64_t etherStatsUndersizePkts; 1833 uint64_t inRangeLengthError; 1834 uint64_t outRangeLengthError; 1835 uint64_t etherStatsPkts64Octets; 1836 uint64_t etherStatsPkts65to127Octets; 1837 uint64_t etherStatsPkts128to255Octets; 1838 uint64_t etherStatsPkts256to511Octets; 1839 uint64_t etherStatsPkts512to1023Octets; 1840 uint64_t etherStatsPkts1024to1518Octets; 1841 uint64_t etherStatsPkts1519to2047Octets; 1842 uint64_t etherStatsPkts2048to4095Octets; 1843 uint64_t etherStatsPkts4096to8191Octets; 1844 uint64_t etherStatsPkts8192to9022Octets; 1845 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 1846 1847 uint64_t ifHCOutOctets; /* 0x0600 */ 1848 uint64_t spare4[1]; 1849 uint64_t etherStatsCollisions; 1850 uint64_t outXonSent; 1851 uint64_t outXoffSent; 1852 uint64_t flowControlDone; 1853 uint64_t dot3StatsInternalMacTransmitErrors; 1854 uint64_t dot3StatsSingleCollisionFrames; 1855 uint64_t dot3StatsMultipleCollisionFrames; 1856 uint64_t dot3StatsDeferredTransmissions; 1857 uint64_t spare5[1]; 1858 uint64_t dot3StatsExcessiveCollisions; 1859 uint64_t dot3StatsLateCollisions; 1860 uint64_t dot3Collided2Times; 1861 uint64_t dot3Collided3Times; 1862 uint64_t dot3Collided4Times; 1863 uint64_t dot3Collided5Times; 1864 uint64_t dot3Collided6Times; 1865 uint64_t dot3Collided7Times; 1866 uint64_t dot3Collided8Times; 1867 uint64_t dot3Collided9Times; 1868 uint64_t dot3Collided10Times; 1869 uint64_t dot3Collided11Times; 1870 uint64_t dot3Collided12Times; 1871 uint64_t dot3Collided13Times; 1872 uint64_t dot3Collided14Times; 1873 uint64_t dot3Collided15Times; 1874 uint64_t ifHCOutUcastPkts; 1875 uint64_t ifHCOutMulticastPkts; 1876 uint64_t ifHCOutBroadcastPkts; 1877 uint64_t dot3StatsCarrierSenseErrors; 1878 uint64_t ifOutDiscards; 1879 uint64_t ifOutErrors; 1880 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 1881 1882 uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 1883 uint64_t COSFramesDroppedDueToFilters; 1884 uint64_t nicDmaWriteQueueFull; 1885 uint64_t nicDmaWriteHighPriQueueFull; 1886 uint64_t nicNoMoreRxBDs; 1887 uint64_t ifInDiscards; 1888 uint64_t ifInErrors; 1889 uint64_t nicRecvThresholdHit; 1890 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 1891 1892 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 1893 uint64_t nicDmaReadQueueFull; 1894 uint64_t nicDmaReadHighPriQueueFull; 1895 uint64_t nicSendDataCompQueueFull; 1896 uint64_t nicRingSetSendProdIndex; 1897 uint64_t nicRingStatusUpdate; 1898 uint64_t nicInterrupts; 1899 uint64_t nicAvoidedInterrupts; 1900 uint64_t nicSendThresholdHit; 1901 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 1902 } s; 1903 } bge_statistics_t; 1904 1905 #define KS_STAT_REG_SIZE (0x1B) 1906 #define KS_STAT_REG_BASE (0x800) 1907 1908 typedef struct { 1909 uint32_t ifHCOutOctets; 1910 uint32_t etherStatsCollisions; 1911 uint32_t outXonSent; 1912 uint32_t outXoffSent; 1913 uint32_t dot3StatsInternalMacTransmitErrors; 1914 uint32_t dot3StatsSingleCollisionFrames; 1915 uint32_t dot3StatsMultipleCollisionFrames; 1916 uint32_t dot3StatsDeferredTransmissions; 1917 uint32_t dot3StatsExcessiveCollisions; 1918 uint32_t dot3StatsLateCollisions; 1919 uint32_t ifHCOutUcastPkts; 1920 uint32_t ifHCOutMulticastPkts; 1921 uint32_t ifHCOutBroadcastPkts; 1922 uint32_t ifHCInOctets; 1923 uint32_t etherStatsFragments; 1924 uint32_t ifHCInUcastPkts; 1925 uint32_t ifHCInMulticastPkts; 1926 uint32_t ifHCInBroadcastPkts; 1927 uint32_t dot3StatsFCSErrors; 1928 uint32_t dot3StatsAlignmentErrors; 1929 uint32_t xonPauseFramesReceived; 1930 uint32_t xoffPauseFramesReceived; 1931 uint32_t macControlFramesReceived; 1932 uint32_t xoffStateEntered; 1933 uint32_t dot3StatsFrameTooLongs; 1934 uint32_t etherStatsJabbers; 1935 uint32_t etherStatsUndersizePkts; 1936 } bge_statistics_reg_t; 1937 1938 1939 #ifdef BGE_IPMI_ASF 1940 1941 /* 1942 * Device internal memory entries 1943 */ 1944 1945 #define BGE_FIRMWARE_MAILBOX 0x0b50 1946 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 1947 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 1948 1949 1950 #define BGE_NIC_DATA_SIG_ADDR 0x0b54 1951 #define BGE_NIC_DATA_SIG 0x4b657654 1952 1953 1954 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 1955 1956 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 1957 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 1958 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 1959 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 1960 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 1961 1962 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 1963 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 1964 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 1965 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 1966 1967 #define BGE_NIC_CFG_ENABLE_WOL 0x000040 1968 #define BGE_NIC_CFG_ENABLE_ASF 0x000080 1969 #define BGE_NIC_CFG_EEPROM_WP 0x000100 1970 #define BGE_NIC_CFG_POWER_SAVING 0x000200 1971 #define BGE_NIC_CFG_SWAP_PORT 0x000800 1972 #define BGE_NIC_CFG_MINI_PCI 0x001000 1973 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 1974 #define BGE_NIC_CFG_5753_12x12 0x100000 1975 1976 1977 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 1978 1979 1980 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 1981 #define BGE_NIC_PHY_ID1_MASK 0xffff0000 1982 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 1983 1984 1985 #define BGE_CMD_MAILBOX 0x0b78 1986 #define BGE_CMD_NICDRV_ALIVE 0x00000001 1987 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 1988 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 1989 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 1990 1991 1992 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 1993 #define BGE_CMD_DATA_MAILBOX 0x0b80 1994 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 1995 1996 #define BGE_DRV_STATE_MAILBOX 0x0c04 1997 #define BGE_DRV_STATE_START 0x00000001 1998 #define BGE_DRV_STATE_START_DONE 0x80000001 1999 #define BGE_DRV_STATE_UNLOAD 0x00000002 2000 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 2001 #define BGE_DRV_STATE_WOL 0x00000003 2002 #define BGE_DRV_STATE_SUSPEND 0x00000004 2003 2004 2005 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 2006 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 2007 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 2008 2009 2010 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 2011 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 2012 2013 2014 /* 2015 * RX-RISC event register 2016 */ 2017 #define RX_RISC_EVENT_REG 0x6810 2018 #define RRER_ASF_EVENT 0x4000 2019 2020 #endif /* BGE_IPMI_ASF */ 2021 2022 #ifdef __cplusplus 2023 } 2024 #endif 2025 2026 #endif /* _BGE_HW_H */ 2027