xref: /titanic_50/usr/src/uts/common/io/bge/bge_chip2.c (revision dab53f9907c56d61cc82bf0ba356b741b92aec63)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #pragma ident	"%Z%%M%	%I%	%E% SMI"
28 
29 #include "sys/bge_impl2.h"
30 
31 #define	PIO_ADDR(bgep, offset)	((void *)((caddr_t)(bgep)->io_regs+(offset)))
32 
33 /*
34  * Future features ... ?
35  */
36 #define	BGE_CFG_IO8	1	/* 8/16-bit cfg space BIS/BIC	*/
37 #define	BGE_IND_IO32	0	/* indirect access code		*/
38 #define	BGE_SEE_IO32	1	/* SEEPROM access code		*/
39 #define	BGE_FLASH_IO32	1	/* FLASH access code		*/
40 
41 /*
42  * BGE MSI tunable:
43  *
44  * By default MSI is enabled on all supported platforms but it is disabled
45  * for some Broadcom chips due to known MSI hardware issues. Currently MSI
46  * is enabled only for 5714C A2 and 5715C A2 broadcom chips.
47  */
48 #if defined(__sparc)
49 boolean_t bge_enable_msi = B_TRUE;
50 #else
51 boolean_t bge_enable_msi = B_FALSE;
52 #endif
53 
54 /*
55  * Property names
56  */
57 static char knownids_propname[] = "bge-known-subsystems";
58 
59 /*
60  * Patchable globals:
61  *
62  *	bge_autorecover
63  *		Enables/disables automatic recovery after fault detection
64  *
65  *	bge_mlcr_default
66  *		Value to program into the MLCR; controls the chip's GPIO pins
67  *
68  *	bge_dma_{rd,wr}prio
69  *		Relative priorities of DMA reads & DMA writes respectively.
70  *		These may each be patched to any value 0-3.  Equal values
71  *		will give "fair" (round-robin) arbitration for PCI access.
72  *		Unequal values will give one or the other function priority.
73  *
74  *	bge_dma_rwctrl
75  *		Value to put in the Read/Write DMA control register.  See
76  *	        the Broadcom PRM for things you can fiddle with in this
77  *		register ...
78  *
79  *	bge_{tx,rx}_{count,ticks}_{norm,intr}
80  *		Send/receive interrupt coalescing parameters.  Counts are
81  *		#s of descriptors, ticks are in microseconds.  *norm* values
82  *		apply between status updates/interrupts; the *intr* values
83  *		refer to the 'during-interrupt' versions - see the PRM.
84  *
85  *		NOTE: these values have been determined by measurement. They
86  *		differ significantly from the values recommended in the PRM.
87  */
88 static uint32_t bge_autorecover = 1;
89 static uint32_t bge_mlcr_default = MLCR_DEFAULT;
90 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714;
91 
92 static uint32_t bge_dma_rdprio = 1;
93 static uint32_t bge_dma_wrprio = 0;
94 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT;
95 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721;
96 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714;
97 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715;
98 
99 uint32_t bge_rx_ticks_norm = 128;
100 uint32_t bge_tx_ticks_norm = 2048;		/* 8 for FJ2+ !?!?	*/
101 uint32_t bge_rx_count_norm = 8;
102 uint32_t bge_tx_count_norm = 128;
103 
104 static uint32_t bge_rx_ticks_intr = 128;
105 static uint32_t bge_tx_ticks_intr = 0;		/* 8 for FJ2+ !?!?	*/
106 static uint32_t bge_rx_count_intr = 2;
107 static uint32_t bge_tx_count_intr = 0;
108 
109 /*
110  * Memory pool configuration parameters.
111  *
112  * These are generally specific to each member of the chip family, since
113  * each one may have a different memory size/configuration.
114  *
115  * Setting the mbuf pool length for a specific type of chip to 0 inhibits
116  * the driver from programming the various registers; instead they are left
117  * at their hardware defaults.  This is the preferred option for later chips
118  * (5705+), whereas the older chips *required* these registers to be set,
119  * since the h/w default was 0 ;-(
120  */
121 static uint32_t bge_mbuf_pool_base	= MBUF_POOL_BASE_DEFAULT;
122 static uint32_t bge_mbuf_pool_base_5704	= MBUF_POOL_BASE_5704;
123 static uint32_t bge_mbuf_pool_base_5705	= MBUF_POOL_BASE_5705;
124 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721;
125 static uint32_t bge_mbuf_pool_len	= MBUF_POOL_LENGTH_DEFAULT;
126 static uint32_t bge_mbuf_pool_len_5704	= MBUF_POOL_LENGTH_5704;
127 static uint32_t bge_mbuf_pool_len_5705	= 0;	/* use h/w default	*/
128 static uint32_t bge_mbuf_pool_len_5721	= 0;
129 
130 /*
131  * Various high and low water marks, thresholds, etc ...
132  *
133  * Note: these are taken from revision 7 of the PRM, and some are different
134  * from both the values in earlier PRMs *and* those determined experimentally
135  * and used in earlier versions of this driver ...
136  */
137 static uint32_t bge_mbuf_hi_water	= MBUF_HIWAT_DEFAULT;
138 static uint32_t bge_mbuf_lo_water_rmac	= MAC_RX_MBUF_LOWAT_DEFAULT;
139 static uint32_t bge_mbuf_lo_water_rdma	= RDMA_MBUF_LOWAT_DEFAULT;
140 
141 static uint32_t bge_dmad_lo_water	= DMAD_POOL_LOWAT_DEFAULT;
142 static uint32_t bge_dmad_hi_water	= DMAD_POOL_HIWAT_DEFAULT;
143 static uint32_t bge_lowat_recv_frames	= LOWAT_MAX_RECV_FRAMES_DEFAULT;
144 
145 static uint32_t bge_replenish_std	= STD_RCV_BD_REPLENISH_DEFAULT;
146 static uint32_t bge_replenish_mini	= MINI_RCV_BD_REPLENISH_DEFAULT;
147 static uint32_t bge_replenish_jumbo	= JUMBO_RCV_BD_REPLENISH_DEFAULT;
148 
149 static uint32_t	bge_watchdog_count	= 1 << 16;
150 static uint16_t bge_dma_miss_limit	= 20;
151 
152 static uint32_t bge_stop_start_on_sync	= 0;
153 
154 boolean_t bge_jumbo_enable		= B_TRUE;
155 static uint32_t bge_default_jumbo_size	= BGE_JUMBO_BUFF_SIZE;
156 
157 /*
158  * ========== Low-level chip & ring buffer manipulation ==========
159  */
160 
161 #define	BGE_DBG		BGE_DBG_REGS	/* debug flag for this code	*/
162 
163 
164 /*
165  * Config space read-modify-write routines
166  */
167 
168 #if	BGE_CFG_IO8
169 
170 /*
171  * 8- and 16-bit set/clr operations are not used; all the config registers
172  * that we need to do bit-twiddling on are 32 bits wide.  I'll leave the
173  * code here, though, in case we ever find that we do want it after all ...
174  */
175 
176 static void bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits);
177 #pragma	inline(bge_cfg_set8)
178 
179 static void
180 bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits)
181 {
182 	uint8_t regval;
183 
184 	BGE_TRACE(("bge_cfg_set8($%p, 0x%lx, 0x%x)",
185 		(void *)bgep, regno, bits));
186 
187 	regval = pci_config_get8(bgep->cfg_handle, regno);
188 
189 	BGE_DEBUG(("bge_cfg_set8($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
190 		(void *)bgep, regno, bits, regval, regval | bits));
191 
192 	regval |= bits;
193 	pci_config_put8(bgep->cfg_handle, regno, regval);
194 }
195 
196 static void bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits);
197 #pragma	inline(bge_cfg_clr8)
198 
199 static void
200 bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits)
201 {
202 	uint8_t regval;
203 
204 	BGE_TRACE(("bge_cfg_clr8($%p, 0x%lx, 0x%x)",
205 		(void *)bgep, regno, bits));
206 
207 	regval = pci_config_get8(bgep->cfg_handle, regno);
208 
209 	BGE_DEBUG(("bge_cfg_clr8($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
210 		(void *)bgep, regno, bits, regval, regval & ~bits));
211 
212 	regval &= ~bits;
213 	pci_config_put8(bgep->cfg_handle, regno, regval);
214 }
215 
216 static void bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits);
217 #pragma	inline(bge_cfg_set16)
218 
219 static void
220 bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits)
221 {
222 	uint16_t regval;
223 
224 	BGE_TRACE(("bge_cfg_set16($%p, 0x%lx, 0x%x)",
225 		(void *)bgep, regno, bits));
226 
227 	regval = pci_config_get16(bgep->cfg_handle, regno);
228 
229 	BGE_DEBUG(("bge_cfg_set16($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
230 		(void *)bgep, regno, bits, regval, regval | bits));
231 
232 	regval |= bits;
233 	pci_config_put16(bgep->cfg_handle, regno, regval);
234 }
235 
236 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits);
237 #pragma	inline(bge_cfg_clr16)
238 
239 static void
240 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits)
241 {
242 	uint16_t regval;
243 
244 	BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)",
245 		(void *)bgep, regno, bits));
246 
247 	regval = pci_config_get16(bgep->cfg_handle, regno);
248 
249 	BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
250 		(void *)bgep, regno, bits, regval, regval & ~bits));
251 
252 	regval &= ~bits;
253 	pci_config_put16(bgep->cfg_handle, regno, regval);
254 }
255 
256 #endif	/* BGE_CFG_IO8 */
257 
258 static void bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
259 #pragma	inline(bge_cfg_set32)
260 
261 static void
262 bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
263 {
264 	uint32_t regval;
265 
266 	BGE_TRACE(("bge_cfg_set32($%p, 0x%lx, 0x%x)",
267 		(void *)bgep, regno, bits));
268 
269 	regval = pci_config_get32(bgep->cfg_handle, regno);
270 
271 	BGE_DEBUG(("bge_cfg_set32($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
272 		(void *)bgep, regno, bits, regval, regval | bits));
273 
274 	regval |= bits;
275 	pci_config_put32(bgep->cfg_handle, regno, regval);
276 }
277 
278 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
279 #pragma	inline(bge_cfg_clr32)
280 
281 static void
282 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
283 {
284 	uint32_t regval;
285 
286 	BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)",
287 		(void *)bgep, regno, bits));
288 
289 	regval = pci_config_get32(bgep->cfg_handle, regno);
290 
291 	BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
292 		(void *)bgep, regno, bits, regval, regval & ~bits));
293 
294 	regval &= ~bits;
295 	pci_config_put32(bgep->cfg_handle, regno, regval);
296 }
297 
298 #if	BGE_IND_IO32
299 
300 /*
301  * Indirect access to registers & RISC scratchpads, using config space
302  * accesses only.
303  *
304  * This isn't currently used, but someday we might want to use it for
305  * restoring the Subsystem Device/Vendor registers (which aren't directly
306  * writable in Config Space), or for downloading firmware into the RISCs
307  *
308  * In any case there are endian issues to be resolved before this code is
309  * enabled; the bizarre way that bytes get twisted by this chip AND by
310  * the PCI bridge in SPARC systems mean that we shouldn't enable it until
311  * it's been thoroughly tested for all access sizes on all supported
312  * architectures (SPARC *and* x86!).
313  */
314 static uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno);
315 #pragma	inline(bge_ind_get32)
316 
317 static uint32_t
318 bge_ind_get32(bge_t *bgep, bge_regno_t regno)
319 {
320 	uint32_t val;
321 
322 	BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno));
323 
324 	ASSERT(mutex_owned(bgep->genlock));
325 
326 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
327 	val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR);
328 
329 	BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x",
330 		(void *)bgep, regno, val));
331 
332 	return (val);
333 }
334 
335 static void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val);
336 #pragma	inline(bge_ind_put32)
337 
338 static void
339 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val)
340 {
341 	BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)",
342 		(void *)bgep, regno, val));
343 
344 	ASSERT(mutex_owned(bgep->genlock));
345 
346 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
347 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val);
348 }
349 
350 #endif	/* BGE_IND_IO32 */
351 
352 #if	BGE_DEBUGGING
353 
354 static void bge_pci_check(bge_t *bgep);
355 #pragma	no_inline(bge_pci_check)
356 
357 static void
358 bge_pci_check(bge_t *bgep)
359 {
360 	uint16_t pcistatus;
361 
362 	pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT);
363 	if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0)
364 		BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x",
365 			(void *)bgep, pcistatus));
366 }
367 
368 #endif	/* BGE_DEBUGGING */
369 
370 /*
371  * Perform first-stage chip (re-)initialisation, using only config-space
372  * accesses:
373  *
374  * + Read the vendor/device/revision/subsystem/cache-line-size registers,
375  *   returning the data in the structure pointed to by <idp>.
376  * + Configure the target-mode endianness (swap) options.
377  * + Disable interrupts and enable Memory Space accesses.
378  * + Enable or disable Bus Mastering according to the <enable_dma> flag.
379  *
380  * This sequence is adapted from Broadcom document 570X-PG102-R,
381  * page 102, steps 1-3, 6-8 and 11-13.  The omitted parts of the sequence
382  * are 4 and 5 (Reset Core and wait) which are handled elsewhere.
383  *
384  * This function MUST be called before any non-config-space accesses
385  * are made; on this first call <enable_dma> is B_FALSE, and it
386  * effectively performs steps 3-1(!) of the initialisation sequence
387  * (the rest are not required but should be harmless).
388  *
389  * It MUST also be called after a chip reset, as this disables
390  * Memory Space cycles!  In this case, <enable_dma> is B_TRUE, and
391  * it is effectively performing steps 6-8.
392  */
393 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma);
394 #pragma	no_inline(bge_chip_cfg_init)
395 
396 void
397 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
398 {
399 	ddi_acc_handle_t handle;
400 	uint16_t command;
401 	uint32_t mhcr;
402 	uint16_t value16;
403 	int i;
404 
405 	BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)",
406 		(void *)bgep, (void *)cidp, enable_dma));
407 
408 	/*
409 	 * Step 3: save PCI cache line size and subsystem vendor ID
410 	 *
411 	 * Read all the config-space registers that characterise the
412 	 * chip, specifically vendor/device/revision/subsystem vendor
413 	 * and subsystem device id.  We expect (but don't check) that
414 	 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704)
415 	 *
416 	 * Also save all bus-transaction related registers (cache-line
417 	 * size, bus-grant/latency parameters, etc).  Some of these are
418 	 * cleared by reset, so we'll have to restore them later.  This
419 	 * comes from the Broadcom document 570X-PG102-R ...
420 	 *
421 	 * Note: Broadcom document 570X-PG102-R seems to be in error
422 	 * here w.r.t. the offsets of the Subsystem Vendor ID and
423 	 * Subsystem (Device) ID registers, which are the opposite way
424 	 * round according to the PCI standard.  For good measure, we
425 	 * save/restore both anyway.
426 	 */
427 	handle = bgep->cfg_handle;
428 
429 	mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR);
430 	cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK;
431 	cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);
432 	cidp->command = pci_config_get16(handle, PCI_CONF_COMM);
433 
434 	cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID);
435 	cidp->device = pci_config_get16(handle, PCI_CONF_DEVID);
436 	cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID);
437 	cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID);
438 	cidp->revision = pci_config_get8(handle, PCI_CONF_REVID);
439 	cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ);
440 	cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER);
441 
442 	BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s",
443 		cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X",
444 		cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow",
445 		cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide",
446 		cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low"));
447 	BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x",
448 		cidp->vendor, cidp->device, cidp->revision));
449 	BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x",
450 		cidp->subven, cidp->subdev, cidp->asic_rev));
451 	BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x",
452 		cidp->clsize, cidp->latency, cidp->command));
453 
454 	/*
455 	 * Step 2 (also step 6): disable and clear interrupts.
456 	 * Steps 11-13: configure PIO endianness options, and enable
457 	 * indirect register access.  We'll also select any other
458 	 * options controlled by the MHCR (e.g. tagged status, mask
459 	 * interrupt mode) at this stage ...
460 	 *
461 	 * Note: internally, the chip is 64-bit and BIG-endian, but
462 	 * since it talks to the host over a (LITTLE-endian) PCI bus,
463 	 * it normally swaps bytes around at the PCI interface.
464 	 * However, the PCI host bridge on SPARC systems normally
465 	 * swaps the byte lanes around too, since SPARCs are also
466 	 * BIG-endian.  So it turns out that on SPARC, the right
467 	 * option is to tell the chip to swap (and the host bridge
468 	 * will swap back again), whereas on x86 we ask the chip
469 	 * NOT to swap, so the natural little-endianness of the
470 	 * PCI bus is assumed.  Then the only thing that doesn't
471 	 * automatically work right is access to an 8-byte register
472 	 * by a little-endian host; but we don't want to set the
473 	 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte
474 	 * accesses don't go where expected ;-(  So we live with
475 	 * that, and perform word-swaps in software in the few cases
476 	 * where a chip register is defined as an 8-byte value --
477 	 * see the code below for details ...
478 	 *
479 	 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't
480 	 * very clear in the register description in the PRM, but
481 	 * Broadcom document 570X-PG104-R page 248 explains a little
482 	 * more (under "Broadcom Mask Mode").  The bit changes the way
483 	 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE
484 	 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same
485 	 * way as the 5700 did, which isn't very convenient.  Setting
486 	 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT
487 	 * bit do just what its name says -- MASK the PCI #INTA output
488 	 * (i.e. deassert the signal at the pin) leaving all internal
489 	 * state unchanged.  This is much more convenient for our
490 	 * interrupt handler, so we set MASK_INTERRUPT_MODE here.
491 	 *
492 	 * Note: the inconvenient semantics of the interrupt mailbox
493 	 * (nonzero disables and acknowledges/clears the interrupt,
494 	 * zero enables AND CLEARS it) would make race conditions
495 	 * likely in the interrupt handler:
496 	 *
497 	 * (1)	acknowledge & disable interrupts
498 	 * (2)	while (more to do)
499 	 * 		process packets
500 	 * (3)	enable interrupts -- also clears pending
501 	 *
502 	 * If the chip received more packets and internally generated
503 	 * an interrupt between the check at (2) and the mbox write
504 	 * at (3), this interrupt would be lost :-(
505 	 *
506 	 * The best way to avoid this is to use TAGGED STATUS mode,
507 	 * where the chip includes a unique tag in each status block
508 	 * update, and the host, when re-enabling interrupts, passes
509 	 * the last tag it saw back to the chip; then the chip can
510 	 * see whether the host is truly up to date, and regenerate
511 	 * its interrupt if not.
512 	 */
513 	mhcr =	MHCR_ENABLE_INDIRECT_ACCESS |
514 		MHCR_ENABLE_TAGGED_STATUS_MODE |
515 		MHCR_MASK_INTERRUPT_MODE |
516 		MHCR_CLEAR_INTERRUPT_INTA;
517 
518 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
519 		mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
520 
521 #ifdef	_BIG_ENDIAN
522 	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
523 #endif	/* _BIG_ENDIAN */
524 
525 	pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr);
526 
527 #ifdef BGE_IPMI_ASF
528 	bgep->asf_wordswapped = B_FALSE;
529 #endif
530 	/*
531 	 * Step 1 (also step 7): Enable PCI Memory Space accesses
532 	 *			 Disable Memory Write/Invalidate
533 	 *			 Enable or disable Bus Mastering
534 	 *
535 	 * Note that all other bits are taken from the original value saved
536 	 * the first time through here, rather than from the current register
537 	 * value, 'cos that will have been cleared by a soft RESET since.
538 	 * In this way we preserve the OBP/nexus-parent's preferred settings
539 	 * of the parity-error and system-error enable bits across multiple
540 	 * chip RESETs.
541 	 */
542 	command = bgep->chipid.command | PCI_COMM_MAE;
543 	command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL);
544 	if (enable_dma)
545 		command |= PCI_COMM_ME;
546 	/*
547 	 * on BCM5714 revision A0, false parity error gets generated
548 	 * due to a logic bug. Provide a workaround by disabling parity
549 	 * error.
550 	 */
551 	if (((cidp->device == DEVICE_ID_5714C) ||
552 	    (cidp->device == DEVICE_ID_5714S)) &&
553 	    (cidp->revision == REVISION_ID_5714_A0)) {
554 		command &= ~PCI_COMM_PARITY_DETECT;
555 	}
556 	pci_config_put16(handle, PCI_CONF_COMM, command);
557 
558 	/*
559 	 * On some PCI-E device, there were instances when
560 	 * the device was still link training.
561 	 */
562 	if (bgep->chipid.pci_type == BGE_PCI_E) {
563 		i = 0;
564 		value16 = pci_config_get16(handle, PCI_CONF_COMM);
565 		while ((value16 != command) && (i < 100)) {
566 			drv_usecwait(200);
567 			value16 = pci_config_get16(handle, PCI_CONF_COMM);
568 			++i;
569 		}
570 	}
571 
572 	/*
573 	 * Clear any remaining error status bits
574 	 */
575 	pci_config_put16(handle, PCI_CONF_STAT, ~0);
576 
577 	/*
578 	 * Do following if and only if the device is NOT BCM5714C OR
579 	 * BCM5715C
580 	 */
581 	if (!((cidp->device == DEVICE_ID_5714C) ||
582 		(cidp->device == DEVICE_ID_5715C))) {
583 		/*
584 		 * Make sure these indirect-access registers are sane
585 		 * rather than random after power-up or reset
586 		 */
587 		pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0);
588 		pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0);
589 	}
590 	/*
591 	 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering
592 	 */
593 	bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED);
594 
595 	if (cidp->pci_type == BGE_PCI_E)
596 		bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL,
597 				DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
598 }
599 
600 #ifdef __amd64
601 /*
602  * Distinguish CPU types
603  *
604  * These use to  distinguish AMD64 or Intel EM64T of CPU running mode.
605  * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine
606  * for PCI-Express based network interface card. This is the work-around
607  * for those nics.
608  */
609 static boolean_t bge_get_em64t_type(void);
610 #pragma	inline(bge_get_em64t_type)
611 
612 static boolean_t
613 bge_get_em64t_type(void)
614 {
615 
616 	return (x86_vendor == X86_VENDOR_Intel);
617 }
618 #endif
619 
620 /*
621  * Operating register get/set access routines
622  */
623 
624 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno);
625 #pragma	inline(bge_reg_get32)
626 
627 uint32_t
628 bge_reg_get32(bge_t *bgep, bge_regno_t regno)
629 {
630 	BGE_TRACE(("bge_reg_get32($%p, 0x%lx)",
631 		(void *)bgep, regno));
632 
633 	return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)));
634 }
635 
636 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data);
637 #pragma	inline(bge_reg_put32)
638 
639 void
640 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data)
641 {
642 	BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)",
643 		(void *)bgep, regno, data));
644 
645 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data);
646 	BGE_PCICHK(bgep);
647 }
648 
649 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
650 #pragma	inline(bge_reg_set32)
651 
652 void
653 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
654 {
655 	uint32_t regval;
656 
657 	BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)",
658 		(void *)bgep, regno, bits));
659 
660 	regval = bge_reg_get32(bgep, regno);
661 	regval |= bits;
662 	bge_reg_put32(bgep, regno, regval);
663 }
664 
665 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
666 #pragma	inline(bge_reg_clr32)
667 
668 void
669 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
670 {
671 	uint32_t regval;
672 
673 	BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)",
674 		(void *)bgep, regno, bits));
675 
676 	regval = bge_reg_get32(bgep, regno);
677 	regval &= ~bits;
678 	bge_reg_put32(bgep, regno, regval);
679 }
680 
681 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno);
682 #pragma	inline(bge_reg_get64)
683 
684 static uint64_t
685 bge_reg_get64(bge_t *bgep, bge_regno_t regno)
686 {
687 	uint64_t regval;
688 
689 #ifdef	__amd64
690 	if (bge_get_em64t_type()) {
691 		regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
692 		regval <<= 32;
693 		regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
694 	} else {
695 		regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
696 	}
697 #else
698 	regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
699 #endif
700 
701 #ifdef	_LITTLE_ENDIAN
702 	regval = (regval >> 32) | (regval << 32);
703 #endif	/* _LITTLE_ENDIAN */
704 
705 	BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx",
706 		(void *)bgep, regno, regval));
707 
708 	return (regval);
709 }
710 
711 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data);
712 #pragma	inline(bge_reg_put64)
713 
714 static void
715 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data)
716 {
717 	BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)",
718 		(void *)bgep, regno, data));
719 
720 #ifdef	_LITTLE_ENDIAN
721 	data = ((data >> 32) | (data << 32));
722 #endif	/* _LITTLE_ENDIAN */
723 
724 #ifdef	__amd64
725 	if (bge_get_em64t_type()) {
726 		ddi_put32(bgep->io_handle,
727 			PIO_ADDR(bgep, regno), (uint32_t)data);
728 		BGE_PCICHK(bgep);
729 		ddi_put32(bgep->io_handle,
730 			PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32));
731 
732 	} else {
733 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
734 	}
735 #else
736 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
737 #endif
738 
739 	BGE_PCICHK(bgep);
740 }
741 
742 /*
743  * The DDI doesn't provide get/put functions for 128 bit data
744  * so we put RCBs out as two 64-bit chunks instead.
745  */
746 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
747 #pragma	inline(bge_reg_putrcb)
748 
749 static void
750 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
751 {
752 	uint64_t *p;
753 
754 	BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
755 		(void *)bgep, addr, rcbp->host_ring_addr,
756 		rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
757 
758 	ASSERT((addr % sizeof (*rcbp)) == 0);
759 
760 	p = (void *)rcbp;
761 	bge_reg_put64(bgep, addr, *p++);
762 	bge_reg_put64(bgep, addr+8, *p);
763 }
764 
765 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data);
766 #pragma	inline(bge_mbx_put)
767 
768 void
769 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data)
770 {
771 	BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)",
772 		(void *)bgep, regno, data));
773 
774 	/*
775 	 * Mailbox registers are nominally 64 bits on the 5701, but
776 	 * the MSW isn't used.  On the 5703, they're only 32 bits
777 	 * anyway.  So here we just write the lower(!) 32 bits -
778 	 * remembering that the chip is big-endian, even though the
779 	 * PCI bus is little-endian ...
780 	 */
781 #ifdef	_BIG_ENDIAN
782 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data);
783 #else
784 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data);
785 #endif	/* _BIG_ENDIAN */
786 	BGE_PCICHK(bgep);
787 }
788 
789 #if	BGE_DEBUGGING
790 
791 void bge_led_mark(bge_t *bgep);
792 #pragma	no_inline(bge_led_mark)
793 
794 void
795 bge_led_mark(bge_t *bgep)
796 {
797 	uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK |
798 			    LED_CONTROL_1000MBPS_LED |
799 			    LED_CONTROL_100MBPS_LED |
800 			    LED_CONTROL_10MBPS_LED;
801 
802 	/*
803 	 * Blink all three LINK LEDs on simultaneously, then all off,
804 	 * then restore to automatic hardware control.  This is used
805 	 * in laboratory testing to trigger a logic analyser or scope.
806 	 */
807 	bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
808 	led_ctrl ^= LED_CONTROL_OVERRIDE_LINK;
809 	bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
810 	led_ctrl = LED_CONTROL_OVERRIDE_LINK;
811 	bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
812 }
813 
814 #endif	/* BGE_DEBUGGING */
815 
816 /*
817  * NIC on-chip memory access routines
818  *
819  * Only 32K of NIC memory is visible at a time, controlled by the
820  * Memory Window Base Address Register (in PCI config space).  Once
821  * this is set, the 32K region of NIC-local memory that it refers
822  * to can be directly addressed in the upper 32K of the 64K of PCI
823  * memory space used for the device.
824  */
825 
826 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base);
827 #pragma	inline(bge_nic_setwin)
828 
829 static void
830 bge_nic_setwin(bge_t *bgep, bge_regno_t base)
831 {
832 	chip_id_t *cidp;
833 
834 	BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)",
835 		(void *)bgep, base));
836 
837 	ASSERT((base & MWBAR_GRANULE_MASK) == 0);
838 
839 	/*
840 	 * Don't do repeated zero data writes,
841 	 * if the device is BCM5714C/15C.
842 	 */
843 	cidp = &bgep->chipid;
844 	if ((cidp->device == DEVICE_ID_5714C) ||
845 		(cidp->device == DEVICE_ID_5715C)) {
846 		if (bgep->lastWriteZeroData && (base == (bge_regno_t)0))
847 			return;
848 		/* Adjust lastWriteZeroData */
849 		bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ?
850 			B_TRUE : B_FALSE);
851 	}
852 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base);
853 }
854 
855 
856 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr);
857 #pragma	inline(bge_nic_get32)
858 
859 static uint32_t
860 bge_nic_get32(bge_t *bgep, bge_regno_t addr)
861 {
862 	uint32_t data;
863 
864 #ifdef BGE_IPMI_ASF
865 	if (bgep->asf_enabled && !bgep->asf_wordswapped) {
866 		/* workaround for word swap error */
867 		if (addr & 4)
868 			addr = addr - 4;
869 		else
870 			addr = addr + 4;
871 	}
872 #endif
873 
874 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
875 	addr &= MWBAR_GRANULE_MASK;
876 	addr += NIC_MEM_WINDOW_OFFSET;
877 
878 	data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
879 
880 	BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x",
881 		(void *)bgep, addr, data));
882 
883 	return (data);
884 }
885 
886 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data);
887 #pragma inline(bge_nic_put32)
888 
889 void
890 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data)
891 {
892 	BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)",
893 		(void *)bgep, addr, data));
894 
895 #ifdef BGE_IPMI_ASF
896 	if (bgep->asf_enabled && !bgep->asf_wordswapped) {
897 		/* workaround for word swap error */
898 		if (addr & 4)
899 			addr = addr - 4;
900 		else
901 			addr = addr + 4;
902 	}
903 #endif
904 
905 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
906 	addr &= MWBAR_GRANULE_MASK;
907 	addr += NIC_MEM_WINDOW_OFFSET;
908 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data);
909 	BGE_PCICHK(bgep);
910 }
911 
912 
913 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr);
914 #pragma	inline(bge_nic_get64)
915 
916 static uint64_t
917 bge_nic_get64(bge_t *bgep, bge_regno_t addr)
918 {
919 	uint64_t data;
920 
921 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
922 	addr &= MWBAR_GRANULE_MASK;
923 	addr += NIC_MEM_WINDOW_OFFSET;
924 
925 #ifdef	__amd64
926 		if (bge_get_em64t_type()) {
927 			data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
928 			data <<= 32;
929 			data |= ddi_get32(bgep->io_handle,
930 				PIO_ADDR(bgep, addr + 4));
931 		} else {
932 			data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
933 		}
934 #else
935 		data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
936 #endif
937 
938 	BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx",
939 		(void *)bgep, addr, data));
940 
941 	return (data);
942 }
943 
944 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data);
945 #pragma	inline(bge_nic_put64)
946 
947 static void
948 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data)
949 {
950 	BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)",
951 		(void *)bgep, addr, data));
952 
953 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
954 	addr &= MWBAR_GRANULE_MASK;
955 	addr += NIC_MEM_WINDOW_OFFSET;
956 
957 #ifdef	__amd64
958 	if (bge_get_em64t_type()) {
959 		ddi_put32(bgep->io_handle,
960 			PIO_ADDR(bgep, addr), (uint32_t)data);
961 		BGE_PCICHK(bgep);
962 		ddi_put32(bgep->io_handle,
963 			PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32));
964 	} else {
965 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
966 	}
967 #else
968 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
969 #endif
970 
971 	BGE_PCICHK(bgep);
972 }
973 
974 /*
975  * The DDI doesn't provide get/put functions for 128 bit data
976  * so we put RCBs out as two 64-bit chunks instead.
977  */
978 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
979 #pragma	inline(bge_nic_putrcb)
980 
981 static void
982 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
983 {
984 	uint64_t *p;
985 
986 	BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
987 		(void *)bgep, addr, rcbp->host_ring_addr,
988 		rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
989 
990 	ASSERT((addr % sizeof (*rcbp)) == 0);
991 
992 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
993 	addr &= MWBAR_GRANULE_MASK;
994 	addr += NIC_MEM_WINDOW_OFFSET;
995 
996 	p = (void *)rcbp;
997 #ifdef	__amd64
998 	if (bge_get_em64t_type()) {
999 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
1000 			(uint32_t)(*p));
1001 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
1002 			(uint32_t)(*p >> 32));
1003 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
1004 			(uint32_t)(*(p + 1)));
1005 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
1006 			(uint32_t)(*p >> 32));
1007 
1008 	} else {
1009 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1010 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p);
1011 	}
1012 #else
1013 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1014 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
1015 #endif
1016 
1017 	BGE_PCICHK(bgep);
1018 }
1019 
1020 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes);
1021 #pragma	inline(bge_nic_zero)
1022 
1023 static void
1024 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes)
1025 {
1026 	BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)",
1027 		(void *)bgep, addr, nbytes));
1028 
1029 	ASSERT((addr & ~MWBAR_GRANULE_MASK) ==
1030 		((addr+nbytes) & ~MWBAR_GRANULE_MASK));
1031 
1032 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1033 	addr &= MWBAR_GRANULE_MASK;
1034 	addr += NIC_MEM_WINDOW_OFFSET;
1035 
1036 	(void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr),
1037 		nbytes, 1, DDI_DATA_SZ08_ACC);
1038 	BGE_PCICHK(bgep);
1039 }
1040 
1041 /*
1042  * MII (PHY) register get/set access routines
1043  *
1044  * These use the chip's MII auto-access method, controlled by the
1045  * MII Communication register at 0x044c, so the CPU doesn't have
1046  * to fiddle with the individual bits.
1047  */
1048 
1049 #undef	BGE_DBG
1050 #define	BGE_DBG		BGE_DBG_MII	/* debug flag for this code	*/
1051 
1052 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno,
1053 				uint16_t data, uint32_t cmd);
1054 #pragma	no_inline(bge_mii_access)
1055 
1056 static uint16_t
1057 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd)
1058 {
1059 	uint32_t timeout;
1060 	uint32_t regval1;
1061 	uint32_t regval2;
1062 
1063 	BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)",
1064 		(void *)bgep, regno, data, cmd));
1065 
1066 	ASSERT(mutex_owned(bgep->genlock));
1067 
1068 	/*
1069 	 * Assemble the command ...
1070 	 */
1071 	cmd |= data << MI_COMMS_DATA_SHIFT;
1072 	cmd |= regno << MI_COMMS_REGISTER_SHIFT;
1073 	cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT;
1074 	cmd |= MI_COMMS_START;
1075 
1076 	/*
1077 	 * Wait for any command already in progress ...
1078 	 *
1079 	 * Note: this *shouldn't* ever find that there is a command
1080 	 * in progress, because we already hold the <genlock> mutex.
1081 	 * Nonetheless, we have sometimes seen the MI_COMMS_START
1082 	 * bit set here -- it seems that the chip can initiate MII
1083 	 * accesses internally, even with polling OFF.
1084 	 */
1085 	regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1086 	for (timeout = 100; ; ) {
1087 		if ((regval2 & MI_COMMS_START) == 0) {
1088 			bge_reg_put32(bgep, MI_COMMS_REG, cmd);
1089 			break;
1090 		}
1091 		if (--timeout == 0)
1092 			break;
1093 		drv_usecwait(10);
1094 		regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1095 	}
1096 
1097 	if (timeout == 0)
1098 		return ((uint16_t)~0u);
1099 
1100 	if (timeout != 100)
1101 		BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1102 			"MI_COMMS_START set for %d us; 0x%x->0x%x",
1103 			cmd, 10*(100-timeout), regval1, regval2));
1104 
1105 	regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1106 	for (timeout = 1000; ; ) {
1107 		if ((regval1 & MI_COMMS_START) == 0)
1108 			break;
1109 		if (--timeout == 0)
1110 			break;
1111 		drv_usecwait(10);
1112 		regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1113 	}
1114 
1115 	/*
1116 	 * Drop out early if the READ FAILED bit is set -- this chip
1117 	 * could be a 5703/4S, with a SerDes instead of a PHY!
1118 	 */
1119 	if (regval2 & MI_COMMS_READ_FAILED)
1120 		return ((uint16_t)~0u);
1121 
1122 	if (timeout == 0)
1123 		return ((uint16_t)~0u);
1124 
1125 	/*
1126 	 * The PRM says to wait 5us after seeing the START bit clear
1127 	 * and then re-read the register to get the final value of the
1128 	 * data field, in order to avoid a race condition where the
1129 	 * START bit is clear but the data field isn't yet valid.
1130 	 *
1131 	 * Note: we don't actually seem to be encounter this race;
1132 	 * except when the START bit is seen set again (see below),
1133 	 * the data field doesn't change during this 5us interval.
1134 	 */
1135 	drv_usecwait(5);
1136 	regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1137 
1138 	/*
1139 	 * Unfortunately, when following the PRMs instructions above,
1140 	 * we have occasionally seen the START bit set again(!) in the
1141 	 * value read after the 5us delay. This seems to be due to the
1142 	 * chip autonomously starting another MII access internally.
1143 	 * In such cases, the command/data/etc fields relate to the
1144 	 * internal command, rather than the one that we thought had
1145 	 * just finished.  So in this case, we fall back to returning
1146 	 * the data from the original read that showed START clear.
1147 	 */
1148 	if (regval2 & MI_COMMS_START) {
1149 		BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1150 			"MI_COMMS_START set after transaction; 0x%x->0x%x",
1151 			cmd, regval1, regval2));
1152 		regval2 = regval1;
1153 	}
1154 
1155 	if (regval2 & MI_COMMS_START)
1156 		return ((uint16_t)~0u);
1157 
1158 	if (regval2 & MI_COMMS_READ_FAILED)
1159 		return ((uint16_t)~0u);
1160 
1161 	return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT);
1162 }
1163 
1164 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno);
1165 #pragma	no_inline(bge_mii_get16)
1166 
1167 uint16_t
1168 bge_mii_get16(bge_t *bgep, bge_regno_t regno)
1169 {
1170 	BGE_TRACE(("bge_mii_get16($%p, 0x%lx)",
1171 		(void *)bgep, regno));
1172 
1173 	ASSERT(mutex_owned(bgep->genlock));
1174 
1175 	return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ));
1176 }
1177 
1178 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data);
1179 #pragma	no_inline(bge_mii_put16)
1180 
1181 void
1182 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data)
1183 {
1184 	BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)",
1185 		(void *)bgep, regno, data));
1186 
1187 	ASSERT(mutex_owned(bgep->genlock));
1188 
1189 	(void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE);
1190 }
1191 
1192 #undef	BGE_DBG
1193 #define	BGE_DBG		BGE_DBG_SEEPROM	/* debug flag for this code	*/
1194 
1195 #if	BGE_SEE_IO32 || BGE_FLASH_IO32
1196 
1197 /*
1198  * Basic SEEPROM get/set access routine
1199  *
1200  * This uses the chip's SEEPROM auto-access method, controlled by the
1201  * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU
1202  * doesn't have to fiddle with the individual bits.
1203  *
1204  * The caller should hold <genlock> and *also* have already acquired
1205  * the right to access the SEEPROM, via bge_nvmem_acquire() above.
1206  *
1207  * Return value:
1208  *	0 on success,
1209  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1210  *	EPROTO on other h/w or s/w errors.
1211  *
1212  * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output
1213  * from a (successful) SEEPROM_ACCESS_READ.
1214  */
1215 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1216 				uint32_t *dp);
1217 #pragma	no_inline(bge_seeprom_access)
1218 
1219 static int
1220 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1221 {
1222 	uint32_t tries;
1223 	uint32_t regval;
1224 
1225 	ASSERT(mutex_owned(bgep->genlock));
1226 
1227 	/*
1228 	 * On the newer chips that support both SEEPROM & Flash, we need
1229 	 * to specifically enable SEEPROM access (Flash is the default).
1230 	 * On older chips, we don't; SEEPROM is the only NVtype supported,
1231 	 * and the NVM control registers don't exist ...
1232 	 */
1233 	switch (bgep->chipid.nvtype) {
1234 	case BGE_NVTYPE_NONE:
1235 	case BGE_NVTYPE_UNKNOWN:
1236 		_NOTE(NOTREACHED)
1237 	case BGE_NVTYPE_SEEPROM:
1238 		break;
1239 
1240 	case BGE_NVTYPE_LEGACY_SEEPROM:
1241 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1242 	case BGE_NVTYPE_BUFFERED_FLASH:
1243 	default:
1244 		bge_reg_set32(bgep, NVM_CONFIG1_REG,
1245 				NVM_CFG1_LEGACY_SEEPROM_MODE);
1246 		break;
1247 	}
1248 
1249 	/*
1250 	 * Check there's no command in progress.
1251 	 *
1252 	 * Note: this *shouldn't* ever find that there is a command
1253 	 * in progress, because we already hold the <genlock> mutex.
1254 	 * Also, to ensure we don't have a conflict with the chip's
1255 	 * internal firmware or a process accessing the same (shared)
1256 	 * SEEPROM through the other port of a 5704, we've already
1257 	 * been through the "software arbitration" protocol.
1258 	 * So this is just a final consistency check: we shouldn't
1259 	 * see EITHER the START bit (command started but not complete)
1260 	 * OR the COMPLETE bit (command completed but not cleared).
1261 	 */
1262 	regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1263 	if (regval & SEEPROM_ACCESS_START)
1264 		return (EPROTO);
1265 	if (regval & SEEPROM_ACCESS_COMPLETE)
1266 		return (EPROTO);
1267 
1268 	/*
1269 	 * Assemble the command ...
1270 	 */
1271 	cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK;
1272 	addr >>= SEEPROM_ACCESS_ADDRESS_SIZE;
1273 	addr <<= SEEPROM_ACCESS_DEVID_SHIFT;
1274 	cmd |= addr & SEEPROM_ACCESS_DEVID_MASK;
1275 	cmd |= SEEPROM_ACCESS_START;
1276 	cmd |= SEEPROM_ACCESS_COMPLETE;
1277 	cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK;
1278 
1279 	bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp);
1280 	bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd);
1281 
1282 	/*
1283 	 * By observation, a successful access takes ~20us on a 5703/4,
1284 	 * but apparently much longer (up to 1000us) on the obsolescent
1285 	 * BCM5700/BCM5701.  We want to be sure we don't get any false
1286 	 * timeouts here; but OTOH, we don't want a bogus access to lock
1287 	 * out interrupts for longer than necessary. So we'll allow up
1288 	 * to 1000us ...
1289 	 */
1290 	for (tries = 0; tries < 1000; ++tries) {
1291 		regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1292 		if (regval & SEEPROM_ACCESS_COMPLETE)
1293 			break;
1294 		drv_usecwait(1);
1295 	}
1296 
1297 	if (regval & SEEPROM_ACCESS_COMPLETE) {
1298 		/*
1299 		 * All OK; read the SEEPROM data register, then write back
1300 		 * the value read from the address register in order to
1301 		 * clear the <complete> bit and leave the SEEPROM access
1302 		 * state machine idle, ready for the next access ...
1303 		 */
1304 		BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries));
1305 		*dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG);
1306 		bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval);
1307 		return (0);
1308 	}
1309 
1310 	/*
1311 	 * Hmm ... what happened here?
1312 	 *
1313 	 * Most likely, the user addressed a non-existent SEEPROM. Or
1314 	 * maybe the SEEPROM was busy internally (e.g. processing a write)
1315 	 * and didn't respond to being addressed. Either way, it's left
1316 	 * the SEEPROM access state machine wedged. So we'll reset it
1317 	 * before we leave, so it's ready for next time ...
1318 	 */
1319 	BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries));
1320 	bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
1321 	return (ENODATA);
1322 }
1323 
1324 /*
1325  * Basic Flash get/set access routine
1326  *
1327  * These use the chip's Flash auto-access method, controlled by the
1328  * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to
1329  * fiddle with the individual bits.
1330  *
1331  * The caller should hold <genlock> and *also* have already acquired
1332  * the right to access the Flash, via bge_nvmem_acquire() above.
1333  *
1334  * Return value:
1335  *	0 on success,
1336  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1337  *	ENODEV if the NVmem device is missing or otherwise unusable
1338  *
1339  * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output
1340  * from a (successful) NVM_FLASH_CMD_RD.
1341  */
1342 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1343 				uint32_t *dp);
1344 #pragma	no_inline(bge_flash_access)
1345 
1346 static int
1347 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1348 {
1349 	uint32_t tries;
1350 	uint32_t regval;
1351 
1352 	ASSERT(mutex_owned(bgep->genlock));
1353 
1354 	/*
1355 	 * On the newer chips that support both SEEPROM & Flash, we need
1356 	 * to specifically disable SEEPROM access while accessing Flash.
1357 	 * The older chips don't support Flash, and the NVM registers don't
1358 	 * exist, so we shouldn't be here at all!
1359 	 */
1360 	switch (bgep->chipid.nvtype) {
1361 	case BGE_NVTYPE_NONE:
1362 	case BGE_NVTYPE_UNKNOWN:
1363 		_NOTE(NOTREACHED)
1364 	case BGE_NVTYPE_SEEPROM:
1365 		return (ENODEV);
1366 
1367 	case BGE_NVTYPE_LEGACY_SEEPROM:
1368 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1369 	case BGE_NVTYPE_BUFFERED_FLASH:
1370 	default:
1371 		bge_reg_clr32(bgep, NVM_CONFIG1_REG,
1372 				NVM_CFG1_LEGACY_SEEPROM_MODE);
1373 		break;
1374 	}
1375 
1376 	/*
1377 	 * Assemble the command ...
1378 	 */
1379 	addr &= NVM_FLASH_ADDR_MASK;
1380 	cmd |= NVM_FLASH_CMD_DOIT;
1381 	cmd |= NVM_FLASH_CMD_FIRST;
1382 	cmd |= NVM_FLASH_CMD_LAST;
1383 	cmd |= NVM_FLASH_CMD_DONE;
1384 
1385 	bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp);
1386 	bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr);
1387 	bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd);
1388 
1389 	/*
1390 	 * Allow up to 1000ms ...
1391 	 */
1392 	for (tries = 0; tries < 1000; ++tries) {
1393 		regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG);
1394 		if (regval & NVM_FLASH_CMD_DONE)
1395 			break;
1396 		drv_usecwait(1);
1397 	}
1398 
1399 	if (regval & NVM_FLASH_CMD_DONE) {
1400 		/*
1401 		 * All OK; read the data from the Flash read register
1402 		 */
1403 		BGE_DEBUG(("bge_flash_access: complete after %d us", tries));
1404 		*dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG);
1405 		return (0);
1406 	}
1407 
1408 	/*
1409 	 * Hmm ... what happened here?
1410 	 *
1411 	 * Most likely, the user addressed a non-existent Flash. Or
1412 	 * maybe the Flash was busy internally (e.g. processing a write)
1413 	 * and didn't respond to being addressed. Either way, there's
1414 	 * nothing we can here ...
1415 	 */
1416 	BGE_DEBUG(("bge_flash_access: timed out after %d us", tries));
1417 	return (ENODATA);
1418 }
1419 
1420 /*
1421  * The next two functions regulate access to the NVram (if fitted).
1422  *
1423  * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash
1424  * (SPI) interface, but they can be accessed through either port. These
1425  * are managed by different instance of this driver and have no software
1426  * state in common.
1427  *
1428  * In addition (and even on a single core chip) the chip's internal
1429  * firmware can access the SEEPROM/Flash, most notably after a RESET
1430  * when it may download code to run internally.
1431  *
1432  * So we need to arbitrate between these various software agents.  For
1433  * this purpose, the chip provides the Software Arbitration Register,
1434  * which implements hardware(!) arbitration.
1435  *
1436  * This functionality didn't exist on older (5700/5701) chips, so there's
1437  * nothing we can do by way of arbitration on those; also, if there's no
1438  * SEEPROM/Flash fitted (or we couldn't determine what type), there's also
1439  * nothing to do.
1440  *
1441  * The internal firmware appears to use Request 0, which is the highest
1442  * priority.  So we'd like to use Request 2, leaving one higher and one
1443  * lower for any future developments ... but apparently this doesn't
1444  * always work.  So for now, the code uses Request 1 ;-(
1445  */
1446 
1447 #define	NVM_READ_REQ	NVM_READ_REQ1
1448 #define	NVM_RESET_REQ	NVM_RESET_REQ1
1449 #define	NVM_SET_REQ	NVM_SET_REQ1
1450 
1451 static void bge_nvmem_relinquish(bge_t *bgep);
1452 #pragma	no_inline(bge_nvmem_relinquish)
1453 
1454 static void
1455 bge_nvmem_relinquish(bge_t *bgep)
1456 {
1457 	ASSERT(mutex_owned(bgep->genlock));
1458 
1459 	switch (bgep->chipid.nvtype) {
1460 	case BGE_NVTYPE_NONE:
1461 	case BGE_NVTYPE_UNKNOWN:
1462 		_NOTE(NOTREACHED)
1463 		return;
1464 
1465 	case BGE_NVTYPE_SEEPROM:
1466 		/*
1467 		 * No arbitration performed, no release needed
1468 		 */
1469 		return;
1470 
1471 	case BGE_NVTYPE_LEGACY_SEEPROM:
1472 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1473 	case BGE_NVTYPE_BUFFERED_FLASH:
1474 	default:
1475 		break;
1476 	}
1477 
1478 	/*
1479 	 * Our own request should be present (whether or not granted) ...
1480 	 */
1481 	(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1482 
1483 	/*
1484 	 * ... this will make it go away.
1485 	 */
1486 	bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ);
1487 	(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1488 }
1489 
1490 /*
1491  * Arbitrate for access to the NVmem, if necessary
1492  *
1493  * Return value:
1494  *	0 on success
1495  *	EAGAIN if the device is in use (retryable)
1496  *	ENODEV if the NVmem device is missing or otherwise unusable
1497  */
1498 static int bge_nvmem_acquire(bge_t *bgep);
1499 #pragma	no_inline(bge_nvmem_acquire)
1500 
1501 static int
1502 bge_nvmem_acquire(bge_t *bgep)
1503 {
1504 	uint32_t regval;
1505 	uint32_t tries;
1506 
1507 	ASSERT(mutex_owned(bgep->genlock));
1508 
1509 	switch (bgep->chipid.nvtype) {
1510 	case BGE_NVTYPE_NONE:
1511 	case BGE_NVTYPE_UNKNOWN:
1512 		/*
1513 		 * Access denied: no (recognisable) device fitted
1514 		 */
1515 		return (ENODEV);
1516 
1517 	case BGE_NVTYPE_SEEPROM:
1518 		/*
1519 		 * Access granted: no arbitration needed (or possible)
1520 		 */
1521 		return (0);
1522 
1523 	case BGE_NVTYPE_LEGACY_SEEPROM:
1524 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1525 	case BGE_NVTYPE_BUFFERED_FLASH:
1526 	default:
1527 		/*
1528 		 * Access conditional: conduct arbitration protocol
1529 		 */
1530 		break;
1531 	}
1532 
1533 	/*
1534 	 * We're holding the per-port mutex <genlock>, so no-one other
1535 	 * thread can be attempting to access the NVmem through *this*
1536 	 * port. But it could be in use by the *other* port (of a 5704),
1537 	 * or by the chip's internal firmware, so we have to go through
1538 	 * the full (hardware) arbitration protocol ...
1539 	 *
1540 	 * Note that *because* we're holding <genlock>, the interrupt handler
1541 	 * won't be able to progress.  So we're only willing to spin for a
1542 	 * fairly short time.  Specifically:
1543 	 *
1544 	 *	We *must* wait long enough for the hardware to resolve all
1545 	 *	requests and determine the winner.  Fortunately, this is
1546 	 *	"almost instantaneous", even as observed by GHz CPUs.
1547 	 *
1548 	 *	A successful access by another Solaris thread (via either
1549 	 *	port) typically takes ~20us.  So waiting a bit longer than
1550 	 *	that will give a good chance of success, if the other user
1551 	 *	*is* another thread on the other port.
1552 	 *
1553 	 *	However, the internal firmware can hold on to the NVmem
1554 	 *	for *much* longer: at least 10 milliseconds just after a
1555 	 *	RESET, and maybe even longer if the NVmem actually contains
1556 	 *	code to download and run on the internal CPUs.
1557 	 *
1558 	 * So, we'll allow 50us; if that's not enough then it's up to the
1559 	 * caller to retry later (hence the choice of return code EAGAIN).
1560 	 */
1561 	regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1562 	bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ);
1563 
1564 	for (tries = 0; tries < 50; ++tries) {
1565 		regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1566 		if (regval & NVM_WON_REQ1)
1567 			break;
1568 		drv_usecwait(1);
1569 	}
1570 
1571 	if (regval & NVM_WON_REQ1) {
1572 		BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries));
1573 		return (0);
1574 	}
1575 
1576 	/*
1577 	 * Somebody else must be accessing the NVmem, so abandon our
1578 	 * attempt take control of it.  The caller can try again later ...
1579 	 */
1580 	BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries));
1581 	bge_nvmem_relinquish(bgep);
1582 	return (EAGAIN);
1583 }
1584 
1585 /*
1586  * This code assumes that the GPIO1 bit has been wired up to the NVmem
1587  * write protect line in such a way that the NVmem is protected when
1588  * GPIO1 is an input, or is an output but driven high.  Thus, to make the
1589  * NVmem writable we have to change GPIO1 to an output AND drive it low.
1590  *
1591  * Note: there's only one set of GPIO pins on a 5704, even though they
1592  * can be accessed through either port.  So the chip has to resolve what
1593  * happens if the two ports program a single pin differently ... the rule
1594  * it uses is that if the ports disagree about the *direction* of a pin,
1595  * "output" wins over "input", but if they disagree about its *value* as
1596  * an output, then the pin is TRISTATED instead!  In such a case, no-one
1597  * wins, and the external signal does whatever the external circuitry
1598  * defines as the default -- which we've assumed is the PROTECTED state.
1599  * So, we always change GPIO1 back to being an *input* whenever we're not
1600  * specifically using it to unprotect the NVmem. This allows either port
1601  * to update the NVmem, although obviously only one at a time!
1602  *
1603  * The caller should hold <genlock> and *also* have already acquired the
1604  * right to access the NVmem, via bge_nvmem_acquire() above.
1605  */
1606 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect);
1607 #pragma	inline(bge_nvmem_protect)
1608 
1609 static void
1610 bge_nvmem_protect(bge_t *bgep, boolean_t protect)
1611 {
1612 	uint32_t regval;
1613 
1614 	ASSERT(mutex_owned(bgep->genlock));
1615 
1616 	regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
1617 	if (protect) {
1618 		regval |= MLCR_MISC_PINS_OUTPUT_1;
1619 		regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1620 	} else {
1621 		regval &= ~MLCR_MISC_PINS_OUTPUT_1;
1622 		regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1623 	}
1624 	bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval);
1625 }
1626 
1627 /*
1628  * Now put it all together ...
1629  *
1630  * Try to acquire control of the NVmem; if successful, then:
1631  *	unprotect it (if we want to write to it)
1632  *	perform the requested access
1633  *	reprotect it (after a write)
1634  *	relinquish control
1635  *
1636  * Return value:
1637  *	0 on success,
1638  *	EAGAIN if the device is in use (retryable)
1639  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1640  *	ENODEV if the NVmem device is missing or otherwise unusable
1641  *	EPROTO on other h/w or s/w errors.
1642  */
1643 static int
1644 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1645 {
1646 	int err;
1647 
1648 	if ((err = bge_nvmem_acquire(bgep)) == 0) {
1649 		switch (cmd) {
1650 		case BGE_SEE_READ:
1651 			err = bge_seeprom_access(bgep,
1652 			    SEEPROM_ACCESS_READ, addr, dp);
1653 			break;
1654 
1655 		case BGE_SEE_WRITE:
1656 			bge_nvmem_protect(bgep, B_FALSE);
1657 			err = bge_seeprom_access(bgep,
1658 			    SEEPROM_ACCESS_WRITE, addr, dp);
1659 			bge_nvmem_protect(bgep, B_TRUE);
1660 			break;
1661 
1662 		case BGE_FLASH_READ:
1663 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1664 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1665 				bge_reg_set32(bgep, NVM_ACCESS_REG,
1666 				    NVM_ACCESS_ENABLE);
1667 			}
1668 			err = bge_flash_access(bgep,
1669 			    NVM_FLASH_CMD_RD, addr, dp);
1670 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1671 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1672 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
1673 				    NVM_ACCESS_ENABLE);
1674 			}
1675 			break;
1676 
1677 		case BGE_FLASH_WRITE:
1678 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1679 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1680 				bge_reg_set32(bgep, NVM_ACCESS_REG,
1681 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1682 			}
1683 			bge_nvmem_protect(bgep, B_FALSE);
1684 			err = bge_flash_access(bgep,
1685 			    NVM_FLASH_CMD_WR, addr, dp);
1686 			bge_nvmem_protect(bgep, B_TRUE);
1687 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1688 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1689 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
1690 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1691 			}
1692 
1693 			break;
1694 
1695 		default:
1696 			_NOTE(NOTREACHED)
1697 			break;
1698 		}
1699 		bge_nvmem_relinquish(bgep);
1700 	}
1701 
1702 	BGE_DEBUG(("bge_nvmem_rw32: err %d", err));
1703 	return (err);
1704 }
1705 
1706 /*
1707  * Attempt to get a MAC address from the SEEPROM or Flash, if any
1708  */
1709 static uint64_t bge_get_nvmac(bge_t *bgep);
1710 #pragma no_inline(bge_get_nvmac)
1711 
1712 static uint64_t
1713 bge_get_nvmac(bge_t *bgep)
1714 {
1715 	uint32_t mac_high;
1716 	uint32_t mac_low;
1717 	uint32_t addr;
1718 	uint32_t cmd;
1719 	uint64_t mac;
1720 
1721 	BGE_TRACE(("bge_get_nvmac($%p)",
1722 		(void *)bgep));
1723 
1724 	switch (bgep->chipid.nvtype) {
1725 	case BGE_NVTYPE_NONE:
1726 	case BGE_NVTYPE_UNKNOWN:
1727 	default:
1728 		return (0ULL);
1729 
1730 	case BGE_NVTYPE_SEEPROM:
1731 	case BGE_NVTYPE_LEGACY_SEEPROM:
1732 		cmd = BGE_SEE_READ;
1733 		break;
1734 
1735 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1736 	case BGE_NVTYPE_BUFFERED_FLASH:
1737 		cmd = BGE_FLASH_READ;
1738 		break;
1739 	}
1740 
1741 	addr = NVMEM_DATA_MAC_ADDRESS;
1742 	if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high))
1743 		return (0ULL);
1744 	addr += 4;
1745 	if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low))
1746 		return (0ULL);
1747 
1748 	/*
1749 	 * The Broadcom chip is natively BIG-endian, so that's how the
1750 	 * MAC address is represented in NVmem.  We may need to swap it
1751 	 * around on a little-endian host ...
1752 	 */
1753 #ifdef	_BIG_ENDIAN
1754 	mac = mac_high;
1755 	mac = mac << 32;
1756 	mac |= mac_low;
1757 #else
1758 	mac = BGE_BSWAP_32(mac_high);
1759 	mac = mac << 32;
1760 	mac |= BGE_BSWAP_32(mac_low);
1761 #endif	/* _BIG_ENDIAN */
1762 
1763 	return (mac);
1764 }
1765 
1766 #else	/* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1767 
1768 /*
1769  * Dummy version for when we're not supporting NVmem access
1770  */
1771 static uint64_t bge_get_nvmac(bge_t *bgep);
1772 #pragma inline(bge_get_nvmac)
1773 
1774 static uint64_t
1775 bge_get_nvmac(bge_t *bgep)
1776 {
1777 	_NOTE(ARGUNUSED(bgep))
1778 	return (0ULL);
1779 }
1780 
1781 #endif	/* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1782 
1783 /*
1784  * Determine the type of NVmem that is (or may be) attached to this chip,
1785  */
1786 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep);
1787 #pragma no_inline(bge_nvmem_id)
1788 
1789 static enum bge_nvmem_type
1790 bge_nvmem_id(bge_t *bgep)
1791 {
1792 	enum bge_nvmem_type nvtype;
1793 	uint32_t config1;
1794 
1795 	BGE_TRACE(("bge_nvmem_id($%p)",
1796 		(void *)bgep));
1797 
1798 	switch (bgep->chipid.device) {
1799 	default:
1800 		/*
1801 		 * We shouldn't get here; it means we don't recognise
1802 		 * the chip, which means we don't know how to determine
1803 		 * what sort of NVmem (if any) it has.  So we'll say
1804 		 * NONE, to disable the NVmem access code ...
1805 		 */
1806 		nvtype = BGE_NVTYPE_NONE;
1807 		break;
1808 
1809 	case DEVICE_ID_5700:
1810 	case DEVICE_ID_5700x:
1811 	case DEVICE_ID_5701:
1812 		/*
1813 		 * These devices support *only* SEEPROMs
1814 		 */
1815 		nvtype = BGE_NVTYPE_SEEPROM;
1816 		break;
1817 
1818 	case DEVICE_ID_5702:
1819 	case DEVICE_ID_5702fe:
1820 	case DEVICE_ID_5703C:
1821 	case DEVICE_ID_5703S:
1822 	case DEVICE_ID_5704C:
1823 	case DEVICE_ID_5704S:
1824 	case DEVICE_ID_5704:
1825 	case DEVICE_ID_5705M:
1826 	case DEVICE_ID_5705C:
1827 	case DEVICE_ID_5706:
1828 	case DEVICE_ID_5782:
1829 	case DEVICE_ID_5788:
1830 	case DEVICE_ID_5789:
1831 	case DEVICE_ID_5751:
1832 	case DEVICE_ID_5751M:
1833 	case DEVICE_ID_5721:
1834 	case DEVICE_ID_5714C:
1835 	case DEVICE_ID_5714S:
1836 	case DEVICE_ID_5715C:
1837 		config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG);
1838 		if (config1 & NVM_CFG1_FLASH_MODE)
1839 			if (config1 & NVM_CFG1_BUFFERED_MODE)
1840 				nvtype = BGE_NVTYPE_BUFFERED_FLASH;
1841 			else
1842 				nvtype = BGE_NVTYPE_UNBUFFERED_FLASH;
1843 		else
1844 			nvtype = BGE_NVTYPE_LEGACY_SEEPROM;
1845 		break;
1846 	}
1847 
1848 	return (nvtype);
1849 }
1850 
1851 #undef	BGE_DBG
1852 #define	BGE_DBG		BGE_DBG_CHIP	/* debug flag for this code	*/
1853 
1854 static void
1855 bge_init_recv_rule(bge_t *bgep)
1856 {
1857 	bge_recv_rule_t *rulep;
1858 	uint32_t i;
1859 
1860 	/*
1861 	 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING
1862 	 * 1. to direct UDP traffic, set:
1863 	 * 	rulep->control = RULE_PROTO_CONTROL;
1864 	 * 	rulep->mask_value = RULE_UDP_MASK_VALUE;
1865 	 * 2. to direct ICMP traffic, set:
1866 	 * 	rulep->control = RULE_PROTO_CONTROL;
1867 	 * 	rulep->mask_value = RULE_ICMP_MASK_VALUE;
1868 	 * 3. to direct traffic by source ip, set:
1869 	 * 	rulep->control = RULE_SIP_CONTROL;
1870 	 * 	rulep->mask_value = RULE_SIP_MASK_VALUE;
1871 	 */
1872 	rulep = bgep->recv_rules;
1873 	rulep->control = RULE_PROTO_CONTROL;
1874 	rulep->mask_value = RULE_TCP_MASK_VALUE;
1875 
1876 	/*
1877 	 * set receive rule registers
1878 	 */
1879 	rulep = bgep->recv_rules;
1880 	for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) {
1881 		bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value);
1882 		bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control);
1883 	}
1884 }
1885 
1886 /*
1887  * Using the values captured by bge_chip_cfg_init(), and additional probes
1888  * as required, characterise the chip fully: determine the label by which
1889  * to refer to this chip, the correct settings for various registers, and
1890  * of course whether the device and/or subsystem are supported!
1891  */
1892 int bge_chip_id_init(bge_t *bgep);
1893 #pragma	no_inline(bge_chip_id_init)
1894 
1895 int
1896 bge_chip_id_init(bge_t *bgep)
1897 {
1898 	char buf[MAXPATHLEN];		/* any risk of stack overflow?	*/
1899 	boolean_t sys_ok;
1900 	boolean_t dev_ok;
1901 	chip_id_t *cidp;
1902 	uint32_t subid;
1903 	char *devname;
1904 	char *sysname;
1905 	int *ids;
1906 	int err;
1907 	uint_t i;
1908 
1909 	ASSERT(bgep->bge_chip_state == BGE_CHIP_INITIAL);
1910 
1911 	sys_ok = dev_ok = B_FALSE;
1912 	cidp = &bgep->chipid;
1913 
1914 	/*
1915 	 * Check the PCI device ID to determine the generic chip type and
1916 	 * select parameters that depend on this.
1917 	 *
1918 	 * Note: because the SPARC platforms in general don't fit the
1919 	 * SEEPROM 'behind' the chip, the PCI revision ID register reads
1920 	 * as zero - which is why we use <asic_rev> rather than <revision>
1921 	 * below ...
1922 	 *
1923 	 * Note: in general we can't distinguish between the Copper/SerDes
1924 	 * versions by ID alone, as some Copper devices (e.g. some but not
1925 	 * all 5703Cs) have the same ID as the SerDes equivalents.  So we
1926 	 * treat them the same here, and the MII code works out the media
1927 	 * type later on ...
1928 	 */
1929 	cidp->mbuf_base = bge_mbuf_pool_base;
1930 	cidp->mbuf_length = bge_mbuf_pool_len;
1931 	cidp->recv_slots = BGE_RECV_SLOTS_USED;
1932 	cidp->bge_dma_rwctrl = bge_dma_rwctrl;
1933 	cidp->pci_type = BGE_PCI_X;
1934 	cidp->statistic_type = BGE_STAT_BLK;
1935 	cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma;
1936 	cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac;
1937 	cidp->mbuf_hi_water = bge_mbuf_hi_water;
1938 
1939 	if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX)
1940 		cidp->rx_rings = BGE_RECV_RINGS_DEFAULT;
1941 	if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX)
1942 		cidp->tx_rings = BGE_SEND_RINGS_DEFAULT;
1943 
1944 	cidp->msi_enabled = B_FALSE;
1945 
1946 	switch (cidp->device) {
1947 	case DEVICE_ID_5700:
1948 	case DEVICE_ID_5700x:
1949 		cidp->chip_label = 5700;
1950 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1951 		break;
1952 
1953 	case DEVICE_ID_5701:
1954 		cidp->chip_label = 5701;
1955 		dev_ok = B_TRUE;
1956 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1957 		break;
1958 
1959 	case DEVICE_ID_5702:
1960 	case DEVICE_ID_5702fe:
1961 		cidp->chip_label = 5702;
1962 		dev_ok = B_TRUE;
1963 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1964 		cidp->pci_type = BGE_PCI;
1965 		break;
1966 
1967 	case DEVICE_ID_5703C:
1968 	case DEVICE_ID_5703S:
1969 	case DEVICE_ID_5703:
1970 		/*
1971 		 * Revision A0 of the 5703/5793 had various errata
1972 		 * that we can't or don't work around, so it's not
1973 		 * supported, but all later versions are
1974 		 */
1975 		cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703;
1976 		if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0)
1977 			dev_ok = B_TRUE;
1978 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1979 		break;
1980 
1981 	case DEVICE_ID_5704C:
1982 	case DEVICE_ID_5704S:
1983 	case DEVICE_ID_5704:
1984 		/*
1985 		 * Revision A0 of the 5704/5794 had various errata
1986 		 * but we have workarounds, so it *is* supported.
1987 		 */
1988 		cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704;
1989 		cidp->mbuf_base = bge_mbuf_pool_base_5704;
1990 		cidp->mbuf_length = bge_mbuf_pool_len_5704;
1991 		dev_ok = B_TRUE;
1992 		if (cidp->asic_rev <  MHCR_CHIP_REV_5704_B0)
1993 			cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1994 		break;
1995 
1996 	case DEVICE_ID_5705C:
1997 	case DEVICE_ID_5705M:
1998 	case DEVICE_ID_5705MA3:
1999 	case DEVICE_ID_5705F:
2000 		cidp->chip_label = 5705;
2001 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2002 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2003 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2004 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2005 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2006 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2007 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2008 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2009 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2010 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2011 		cidp->pci_type = BGE_PCI;
2012 		cidp->statistic_type = BGE_STAT_REG;
2013 		dev_ok = B_TRUE;
2014 		break;
2015 
2016 	case DEVICE_ID_5706:
2017 		cidp->chip_label = 5706;
2018 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2019 		break;
2020 
2021 	case DEVICE_ID_5782:
2022 		/*
2023 		 * Apart from the label, we treat this as a 5705(?)
2024 		 */
2025 		cidp->chip_label = 5782;
2026 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2027 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2028 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2029 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2030 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2031 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2032 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2033 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2034 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2035 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2036 		cidp->statistic_type = BGE_STAT_REG;
2037 		dev_ok = B_TRUE;
2038 		break;
2039 
2040 	case DEVICE_ID_5788:
2041 		/*
2042 		 * Apart from the label, we treat this as a 5705(?)
2043 		 */
2044 		cidp->chip_label = 5788;
2045 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2046 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2047 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2048 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2049 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2050 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2051 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2052 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2053 		cidp->statistic_type = BGE_STAT_REG;
2054 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2055 		dev_ok = B_TRUE;
2056 		break;
2057 
2058 	case DEVICE_ID_5714C:
2059 		if (cidp->revision >= REVISION_ID_5714_A2)
2060 			cidp->msi_enabled = bge_enable_msi;
2061 		/* FALLTHRU */
2062 	case DEVICE_ID_5714S:
2063 		cidp->chip_label = 5714;
2064 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2065 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2066 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2067 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2068 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2069 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2070 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714;
2071 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
2072 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2073 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2074 		cidp->pci_type = BGE_PCI_E;
2075 		cidp->statistic_type = BGE_STAT_REG;
2076 		dev_ok = B_TRUE;
2077 		break;
2078 
2079 	case DEVICE_ID_5715C:
2080 		cidp->chip_label = 5715;
2081 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2082 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2083 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2084 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2085 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2086 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2087 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715;
2088 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
2089 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2090 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2091 		cidp->pci_type = BGE_PCI_E;
2092 		cidp->statistic_type = BGE_STAT_REG;
2093 		if (cidp->revision >= REVISION_ID_5715_A2)
2094 			cidp->msi_enabled = bge_enable_msi;
2095 		dev_ok = B_TRUE;
2096 		break;
2097 
2098 	case DEVICE_ID_5721:
2099 		cidp->chip_label = 5721;
2100 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2101 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2102 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2103 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2104 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2105 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2106 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2107 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2108 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2109 		cidp->pci_type = BGE_PCI_E;
2110 		cidp->statistic_type = BGE_STAT_REG;
2111 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2112 		dev_ok = B_TRUE;
2113 		break;
2114 
2115 	case DEVICE_ID_5751:
2116 	case DEVICE_ID_5751M:
2117 		cidp->chip_label = 5751;
2118 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2119 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2120 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2121 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2122 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2123 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2124 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2125 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2126 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2127 		cidp->pci_type = BGE_PCI_E;
2128 		cidp->statistic_type = BGE_STAT_REG;
2129 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2130 		dev_ok = B_TRUE;
2131 		break;
2132 
2133 	case DEVICE_ID_5789:
2134 		cidp->chip_label = 5789;
2135 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2136 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2137 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2138 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2139 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2140 		cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
2141 		cidp->pci_type = BGE_PCI_E;
2142 		cidp->statistic_type = BGE_STAT_REG;
2143 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2144 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2145 		cidp->msi_enabled = B_TRUE;
2146 		dev_ok = B_TRUE;
2147 		break;
2148 
2149 	}
2150 
2151 	/*
2152 	 * Setup the default jumbo parameter.
2153 	 */
2154 	cidp->ethmax_size = ETHERMAX;
2155 	cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT;
2156 	cidp->std_buf_size = BGE_STD_BUFF_SIZE;
2157 
2158 	/*
2159 	 * If jumbo is enabled and this kind of chipset supports jumbo feature,
2160 	 * setup below jumbo specific parameters.
2161 	 *
2162 	 * For BCM5714/5715, there is only one standard receive ring. So the
2163 	 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo
2164 	 * feature is enabled.
2165 	 */
2166 	if (bge_jumbo_enable &&
2167 	    !(cidp->flags & CHIP_FLAG_NO_JUMBO) &&
2168 	    (cidp->default_mtu > BGE_DEFAULT_MTU) &&
2169 	    (cidp->default_mtu <= BGE_MAXIMUM_MTU)) {
2170 	    if (DEVICE_5714_SERIES_CHIPSETS(bgep)) {
2171 			cidp->mbuf_lo_water_rdma =
2172 			    RDMA_MBUF_LOWAT_5714_JUMBO;
2173 			cidp->mbuf_lo_water_rmac =
2174 			    MAC_RX_MBUF_LOWAT_5714_JUMBO;
2175 			cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO;
2176 			cidp->jumbo_slots = 0;
2177 			cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE;
2178 	    } else {
2179 			cidp->mbuf_lo_water_rdma =
2180 			    RDMA_MBUF_LOWAT_JUMBO;
2181 			cidp->mbuf_lo_water_rmac =
2182 			    MAC_RX_MBUF_LOWAT_JUMBO;
2183 			cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO;
2184 			cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED;
2185 		}
2186 		cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE;
2187 		cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO;
2188 		cidp->ethmax_size = cidp->default_mtu +
2189 		    sizeof (struct ether_header);
2190 	}
2191 
2192 	/*
2193 	 * Identify the NV memory type: SEEPROM or Flash?
2194 	 */
2195 	cidp->nvtype = bge_nvmem_id(bgep);
2196 
2197 	/*
2198 	 * Now, we want to check whether this device is part of a
2199 	 * supported subsystem (e.g., on the motherboard of a Sun
2200 	 * branded platform).
2201 	 *
2202 	 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-)
2203 	 */
2204 	if (cidp->subven == VENDOR_ID_SUN)
2205 		sys_ok = B_TRUE;
2206 
2207 	/*
2208 	 * Rule 2: If it's on the list on known subsystems, then it's OK.
2209 	 * Note: 0x14e41647 should *not* appear in the list, but the code
2210 	 * doesn't enforce that.
2211 	 */
2212 	err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo,
2213 		DDI_PROP_DONTPASS, knownids_propname, &ids, &i);
2214 	if (err == DDI_PROP_SUCCESS) {
2215 		/*
2216 		 * Got the list; scan for a matching subsystem vendor/device
2217 		 */
2218 		subid = (cidp->subven << 16) | cidp->subdev;
2219 		while (i--)
2220 			if (ids[i] == subid)
2221 				sys_ok = B_TRUE;
2222 		ddi_prop_free(ids);
2223 	}
2224 
2225 	/*
2226 	 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK
2227 	 *
2228 	 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram
2229 	 * the Subsystem Vendor ID, so it defaults to Broadcom.  Therefore,
2230 	 * we have to check specially for the exact device paths to the
2231 	 * motherboard devices on those platforms ;-(
2232 	 *
2233 	 * Note: we can't just use the "supported-subsystems" mechanism
2234 	 * above, because the entry would have to be 0x14e41647 -- which
2235 	 * would then accept *any* plugin card that *didn't* contain a
2236 	 * (valid) SEEPROM ;-(
2237 	 */
2238 	sysname = ddi_node_name(ddi_root_node());
2239 	devname = ddi_pathname(bgep->devinfo, buf);
2240 	ASSERT(strlen(devname) > 0);
2241 	if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0)	/* Taco */
2242 		if (strcmp(devname, "/pci@1f,700000/network@2") == 0)
2243 			sys_ok = B_TRUE;
2244 	if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0)	/* ENWS */
2245 		if (strcmp(devname, "/pci@1c,600000/network@3") == 0)
2246 			sys_ok = B_TRUE;
2247 
2248 	/*
2249 	 * Now check what we've discovered: is this truly a supported
2250 	 * chip on (the motherboard of) a supported platform?
2251 	 *
2252 	 * Possible problems here:
2253 	 * 1)	it's a completely unheard-of chip (e.g. 5761)
2254 	 * 2)	it's a recognised but unsupported chip (e.g. 5701, 5703C-A0)
2255 	 * 3)	it's a chip we would support if it were on the motherboard
2256 	 *	of a Sun platform, but this one isn't ;-(
2257 	 */
2258 	if (cidp->chip_label == 0)
2259 		bge_problem(bgep,
2260 			"Device 'pci%04x,%04x' not recognized (%d?)",
2261 			cidp->vendor, cidp->device, cidp->device);
2262 	else if (!dev_ok)
2263 		bge_problem(bgep,
2264 			"Device 'pci%04x,%04x' (%d) revision %d not supported",
2265 			cidp->vendor, cidp->device, cidp->chip_label,
2266 			cidp->revision);
2267 #if	BGE_DEBUGGING
2268 	else if (!sys_ok)
2269 		bge_problem(bgep,
2270 			"%d-based subsystem 'pci%04x,%04x' not validated",
2271 			cidp->chip_label, cidp->subven, cidp->subdev);
2272 #endif
2273 	else
2274 		cidp->flags |= CHIP_FLAG_SUPPORTED;
2275 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
2276 		return (EIO);
2277 	return (0);
2278 }
2279 
2280 void
2281 bge_chip_msi_trig(bge_t *bgep)
2282 {
2283 	uint32_t	regval;
2284 
2285 	regval = bgep->param_msi_cnt<<4;
2286 	bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval);
2287 	BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval));
2288 }
2289 
2290 /*
2291  * Various registers that control the chip's internal engines (state
2292  * machines) have a <reset> and <enable> bits (fortunately, in the
2293  * same place in each such register :-).
2294  *
2295  * To reset the state machine, the <reset> bit must be written with 1;
2296  * it will then read back as 1 while the reset is in progress, but
2297  * self-clear to 0 when the reset completes.
2298  *
2299  * To enable a state machine, one must set the <enable> bit, which
2300  * will continue to read back as 0 until the state machine is running.
2301  *
2302  * To disable a state machine, the <enable> bit must be cleared, but
2303  * it will continue to read back as 1 until the state machine actually
2304  * stops.
2305  *
2306  * This routine implements polling for completion of a reset, enable
2307  * or disable operation, returning B_TRUE on success (bit reached the
2308  * required state) or B_FALSE on timeout (200*100us == 20ms).
2309  */
2310 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2311 					uint32_t mask, uint32_t val);
2312 #pragma	no_inline(bge_chip_poll_engine)
2313 
2314 static boolean_t
2315 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2316 	uint32_t mask, uint32_t val)
2317 {
2318 	uint32_t regval;
2319 	uint32_t n;
2320 
2321 	BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)",
2322 		(void *)bgep, regno, mask, val));
2323 
2324 	for (n = 200; n; --n) {
2325 		regval = bge_reg_get32(bgep, regno);
2326 		if ((regval & mask) == val)
2327 			return (B_TRUE);
2328 		drv_usecwait(100);
2329 	}
2330 
2331 	bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE);
2332 	return (B_FALSE);
2333 }
2334 
2335 /*
2336  * Various registers that control the chip's internal engines (state
2337  * machines) have a <reset> bit (fortunately, in the same place in
2338  * each such register :-).  To reset the state machine, this bit must
2339  * be written with 1; it will then read back as 1 while the reset is
2340  * in progress, but self-clear to 0 when the reset completes.
2341  *
2342  * This code sets the bit, then polls for it to read back as zero.
2343  * The return value is B_TRUE on success (reset bit cleared itself),
2344  * or B_FALSE if the state machine didn't recover :(
2345  *
2346  * NOTE: the Core reset is similar to other resets, except that we
2347  * can't poll for completion, since the Core reset disables memory
2348  * access!  So we just have to assume that it will all complete in
2349  * 100us.  See Broadcom document 570X-PG102-R, p102, steps 4-5.
2350  */
2351 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno);
2352 #pragma	no_inline(bge_chip_reset_engine)
2353 
2354 static boolean_t
2355 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno)
2356 {
2357 	uint32_t regval;
2358 	uint32_t val32;
2359 
2360 	regval = bge_reg_get32(bgep, regno);
2361 
2362 	BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)",
2363 		(void *)bgep, regno));
2364 	BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x",
2365 		regno, regval));
2366 
2367 	regval |= STATE_MACHINE_RESET_BIT;
2368 
2369 	switch (regno) {
2370 	case MISC_CONFIG_REG:
2371 		/*
2372 		 * BCM5714/5721/5751 pcie chip special case. In order to avoid
2373 		 * resetting PCIE block and bringing PCIE link down, bit 29
2374 		 * in the register needs to be set first, and then set it again
2375 		 * while the reset bit is written.
2376 		 * See:P500 of 57xx-PG102-RDS.pdf.
2377 		 */
2378 		if (DEVICE_5705_SERIES_CHIPSETS(bgep)||
2379 		    DEVICE_5721_SERIES_CHIPSETS(bgep)||
2380 		    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
2381 			regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE;
2382 			if (bgep->chipid.pci_type == BGE_PCI_E) {
2383 				if (bgep->chipid.asic_rev ==
2384 				    MHCR_CHIP_REV_5751_A0 ||
2385 				    bgep->chipid.asic_rev ==
2386 				    MHCR_CHIP_REV_5721_A0) {
2387 					val32 = bge_reg_get32(bgep,
2388 					    PHY_TEST_CTRL_REG);
2389 					if (val32 == (PHY_PCIE_SCRAM_MODE |
2390 					    PHY_PCIE_LTASS_MODE))
2391 						bge_reg_put32(bgep,
2392 						    PHY_TEST_CTRL_REG,
2393 						    PHY_PCIE_SCRAM_MODE);
2394 					val32 = pci_config_get32
2395 					    (bgep->cfg_handle,
2396 					    PCI_CONF_BGE_CLKCTL);
2397 					val32 |= CLKCTL_PCIE_A0_FIX;
2398 					pci_config_put32(bgep->cfg_handle,
2399 					    PCI_CONF_BGE_CLKCTL, val32);
2400 				}
2401 				bge_reg_set32(bgep, regno,
2402 					MISC_CONFIG_GRC_RESET_DISABLE);
2403 				regval |= MISC_CONFIG_GRC_RESET_DISABLE;
2404 			}
2405 		}
2406 
2407 		/*
2408 		 * Special case - causes Core reset
2409 		 *
2410 		 * On SPARC v9 we want to ensure that we don't start
2411 		 * timing until the I/O access has actually reached
2412 		 * the chip, otherwise we might make the next access
2413 		 * too early.  And we can't just force the write out
2414 		 * by following it with a read (even to config space)
2415 		 * because that would cause the fault we're trying
2416 		 * to avoid.  Hence the need for membar_sync() here.
2417 		 */
2418 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval);
2419 #ifdef	__sparcv9
2420 		membar_sync();
2421 #endif	/* __sparcv9 */
2422 		/*
2423 		 * On some platforms,system need about 300us for
2424 		 * link setup.
2425 		 */
2426 		drv_usecwait(300);
2427 
2428 		if (bgep->chipid.pci_type == BGE_PCI_E) {
2429 			/* PCI-E device need more reset time */
2430 			drv_usecwait(120000);
2431 
2432 			/* Set PCIE max payload size and clear error status. */
2433 			if ((bgep->chipid.chip_label == 5721) ||
2434 			    (bgep->chipid.chip_label == 5751) ||
2435 			    (bgep->chipid.chip_label == 5789)) {
2436 				pci_config_put16(bgep->cfg_handle,
2437 					PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX);
2438 				pci_config_put16(bgep->cfg_handle,
2439 					PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS);
2440 			}
2441 		}
2442 
2443 		BGE_PCICHK(bgep);
2444 		return (B_TRUE);
2445 
2446 	default:
2447 		bge_reg_put32(bgep, regno, regval);
2448 		return (bge_chip_poll_engine(bgep, regno,
2449 		    STATE_MACHINE_RESET_BIT, 0));
2450 	}
2451 }
2452 
2453 /*
2454  * Various registers that control the chip's internal engines (state
2455  * machines) have an <enable> bit (fortunately, in the same place in
2456  * each such register :-).  To stop the state machine, this bit must
2457  * be written with 0, then polled to see when the state machine has
2458  * actually stopped.
2459  *
2460  * The return value is B_TRUE on success (enable bit cleared), or
2461  * B_FALSE if the state machine didn't stop :(
2462  */
2463 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno,
2464 						uint32_t morebits);
2465 #pragma	no_inline(bge_chip_disable_engine)
2466 
2467 static boolean_t
2468 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2469 {
2470 	uint32_t regval;
2471 
2472 	BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)",
2473 		(void *)bgep, regno, morebits));
2474 
2475 	switch (regno) {
2476 	case FTQ_RESET_REG:
2477 		/*
2478 		 * Not quite like the others; it doesn't
2479 		 * have an <enable> bit, but instead we
2480 		 * have to set and then clear all the bits
2481 		 */
2482 		bge_reg_put32(bgep, regno, ~(uint32_t)0);
2483 		drv_usecwait(100);
2484 		bge_reg_put32(bgep, regno, 0);
2485 		return (B_TRUE);
2486 
2487 	default:
2488 		regval = bge_reg_get32(bgep, regno);
2489 		regval &= ~STATE_MACHINE_ENABLE_BIT;
2490 		regval &= ~morebits;
2491 		bge_reg_put32(bgep, regno, regval);
2492 		return (bge_chip_poll_engine(bgep, regno,
2493 		    STATE_MACHINE_ENABLE_BIT, 0));
2494 	}
2495 }
2496 
2497 /*
2498  * Various registers that control the chip's internal engines (state
2499  * machines) have an <enable> bit (fortunately, in the same place in
2500  * each such register :-).  To start the state machine, this bit must
2501  * be written with 1, then polled to see when the state machine has
2502  * actually started.
2503  *
2504  * The return value is B_TRUE on success (enable bit set), or
2505  * B_FALSE if the state machine didn't start :(
2506  */
2507 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno,
2508 					uint32_t morebits);
2509 #pragma	no_inline(bge_chip_enable_engine)
2510 
2511 static boolean_t
2512 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2513 {
2514 	uint32_t regval;
2515 
2516 	BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)",
2517 		(void *)bgep, regno, morebits));
2518 
2519 	switch (regno) {
2520 	case FTQ_RESET_REG:
2521 		/*
2522 		 * Not quite like the others; it doesn't
2523 		 * have an <enable> bit, but instead we
2524 		 * have to set and then clear all the bits
2525 		 */
2526 		bge_reg_put32(bgep, regno, ~(uint32_t)0);
2527 		drv_usecwait(100);
2528 		bge_reg_put32(bgep, regno, 0);
2529 		return (B_TRUE);
2530 
2531 	default:
2532 		regval = bge_reg_get32(bgep, regno);
2533 		regval |= STATE_MACHINE_ENABLE_BIT;
2534 		regval |= morebits;
2535 		bge_reg_put32(bgep, regno, regval);
2536 		return (bge_chip_poll_engine(bgep, regno,
2537 		    STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT));
2538 	}
2539 }
2540 
2541 /*
2542  * Reprogram the Ethernet, Transmit, and Receive MAC
2543  * modes to match the param_* variables
2544  */
2545 static void bge_sync_mac_modes(bge_t *bgep);
2546 #pragma	no_inline(bge_sync_mac_modes)
2547 
2548 static void
2549 bge_sync_mac_modes(bge_t *bgep)
2550 {
2551 	uint32_t macmode;
2552 	uint32_t regval;
2553 
2554 	ASSERT(mutex_owned(bgep->genlock));
2555 
2556 	/*
2557 	 * Reprogram the Ethernet MAC mode ...
2558 	 */
2559 	macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
2560 	if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
2561 		(bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC))
2562 		macmode &= ~ETHERNET_MODE_LINK_POLARITY;
2563 	else
2564 		macmode |= ETHERNET_MODE_LINK_POLARITY;
2565 	macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
2566 	if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
2567 		(bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC))
2568 		macmode |= ETHERNET_MODE_PORTMODE_TBI;
2569 	else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100)
2570 		macmode |= ETHERNET_MODE_PORTMODE_MII;
2571 	else
2572 		macmode |= ETHERNET_MODE_PORTMODE_GMII;
2573 	if (bgep->param_link_duplex == LINK_DUPLEX_HALF)
2574 		macmode |= ETHERNET_MODE_HALF_DUPLEX;
2575 	else
2576 		macmode &= ~ETHERNET_MODE_HALF_DUPLEX;
2577 	if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC)
2578 		macmode |= ETHERNET_MODE_MAC_LOOPBACK;
2579 	else
2580 		macmode &= ~ETHERNET_MODE_MAC_LOOPBACK;
2581 	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
2582 	BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x",
2583 		(void *)bgep, regval, macmode));
2584 
2585 	/*
2586 	 * ... the Transmit MAC mode ...
2587 	 */
2588 	macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG);
2589 	if (bgep->param_link_tx_pause)
2590 		macmode |= TRANSMIT_MODE_FLOW_CONTROL;
2591 	else
2592 		macmode &= ~TRANSMIT_MODE_FLOW_CONTROL;
2593 	bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode);
2594 	BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x",
2595 		(void *)bgep, regval, macmode));
2596 
2597 	/*
2598 	 * ... and the Receive MAC mode
2599 	 */
2600 	macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG);
2601 	if (bgep->param_link_rx_pause)
2602 		macmode |= RECEIVE_MODE_FLOW_CONTROL;
2603 	else
2604 		macmode &= ~RECEIVE_MODE_FLOW_CONTROL;
2605 	bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode);
2606 	BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x",
2607 		(void *)bgep, regval, macmode));
2608 }
2609 
2610 /*
2611  * bge_chip_sync() -- program the chip with the unicast MAC address,
2612  * the multicast hash table, the required level of promiscuity, and
2613  * the current loopback mode ...
2614  */
2615 #ifdef BGE_IPMI_ASF
2616 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive);
2617 #else
2618 int bge_chip_sync(bge_t *bgep);
2619 #endif
2620 #pragma	no_inline(bge_chip_sync)
2621 
2622 int
2623 #ifdef BGE_IPMI_ASF
2624 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive)
2625 #else
2626 bge_chip_sync(bge_t *bgep)
2627 #endif
2628 {
2629 	void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits);
2630 	boolean_t promisc;
2631 	uint64_t macaddr;
2632 	uint32_t fill;
2633 	int i;
2634 	int retval = DDI_SUCCESS;
2635 
2636 	BGE_TRACE(("bge_chip_sync($%p)",
2637 		(void *)bgep));
2638 
2639 	ASSERT(mutex_owned(bgep->genlock));
2640 
2641 	promisc = B_FALSE;
2642 	fill = ~(uint32_t)0;
2643 
2644 	if (bgep->promisc)
2645 		promisc = B_TRUE;
2646 	else
2647 		fill = (uint32_t)0;
2648 
2649 	/*
2650 	 * If the TX/RX MAC engines are already running, we should stop
2651 	 * them (and reset the RX engine) before changing the parameters.
2652 	 * If they're not running, this will have no effect ...
2653 	 *
2654 	 * NOTE: this is currently disabled by default because stopping
2655 	 * and restarting the Tx engine may cause an outgoing packet in
2656 	 * transit to be truncated.  Also, stopping and restarting the
2657 	 * Rx engine seems to not work correctly on the 5705.  Testing
2658 	 * has not (yet!) revealed any problems with NOT stopping and
2659 	 * restarting these engines (and Broadcom say their drivers don't
2660 	 * do this), but if it is found to cause problems, this variable
2661 	 * can be patched to re-enable the old behaviour ...
2662 	 */
2663 	if (bge_stop_start_on_sync) {
2664 #ifdef BGE_IPMI_ASF
2665 		if (!bgep->asf_enabled) {
2666 			if (!bge_chip_disable_engine(bgep,
2667 			    RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
2668 				retval = DDI_FAILURE;
2669 		} else {
2670 			if (!bge_chip_disable_engine(bgep,
2671 			    RECEIVE_MAC_MODE_REG, 0))
2672 				retval = DDI_FAILURE;
2673 		}
2674 #else
2675 		if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG,
2676 		    RECEIVE_MODE_KEEP_VLAN_TAG))
2677 			retval = DDI_FAILURE;
2678 #endif
2679 		if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
2680 			retval = DDI_FAILURE;
2681 		if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG))
2682 			retval = DDI_FAILURE;
2683 	}
2684 
2685 	/*
2686 	 * Reprogram the hashed multicast address table ...
2687 	 */
2688 	for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
2689 		bge_reg_put32(bgep, MAC_HASH_REG(i),
2690 			bgep->mcast_hash[i] | fill);
2691 
2692 #ifdef BGE_IPMI_ASF
2693 	if (!bgep->asf_enabled || !asf_keeplive) {
2694 #endif
2695 		/*
2696 		 * Transform the MAC address from host to chip format, then
2697 		 * reprogram the transmit random backoff seed and the unicast
2698 		 * MAC address(es) ...
2699 		 */
2700 		for (i = 0, fill = 0, macaddr = 0ull; i < ETHERADDRL; ++i) {
2701 			macaddr <<= 8;
2702 			macaddr |= bgep->curr_addr.addr[i];
2703 			fill += bgep->curr_addr.addr[i];
2704 		}
2705 		bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill);
2706 		for (i = 0; i < MAC_ADDRESS_REGS_MAX; ++i)
2707 			bge_reg_put64(bgep, MAC_ADDRESS_REG(i), macaddr);
2708 
2709 		BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx",
2710 			(void *)bgep, macaddr));
2711 #ifdef BGE_IPMI_ASF
2712 	}
2713 #endif
2714 
2715 	/*
2716 	 * Set or clear the PROMISCUOUS mode bit
2717 	 */
2718 	opfn = promisc ? bge_reg_set32 : bge_reg_clr32;
2719 	(*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS);
2720 
2721 	/*
2722 	 * Sync the rest of the MAC modes too ...
2723 	 */
2724 	bge_sync_mac_modes(bgep);
2725 
2726 	/*
2727 	 * Restart RX/TX MAC engines if required ...
2728 	 */
2729 	if (bgep->bge_chip_state == BGE_CHIP_RUNNING) {
2730 		if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
2731 			retval = DDI_FAILURE;
2732 #ifdef BGE_IPMI_ASF
2733 		if (!bgep->asf_enabled) {
2734 			if (!bge_chip_enable_engine(bgep,
2735 			    RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
2736 				retval = DDI_FAILURE;
2737 		} else {
2738 			if (!bge_chip_enable_engine(bgep,
2739 			    RECEIVE_MAC_MODE_REG, 0))
2740 				retval = DDI_FAILURE;
2741 		}
2742 #else
2743 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
2744 		    RECEIVE_MODE_KEEP_VLAN_TAG))
2745 			retval = DDI_FAILURE;
2746 #endif
2747 	}
2748 	return (retval);
2749 }
2750 
2751 /*
2752  * This array defines the sequence of state machine control registers
2753  * in which the <enable> bit must be cleared to bring the chip to a
2754  * clean stop.  Taken from Broadcom document 570X-PG102-R, p116.
2755  */
2756 static bge_regno_t shutdown_engine_regs[] = {
2757 	RECEIVE_MAC_MODE_REG,
2758 	RCV_BD_INITIATOR_MODE_REG,
2759 	RCV_LIST_PLACEMENT_MODE_REG,
2760 	RCV_LIST_SELECTOR_MODE_REG,		/* BCM5704 series only	*/
2761 	RCV_DATA_BD_INITIATOR_MODE_REG,
2762 	RCV_DATA_COMPLETION_MODE_REG,
2763 	RCV_BD_COMPLETION_MODE_REG,
2764 
2765 	SEND_BD_SELECTOR_MODE_REG,
2766 	SEND_BD_INITIATOR_MODE_REG,
2767 	SEND_DATA_INITIATOR_MODE_REG,
2768 	READ_DMA_MODE_REG,
2769 	SEND_DATA_COMPLETION_MODE_REG,
2770 	DMA_COMPLETION_MODE_REG,		/* BCM5704 series only	*/
2771 	SEND_BD_COMPLETION_MODE_REG,
2772 	TRANSMIT_MAC_MODE_REG,
2773 
2774 	HOST_COALESCE_MODE_REG,
2775 	WRITE_DMA_MODE_REG,
2776 	MBUF_CLUSTER_FREE_MODE_REG,		/* BCM5704 series only	*/
2777 	FTQ_RESET_REG,		/* special - see code	*/
2778 	BUFFER_MANAGER_MODE_REG,		/* BCM5704 series only	*/
2779 	MEMORY_ARBITER_MODE_REG,		/* BCM5704 series only	*/
2780 	BGE_REGNO_NONE		/* terminator		*/
2781 };
2782 
2783 /*
2784  * bge_chip_stop() -- stop all chip processing
2785  *
2786  * If the <fault> parameter is B_TRUE, we're stopping the chip because
2787  * we've detected a problem internally; otherwise, this is a normal
2788  * (clean) stop (at user request i.e. the last STREAM has been closed).
2789  */
2790 void bge_chip_stop(bge_t *bgep, boolean_t fault);
2791 #pragma	no_inline(bge_chip_stop)
2792 
2793 void
2794 bge_chip_stop(bge_t *bgep, boolean_t fault)
2795 {
2796 	bge_regno_t regno;
2797 	bge_regno_t *rbp;
2798 	boolean_t ok;
2799 
2800 	BGE_TRACE(("bge_chip_stop($%p)",
2801 		(void *)bgep));
2802 
2803 	ASSERT(mutex_owned(bgep->genlock));
2804 
2805 	rbp = shutdown_engine_regs;
2806 	/*
2807 	 * When driver try to shutdown the BCM5705/5788/5721/5751/
2808 	 * 5752/5714 and 5715 chipsets,the buffer manager and the mem
2809 	 * -ory arbiter should not be disabled.
2810 	 */
2811 	for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) {
2812 			if (DEVICE_5704_SERIES_CHIPSETS(bgep))
2813 			    ok &= bge_chip_disable_engine(bgep, regno, 0);
2814 			else if ((regno != RCV_LIST_SELECTOR_MODE_REG) &&
2815 				    (regno != DMA_COMPLETION_MODE_REG) &&
2816 				    (regno != MBUF_CLUSTER_FREE_MODE_REG)&&
2817 				    (regno != BUFFER_MANAGER_MODE_REG) &&
2818 				    (regno != MEMORY_ARBITER_MODE_REG))
2819 					ok &= bge_chip_disable_engine(bgep,
2820 					    regno, 0);
2821 	}
2822 
2823 	if (!ok && !fault)
2824 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
2825 
2826 	/*
2827 	 * Finally, disable (all) MAC events & clear the MAC status
2828 	 */
2829 	bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0);
2830 	bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0);
2831 
2832 	/*
2833 	 * if we're stopping the chip because of a detected fault then do
2834 	 * appropriate actions
2835 	 */
2836 	if (fault) {
2837 		if (bgep->bge_chip_state != BGE_CHIP_FAULT) {
2838 			bgep->bge_chip_state = BGE_CHIP_FAULT;
2839 			ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST);
2840 			if (bgep->bge_dma_error) {
2841 				/*
2842 				 * need to free buffers in case the fault was
2843 				 * due to a memory error in a buffer - got to
2844 				 * do a fair bit of tidying first
2845 				 */
2846 				if (bgep->progress & PROGRESS_KSTATS) {
2847 					bge_fini_kstats(bgep);
2848 					bgep->progress &= ~PROGRESS_KSTATS;
2849 				}
2850 				if (bgep->progress & PROGRESS_INTR) {
2851 					bge_intr_disable(bgep);
2852 					rw_enter(bgep->errlock, RW_WRITER);
2853 					bge_fini_rings(bgep);
2854 					rw_exit(bgep->errlock);
2855 					bgep->progress &= ~PROGRESS_INTR;
2856 				}
2857 				if (bgep->progress & PROGRESS_BUFS) {
2858 					bge_free_bufs(bgep);
2859 					bgep->progress &= ~PROGRESS_BUFS;
2860 				}
2861 				bgep->bge_dma_error = B_FALSE;
2862 			}
2863 		}
2864 	} else
2865 		bgep->bge_chip_state = BGE_CHIP_STOPPED;
2866 }
2867 
2868 /*
2869  * Poll for completion of chip's ROM firmware; also, at least on the
2870  * first time through, find and return the hardware MAC address, if any.
2871  */
2872 static uint64_t bge_poll_firmware(bge_t *bgep);
2873 #pragma	no_inline(bge_poll_firmware)
2874 
2875 static uint64_t
2876 bge_poll_firmware(bge_t *bgep)
2877 {
2878 	uint64_t magic;
2879 	uint64_t mac;
2880 	uint32_t gen;
2881 	uint32_t i;
2882 
2883 	/*
2884 	 * Step 19: poll for firmware completion (GENCOMM port set
2885 	 * to the ones complement of T3_MAGIC_NUMBER).
2886 	 *
2887 	 * While we're at it, we also read the MAC address register;
2888 	 * at some stage the firmware will load this with the
2889 	 * factory-set value.
2890 	 *
2891 	 * When both the magic number and the MAC address are set,
2892 	 * we're done; but we impose a time limit of one second
2893 	 * (1000*1000us) in case the firmware fails in some fashion
2894 	 * or the SEEPROM that provides that MAC address isn't fitted.
2895 	 *
2896 	 * After the first time through (chip state != INITIAL), we
2897 	 * don't need the MAC address to be set (we've already got it
2898 	 * or not, from the first time), so we don't wait for it, but
2899 	 * we still have to wait for the T3_MAGIC_NUMBER.
2900 	 *
2901 	 * Note: the magic number is only a 32-bit quantity, but the NIC
2902 	 * memory is 64-bit (and big-endian) internally.  Addressing the
2903 	 * GENCOMM word as "the upper half of a 64-bit quantity" makes
2904 	 * it work correctly on both big- and little-endian hosts.
2905 	 */
2906 	for (i = 0; i < 1000; ++i) {
2907 		drv_usecwait(1000);
2908 		gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32;
2909 		mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
2910 #ifdef BGE_IPMI_ASF
2911 		if (!bgep->asf_enabled) {
2912 #endif
2913 			if (gen != ~T3_MAGIC_NUMBER)
2914 				continue;
2915 #ifdef BGE_IPMI_ASF
2916 		}
2917 #endif
2918 		if (mac != 0ULL)
2919 			break;
2920 		if (bgep->bge_chip_state != BGE_CHIP_INITIAL)
2921 			break;
2922 	}
2923 
2924 	magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM);
2925 	BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops",
2926 		(void *)bgep, gen, i));
2927 	BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx",
2928 		mac, magic));
2929 
2930 	return (mac);
2931 }
2932 
2933 #ifdef BGE_IPMI_ASF
2934 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode);
2935 #else
2936 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma);
2937 #endif
2938 #pragma	no_inline(bge_chip_reset)
2939 
2940 int
2941 #ifdef BGE_IPMI_ASF
2942 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode)
2943 #else
2944 bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
2945 #endif
2946 {
2947 	chip_id_t chipid;
2948 	uint64_t mac;
2949 	uint64_t magic;
2950 	uint32_t modeflags;
2951 	uint32_t mhcr;
2952 	uint32_t sx0;
2953 	uint32_t i;
2954 #ifdef BGE_IPMI_ASF
2955 	uint32_t mailbox;
2956 #endif
2957 	int retval = DDI_SUCCESS;
2958 
2959 	BGE_TRACE(("bge_chip_reset($%p, %d)",
2960 		(void *)bgep, enable_dma));
2961 
2962 	ASSERT(mutex_owned(bgep->genlock));
2963 
2964 	BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d",
2965 		(void *)bgep, enable_dma, bgep->bge_chip_state));
2966 
2967 	/*
2968 	 * Do we need to stop the chip cleanly before resetting?
2969 	 */
2970 	switch (bgep->bge_chip_state) {
2971 	default:
2972 		_NOTE(NOTREACHED)
2973 		return (DDI_FAILURE);
2974 
2975 	case BGE_CHIP_INITIAL:
2976 	case BGE_CHIP_STOPPED:
2977 	case BGE_CHIP_RESET:
2978 		break;
2979 
2980 	case BGE_CHIP_RUNNING:
2981 	case BGE_CHIP_ERROR:
2982 	case BGE_CHIP_FAULT:
2983 		bge_chip_stop(bgep, B_FALSE);
2984 		break;
2985 	}
2986 
2987 #ifdef BGE_IPMI_ASF
2988 	if (bgep->asf_enabled) {
2989 		if (asf_mode == ASF_MODE_INIT) {
2990 			bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
2991 		} else if (asf_mode == ASF_MODE_SHUTDOWN) {
2992 			bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET);
2993 		}
2994 	}
2995 #endif
2996 	/*
2997 	 * Adapted from Broadcom document 570X-PG102-R, pp 102-116.
2998 	 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159.
2999 	 *
3000 	 * Before reset Core clock,it is
3001 	 * also required to initialize the Memory Arbiter as specified in step9
3002 	 * and Misc Host Control Register as specified in step-13
3003 	 * Step 4-5: reset Core clock & wait for completion
3004 	 * Steps 6-8: are done by bge_chip_cfg_init()
3005 	 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset
3006 	 */
3007 	if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3008 		retval = DDI_FAILURE;
3009 
3010 	mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3011 	    MHCR_ENABLE_TAGGED_STATUS_MODE |
3012 	    MHCR_MASK_INTERRUPT_MODE |
3013 	    MHCR_MASK_PCI_INT_OUTPUT |
3014 	    MHCR_CLEAR_INTERRUPT_INTA;
3015 #ifdef  _BIG_ENDIAN
3016 	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3017 #endif  /* _BIG_ENDIAN */
3018 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3019 #ifdef BGE_IPMI_ASF
3020 	if (bgep->asf_enabled)
3021 		bgep->asf_wordswapped = B_FALSE;
3022 #endif
3023 #ifdef BGE_IPMI_ASF
3024 	if (!bgep->asf_enabled) {
3025 #endif
3026 		magic = (uint64_t)T3_MAGIC_NUMBER << 32;
3027 		bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic);
3028 #ifdef BGE_IPMI_ASF
3029 	}
3030 #endif
3031 
3032 	if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG))
3033 		retval = DDI_FAILURE;
3034 	bge_chip_cfg_init(bgep, &chipid, enable_dma);
3035 
3036 	/*
3037 	 * Step 8a: This may belong elsewhere, but BCM5721 needs
3038 	 * a bit set to avoid a fifo overflow/underflow bug.
3039 	 */
3040 	if ((bgep->chipid.chip_label == 5721) ||
3041 		(bgep->chipid.chip_label == 5751) ||
3042 		(bgep->chipid.chip_label == 5789))
3043 		bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT);
3044 
3045 
3046 	/*
3047 	 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should
3048 	 * not be changed.
3049 	 */
3050 	if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3051 		retval = DDI_FAILURE;
3052 
3053 	/*
3054 	 * Steps 10-11: configure PIO endianness options and
3055 	 * enable indirect register access -- already done
3056 	 * Steps 12-13: enable writing to the PCI state & clock
3057 	 * control registers -- not required; we aren't going to
3058 	 * use those features.
3059 	 * Steps 14-15: Configure DMA endianness options.  See
3060 	 * the comments on the setting of the MHCR above.
3061 	 */
3062 #ifdef	_BIG_ENDIAN
3063 	modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME |
3064 		    MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME;
3065 #else
3066 	modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME;
3067 #endif	/* _BIG_ENDIAN */
3068 #ifdef BGE_IPMI_ASF
3069 	if (bgep->asf_enabled)
3070 		modeflags |= MODE_HOST_STACK_UP;
3071 #endif
3072 	bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags);
3073 
3074 #ifdef BGE_IPMI_ASF
3075 	if (bgep->asf_enabled) {
3076 		if (asf_mode != ASF_MODE_NONE) {
3077 			/* Wait for NVRAM init */
3078 			i = 0;
3079 			drv_usecwait(5000);
3080 			mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX);
3081 			while ((mailbox != (uint32_t)
3082 				~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) &&
3083 				(i < 10000)) {
3084 				drv_usecwait(100);
3085 				mailbox = bge_nic_get32(bgep,
3086 					BGE_FIRMWARE_MAILBOX);
3087 				i++;
3088 			}
3089 			if (!bgep->asf_newhandshake) {
3090 				if ((asf_mode == ASF_MODE_INIT) ||
3091 					(asf_mode == ASF_MODE_POST_INIT)) {
3092 
3093 					bge_asf_post_reset_old_mode(bgep,
3094 						BGE_INIT_RESET);
3095 				} else {
3096 					bge_asf_post_reset_old_mode(bgep,
3097 						BGE_SHUTDOWN_RESET);
3098 				}
3099 			}
3100 		}
3101 	}
3102 #endif
3103 	/*
3104 	 * Steps 16-17: poll for firmware completion
3105 	 */
3106 	mac = bge_poll_firmware(bgep);
3107 
3108 	/*
3109 	 * Step 18: enable external memory -- doesn't apply.
3110 	 *
3111 	 * However we take the opportunity to set the MLCR anyway, as
3112 	 * this register also controls the SEEPROM auto-access method
3113 	 * which we may want to use later ...
3114 	 *
3115 	 * The proper value here depends on the way the chip is wired
3116 	 * into the circuit board, as this register *also* controls which
3117 	 * of the "Miscellaneous I/O" pins are driven as outputs and the
3118 	 * values driven onto those pins!
3119 	 *
3120 	 * See also step 74 in the PRM ...
3121 	 */
3122 	bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG,
3123 	    bgep->chipid.bge_mlcr_default);
3124 	bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
3125 
3126 	/*
3127 	 * Step 20: clear the Ethernet MAC mode register
3128 	 */
3129 	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0);
3130 
3131 	/*
3132 	 * Step 21: restore cache-line-size, latency timer, and
3133 	 * subsystem ID registers to their original values (not
3134 	 * those read into the local structure <chipid>, 'cos
3135 	 * that was after they were cleared by the RESET).
3136 	 *
3137 	 * Note: the Subsystem Vendor/Device ID registers are not
3138 	 * directly writable in config space, so we use the shadow
3139 	 * copy in "Page Zero" of register space to restore them
3140 	 * both in one go ...
3141 	 */
3142 	pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ,
3143 		bgep->chipid.clsize);
3144 	pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER,
3145 		bgep->chipid.latency);
3146 	bge_reg_put32(bgep, PCI_CONF_SUBVENID,
3147 		(bgep->chipid.subdev << 16) | bgep->chipid.subven);
3148 
3149 	/*
3150 	 * The SEND INDEX registers should be reset to zero by the
3151 	 * global chip reset; if they're not, there'll be trouble
3152 	 * later on.
3153 	 */
3154 	sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0));
3155 	if (sx0 != 0) {
3156 		BGE_REPORT((bgep, "SEND INDEX - device didn't RESET"));
3157 		bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE);
3158 		return (DDI_FAILURE);
3159 	}
3160 
3161 	/* Enable MSI code */
3162 	if (bgep->intr_type == DDI_INTR_TYPE_MSI)
3163 		bge_reg_set32(bgep, MSI_MODE_REG,
3164 		    MSI_PRI_HIGHEST|MSI_MSI_ENABLE);
3165 
3166 	/*
3167 	 * On the first time through, save the factory-set MAC address
3168 	 * (if any).  If bge_poll_firmware() above didn't return one
3169 	 * (from a chip register) consider looking in the attached NV
3170 	 * memory device, if any.  Once we have it, we save it in both
3171 	 * register-image (64-bit) and byte-array forms.  All-zero and
3172 	 * all-one addresses are not valid, and we refuse to stash those.
3173 	 */
3174 	if (bgep->bge_chip_state == BGE_CHIP_INITIAL) {
3175 		if (mac == 0ULL)
3176 			mac = bge_get_nvmac(bgep);
3177 		if (mac != 0ULL && mac != ~0ULL) {
3178 			bgep->chipid.hw_mac_addr = mac;
3179 			for (i = ETHERADDRL; i-- != 0; ) {
3180 				bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac;
3181 				mac >>= 8;
3182 			}
3183 			bgep->chipid.vendor_addr.set = 1;
3184 		}
3185 	}
3186 
3187 #ifdef BGE_IPMI_ASF
3188 	if (bgep->asf_enabled && bgep->asf_newhandshake) {
3189 		if (asf_mode != ASF_MODE_NONE) {
3190 			if ((asf_mode == ASF_MODE_INIT) ||
3191 				(asf_mode == ASF_MODE_POST_INIT)) {
3192 
3193 				bge_asf_post_reset_new_mode(bgep,
3194 					BGE_INIT_RESET);
3195 			} else {
3196 				bge_asf_post_reset_new_mode(bgep,
3197 					BGE_SHUTDOWN_RESET);
3198 			}
3199 		}
3200 	}
3201 #endif
3202 
3203 	/*
3204 	 * Record the new state
3205 	 */
3206 	bgep->chip_resets += 1;
3207 	bgep->bge_chip_state = BGE_CHIP_RESET;
3208 	return (retval);
3209 }
3210 
3211 /*
3212  * bge_chip_start() -- start the chip transmitting and/or receiving,
3213  * including enabling interrupts
3214  */
3215 int bge_chip_start(bge_t *bgep, boolean_t reset_phys);
3216 #pragma	no_inline(bge_chip_start)
3217 
3218 int
3219 bge_chip_start(bge_t *bgep, boolean_t reset_phys)
3220 {
3221 	uint32_t coalmode;
3222 	uint32_t ledctl;
3223 	uint32_t mtu;
3224 	uint32_t maxring;
3225 	uint64_t ring;
3226 	int retval = DDI_SUCCESS;
3227 
3228 	BGE_TRACE(("bge_chip_start($%p)",
3229 		(void *)bgep));
3230 
3231 	ASSERT(mutex_owned(bgep->genlock));
3232 	ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET);
3233 
3234 	/*
3235 	 * Taken from Broadcom document 570X-PG102-R, pp 102-116.
3236 	 * The document specifies 95 separate steps to fully
3237 	 * initialise the chip!!!!
3238 	 *
3239 	 * The reset code above has already got us as far as step
3240 	 * 21, so we continue with ...
3241 	 *
3242 	 * Step 22: clear the MAC statistics block
3243 	 * (0x0300-0x0aff in NIC-local memory)
3244 	 */
3245 	if (bgep->chipid.statistic_type == BGE_STAT_BLK)
3246 		bge_nic_zero(bgep, NIC_MEM_STATISTICS,
3247 		    NIC_MEM_STATISTICS_SIZE);
3248 
3249 	/*
3250 	 * Step 23: clear the status block (in host memory)
3251 	 */
3252 	DMA_ZERO(bgep->status_block);
3253 
3254 	/*
3255 	 * Step 24: set DMA read/write control register
3256 	 */
3257 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR,
3258 		bgep->chipid.bge_dma_rwctrl);
3259 
3260 	/*
3261 	 * Step 25: Configure DMA endianness -- already done (16/17)
3262 	 * Step 26: Configure Host-Based Send Rings
3263 	 * Step 27: Indicate Host Stack Up
3264 	 */
3265 	bge_reg_set32(bgep, MODE_CONTROL_REG,
3266 		MODE_HOST_SEND_BDS |
3267 		MODE_HOST_STACK_UP);
3268 
3269 	/*
3270 	 * Step 28: Configure checksum options:
3271 	 *	Solaris supports the hardware default checksum options.
3272 	 *
3273 	 *	Workaround for Incorrect pseudo-header checksum calculation.
3274 	 */
3275 	if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM)
3276 		bge_reg_set32(bgep, MODE_CONTROL_REG,
3277 		    MODE_SEND_NO_PSEUDO_HDR_CSUM);
3278 
3279 	/*
3280 	 * Step 29: configure Timer Prescaler.  The value is always the
3281 	 * same: the Core Clock frequency in MHz (66), minus 1, shifted
3282 	 * into bits 7-1.  Don't set bit 0, 'cos that's the RESET bit
3283 	 * for the whole chip!
3284 	 */
3285 	bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT);
3286 
3287 	/*
3288 	 * Steps 30-31: Configure MAC local memory pool & DMA pool registers
3289 	 *
3290 	 * If the mbuf_length is specified as 0, we just leave these at
3291 	 * their hardware defaults, rather than explicitly setting them.
3292 	 * As the Broadcom HRM,driver better not change the parameters
3293 	 * when the chipsets is 5705/5788/5721/5751/5714 and 5715.
3294 	 */
3295 	if ((bgep->chipid.mbuf_length != 0) &&
3296 		(DEVICE_5704_SERIES_CHIPSETS(bgep))) {
3297 			bge_reg_put32(bgep, MBUF_POOL_BASE_REG,
3298 				bgep->chipid.mbuf_base);
3299 			bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG,
3300 				bgep->chipid.mbuf_length);
3301 			bge_reg_put32(bgep, DMAD_POOL_BASE_REG,
3302 				DMAD_POOL_BASE_DEFAULT);
3303 			bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG,
3304 				DMAD_POOL_LENGTH_DEFAULT);
3305 	}
3306 
3307 	/*
3308 	 * Step 32: configure MAC memory pool watermarks
3309 	 */
3310 	bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG,
3311 		bgep->chipid.mbuf_lo_water_rdma);
3312 	bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG,
3313 		bgep->chipid.mbuf_lo_water_rmac);
3314 	bge_reg_put32(bgep, MBUF_HIWAT_REG,
3315 		bgep->chipid.mbuf_hi_water);
3316 
3317 	/*
3318 	 * Step 33: configure DMA resource watermarks
3319 	 */
3320 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3321 		bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG,
3322 		    bge_dmad_lo_water);
3323 		bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG,
3324 		    bge_dmad_hi_water);
3325 	}
3326 	bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames);
3327 
3328 	/*
3329 	 * Steps 34-36: enable buffer manager & internal h/w queues
3330 	 */
3331 	if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG,
3332 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3333 		retval = DDI_FAILURE;
3334 	if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0))
3335 		retval = DDI_FAILURE;
3336 
3337 	/*
3338 	 * Steps 37-39: initialise Receive Buffer (Producer) RCBs
3339 	 */
3340 	bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG,
3341 		&bgep->buff[BGE_STD_BUFF_RING].hw_rcb);
3342 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3343 		bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG,
3344 			&bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb);
3345 		bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG,
3346 			&bgep->buff[BGE_MINI_BUFF_RING].hw_rcb);
3347 	}
3348 
3349 	/*
3350 	 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds
3351 	 */
3352 	bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std);
3353 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3354 		bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG,
3355 		    bge_replenish_jumbo);
3356 		bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG,
3357 		    bge_replenish_mini);
3358 	}
3359 
3360 	/*
3361 	 * Steps 41-43: clear Send Ring Producer Indices and initialise
3362 	 * Send Producer Rings (0x0100-0x01ff in NIC-local memory)
3363 	 */
3364 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3365 		maxring = BGE_SEND_RINGS_MAX;
3366 	else
3367 		maxring = BGE_SEND_RINGS_MAX_5705;
3368 	for (ring = 0; ring < maxring; ++ring) {
3369 		bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0);
3370 		bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0);
3371 		bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring),
3372 			&bgep->send[ring].hw_rcb);
3373 	}
3374 
3375 	/*
3376 	 * Steps 44-45: initialise Receive Return Rings
3377 	 * (0x0200-0x02ff in NIC-local memory)
3378 	 */
3379 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3380 		maxring = BGE_RECV_RINGS_MAX;
3381 	else
3382 		maxring = BGE_RECV_RINGS_MAX_5705;
3383 	for (ring = 0; ring < maxring; ++ring)
3384 		bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring),
3385 			&bgep->recv[ring].hw_rcb);
3386 
3387 	/*
3388 	 * Step 46: initialise Receive Buffer (Producer) Ring indexes
3389 	 */
3390 	bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0);
3391 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3392 		bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0);
3393 		bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0);
3394 	}
3395 	/*
3396 	 * Step 47: configure the MAC unicast address
3397 	 * Step 48: configure the random backoff seed
3398 	 * Step 96: set up multicast filters
3399 	 */
3400 #ifdef BGE_IPMI_ASF
3401 	if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE)
3402 #else
3403 	if (bge_chip_sync(bgep) == DDI_FAILURE)
3404 #endif
3405 		retval = DDI_FAILURE;
3406 
3407 	/*
3408 	 * Step 49: configure the MTU
3409 	 */
3410 	mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ;
3411 	bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu);
3412 
3413 	/*
3414 	 * Step 50: configure the IPG et al
3415 	 */
3416 	bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT);
3417 
3418 	/*
3419 	 * Step 51: configure the default Rx Return Ring
3420 	 */
3421 	bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT);
3422 
3423 	/*
3424 	 * Steps 52-54: configure Receive List Placement,
3425 	 * and enable Receive List Placement Statistics
3426 	 */
3427 	bge_reg_put32(bgep, RCV_LP_CONFIG_REG,
3428 		RCV_LP_CONFIG(bgep->chipid.rx_rings));
3429 	bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0);
3430 	bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE);
3431 
3432 	if (bgep->chipid.rx_rings > 1)
3433 		bge_init_recv_rule(bgep);
3434 
3435 	/*
3436 	 * Steps 55-56: enable Send Data Initiator Statistics
3437 	 */
3438 	bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0);
3439 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3440 		bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3441 		    SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER);
3442 	} else {
3443 		bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3444 		    SEND_INIT_STATS_ENABLE);
3445 	}
3446 	/*
3447 	 * Steps 57-58: stop (?) the Host Coalescing Engine
3448 	 */
3449 	if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0))
3450 		retval = DDI_FAILURE;
3451 
3452 	/*
3453 	 * Steps 59-62: initialise Host Coalescing parameters
3454 	 */
3455 	bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm);
3456 	bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm);
3457 	bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm);
3458 	bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm);
3459 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3460 		bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG,
3461 		    bge_tx_count_intr);
3462 		bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG,
3463 		    bge_tx_ticks_intr);
3464 		bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG,
3465 		    bge_rx_count_intr);
3466 		bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG,
3467 		    bge_rx_ticks_intr);
3468 	}
3469 
3470 	/*
3471 	 * Steps 63-64: initialise status block & statistics
3472 	 * host memory addresses
3473 	 * The statistic block does not exist in some chipsets
3474 	 * Step 65: initialise Statistics Coalescing Tick Counter
3475 	 */
3476 	bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG,
3477 		bgep->status_block.cookie.dmac_laddress);
3478 
3479 	/*
3480 	 * Steps 66-67: initialise status block & statistics
3481 	 * NIC-local memory addresses
3482 	 */
3483 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3484 		bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG,
3485 		    bgep->statistics.cookie.dmac_laddress);
3486 		bge_reg_put32(bgep, STATISTICS_TICKS_REG,
3487 		    STATISTICS_TICKS_DEFAULT);
3488 		bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG,
3489 		    NIC_MEM_STATUS_BLOCK);
3490 		bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG,
3491 		    NIC_MEM_STATISTICS);
3492 	}
3493 
3494 	/*
3495 	 * Steps 68-71: start the Host Coalescing Engine, the Receive BD
3496 	 * Completion Engine, the Receive List Placement Engine, and the
3497 	 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714
3498 	 * and BCM5715.
3499 	 */
3500 	if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS &&
3501 	    bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS)
3502 		coalmode = COALESCE_64_BYTE_STATUS;
3503 	else
3504 		coalmode = 0;
3505 	if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode))
3506 		retval = DDI_FAILURE;
3507 	if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG,
3508 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3509 		retval = DDI_FAILURE;
3510 	if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0))
3511 		retval = DDI_FAILURE;
3512 
3513 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3514 		if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG,
3515 		    STATE_MACHINE_ATTN_ENABLE_BIT))
3516 			retval = DDI_FAILURE;
3517 
3518 	/*
3519 	 * Step 72: Enable MAC DMA engines
3520 	 * Step 73: Clear & enable MAC statistics
3521 	 */
3522 	bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
3523 		ETHERNET_MODE_ENABLE_FHDE |
3524 		ETHERNET_MODE_ENABLE_RDE |
3525 		ETHERNET_MODE_ENABLE_TDE);
3526 	bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
3527 		ETHERNET_MODE_ENABLE_TX_STATS |
3528 		ETHERNET_MODE_ENABLE_RX_STATS |
3529 		ETHERNET_MODE_CLEAR_TX_STATS |
3530 		ETHERNET_MODE_CLEAR_RX_STATS);
3531 
3532 	/*
3533 	 * Step 74: configure the MLCR (Miscellaneous Local Control
3534 	 * Register); not required, as we set up the MLCR in step 10
3535 	 * (part of the reset code) above.
3536 	 *
3537 	 * Step 75: clear Interrupt Mailbox 0
3538 	 */
3539 	bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0);
3540 
3541 	/*
3542 	 * Steps 76-87: Gentlemen, start your engines ...
3543 	 *
3544 	 * Enable the DMA Completion Engine, the Write DMA Engine,
3545 	 * the Read DMA Engine, Receive Data Completion Engine,
3546 	 * the MBuf Cluster Free Engine, the Send Data Completion Engine,
3547 	 * the Send BD Completion Engine, the Receive BD Initiator Engine,
3548 	 * the Receive Data Initiator Engine, the Send Data Initiator Engine,
3549 	 * the Send BD Initiator Engine, and the Send BD Selector Engine.
3550 	 *
3551 	 * Beware exhaust fumes?
3552 	 */
3553 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3554 		if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0))
3555 			retval = DDI_FAILURE;
3556 	if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG,
3557 	    (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS))
3558 		retval = DDI_FAILURE;
3559 	if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG,
3560 	    (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS))
3561 		retval = DDI_FAILURE;
3562 	if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG,
3563 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3564 		retval = DDI_FAILURE;
3565 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3566 		if (!bge_chip_enable_engine(bgep,
3567 		    MBUF_CLUSTER_FREE_MODE_REG, 0))
3568 			retval = DDI_FAILURE;
3569 	if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0))
3570 		retval = DDI_FAILURE;
3571 	if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG,
3572 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3573 		retval = DDI_FAILURE;
3574 	if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG,
3575 	    RCV_BD_DISABLED_RING_ATTN))
3576 		retval = DDI_FAILURE;
3577 	if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG,
3578 	    RCV_DATA_BD_ILL_RING_ATTN))
3579 		retval = DDI_FAILURE;
3580 	if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0))
3581 		retval = DDI_FAILURE;
3582 	if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG,
3583 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3584 		retval = DDI_FAILURE;
3585 	if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG,
3586 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3587 		retval = DDI_FAILURE;
3588 
3589 	/*
3590 	 * Step 88: download firmware -- doesn't apply
3591 	 * Steps 89-90: enable Transmit & Receive MAC Engines
3592 	 */
3593 	if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3594 		retval = DDI_FAILURE;
3595 #ifdef BGE_IPMI_ASF
3596 	if (!bgep->asf_enabled) {
3597 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
3598 		    RECEIVE_MODE_KEEP_VLAN_TAG))
3599 			retval = DDI_FAILURE;
3600 	} else {
3601 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0))
3602 			retval = DDI_FAILURE;
3603 	}
3604 #else
3605 	if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
3606 	    RECEIVE_MODE_KEEP_VLAN_TAG))
3607 		retval = DDI_FAILURE;
3608 #endif
3609 
3610 	/*
3611 	 * Step 91: disable auto-polling of PHY status
3612 	 */
3613 	bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT);
3614 
3615 	/*
3616 	 * Step 92: configure D0 power state (not required)
3617 	 * Step 93: initialise LED control register ()
3618 	 */
3619 	ledctl = LED_CONTROL_DEFAULT;
3620 	switch (bgep->chipid.device) {
3621 	case DEVICE_ID_5700:
3622 	case DEVICE_ID_5700x:
3623 	case DEVICE_ID_5701:
3624 		/*
3625 		 * Switch to 5700 (MAC) mode on these older chips
3626 		 */
3627 		ledctl &= ~LED_CONTROL_LED_MODE_MASK;
3628 		ledctl |= LED_CONTROL_LED_MODE_5700;
3629 		break;
3630 
3631 	default:
3632 		break;
3633 	}
3634 	bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl);
3635 
3636 	/*
3637 	 * Step 94: activate link
3638 	 */
3639 	bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
3640 
3641 	/*
3642 	 * Step 95: set up physical layer (PHY/SerDes)
3643 	 * restart autoneg (if required)
3644 	 */
3645 	if (reset_phys)
3646 		if (bge_phys_update(bgep) == DDI_FAILURE)
3647 			retval = DDI_FAILURE;
3648 
3649 	/*
3650 	 * Extra step (DSG): hand over all the Receive Buffers to the chip
3651 	 */
3652 	for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring)
3653 		bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg,
3654 			bgep->buff[ring].rf_next);
3655 
3656 	/*
3657 	 * MSI bits:The least significant MSI 16-bit word.
3658 	 * ISR will be triggered different.
3659 	 */
3660 	if (bgep->intr_type == DDI_INTR_TYPE_MSI)
3661 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70);
3662 
3663 	/*
3664 	 * Extra step (DSG): select which interrupts are enabled
3665 	 *
3666 	 * Program the Ethernet MAC engine to signal attention on
3667 	 * Link Change events, then enable interrupts on MAC, DMA,
3668 	 * and FLOW attention signals.
3669 	 */
3670 	bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG,
3671 		ETHERNET_EVENT_LINK_INT |
3672 		ETHERNET_STATUS_PCS_ERROR_INT);
3673 #ifdef BGE_IPMI_ASF
3674 	if (bgep->asf_enabled) {
3675 		bge_reg_set32(bgep, MODE_CONTROL_REG,
3676 			MODE_INT_ON_FLOW_ATTN |
3677 			MODE_INT_ON_DMA_ATTN |
3678 			MODE_HOST_STACK_UP|
3679 			MODE_INT_ON_MAC_ATTN);
3680 	} else {
3681 #endif
3682 		bge_reg_set32(bgep, MODE_CONTROL_REG,
3683 			MODE_INT_ON_FLOW_ATTN |
3684 			MODE_INT_ON_DMA_ATTN |
3685 			MODE_INT_ON_MAC_ATTN);
3686 #ifdef BGE_IPMI_ASF
3687 	}
3688 #endif
3689 
3690 	/*
3691 	 * Step 97: enable PCI interrupts!!!
3692 	 */
3693 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
3694 		bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR,
3695 		    MHCR_MASK_PCI_INT_OUTPUT);
3696 
3697 	/*
3698 	 * All done!
3699 	 */
3700 	bgep->bge_chip_state = BGE_CHIP_RUNNING;
3701 	return (retval);
3702 }
3703 
3704 
3705 /*
3706  * ========== Hardware interrupt handler ==========
3707  */
3708 
3709 #undef	BGE_DBG
3710 #define	BGE_DBG		BGE_DBG_INT	/* debug flag for this code	*/
3711 
3712 /*
3713  * Sync the status block, then atomically clear the specified bits in
3714  * the <flags-and-tag> field of the status block.
3715  * the <flags> word of the status block, returning the value of the
3716  * <tag> and the <flags> before the bits were cleared.
3717  */
3718 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags);
3719 #pragma	inline(bge_status_sync)
3720 
3721 static int
3722 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags)
3723 {
3724 	bge_status_t *bsp;
3725 	int retval;
3726 
3727 	BGE_TRACE(("bge_status_sync($%p, 0x%llx)",
3728 		(void *)bgep, bits));
3729 
3730 	ASSERT(bgep->bge_guard == BGE_GUARD);
3731 
3732 	DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL);
3733 	retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl);
3734 	if (retval != DDI_FM_OK)
3735 		return (retval);
3736 
3737 	bsp = DMA_VPTR(bgep->status_block);
3738 	*flags = bge_atomic_clr64(&bsp->flags_n_tag, bits);
3739 
3740 	BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx",
3741 		(void *)bgep, bits, *flags));
3742 
3743 	return (retval);
3744 }
3745 
3746 static void bge_wake_factotum(bge_t *bgep);
3747 #pragma	inline(bge_wake_factotum)
3748 
3749 static void
3750 bge_wake_factotum(bge_t *bgep)
3751 {
3752 	mutex_enter(bgep->softintrlock);
3753 	if (bgep->factotum_flag == 0) {
3754 		bgep->factotum_flag = 1;
3755 		ddi_trigger_softintr(bgep->factotum_id);
3756 	}
3757 	mutex_exit(bgep->softintrlock);
3758 }
3759 
3760 /*
3761  *	bge_intr() -- handle chip interrupts
3762  */
3763 uint_t bge_intr(caddr_t arg1, caddr_t arg2);
3764 #pragma	no_inline(bge_intr)
3765 
3766 uint_t
3767 bge_intr(caddr_t arg1, caddr_t arg2)
3768 {
3769 	bge_t *bgep = (bge_t *)arg1;		/* private device info	*/
3770 	bge_status_t *bsp;
3771 	uint64_t flags;
3772 	uint32_t mlcr = 0;
3773 	uint_t result;
3774 	int retval;
3775 
3776 	BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2));
3777 
3778 	/*
3779 	 * GLD v2 checks that s/w setup is complete before passing
3780 	 * interrupts to this routine, thus eliminating the old
3781 	 * (and well-known) race condition around ddi_add_intr()
3782 	 */
3783 	ASSERT(bgep->progress & PROGRESS_HWINT);
3784 
3785 	/*
3786 	 * Check whether chip's says it's asserting #INTA;
3787 	 * if not, don't process or claim the interrupt.
3788 	 *
3789 	 * Note that the PCI signal is active low, so the
3790 	 * bit is *zero* when the interrupt is asserted.
3791 	 */
3792 	result = DDI_INTR_UNCLAIMED;
3793 	mutex_enter(bgep->genlock);
3794 
3795 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
3796 		mlcr = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
3797 
3798 	BGE_DEBUG(("bge_intr($%p) ($%p) mlcr 0x%08x", arg1, arg2, mlcr));
3799 
3800 	if ((mlcr & MLCR_INTA_STATE) == 0) {
3801 		/*
3802 		 * Block further PCI interrupts ...
3803 		 */
3804 		result = DDI_INTR_CLAIMED;
3805 
3806 		if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
3807 			bge_reg_set32(bgep, PCI_CONF_BGE_MHCR,
3808 				MHCR_MASK_PCI_INT_OUTPUT);
3809 			if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
3810 			    DDI_FM_OK)
3811 				goto chip_stop;
3812 		}
3813 
3814 		/*
3815 		 * Sync the status block and grab the flags-n-tag from it.
3816 		 * We count the number of interrupts where there doesn't
3817 		 * seem to have been a DMA update of the status block; if
3818 		 * it *has* been updated, the counter will be cleared in
3819 		 * the while() loop below ...
3820 		 */
3821 		bgep->missed_dmas += 1;
3822 		bsp = DMA_VPTR(bgep->status_block);
3823 		for (;;) {
3824 			if (bgep->bge_chip_state != BGE_CHIP_RUNNING) {
3825 				/*
3826 				 * bge_chip_stop() may have freed dma area etc
3827 				 * while we were in this interrupt handler -
3828 				 * better not call bge_status_sync()
3829 				 */
3830 				(void) bge_check_acc_handle(bgep,
3831 				    bgep->io_handle);
3832 				mutex_exit(bgep->genlock);
3833 				return (DDI_INTR_CLAIMED);
3834 			}
3835 			retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED,
3836 			    &flags);
3837 			if (retval != DDI_FM_OK) {
3838 				bgep->bge_dma_error = B_TRUE;
3839 				goto chip_stop;
3840 			}
3841 
3842 			if (!(flags & STATUS_FLAG_UPDATED))
3843 				break;
3844 
3845 			/*
3846 			 * Tell the chip that we're processing the interrupt
3847 			 */
3848 			bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
3849 				INTERRUPT_MBOX_DISABLE(flags));
3850 			if (bge_check_acc_handle(bgep, bgep->io_handle) !=
3851 			    DDI_FM_OK)
3852 				goto chip_stop;
3853 
3854 			/*
3855 			 * Drop the mutex while we:
3856 			 * 	Receive any newly-arrived packets
3857 			 *	Recycle any newly-finished send buffers
3858 			 */
3859 			bgep->bge_intr_running = B_TRUE;
3860 			mutex_exit(bgep->genlock);
3861 			bge_receive(bgep, bsp);
3862 			bge_recycle(bgep, bsp);
3863 			mutex_enter(bgep->genlock);
3864 			bgep->bge_intr_running = B_FALSE;
3865 
3866 			/*
3867 			 * Tell the chip we've finished processing, and
3868 			 * give it the tag that we got from the status
3869 			 * block earlier, so that it knows just how far
3870 			 * we've gone.  If it's got more for us to do,
3871 			 * it will now update the status block and try
3872 			 * to assert an interrupt (but we've got the
3873 			 * #INTA blocked at present).  If we see the
3874 			 * update, we'll loop around to do some more.
3875 			 * Eventually we'll get out of here ...
3876 			 */
3877 			bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
3878 				INTERRUPT_MBOX_ENABLE(flags));
3879 			bgep->missed_dmas = 0;
3880 		}
3881 
3882 		/*
3883 		 * Check for exceptional conditions that we need to handle
3884 		 *
3885 		 * Link status changed
3886 		 * Status block not updated
3887 		 */
3888 		if (flags & STATUS_FLAG_LINK_CHANGED)
3889 			bge_wake_factotum(bgep);
3890 
3891 		if (bgep->missed_dmas) {
3892 			/*
3893 			 * Probably due to the internal status tag not
3894 			 * being reset.  Force a status block update now;
3895 			 * this should ensure that we get an update and
3896 			 * a new interrupt.  After that, we should be in
3897 			 * sync again ...
3898 			 */
3899 			BGE_REPORT((bgep, "interrupt: flags 0x%llx - "
3900 				"not updated?", flags));
3901 			bge_reg_set32(bgep, HOST_COALESCE_MODE_REG,
3902 				COALESCE_NOW);
3903 
3904 			if (bgep->missed_dmas >= bge_dma_miss_limit) {
3905 				/*
3906 				 * If this happens multiple times in a row,
3907 				 * it means DMA is just not working.  Maybe
3908 				 * the chip's failed, or maybe there's a
3909 				 * problem on the PCI bus or in the host-PCI
3910 				 * bridge (Tomatillo).
3911 				 *
3912 				 * At all events, we want to stop further
3913 				 * interrupts and let the recovery code take
3914 				 * over to see whether anything can be done
3915 				 * about it ...
3916 				 */
3917 				bge_fm_ereport(bgep,
3918 				    DDI_FM_DEVICE_BADINT_LIMIT);
3919 				goto chip_stop;
3920 			}
3921 		}
3922 
3923 		/*
3924 		 * Reenable assertion of #INTA, unless there's a DMA fault
3925 		 */
3926 		if (result == DDI_INTR_CLAIMED) {
3927 			if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
3928 				bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR,
3929 					MHCR_MASK_PCI_INT_OUTPUT);
3930 				if (bge_check_acc_handle(bgep,
3931 				    bgep->cfg_handle) != DDI_FM_OK)
3932 					goto chip_stop;
3933 			}
3934 		}
3935 	}
3936 
3937 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
3938 		goto chip_stop;
3939 
3940 	mutex_exit(bgep->genlock);
3941 	return (result);
3942 
3943 chip_stop:
3944 #ifdef BGE_IPMI_ASF
3945 	if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) {
3946 		/*
3947 		 * We must stop ASF heart beat before
3948 		 * bge_chip_stop(), otherwise some
3949 		 * computers (ex. IBM HS20 blade
3950 		 * server) may crash.
3951 		 */
3952 		bge_asf_update_status(bgep);
3953 		bge_asf_stop_timer(bgep);
3954 		bgep->asf_status = ASF_STAT_STOP;
3955 
3956 		bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
3957 		(void) bge_check_acc_handle(bgep, bgep->cfg_handle);
3958 	}
3959 #endif
3960 	bge_chip_stop(bgep, B_TRUE);
3961 	(void) bge_check_acc_handle(bgep, bgep->io_handle);
3962 	mutex_exit(bgep->genlock);
3963 	return (result);
3964 }
3965 
3966 /*
3967  * ========== Factotum, implemented as a softint handler ==========
3968  */
3969 
3970 #undef	BGE_DBG
3971 #define	BGE_DBG		BGE_DBG_FACT	/* debug flag for this code	*/
3972 
3973 static void bge_factotum_error_handler(bge_t *bgep);
3974 #pragma	no_inline(bge_factotum_error_handler)
3975 
3976 static void
3977 bge_factotum_error_handler(bge_t *bgep)
3978 {
3979 	uint32_t flow;
3980 	uint32_t rdma;
3981 	uint32_t wdma;
3982 	uint32_t tmac;
3983 	uint32_t rmac;
3984 	uint32_t rxrs;
3985 	uint32_t txrs = 0;
3986 
3987 	ASSERT(mutex_owned(bgep->genlock));
3988 
3989 	/*
3990 	 * Read all the registers that show the possible
3991 	 * reasons for the ERROR bit to be asserted
3992 	 */
3993 	flow = bge_reg_get32(bgep, FLOW_ATTN_REG);
3994 	rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG);
3995 	wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG);
3996 	tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
3997 	rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG);
3998 	rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG);
3999 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4000 		txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG);
4001 
4002 	BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x",
4003 		(void *)bgep, flow, rdma, wdma));
4004 	BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x",
4005 		(void *)bgep, tmac, rmac, rxrs, txrs));
4006 
4007 	/*
4008 	 * For now, just clear all the errors ...
4009 	 */
4010 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4011 		bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0);
4012 	bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0);
4013 	bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0);
4014 	bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0);
4015 	bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0);
4016 	bge_reg_put32(bgep, FLOW_ATTN_REG, ~0);
4017 }
4018 
4019 /*
4020  * Handler for hardware link state change.
4021  *
4022  * When this routine is called, the hardware link state has changed
4023  * and the new state is reflected in the param_* variables.  Here
4024  * we must update the softstate, reprogram the MAC to match, and
4025  * record the change in the log and/or on the console.
4026  */
4027 static void bge_factotum_link_handler(bge_t *bgep);
4028 #pragma	no_inline(bge_factotum_link_handler)
4029 
4030 static void
4031 bge_factotum_link_handler(bge_t *bgep)
4032 {
4033 	void (*logfn)(bge_t *bgep, const char *fmt, ...);
4034 	const char *msg;
4035 	hrtime_t deltat;
4036 
4037 	ASSERT(mutex_owned(bgep->genlock));
4038 
4039 	/*
4040 	 * Update the s/w link_state
4041 	 */
4042 	if (bgep->param_link_up)
4043 		bgep->link_state = LINK_STATE_UP;
4044 	else
4045 		bgep->link_state = LINK_STATE_DOWN;
4046 
4047 	/*
4048 	 * Reprogram the MAC modes to match
4049 	 */
4050 	bge_sync_mac_modes(bgep);
4051 
4052 	/*
4053 	 * Finally, we have to decide whether to write a message
4054 	 * on the console or only in the log.  If the PHY has
4055 	 * been reprogrammed (at user request) "recently", then
4056 	 * the message only goes in the log.  Otherwise it's an
4057 	 * "unexpected" event, and it goes on the console as well.
4058 	 */
4059 	deltat = bgep->phys_event_time - bgep->phys_write_time;
4060 	if (deltat > BGE_LINK_SETTLE_TIME)
4061 		msg = "";
4062 	else if (bgep->param_link_up)
4063 		msg = bgep->link_up_msg;
4064 	else
4065 		msg = bgep->link_down_msg;
4066 
4067 	logfn = (msg == NULL || *msg == '\0') ? bge_notice : bge_log;
4068 	(*logfn)(bgep, "link %s%s", bgep->link_mode_msg, msg);
4069 }
4070 
4071 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state);
4072 #pragma	no_inline(bge_factotum_link_check)
4073 
4074 static boolean_t
4075 bge_factotum_link_check(bge_t *bgep, int *dma_state)
4076 {
4077 	boolean_t check;
4078 	uint64_t flags;
4079 	uint32_t tmac_status;
4080 
4081 	ASSERT(mutex_owned(bgep->genlock));
4082 
4083 	/*
4084 	 * Get & clear the writable status bits in the Tx status register
4085 	 * (some bits are write-1-to-clear, others are just readonly).
4086 	 */
4087 	tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
4088 	bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status);
4089 
4090 	/*
4091 	 * Get & clear the ERROR and LINK_CHANGED bits from the status block
4092 	 */
4093 	*dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR |
4094 	    STATUS_FLAG_LINK_CHANGED, &flags);
4095 	if (*dma_state != DDI_FM_OK)
4096 		return (B_FALSE);
4097 
4098 	/*
4099 	 * Clear any errors flagged in the status block ...
4100 	 */
4101 	if (flags & STATUS_FLAG_ERROR)
4102 		bge_factotum_error_handler(bgep);
4103 
4104 	/*
4105 	 * We need to check the link status if:
4106 	 *	the status block says there's been a link change
4107 	 *	or there's any discrepancy between the various
4108 	 *	flags indicating the link state (link_state,
4109 	 *	param_link_up, and the LINK STATE bit in the
4110 	 *	Transmit MAC status register).
4111 	 */
4112 	check = (flags & STATUS_FLAG_LINK_CHANGED) != 0;
4113 	switch (bgep->link_state) {
4114 	case LINK_STATE_UP:
4115 		check |= (bgep->param_link_up == B_FALSE);
4116 		check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0);
4117 		break;
4118 
4119 	case LINK_STATE_DOWN:
4120 		check |= (bgep->param_link_up != B_FALSE);
4121 		check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0);
4122 		break;
4123 
4124 	default:
4125 		check = B_TRUE;
4126 		break;
4127 	}
4128 
4129 	/*
4130 	 * If <check> is false, we're sure the link hasn't changed.
4131 	 * If true, however, it's not yet definitive; we have to call
4132 	 * bge_phys_check() to determine whether the link has settled
4133 	 * into a new state yet ... and if it has, then call the link
4134 	 * state change handler.But when the chip is 5700 in Dell 6650
4135 	 * ,even if check is false, the link may have changed.So we
4136 	 * have to call bge_phys_check() to determine the link state.
4137 	 */
4138 	if (check || bgep->chipid.device == DEVICE_ID_5700) {
4139 		check = bge_phys_check(bgep);
4140 		if (check)
4141 			bge_factotum_link_handler(bgep);
4142 	}
4143 
4144 	return (check);
4145 }
4146 
4147 /*
4148  * Factotum routine to check for Tx stall, using the 'watchdog' counter
4149  */
4150 static boolean_t bge_factotum_stall_check(bge_t *bgep);
4151 #pragma	no_inline(bge_factotum_stall_check)
4152 
4153 static boolean_t
4154 bge_factotum_stall_check(bge_t *bgep)
4155 {
4156 	uint32_t dogval;
4157 
4158 	ASSERT(mutex_owned(bgep->genlock));
4159 
4160 	/*
4161 	 * Specific check for Tx stall ...
4162 	 *
4163 	 * The 'watchdog' counter is incremented whenever a packet
4164 	 * is queued, reset to 1 when some (but not all) buffers
4165 	 * are reclaimed, reset to 0 (disabled) when all buffers
4166 	 * are reclaimed, and shifted left here.  If it exceeds the
4167 	 * threshold value, the chip is assumed to have stalled and
4168 	 * is put into the ERROR state.  The factotum will then reset
4169 	 * it on the next pass.
4170 	 *
4171 	 * All of which should ensure that we don't get into a state
4172 	 * where packets are left pending indefinitely!
4173 	 */
4174 	dogval = bge_atomic_shl32(&bgep->watchdog, 1);
4175 	if (dogval < bge_watchdog_count)
4176 		return (B_FALSE);
4177 
4178 	BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval));
4179 	bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL);
4180 	return (B_TRUE);
4181 }
4182 
4183 /*
4184  * The factotum is woken up when there's something to do that we'd rather
4185  * not do from inside a hardware interrupt handler or high-level cyclic.
4186  * Its two main tasks are:
4187  *	reset & restart the chip after an error
4188  *	check the link status whenever necessary
4189  */
4190 uint_t bge_chip_factotum(caddr_t arg);
4191 #pragma	no_inline(bge_chip_factotum)
4192 
4193 uint_t
4194 bge_chip_factotum(caddr_t arg)
4195 {
4196 	bge_t *bgep;
4197 	uint_t result;
4198 	boolean_t error;
4199 	boolean_t linkchg;
4200 	int dma_state;
4201 
4202 	bgep = (bge_t *)arg;
4203 
4204 	BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep));
4205 
4206 	mutex_enter(bgep->softintrlock);
4207 	if (bgep->factotum_flag == 0) {
4208 		mutex_exit(bgep->softintrlock);
4209 		return (DDI_INTR_UNCLAIMED);
4210 	}
4211 	bgep->factotum_flag = 0;
4212 	mutex_exit(bgep->softintrlock);
4213 
4214 	result = DDI_INTR_CLAIMED;
4215 	error = B_FALSE;
4216 	linkchg = B_FALSE;
4217 
4218 	mutex_enter(bgep->genlock);
4219 	switch (bgep->bge_chip_state) {
4220 	default:
4221 		break;
4222 
4223 	case BGE_CHIP_RUNNING:
4224 		linkchg = bge_factotum_link_check(bgep, &dma_state);
4225 		error = bge_factotum_stall_check(bgep);
4226 		if (dma_state != DDI_FM_OK) {
4227 			bgep->bge_dma_error = B_TRUE;
4228 			error = B_TRUE;
4229 		}
4230 		if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4231 			error = B_TRUE;
4232 		if (error)
4233 			bgep->bge_chip_state = BGE_CHIP_ERROR;
4234 		break;
4235 
4236 	case BGE_CHIP_ERROR:
4237 		error = B_TRUE;
4238 		break;
4239 
4240 	case BGE_CHIP_FAULT:
4241 		/*
4242 		 * Fault detected, time to reset ...
4243 		 */
4244 		if (bge_autorecover) {
4245 			if (!(bgep->progress & PROGRESS_BUFS)) {
4246 				/*
4247 				 * if we can't allocate the ring buffers,
4248 				 * try later
4249 				 */
4250 				if (bge_alloc_bufs(bgep) != DDI_SUCCESS) {
4251 					mutex_exit(bgep->genlock);
4252 					return (result);
4253 				}
4254 				bgep->progress |= PROGRESS_BUFS;
4255 			}
4256 			if (!(bgep->progress & PROGRESS_INTR)) {
4257 				bge_init_rings(bgep);
4258 				bge_intr_enable(bgep);
4259 				bgep->progress |= PROGRESS_INTR;
4260 			}
4261 			if (!(bgep->progress & PROGRESS_KSTATS)) {
4262 				bge_init_kstats(bgep,
4263 				    ddi_get_instance(bgep->devinfo));
4264 				bgep->progress |= PROGRESS_KSTATS;
4265 			}
4266 
4267 			BGE_REPORT((bgep, "automatic recovery activated"));
4268 
4269 			if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) {
4270 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4271 				error = B_TRUE;
4272 			}
4273 			if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
4274 			    DDI_FM_OK) {
4275 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4276 				error = B_TRUE;
4277 			}
4278 			if (bge_check_acc_handle(bgep, bgep->io_handle) !=
4279 			    DDI_FM_OK) {
4280 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4281 				error = B_TRUE;
4282 			}
4283 			if (error == B_FALSE) {
4284 #ifdef BGE_IPMI_ASF
4285 				if (bgep->asf_enabled &&
4286 				    bgep->asf_status != ASF_STAT_RUN) {
4287 					bgep->asf_timeout_id = timeout(
4288 					    bge_asf_heartbeat, (void *)bgep,
4289 					    drv_usectohz(
4290 					    BGE_ASF_HEARTBEAT_INTERVAL));
4291 					bgep->asf_status = ASF_STAT_RUN;
4292 				}
4293 #endif
4294 				ddi_fm_service_impact(bgep->devinfo,
4295 				    DDI_SERVICE_RESTORED);
4296 			}
4297 		}
4298 		break;
4299 	}
4300 
4301 
4302 	/*
4303 	 * If an error is detected, stop the chip now, marking it as
4304 	 * faulty, so that it will be reset next time through ...
4305 	 *
4306 	 * Note that if intr_running is set, then bge_intr() has dropped
4307 	 * genlock to call bge_receive/bge_recycle. Can't stop the chip at
4308 	 * this point so have to wait until the next time the factotum runs.
4309 	 */
4310 	if (error && !bgep->bge_intr_running) {
4311 #ifdef BGE_IPMI_ASF
4312 		if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) {
4313 			/*
4314 			 * We must stop ASF heart beat before bge_chip_stop(),
4315 			 * otherwise some computers (ex. IBM HS20 blade server)
4316 			 * may crash.
4317 			 */
4318 			bge_asf_update_status(bgep);
4319 			bge_asf_stop_timer(bgep);
4320 			bgep->asf_status = ASF_STAT_STOP;
4321 
4322 			bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
4323 			(void) bge_check_acc_handle(bgep, bgep->cfg_handle);
4324 		}
4325 #endif
4326 		bge_chip_stop(bgep, B_TRUE);
4327 		(void) bge_check_acc_handle(bgep, bgep->io_handle);
4328 	}
4329 	mutex_exit(bgep->genlock);
4330 
4331 	/*
4332 	 * If the link state changed, tell the world about it.
4333 	 * Note: can't do this while still holding the mutex.
4334 	 */
4335 	if (linkchg)
4336 		mac_link_update(bgep->mh, bgep->link_state);
4337 
4338 	return (result);
4339 }
4340 
4341 /*
4342  * High-level cyclic handler
4343  *
4344  * This routine schedules a (low-level) softint callback to the
4345  * factotum, and prods the chip to update the status block (which
4346  * will cause a hardware interrupt when complete).
4347  */
4348 void bge_chip_cyclic(void *arg);
4349 #pragma	no_inline(bge_chip_cyclic)
4350 
4351 void
4352 bge_chip_cyclic(void *arg)
4353 {
4354 	bge_t *bgep;
4355 
4356 	bgep = arg;
4357 
4358 	switch (bgep->bge_chip_state) {
4359 	default:
4360 		return;
4361 
4362 	case BGE_CHIP_RUNNING:
4363 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW);
4364 		if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4365 			ddi_fm_service_impact(bgep->devinfo,
4366 			    DDI_SERVICE_UNAFFECTED);
4367 		break;
4368 
4369 	case BGE_CHIP_FAULT:
4370 	case BGE_CHIP_ERROR:
4371 		break;
4372 	}
4373 
4374 	bge_wake_factotum(bgep);
4375 }
4376 
4377 
4378 /*
4379  * ========== Ioctl subfunctions ==========
4380  */
4381 
4382 #undef	BGE_DBG
4383 #define	BGE_DBG		BGE_DBG_PPIO	/* debug flag for this code	*/
4384 
4385 #if	BGE_DEBUGGING || BGE_DO_PPIO
4386 
4387 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
4388 #pragma	no_inline(bge_chip_peek_cfg)
4389 
4390 static void
4391 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
4392 {
4393 	uint64_t regval;
4394 	uint64_t regno;
4395 
4396 	BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)",
4397 		(void *)bgep, (void *)ppd));
4398 
4399 	regno = ppd->pp_acc_offset;
4400 
4401 	switch (ppd->pp_acc_size) {
4402 	case 1:
4403 		regval = pci_config_get8(bgep->cfg_handle, regno);
4404 		break;
4405 
4406 	case 2:
4407 		regval = pci_config_get16(bgep->cfg_handle, regno);
4408 		break;
4409 
4410 	case 4:
4411 		regval = pci_config_get32(bgep->cfg_handle, regno);
4412 		break;
4413 
4414 	case 8:
4415 		regval = pci_config_get64(bgep->cfg_handle, regno);
4416 		break;
4417 	}
4418 
4419 	ppd->pp_acc_data = regval;
4420 }
4421 
4422 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
4423 #pragma	no_inline(bge_chip_poke_cfg)
4424 
4425 static void
4426 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
4427 {
4428 	uint64_t regval;
4429 	uint64_t regno;
4430 
4431 	BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)",
4432 		(void *)bgep, (void *)ppd));
4433 
4434 	regno = ppd->pp_acc_offset;
4435 	regval = ppd->pp_acc_data;
4436 
4437 	switch (ppd->pp_acc_size) {
4438 	case 1:
4439 		pci_config_put8(bgep->cfg_handle, regno, regval);
4440 		break;
4441 
4442 	case 2:
4443 		pci_config_put16(bgep->cfg_handle, regno, regval);
4444 		break;
4445 
4446 	case 4:
4447 		pci_config_put32(bgep->cfg_handle, regno, regval);
4448 		break;
4449 
4450 	case 8:
4451 		pci_config_put64(bgep->cfg_handle, regno, regval);
4452 		break;
4453 	}
4454 }
4455 
4456 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd);
4457 #pragma	no_inline(bge_chip_peek_reg)
4458 
4459 static void
4460 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd)
4461 {
4462 	uint64_t regval;
4463 	void *regaddr;
4464 
4465 	BGE_TRACE(("bge_chip_peek_reg($%p, $%p)",
4466 		(void *)bgep, (void *)ppd));
4467 
4468 	regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
4469 
4470 	switch (ppd->pp_acc_size) {
4471 	case 1:
4472 		regval = ddi_get8(bgep->io_handle, regaddr);
4473 		break;
4474 
4475 	case 2:
4476 		regval = ddi_get16(bgep->io_handle, regaddr);
4477 		break;
4478 
4479 	case 4:
4480 		regval = ddi_get32(bgep->io_handle, regaddr);
4481 		break;
4482 
4483 	case 8:
4484 		regval = ddi_get64(bgep->io_handle, regaddr);
4485 		break;
4486 	}
4487 
4488 	ppd->pp_acc_data = regval;
4489 }
4490 
4491 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd);
4492 #pragma	no_inline(bge_chip_peek_reg)
4493 
4494 static void
4495 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd)
4496 {
4497 	uint64_t regval;
4498 	void *regaddr;
4499 
4500 	BGE_TRACE(("bge_chip_poke_reg($%p, $%p)",
4501 		(void *)bgep, (void *)ppd));
4502 
4503 	regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
4504 	regval = ppd->pp_acc_data;
4505 
4506 	switch (ppd->pp_acc_size) {
4507 	case 1:
4508 		ddi_put8(bgep->io_handle, regaddr, regval);
4509 		break;
4510 
4511 	case 2:
4512 		ddi_put16(bgep->io_handle, regaddr, regval);
4513 		break;
4514 
4515 	case 4:
4516 		ddi_put32(bgep->io_handle, regaddr, regval);
4517 		break;
4518 
4519 	case 8:
4520 		ddi_put64(bgep->io_handle, regaddr, regval);
4521 		break;
4522 	}
4523 	BGE_PCICHK(bgep);
4524 }
4525 
4526 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd);
4527 #pragma	no_inline(bge_chip_peek_nic)
4528 
4529 static void
4530 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd)
4531 {
4532 	uint64_t regoff;
4533 	uint64_t regval;
4534 	void *regaddr;
4535 
4536 	BGE_TRACE(("bge_chip_peek_nic($%p, $%p)",
4537 		(void *)bgep, (void *)ppd));
4538 
4539 	regoff = ppd->pp_acc_offset;
4540 	bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
4541 	regoff &= MWBAR_GRANULE_MASK;
4542 	regoff += NIC_MEM_WINDOW_OFFSET;
4543 	regaddr = PIO_ADDR(bgep, regoff);
4544 
4545 	switch (ppd->pp_acc_size) {
4546 	case 1:
4547 		regval = ddi_get8(bgep->io_handle, regaddr);
4548 		break;
4549 
4550 	case 2:
4551 		regval = ddi_get16(bgep->io_handle, regaddr);
4552 		break;
4553 
4554 	case 4:
4555 		regval = ddi_get32(bgep->io_handle, regaddr);
4556 		break;
4557 
4558 	case 8:
4559 		regval = ddi_get64(bgep->io_handle, regaddr);
4560 		break;
4561 	}
4562 
4563 	ppd->pp_acc_data = regval;
4564 }
4565 
4566 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd);
4567 #pragma	no_inline(bge_chip_poke_nic)
4568 
4569 static void
4570 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd)
4571 {
4572 	uint64_t regoff;
4573 	uint64_t regval;
4574 	void *regaddr;
4575 
4576 	BGE_TRACE(("bge_chip_poke_nic($%p, $%p)",
4577 		(void *)bgep, (void *)ppd));
4578 
4579 	regoff = ppd->pp_acc_offset;
4580 	bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
4581 	regoff &= MWBAR_GRANULE_MASK;
4582 	regoff += NIC_MEM_WINDOW_OFFSET;
4583 	regaddr = PIO_ADDR(bgep, regoff);
4584 	regval = ppd->pp_acc_data;
4585 
4586 	switch (ppd->pp_acc_size) {
4587 	case 1:
4588 		ddi_put8(bgep->io_handle, regaddr, regval);
4589 		break;
4590 
4591 	case 2:
4592 		ddi_put16(bgep->io_handle, regaddr, regval);
4593 		break;
4594 
4595 	case 4:
4596 		ddi_put32(bgep->io_handle, regaddr, regval);
4597 		break;
4598 
4599 	case 8:
4600 		ddi_put64(bgep->io_handle, regaddr, regval);
4601 		break;
4602 	}
4603 	BGE_PCICHK(bgep);
4604 }
4605 
4606 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd);
4607 #pragma	no_inline(bge_chip_peek_mii)
4608 
4609 static void
4610 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd)
4611 {
4612 	BGE_TRACE(("bge_chip_peek_mii($%p, $%p)",
4613 		(void *)bgep, (void *)ppd));
4614 
4615 	ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2);
4616 }
4617 
4618 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd);
4619 #pragma	no_inline(bge_chip_poke_mii)
4620 
4621 static void
4622 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd)
4623 {
4624 	BGE_TRACE(("bge_chip_poke_mii($%p, $%p)",
4625 		(void *)bgep, (void *)ppd));
4626 
4627 	bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
4628 }
4629 
4630 #if	BGE_SEE_IO32
4631 
4632 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
4633 #pragma	no_inline(bge_chip_peek_seeprom)
4634 
4635 static void
4636 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
4637 {
4638 	uint32_t data;
4639 	int err;
4640 
4641 	BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)",
4642 		(void *)bgep, (void *)ppd));
4643 
4644 	err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data);
4645 	ppd->pp_acc_data = err ? ~0ull : data;
4646 }
4647 
4648 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
4649 #pragma	no_inline(bge_chip_poke_seeprom)
4650 
4651 static void
4652 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
4653 {
4654 	uint32_t data;
4655 
4656 	BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)",
4657 		(void *)bgep, (void *)ppd));
4658 
4659 	data = ppd->pp_acc_data;
4660 	(void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data);
4661 }
4662 #endif	/* BGE_SEE_IO32 */
4663 
4664 #if	BGE_FLASH_IO32
4665 
4666 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd);
4667 #pragma	no_inline(bge_chip_peek_flash)
4668 
4669 static void
4670 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd)
4671 {
4672 	uint32_t data;
4673 	int err;
4674 
4675 	BGE_TRACE(("bge_chip_peek_flash($%p, $%p)",
4676 		(void *)bgep, (void *)ppd));
4677 
4678 	err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data);
4679 	ppd->pp_acc_data = err ? ~0ull : data;
4680 }
4681 
4682 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd);
4683 #pragma	no_inline(bge_chip_poke_flash)
4684 
4685 static void
4686 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd)
4687 {
4688 	uint32_t data;
4689 
4690 	BGE_TRACE(("bge_chip_poke_flash($%p, $%p)",
4691 		(void *)bgep, (void *)ppd));
4692 
4693 	data = ppd->pp_acc_data;
4694 	(void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE,
4695 	    ppd->pp_acc_offset, &data);
4696 }
4697 #endif	/* BGE_FLASH_IO32 */
4698 
4699 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd);
4700 #pragma	no_inline(bge_chip_peek_mem)
4701 
4702 static void
4703 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd)
4704 {
4705 	uint64_t regval;
4706 	void *vaddr;
4707 
4708 	BGE_TRACE(("bge_chip_peek_bge($%p, $%p)",
4709 		(void *)bgep, (void *)ppd));
4710 
4711 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
4712 
4713 	switch (ppd->pp_acc_size) {
4714 	case 1:
4715 		regval = *(uint8_t *)vaddr;
4716 		break;
4717 
4718 	case 2:
4719 		regval = *(uint16_t *)vaddr;
4720 		break;
4721 
4722 	case 4:
4723 		regval = *(uint32_t *)vaddr;
4724 		break;
4725 
4726 	case 8:
4727 		regval = *(uint64_t *)vaddr;
4728 		break;
4729 	}
4730 
4731 	BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p",
4732 		(void *)bgep, (void *)ppd, regval, vaddr));
4733 
4734 	ppd->pp_acc_data = regval;
4735 }
4736 
4737 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd);
4738 #pragma	no_inline(bge_chip_poke_mem)
4739 
4740 static void
4741 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd)
4742 {
4743 	uint64_t regval;
4744 	void *vaddr;
4745 
4746 	BGE_TRACE(("bge_chip_poke_mem($%p, $%p)",
4747 		(void *)bgep, (void *)ppd));
4748 
4749 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
4750 	regval = ppd->pp_acc_data;
4751 
4752 	BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p",
4753 		(void *)bgep, (void *)ppd, regval, vaddr));
4754 
4755 	switch (ppd->pp_acc_size) {
4756 	case 1:
4757 		*(uint8_t *)vaddr = (uint8_t)regval;
4758 		break;
4759 
4760 	case 2:
4761 		*(uint16_t *)vaddr = (uint16_t)regval;
4762 		break;
4763 
4764 	case 4:
4765 		*(uint32_t *)vaddr = (uint32_t)regval;
4766 		break;
4767 
4768 	case 8:
4769 		*(uint64_t *)vaddr = (uint64_t)regval;
4770 		break;
4771 	}
4772 }
4773 
4774 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
4775 					struct iocblk *iocp);
4776 #pragma	no_inline(bge_pp_ioctl)
4777 
4778 static enum ioc_reply
4779 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
4780 {
4781 	void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd);
4782 	bge_peekpoke_t *ppd;
4783 	dma_area_t *areap;
4784 	uint64_t sizemask;
4785 	uint64_t mem_va;
4786 	uint64_t maxoff;
4787 	boolean_t peek;
4788 
4789 	switch (cmd) {
4790 	default:
4791 		/* NOTREACHED */
4792 		bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd);
4793 		return (IOC_INVAL);
4794 
4795 	case BGE_PEEK:
4796 		peek = B_TRUE;
4797 		break;
4798 
4799 	case BGE_POKE:
4800 		peek = B_FALSE;
4801 		break;
4802 	}
4803 
4804 	/*
4805 	 * Validate format of ioctl
4806 	 */
4807 	if (iocp->ioc_count != sizeof (bge_peekpoke_t))
4808 		return (IOC_INVAL);
4809 	if (mp->b_cont == NULL)
4810 		return (IOC_INVAL);
4811 	ppd = (bge_peekpoke_t *)mp->b_cont->b_rptr;
4812 
4813 	/*
4814 	 * Validate request parameters
4815 	 */
4816 	switch (ppd->pp_acc_space) {
4817 	default:
4818 		return (IOC_INVAL);
4819 
4820 	case BGE_PP_SPACE_CFG:
4821 		/*
4822 		 * Config space
4823 		 */
4824 		sizemask = 8|4|2|1;
4825 		mem_va = 0;
4826 		maxoff = PCI_CONF_HDR_SIZE;
4827 		ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg;
4828 		break;
4829 
4830 	case BGE_PP_SPACE_REG:
4831 		/*
4832 		 * Memory-mapped I/O space
4833 		 */
4834 		sizemask = 8|4|2|1;
4835 		mem_va = 0;
4836 		maxoff = RIAAR_REGISTER_MAX;
4837 		ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg;
4838 		break;
4839 
4840 	case BGE_PP_SPACE_NIC:
4841 		/*
4842 		 * NIC on-chip memory
4843 		 */
4844 		sizemask = 8|4|2|1;
4845 		mem_va = 0;
4846 		maxoff = MWBAR_ONCHIP_MAX;
4847 		ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic;
4848 		break;
4849 
4850 	case BGE_PP_SPACE_MII:
4851 		/*
4852 		 * PHY's MII registers
4853 		 * NB: all PHY registers are two bytes, but the
4854 		 * addresses increment in ones (word addressing).
4855 		 * So we scale the address here, then undo the
4856 		 * transformation inside the peek/poke functions.
4857 		 */
4858 		ppd->pp_acc_offset *= 2;
4859 		sizemask = 2;
4860 		mem_va = 0;
4861 		maxoff = (MII_MAXREG+1)*2;
4862 		ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii;
4863 		break;
4864 
4865 #if	BGE_SEE_IO32
4866 	case BGE_PP_SPACE_SEEPROM:
4867 		/*
4868 		 * Attached SEEPROM(s), if any.
4869 		 * NB: we use the high-order bits of the 'address' as
4870 		 * a device select to accommodate multiple SEEPROMS,
4871 		 * If each one is the maximum size (64kbytes), this
4872 		 * makes them appear contiguous.  Otherwise, there may
4873 		 * be holes in the mapping.  ENxS doesn't have any
4874 		 * SEEPROMs anyway ...
4875 		 */
4876 		sizemask = 4;
4877 		mem_va = 0;
4878 		maxoff = SEEPROM_DEV_AND_ADDR_MASK;
4879 		ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom;
4880 		break;
4881 #endif	/* BGE_SEE_IO32 */
4882 
4883 #if	BGE_FLASH_IO32
4884 	case BGE_PP_SPACE_FLASH:
4885 		/*
4886 		 * Attached Flash device (if any); a maximum of one device
4887 		 * is currently supported.  But it can be up to 1MB (unlike
4888 		 * the 64k limit on SEEPROMs) so why would you need more ;-)
4889 		 */
4890 		sizemask = 4;
4891 		mem_va = 0;
4892 		maxoff = NVM_FLASH_ADDR_MASK;
4893 		ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash;
4894 		break;
4895 #endif	/* BGE_FLASH_IO32 */
4896 
4897 	case BGE_PP_SPACE_BGE:
4898 		/*
4899 		 * BGE data structure!
4900 		 */
4901 		sizemask = 8|4|2|1;
4902 		mem_va = (uintptr_t)bgep;
4903 		maxoff = sizeof (*bgep);
4904 		ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
4905 		break;
4906 
4907 	case BGE_PP_SPACE_STATUS:
4908 	case BGE_PP_SPACE_STATISTICS:
4909 	case BGE_PP_SPACE_TXDESC:
4910 	case BGE_PP_SPACE_TXBUFF:
4911 	case BGE_PP_SPACE_RXDESC:
4912 	case BGE_PP_SPACE_RXBUFF:
4913 		/*
4914 		 * Various DMA_AREAs
4915 		 */
4916 		switch (ppd->pp_acc_space) {
4917 		case BGE_PP_SPACE_TXDESC:
4918 			areap = &bgep->tx_desc;
4919 			break;
4920 		case BGE_PP_SPACE_TXBUFF:
4921 			areap = &bgep->tx_buff[0];
4922 			break;
4923 		case BGE_PP_SPACE_RXDESC:
4924 			areap = &bgep->rx_desc[0];
4925 			break;
4926 		case BGE_PP_SPACE_RXBUFF:
4927 			areap = &bgep->rx_buff[0];
4928 			break;
4929 		case BGE_PP_SPACE_STATUS:
4930 			areap = &bgep->status_block;
4931 			break;
4932 		case BGE_PP_SPACE_STATISTICS:
4933 			if (bgep->chipid.statistic_type == BGE_STAT_BLK)
4934 				areap = &bgep->statistics;
4935 			break;
4936 		}
4937 
4938 		sizemask = 8|4|2|1;
4939 		mem_va = (uintptr_t)areap->mem_va;
4940 		maxoff = areap->alength;
4941 		ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
4942 		break;
4943 	}
4944 
4945 	switch (ppd->pp_acc_size) {
4946 	default:
4947 		return (IOC_INVAL);
4948 
4949 	case 8:
4950 	case 4:
4951 	case 2:
4952 	case 1:
4953 		if ((ppd->pp_acc_size & sizemask) == 0)
4954 			return (IOC_INVAL);
4955 		break;
4956 	}
4957 
4958 	if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
4959 		return (IOC_INVAL);
4960 
4961 	if (ppd->pp_acc_offset >= maxoff)
4962 		return (IOC_INVAL);
4963 
4964 	if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff)
4965 		return (IOC_INVAL);
4966 
4967 	/*
4968 	 * All OK - go do it!
4969 	 */
4970 	ppd->pp_acc_offset += mem_va;
4971 	(*ppfn)(bgep, ppd);
4972 	return (peek ? IOC_REPLY : IOC_ACK);
4973 }
4974 
4975 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
4976 					struct iocblk *iocp);
4977 #pragma	no_inline(bge_diag_ioctl)
4978 
4979 static enum ioc_reply
4980 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
4981 {
4982 	ASSERT(mutex_owned(bgep->genlock));
4983 
4984 	switch (cmd) {
4985 	default:
4986 		/* NOTREACHED */
4987 		bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd);
4988 		return (IOC_INVAL);
4989 
4990 	case BGE_DIAG:
4991 		/*
4992 		 * Currently a no-op
4993 		 */
4994 		return (IOC_ACK);
4995 
4996 	case BGE_PEEK:
4997 	case BGE_POKE:
4998 		return (bge_pp_ioctl(bgep, cmd, mp, iocp));
4999 
5000 	case BGE_PHY_RESET:
5001 		return (IOC_RESTART_ACK);
5002 
5003 	case BGE_SOFT_RESET:
5004 	case BGE_HARD_RESET:
5005 		/*
5006 		 * Reset and reinitialise the 570x hardware
5007 		 */
5008 		(void) bge_restart(bgep, cmd == BGE_HARD_RESET);
5009 		return (IOC_ACK);
5010 	}
5011 
5012 	/* NOTREACHED */
5013 }
5014 
5015 #endif	/* BGE_DEBUGGING || BGE_DO_PPIO */
5016 
5017 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5018 				    struct iocblk *iocp);
5019 #pragma	no_inline(bge_mii_ioctl)
5020 
5021 static enum ioc_reply
5022 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5023 {
5024 	struct bge_mii_rw *miirwp;
5025 
5026 	/*
5027 	 * Validate format of ioctl
5028 	 */
5029 	if (iocp->ioc_count != sizeof (struct bge_mii_rw))
5030 		return (IOC_INVAL);
5031 	if (mp->b_cont == NULL)
5032 		return (IOC_INVAL);
5033 	miirwp = (struct bge_mii_rw *)mp->b_cont->b_rptr;
5034 
5035 	/*
5036 	 * Validate request parameters ...
5037 	 */
5038 	if (miirwp->mii_reg > MII_MAXREG)
5039 		return (IOC_INVAL);
5040 
5041 	switch (cmd) {
5042 	default:
5043 		/* NOTREACHED */
5044 		bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd);
5045 		return (IOC_INVAL);
5046 
5047 	case BGE_MII_READ:
5048 		miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg);
5049 		return (IOC_REPLY);
5050 
5051 	case BGE_MII_WRITE:
5052 		bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data);
5053 		return (IOC_ACK);
5054 	}
5055 
5056 	/* NOTREACHED */
5057 }
5058 
5059 #if	BGE_SEE_IO32
5060 
5061 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5062 				    struct iocblk *iocp);
5063 #pragma	no_inline(bge_see_ioctl)
5064 
5065 static enum ioc_reply
5066 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5067 {
5068 	struct bge_see_rw *seerwp;
5069 
5070 	/*
5071 	 * Validate format of ioctl
5072 	 */
5073 	if (iocp->ioc_count != sizeof (struct bge_see_rw))
5074 		return (IOC_INVAL);
5075 	if (mp->b_cont == NULL)
5076 		return (IOC_INVAL);
5077 	seerwp = (struct bge_see_rw *)mp->b_cont->b_rptr;
5078 
5079 	/*
5080 	 * Validate request parameters ...
5081 	 */
5082 	if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK)
5083 		return (IOC_INVAL);
5084 
5085 	switch (cmd) {
5086 	default:
5087 		/* NOTREACHED */
5088 		bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd);
5089 		return (IOC_INVAL);
5090 
5091 	case BGE_SEE_READ:
5092 	case BGE_SEE_WRITE:
5093 		iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5094 		    seerwp->see_addr, &seerwp->see_data);
5095 		return (IOC_REPLY);
5096 	}
5097 
5098 	/* NOTREACHED */
5099 }
5100 
5101 #endif	/* BGE_SEE_IO32 */
5102 
5103 #if	BGE_FLASH_IO32
5104 
5105 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5106 				    struct iocblk *iocp);
5107 #pragma	no_inline(bge_flash_ioctl)
5108 
5109 static enum ioc_reply
5110 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5111 {
5112 	struct bge_flash_rw *flashrwp;
5113 
5114 	/*
5115 	 * Validate format of ioctl
5116 	 */
5117 	if (iocp->ioc_count != sizeof (struct bge_flash_rw))
5118 		return (IOC_INVAL);
5119 	if (mp->b_cont == NULL)
5120 		return (IOC_INVAL);
5121 	flashrwp = (struct bge_flash_rw *)mp->b_cont->b_rptr;
5122 
5123 	/*
5124 	 * Validate request parameters ...
5125 	 */
5126 	if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK)
5127 		return (IOC_INVAL);
5128 
5129 	switch (cmd) {
5130 	default:
5131 		/* NOTREACHED */
5132 		bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd);
5133 		return (IOC_INVAL);
5134 
5135 	case BGE_FLASH_READ:
5136 	case BGE_FLASH_WRITE:
5137 		iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5138 		    flashrwp->flash_addr, &flashrwp->flash_data);
5139 		return (IOC_REPLY);
5140 	}
5141 
5142 	/* NOTREACHED */
5143 }
5144 
5145 #endif	/* BGE_FLASH_IO32 */
5146 
5147 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp,
5148 				struct iocblk *iocp);
5149 #pragma	no_inline(bge_chip_ioctl)
5150 
5151 enum ioc_reply
5152 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
5153 {
5154 	int cmd;
5155 
5156 	BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)",
5157 		(void *)bgep, (void *)wq, (void *)mp, (void *)iocp));
5158 
5159 	ASSERT(mutex_owned(bgep->genlock));
5160 
5161 	cmd = iocp->ioc_cmd;
5162 	switch (cmd) {
5163 	default:
5164 		/* NOTREACHED */
5165 		bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd);
5166 		return (IOC_INVAL);
5167 
5168 	case BGE_DIAG:
5169 	case BGE_PEEK:
5170 	case BGE_POKE:
5171 	case BGE_PHY_RESET:
5172 	case BGE_SOFT_RESET:
5173 	case BGE_HARD_RESET:
5174 #if	BGE_DEBUGGING || BGE_DO_PPIO
5175 		return (bge_diag_ioctl(bgep, cmd, mp, iocp));
5176 #else
5177 		return (IOC_INVAL);
5178 #endif	/* BGE_DEBUGGING || BGE_DO_PPIO */
5179 
5180 	case BGE_MII_READ:
5181 	case BGE_MII_WRITE:
5182 		return (bge_mii_ioctl(bgep, cmd, mp, iocp));
5183 
5184 #if	BGE_SEE_IO32
5185 	case BGE_SEE_READ:
5186 	case BGE_SEE_WRITE:
5187 		return (bge_see_ioctl(bgep, cmd, mp, iocp));
5188 #endif	/* BGE_SEE_IO32 */
5189 
5190 #if	BGE_FLASH_IO32
5191 	case BGE_FLASH_READ:
5192 	case BGE_FLASH_WRITE:
5193 		return (bge_flash_ioctl(bgep, cmd, mp, iocp));
5194 #endif	/* BGE_FLASH_IO32 */
5195 	}
5196 
5197 	/* NOTREACHED */
5198 }
5199 
5200 void
5201 bge_chip_blank(void *arg, time_t ticks, uint_t count)
5202 {
5203 	bge_t *bgep = arg;
5204 
5205 	mutex_enter(bgep->genlock);
5206 	bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks);
5207 	bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count);
5208 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5209 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
5210 	mutex_exit(bgep->genlock);
5211 }
5212 
5213 #ifdef BGE_IPMI_ASF
5214 
5215 uint32_t
5216 bge_nic_read32(bge_t *bgep, bge_regno_t addr)
5217 {
5218 	uint32_t data;
5219 
5220 	if (!bgep->asf_wordswapped) {
5221 		/* a workaround word swap error */
5222 		if (addr & 4)
5223 			addr = addr - 4;
5224 		else
5225 			addr = addr + 4;
5226 	}
5227 
5228 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
5229 	data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR);
5230 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
5231 
5232 	return (data);
5233 }
5234 
5235 
5236 void
5237 bge_asf_update_status(bge_t *bgep)
5238 {
5239 	uint32_t event;
5240 
5241 	bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE);
5242 	bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4);
5243 	bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX,   3);
5244 
5245 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5246 	bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
5247 }
5248 
5249 
5250 /*
5251  * The driver is supposed to notify ASF that the OS is still running
5252  * every three seconds, otherwise the management server may attempt
5253  * to reboot the machine.  If it hasn't actually failed, this is
5254  * not a desirable result.  However, this isn't running as a real-time
5255  * thread, and even if it were, it might not be able to generate the
5256  * heartbeat in a timely manner due to system load.  As it isn't a
5257  * significant strain on the machine, we will set the interval to half
5258  * of the required value.
5259  */
5260 void
5261 bge_asf_heartbeat(void *arg)
5262 {
5263 	bge_t *bgep = (bge_t *)arg;
5264 
5265 	mutex_enter(bgep->genlock);
5266 	bge_asf_update_status((bge_t *)bgep);
5267 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5268 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
5269 	if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK)
5270 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
5271 	mutex_exit(bgep->genlock);
5272 	((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep,
5273 		drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL));
5274 }
5275 
5276 
5277 void
5278 bge_asf_stop_timer(bge_t *bgep)
5279 {
5280 	timeout_id_t tmp_id = 0;
5281 
5282 	while ((bgep->asf_timeout_id != 0) &&
5283 		(tmp_id != bgep->asf_timeout_id)) {
5284 		tmp_id = bgep->asf_timeout_id;
5285 		(void) untimeout(tmp_id);
5286 	}
5287 	bgep->asf_timeout_id = 0;
5288 }
5289 
5290 
5291 
5292 /*
5293  * This function should be placed at the earliest position of bge_attach().
5294  */
5295 void
5296 bge_asf_get_config(bge_t *bgep)
5297 {
5298 	uint32_t nicsig;
5299 	uint32_t niccfg;
5300 
5301 	nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR);
5302 	if (nicsig == BGE_NIC_DATA_SIG) {
5303 		niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR);
5304 		if (niccfg & BGE_NIC_CFG_ENABLE_ASF)
5305 			/*
5306 			 * Here, we don't consider BAXTER, because BGE haven't
5307 			 * supported BAXTER (that is 5752). Also, as I know,
5308 			 * BAXTER doesn't support ASF feature.
5309 			 */
5310 			bgep->asf_enabled = B_TRUE;
5311 		else
5312 			bgep->asf_enabled = B_FALSE;
5313 	} else
5314 		bgep->asf_enabled = B_FALSE;
5315 }
5316 
5317 
5318 void
5319 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode)
5320 {
5321 	uint32_t tries;
5322 	uint32_t event;
5323 
5324 	ASSERT(bgep->asf_enabled);
5325 
5326 	/* Issues "pause firmware" command and wait for ACK */
5327 	bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW);
5328 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5329 	bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
5330 
5331 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5332 	tries = 0;
5333 	while ((event & RRER_ASF_EVENT) && (tries < 100)) {
5334 		drv_usecwait(1);
5335 		tries ++;
5336 		event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5337 	}
5338 
5339 	bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX,
5340 		BGE_MAGIC_NUM_FIRMWARE_INIT_DONE);
5341 
5342 	if (bgep->asf_newhandshake) {
5343 		switch (mode) {
5344 		case BGE_INIT_RESET:
5345 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5346 				BGE_DRV_STATE_START);
5347 			break;
5348 		case BGE_SHUTDOWN_RESET:
5349 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5350 				BGE_DRV_STATE_UNLOAD);
5351 			break;
5352 		case BGE_SUSPEND_RESET:
5353 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5354 				BGE_DRV_STATE_SUSPEND);
5355 			break;
5356 		default:
5357 			break;
5358 		}
5359 	}
5360 }
5361 
5362 
5363 void
5364 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode)
5365 {
5366 	switch (mode) {
5367 	case BGE_INIT_RESET:
5368 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5369 			BGE_DRV_STATE_START);
5370 		break;
5371 	case BGE_SHUTDOWN_RESET:
5372 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5373 			BGE_DRV_STATE_UNLOAD);
5374 		break;
5375 	case BGE_SUSPEND_RESET:
5376 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5377 			BGE_DRV_STATE_SUSPEND);
5378 		break;
5379 	default:
5380 		break;
5381 	}
5382 }
5383 
5384 
5385 void
5386 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode)
5387 {
5388 	switch (mode) {
5389 	case BGE_INIT_RESET:
5390 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5391 			BGE_DRV_STATE_START_DONE);
5392 		break;
5393 	case BGE_SHUTDOWN_RESET:
5394 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5395 			BGE_DRV_STATE_UNLOAD_DONE);
5396 		break;
5397 	default:
5398 		break;
5399 	}
5400 }
5401 
5402 #endif /* BGE_IPMI_ASF */
5403