1 /* 2 * Solaris driver for ethernet cards based on the ADMtek Centaur 3 * 4 * Copyright (c) 2007 by Garrett D'Amore <garrett@damore.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the author nor the names of any co-contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS ``AS IS'' 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #pragma ident "%Z%%M% %I% %E% SMI" 33 34 #include <sys/varargs.h> 35 #include <sys/types.h> 36 #include <sys/modctl.h> 37 #include <sys/conf.h> 38 #include <sys/devops.h> 39 #include <sys/stream.h> 40 #include <sys/strsun.h> 41 #include <sys/priv.h> 42 #include <sys/policy.h> 43 #include <sys/cred.h> 44 #include <sys/cmn_err.h> 45 #include <sys/dlpi.h> 46 #include <sys/ethernet.h> 47 #include <sys/kmem.h> 48 #include <sys/time.h> 49 #include <sys/crc32.h> 50 #include <sys/miiregs.h> 51 #include <sys/mac.h> 52 #include <sys/mac_ether.h> 53 #include <sys/ddi.h> 54 #include <sys/sunddi.h> 55 #include <sys/vlan.h> 56 57 #include "afe.h" 58 #include "afeimpl.h" 59 60 /* 61 * Driver globals. 62 */ 63 64 /* patchable debug flag ... must not be static! */ 65 #ifdef DEBUG 66 unsigned afe_debug = DWARN; 67 #endif 68 69 /* table of supported devices */ 70 static afe_card_t afe_cards[] = { 71 72 /* 73 * ADMtek Centaur and Comet 74 */ 75 { 0x1317, 0x0981, "ADMtek AL981", MODEL_COMET }, 76 { 0x1317, 0x0985, "ADMtek AN983", MODEL_CENTAUR }, 77 { 0x1317, 0x1985, "ADMtek AN985", MODEL_CENTAUR }, 78 { 0x1317, 0x9511, "ADMtek ADM9511", MODEL_CENTAUR }, 79 { 0x1317, 0x9513, "ADMtek ADM9513", MODEL_CENTAUR }, 80 /* 81 * Accton just relabels other companies' controllers 82 */ 83 { 0x1113, 0x1216, "Accton EN5251", MODEL_CENTAUR }, 84 /* 85 * Models listed here. 86 */ 87 { 0x10b7, 0x9300, "3Com 3CSOHO100B-TX", MODEL_CENTAUR }, 88 { 0x1113, 0xec02, "SMC SMC1244TX", MODEL_CENTAUR }, 89 { 0x10b8, 0x1255, "SMC SMC1255TX", MODEL_CENTAUR }, 90 { 0x111a, 0x1020, "Siemens SpeedStream PCI 10/100", MODEL_CENTAUR }, 91 { 0x1113, 0x1207, "Accton EN1207F", MODEL_CENTAUR }, 92 { 0x1113, 0x2242, "Accton EN2242", MODEL_CENTAUR }, 93 { 0x1113, 0x2220, "Accton EN2220", MODEL_CENTAUR }, 94 { 0x1113, 0x9216, "3M VOL-N100VF+TX", MODEL_CENTAUR }, 95 { 0x1317, 0x0574, "Linksys LNE100TX", MODEL_CENTAUR }, 96 { 0x1317, 0x0570, "Linksys NC100", MODEL_CENTAUR }, 97 { 0x1385, 0x511a, "Netgear FA511", MODEL_CENTAUR }, 98 { 0x13d1, 0xab02, "AboCom FE2500", MODEL_CENTAUR }, 99 { 0x13d1, 0xab03, "AboCom PCM200", MODEL_CENTAUR }, 100 { 0x13d1, 0xab08, "AboCom FE2500MX", MODEL_CENTAUR }, 101 { 0x1414, 0x0001, "Microsoft MN-120", MODEL_CENTAUR }, 102 { 0x16ec, 0x00ed, "U.S. Robotics USR997900", MODEL_CENTAUR }, 103 { 0x1734, 0x100c, "Fujitsu-Siemens D1961", MODEL_CENTAUR }, 104 { 0x1737, 0xab08, "Linksys PCMPC200", MODEL_CENTAUR }, 105 { 0x1737, 0xab09, "Linksys PCM200", MODEL_CENTAUR }, 106 { 0x17b3, 0xab08, "Hawking PN672TX", MODEL_CENTAUR }, 107 }; 108 109 #define ETHERVLANMTU (ETHERMAX + 4) 110 111 /* 112 * Function prototypes 113 */ 114 static int afe_attach(dev_info_t *, ddi_attach_cmd_t); 115 static int afe_detach(dev_info_t *, ddi_detach_cmd_t); 116 static int afe_resume(dev_info_t *); 117 static int afe_m_unicst(void *, const uint8_t *); 118 static int afe_m_multicst(void *, boolean_t, const uint8_t *); 119 static int afe_m_promisc(void *, boolean_t); 120 static mblk_t *afe_m_tx(void *, mblk_t *); 121 static int afe_m_stat(void *, uint_t, uint64_t *); 122 static int afe_m_start(void *); 123 static void afe_m_stop(void *); 124 static void afe_m_ioctl(void *, queue_t *, mblk_t *); 125 static unsigned afe_intr(caddr_t); 126 static void afe_startmac(afe_t *); 127 static void afe_stopmac(afe_t *); 128 static void afe_resetrings(afe_t *); 129 static boolean_t afe_initialize(afe_t *); 130 static void afe_startall(afe_t *); 131 static void afe_stopall(afe_t *); 132 static void afe_resetall(afe_t *); 133 static afe_txbuf_t *afe_alloctxbuf(afe_t *); 134 static void afe_destroytxbuf(afe_txbuf_t *); 135 static afe_rxbuf_t *afe_allocrxbuf(afe_t *); 136 static void afe_destroyrxbuf(afe_rxbuf_t *); 137 static boolean_t afe_send(afe_t *, mblk_t *); 138 static int afe_allocrxring(afe_t *); 139 static void afe_freerxring(afe_t *); 140 static int afe_alloctxring(afe_t *); 141 static void afe_freetxring(afe_t *); 142 static void afe_error(dev_info_t *, char *, ...); 143 static void afe_setrxfilt(afe_t *); 144 static uint8_t afe_sromwidth(afe_t *); 145 static uint16_t afe_readsromword(afe_t *, unsigned); 146 static void afe_readsrom(afe_t *, unsigned, unsigned, char *); 147 static void afe_getfactaddr(afe_t *, uchar_t *); 148 static int afe_miireadbit(afe_t *); 149 static void afe_miiwritebit(afe_t *, int); 150 static void afe_miitristate(afe_t *); 151 static unsigned afe_miiread(afe_t *, int, int); 152 static void afe_miiwrite(afe_t *, int, int, uint16_t); 153 static unsigned afe_miireadgeneral(afe_t *, int, int); 154 static void afe_miiwritegeneral(afe_t *, int, int, uint16_t); 155 static unsigned afe_miireadcomet(afe_t *, int, int); 156 static void afe_miiwritecomet(afe_t *, int, int, uint16_t); 157 static int afe_getmiibit(afe_t *, uint16_t, uint16_t); 158 static void afe_startphy(afe_t *); 159 static void afe_stopphy(afe_t *); 160 static void afe_reportlink(afe_t *); 161 static void afe_checklink(afe_t *); 162 static void afe_checklinkcomet(afe_t *); 163 static void afe_checklinkcentaur(afe_t *); 164 static void afe_checklinkmii(afe_t *); 165 static void afe_disableinterrupts(afe_t *); 166 static void afe_enableinterrupts(afe_t *); 167 static void afe_reclaim(afe_t *); 168 static mblk_t *afe_receive(afe_t *); 169 static int afe_ndaddbytes(mblk_t *, char *, int); 170 static int afe_ndaddstr(mblk_t *, char *, int); 171 static void afe_ndparsestring(mblk_t *, char *, int); 172 static int afe_ndparselen(mblk_t *); 173 static int afe_ndparseint(mblk_t *); 174 static void afe_ndget(afe_t *, queue_t *, mblk_t *); 175 static void afe_ndset(afe_t *, queue_t *, mblk_t *); 176 static void afe_ndfini(afe_t *); 177 static void afe_ndinit(afe_t *); 178 static int afe_ndquestion(afe_t *, mblk_t *, afe_nd_t *); 179 static int afe_ndgetint(afe_t *, mblk_t *, afe_nd_t *); 180 static int afe_ndgetmiibit(afe_t *, mblk_t *, afe_nd_t *); 181 static int afe_ndsetadv(afe_t *, mblk_t *, afe_nd_t *); 182 static afe_nd_t *afe_ndfind(afe_t *, char *); 183 static void afe_ndempty(mblk_t *); 184 static void afe_ndadd(afe_t *, char *, afe_nd_pf_t, afe_nd_pf_t, 185 intptr_t, intptr_t); 186 187 #ifdef DEBUG 188 static void afe_dprintf(afe_t *, const char *, int, char *, ...); 189 #endif 190 191 #define KIOIP KSTAT_INTR_PTR(afep->afe_intrstat) 192 193 static mac_callbacks_t afe_m_callbacks = { 194 MC_IOCTL, 195 afe_m_stat, 196 afe_m_start, 197 afe_m_stop, 198 afe_m_promisc, 199 afe_m_multicst, 200 afe_m_unicst, 201 afe_m_tx, 202 NULL, 203 afe_m_ioctl, 204 NULL, /* m_getcapab */ 205 }; 206 207 208 /* 209 * Stream information 210 */ 211 DDI_DEFINE_STREAM_OPS(afe_devops, nulldev, nulldev, afe_attach, afe_detach, 212 nodev, NULL, D_MP, NULL); 213 214 /* 215 * Module linkage information. 216 */ 217 218 static struct modldrv afe_modldrv = { 219 &mod_driverops, /* drv_modops */ 220 "ADMtek Fast Ethernet", /* drv_linkinfo */ 221 &afe_devops /* drv_dev_ops */ 222 }; 223 224 static struct modlinkage afe_modlinkage = { 225 MODREV_1, /* ml_rev */ 226 { &afe_modldrv, NULL } /* ml_linkage */ 227 }; 228 229 /* 230 * Device attributes. 231 */ 232 static ddi_device_acc_attr_t afe_devattr = { 233 DDI_DEVICE_ATTR_V0, 234 DDI_STRUCTURE_LE_ACC, 235 DDI_STRICTORDER_ACC 236 }; 237 238 static ddi_device_acc_attr_t afe_bufattr = { 239 DDI_DEVICE_ATTR_V0, 240 DDI_NEVERSWAP_ACC, 241 DDI_STRICTORDER_ACC 242 }; 243 244 static ddi_dma_attr_t afe_dma_attr = { 245 DMA_ATTR_V0, /* dma_attr_version */ 246 0, /* dma_attr_addr_lo */ 247 0xFFFFFFFFU, /* dma_attr_addr_hi */ 248 0x7FFFFFFFU, /* dma_attr_count_max */ 249 4, /* dma_attr_align */ 250 0x3F, /* dma_attr_burstsizes */ 251 1, /* dma_attr_minxfer */ 252 0xFFFFFFFFU, /* dma_attr_maxxfer */ 253 0xFFFFFFFFU, /* dma_attr_seg */ 254 1, /* dma_attr_sgllen */ 255 1, /* dma_attr_granular */ 256 0 /* dma_attr_flags */ 257 }; 258 259 /* 260 * Tx buffers can be arbitrarily aligned. Additionally, they can 261 * cross a page boundary, so we use the two buffer addresses of the 262 * chip to provide a two-entry scatter-gather list. 263 */ 264 static ddi_dma_attr_t afe_dma_txattr = { 265 DMA_ATTR_V0, /* dma_attr_version */ 266 0, /* dma_attr_addr_lo */ 267 0xFFFFFFFFU, /* dma_attr_addr_hi */ 268 0x7FFFFFFFU, /* dma_attr_count_max */ 269 1, /* dma_attr_align */ 270 0x3F, /* dma_attr_burstsizes */ 271 1, /* dma_attr_minxfer */ 272 0xFFFFFFFFU, /* dma_attr_maxxfer */ 273 0xFFFFFFFFU, /* dma_attr_seg */ 274 2, /* dma_attr_sgllen */ 275 1, /* dma_attr_granular */ 276 0 /* dma_attr_flags */ 277 }; 278 279 /* 280 * Ethernet addresses. 281 */ 282 static uchar_t afe_broadcast[ETHERADDRL] = { 283 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 284 }; 285 286 /* 287 * DDI entry points. 288 */ 289 int 290 _init(void) 291 { 292 int rv; 293 mac_init_ops(&afe_devops, "afe"); 294 if ((rv = mod_install(&afe_modlinkage)) != DDI_SUCCESS) { 295 mac_fini_ops(&afe_devops); 296 } 297 return (rv); 298 } 299 300 int 301 _fini(void) 302 { 303 int rv; 304 if ((rv = mod_remove(&afe_modlinkage)) == DDI_SUCCESS) { 305 mac_fini_ops(&afe_devops); 306 } 307 return (rv); 308 } 309 310 int 311 _info(struct modinfo *modinfop) 312 { 313 return (mod_info(&afe_modlinkage, modinfop)); 314 } 315 316 int 317 afe_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 318 { 319 afe_t *afep; 320 mac_register_t *macp; 321 int inst = ddi_get_instance(dip); 322 ddi_acc_handle_t pci; 323 uint16_t venid; 324 uint16_t devid; 325 uint16_t svid; 326 uint16_t ssid; 327 uint16_t cachesize; 328 afe_card_t *cardp; 329 int i; 330 331 switch (cmd) { 332 case DDI_RESUME: 333 return (afe_resume(dip)); 334 335 case DDI_ATTACH: 336 break; 337 338 default: 339 return (DDI_FAILURE); 340 } 341 342 /* this card is a bus master, reject any slave-only slot */ 343 if (ddi_slaveonly(dip) == DDI_SUCCESS) { 344 afe_error(dip, "slot does not support PCI bus-master"); 345 return (DDI_FAILURE); 346 } 347 /* PCI devices shouldn't generate hilevel interrupts */ 348 if (ddi_intr_hilevel(dip, 0) != 0) { 349 afe_error(dip, "hilevel interrupts not supported"); 350 return (DDI_FAILURE); 351 } 352 if (pci_config_setup(dip, &pci) != DDI_SUCCESS) { 353 afe_error(dip, "unable to setup PCI config handle"); 354 return (DDI_FAILURE); 355 } 356 357 venid = pci_config_get16(pci, PCI_VID); 358 devid = pci_config_get16(pci, PCI_DID); 359 svid = pci_config_get16(pci, PCI_SVID); 360 ssid = pci_config_get16(pci, PCI_SSID); 361 362 /* 363 * Note: ADMtek boards seem to misprogram themselves with bogus 364 * timings, which do not seem to work properly on SPARC. We 365 * reprogram them zero (but only if they appear to be broken), 366 * which seems to at least work. Its unclear that this is a 367 * legal or wise practice to me, but it certainly works better 368 * than the original values. (I would love to hear 369 * suggestions for better values, or a better strategy.) 370 */ 371 if ((pci_config_get8(pci, PCI_MINGNT) == 0xff) && 372 (pci_config_get8(pci, PCI_MAXLAT) == 0xff)) { 373 pci_config_put8(pci, PCI_MINGNT, 0); 374 pci_config_put8(pci, PCI_MAXLAT, 0); 375 } 376 377 /* 378 * the last entry in the card table matches every possible 379 * card, so the for-loop always terminates properly. 380 */ 381 cardp = NULL; 382 for (i = 0; i < (sizeof (afe_cards) / sizeof (afe_card_t)); i++) { 383 if ((venid == afe_cards[i].card_venid) && 384 (devid == afe_cards[i].card_devid)) { 385 cardp = &afe_cards[i]; 386 } 387 if ((svid == afe_cards[i].card_venid) && 388 (ssid == afe_cards[i].card_devid)) { 389 cardp = &afe_cards[i]; 390 break; 391 } 392 } 393 394 if (cardp == NULL) { 395 pci_config_teardown(&pci); 396 afe_error(dip, "Unable to identify PCI card"); 397 return (DDI_FAILURE); 398 } 399 400 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 401 cardp->card_cardname) != DDI_PROP_SUCCESS) { 402 pci_config_teardown(&pci); 403 afe_error(dip, "Unable to create model property"); 404 return (DDI_FAILURE); 405 } 406 407 /* 408 * Grab the PCI cachesize -- we use this to program the 409 * cache-optimization bus access bits. 410 */ 411 cachesize = pci_config_get8(pci, PCI_CLS); 412 413 /* this cannot fail */ 414 afep = kmem_zalloc(sizeof (afe_t), KM_SLEEP); 415 ddi_set_driver_private(dip, afep); 416 417 /* get the interrupt block cookie */ 418 if (ddi_get_iblock_cookie(dip, 0, &afep->afe_icookie) != DDI_SUCCESS) { 419 afe_error(dip, "ddi_get_iblock_cookie failed"); 420 pci_config_teardown(&pci); 421 kmem_free(afep, sizeof (afe_t)); 422 return (DDI_FAILURE); 423 } 424 425 afep->afe_dip = dip; 426 afep->afe_cardp = cardp; 427 afep->afe_phyaddr = -1; 428 afep->afe_cachesize = cachesize; 429 430 /* default properties */ 431 afep->afe_adv_aneg = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 432 "adv_autoneg_cap", 1); 433 afep->afe_adv_100T4 = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 434 "adv_100T4_cap", 1); 435 afep->afe_adv_100fdx = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 436 "adv_100fdx_cap", 1); 437 afep->afe_adv_100hdx = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 438 "adv_100hdx_cap", 1); 439 afep->afe_adv_10fdx = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 440 "adv_10fdx_cap", 1); 441 afep->afe_adv_10hdx = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 442 "adv_10hdx_cap", 1); 443 444 afep->afe_forcefiber = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 445 "fiber", 0); 446 447 DBG(DPCI, "PCI vendor id = %x", venid); 448 DBG(DPCI, "PCI device id = %x", devid); 449 DBG(DPCI, "PCI cachesize = %d", cachesize); 450 DBG(DPCI, "PCI COMM = %x", pci_config_get8(pci, PCI_CMD)); 451 DBG(DPCI, "PCI STAT = %x", pci_config_get8(pci, PCI_STAT)); 452 453 mutex_init(&afep->afe_xmtlock, NULL, MUTEX_DRIVER, afep->afe_icookie); 454 mutex_init(&afep->afe_intrlock, NULL, MUTEX_DRIVER, afep->afe_icookie); 455 456 afe_ndinit(afep); 457 458 /* 459 * Enable bus master, IO space, and memory space accesses. 460 */ 461 pci_config_put16(pci, PCI_CMD, 462 pci_config_get16(pci, PCI_CMD) | PCI_CMD_BME | PCI_CMD_MAE); 463 464 /* we're done with this now, drop it */ 465 pci_config_teardown(&pci); 466 467 /* 468 * Initialize interrupt kstat. This should not normally fail, since 469 * we don't use a persistent stat. We do it this way to avoid having 470 * to test for it at run time on the hot path. 471 */ 472 afep->afe_intrstat = kstat_create("afe", inst, "intr", "controller", 473 KSTAT_TYPE_INTR, 1, 0); 474 if (afep->afe_intrstat == NULL) { 475 afe_error(dip, "kstat_create failed"); 476 goto failed; 477 } 478 kstat_install(afep->afe_intrstat); 479 480 /* 481 * Map in the device registers. 482 */ 483 if (ddi_regs_map_setup(dip, 1, (caddr_t *)&afep->afe_regs, 484 0, 0, &afe_devattr, &afep->afe_regshandle)) { 485 afe_error(dip, "ddi_regs_map_setup failed"); 486 goto failed; 487 } 488 489 /* 490 * Allocate DMA resources (descriptor rings and buffers). 491 */ 492 if ((afe_allocrxring(afep) != DDI_SUCCESS) || 493 (afe_alloctxring(afep) != DDI_SUCCESS)) { 494 afe_error(dip, "unable to allocate DMA resources"); 495 goto failed; 496 } 497 498 /* Initialize the chip. */ 499 mutex_enter(&afep->afe_intrlock); 500 mutex_enter(&afep->afe_xmtlock); 501 if (!afe_initialize(afep)) { 502 mutex_exit(&afep->afe_xmtlock); 503 mutex_exit(&afep->afe_intrlock); 504 goto failed; 505 } 506 mutex_exit(&afep->afe_xmtlock); 507 mutex_exit(&afep->afe_intrlock); 508 509 /* Determine the number of address bits to our EEPROM. */ 510 afep->afe_sromwidth = afe_sromwidth(afep); 511 512 /* 513 * Get the factory ethernet address. This becomes the current 514 * ethernet address (it can be overridden later via ifconfig). 515 */ 516 afe_getfactaddr(afep, afep->afe_curraddr); 517 afep->afe_promisc = B_FALSE; 518 519 /* make sure we add configure the initial filter */ 520 (void) afe_m_unicst(afep, afep->afe_curraddr); 521 (void) afe_m_multicst(afep, B_TRUE, afe_broadcast); 522 523 /* 524 * Establish interrupt handler. 525 */ 526 if (ddi_add_intr(dip, 0, NULL, NULL, afe_intr, (caddr_t)afep) != 527 DDI_SUCCESS) { 528 afe_error(dip, "unable to add interrupt"); 529 goto failed; 530 } 531 532 /* TODO: do the power management stuff */ 533 534 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 535 afe_error(dip, "mac_alloc failed"); 536 goto failed; 537 } 538 539 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 540 macp->m_driver = afep; 541 macp->m_dip = dip; 542 macp->m_src_addr = afep->afe_curraddr; 543 macp->m_callbacks = &afe_m_callbacks; 544 macp->m_min_sdu = 0; 545 macp->m_max_sdu = ETHERMTU; 546 macp->m_margin = VLAN_TAGSZ; 547 548 if (mac_register(macp, &afep->afe_mh) == DDI_SUCCESS) { 549 mac_free(macp); 550 return (DDI_SUCCESS); 551 } 552 553 /* failed to register with MAC */ 554 mac_free(macp); 555 failed: 556 if (afep->afe_icookie != NULL) { 557 ddi_remove_intr(dip, 0, afep->afe_icookie); 558 } 559 if (afep->afe_intrstat) { 560 kstat_delete(afep->afe_intrstat); 561 } 562 afe_ndfini(afep); 563 mutex_destroy(&afep->afe_intrlock); 564 mutex_destroy(&afep->afe_xmtlock); 565 566 afe_freerxring(afep); 567 afe_freetxring(afep); 568 569 if (afep->afe_regshandle != NULL) { 570 ddi_regs_map_free(&afep->afe_regshandle); 571 } 572 kmem_free(afep, sizeof (afe_t)); 573 return (DDI_FAILURE); 574 } 575 576 int 577 afe_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 578 { 579 afe_t *afep; 580 581 afep = ddi_get_driver_private(dip); 582 if (afep == NULL) { 583 afe_error(dip, "no soft state in detach!"); 584 return (DDI_FAILURE); 585 } 586 587 switch (cmd) { 588 case DDI_DETACH: 589 590 if (mac_unregister(afep->afe_mh) != 0) { 591 return (DDI_FAILURE); 592 } 593 594 /* make sure hardware is quiesced */ 595 mutex_enter(&afep->afe_intrlock); 596 mutex_enter(&afep->afe_xmtlock); 597 afep->afe_flags &= ~AFE_RUNNING; 598 afe_stopall(afep); 599 mutex_exit(&afep->afe_xmtlock); 600 mutex_exit(&afep->afe_intrlock); 601 602 /* clean up and shut down device */ 603 ddi_remove_intr(dip, 0, afep->afe_icookie); 604 605 /* clean up kstats */ 606 kstat_delete(afep->afe_intrstat); 607 608 ddi_prop_remove_all(dip); 609 610 /* free up any left over buffers or DMA resources */ 611 afe_freerxring(afep); 612 afe_freetxring(afep); 613 614 afe_ndfini(afep); 615 ddi_regs_map_free(&afep->afe_regshandle); 616 mutex_destroy(&afep->afe_intrlock); 617 mutex_destroy(&afep->afe_xmtlock); 618 619 kmem_free(afep, sizeof (afe_t)); 620 return (DDI_SUCCESS); 621 622 case DDI_SUSPEND: 623 /* quiesce the hardware */ 624 mutex_enter(&afep->afe_intrlock); 625 mutex_enter(&afep->afe_xmtlock); 626 afep->afe_flags |= AFE_SUSPENDED; 627 afe_stopall(afep); 628 mutex_exit(&afep->afe_xmtlock); 629 mutex_exit(&afep->afe_intrlock); 630 return (DDI_SUCCESS); 631 default: 632 return (DDI_FAILURE); 633 } 634 } 635 636 int 637 afe_resume(dev_info_t *dip) 638 { 639 afe_t *afep; 640 641 if ((afep = ddi_get_driver_private(dip)) == NULL) { 642 return (DDI_FAILURE); 643 } 644 645 mutex_enter(&afep->afe_intrlock); 646 mutex_enter(&afep->afe_xmtlock); 647 648 afep->afe_flags &= ~AFE_SUSPENDED; 649 650 /* re-initialize chip */ 651 if (!afe_initialize(afep)) { 652 afe_error(afep->afe_dip, "unable to resume chip!"); 653 afep->afe_flags |= AFE_SUSPENDED; 654 mutex_exit(&afep->afe_intrlock); 655 mutex_exit(&afep->afe_xmtlock); 656 return (DDI_SUCCESS); 657 } 658 659 /* start the chip */ 660 if (afep->afe_flags & AFE_RUNNING) { 661 afe_startall(afep); 662 } 663 664 /* drop locks */ 665 mutex_exit(&afep->afe_xmtlock); 666 mutex_exit(&afep->afe_intrlock); 667 668 return (DDI_SUCCESS); 669 } 670 671 void 672 afe_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 673 { 674 afe_t *afep = arg; 675 676 switch (*(int *)(void *)(mp->b_rptr)) { 677 678 case NDIOC_GET: 679 afe_ndget(afep, wq, mp); 680 break; 681 682 case NDIOC_SET: 683 afe_ndset(afep, wq, mp); 684 break; 685 686 default: 687 miocnak(wq, mp, 0, EINVAL); 688 break; 689 } 690 } 691 692 void 693 afe_setrxfilt(afe_t *afep) 694 { 695 unsigned rxen, pa0, pa1; 696 697 if (afep->afe_flags & AFE_SUSPENDED) { 698 /* don't touch a suspended interface */ 699 return; 700 } 701 702 rxen = GETCSR(afep, CSR_NAR) & NAR_RX_ENABLE; 703 704 /* stop receiver */ 705 if (rxen) { 706 afe_stopmac(afep); 707 } 708 709 /* program promiscuous mode */ 710 if (afep->afe_promisc) 711 SETBIT(afep, CSR_NAR, NAR_RX_PROMISC); 712 else 713 CLRBIT(afep, CSR_NAR, NAR_RX_PROMISC); 714 715 /* program mac address */ 716 pa0 = (afep->afe_curraddr[3] << 24) | (afep->afe_curraddr[2] << 16) | 717 (afep->afe_curraddr[1] << 8) | afep->afe_curraddr[0]; 718 pa1 = (afep->afe_curraddr[5] << 8) | afep->afe_curraddr[4]; 719 720 DBG(DMACID, "programming PAR0 with %x", pa0); 721 DBG(DMACID, "programming PAR1 with %x", pa1); 722 PUTCSR(afep, CSR_PAR0, pa0); 723 PUTCSR(afep, CSR_PAR1, pa1); 724 if (rxen) { 725 SETBIT(afep, CSR_NAR, rxen); 726 } 727 728 DBG(DMACID, "programming MAR0 = %x", afep->afe_mctab[0]); 729 DBG(DMACID, "programming MAR1 = %x", afep->afe_mctab[1]); 730 731 /* program multicast filter */ 732 if (AFE_MODEL(afep) == MODEL_COMET) { 733 if (afep->afe_mctab[0] || afep->afe_mctab[1]) { 734 SETBIT(afep, CSR_NAR, NAR_RX_MULTI); 735 } else { 736 CLRBIT(afep, CSR_NAR, NAR_RX_MULTI); 737 } 738 } else { 739 CLRBIT(afep, CSR_NAR, NAR_RX_MULTI); 740 PUTCSR(afep, CSR_MAR0, afep->afe_mctab[0]); 741 PUTCSR(afep, CSR_MAR1, afep->afe_mctab[1]); 742 } 743 744 /* restart receiver */ 745 if (rxen) { 746 afe_startmac(afep); 747 } 748 } 749 750 int 751 afe_m_multicst(void *arg, boolean_t add, const uint8_t *macaddr) 752 { 753 afe_t *afep = arg; 754 int index; 755 uint32_t crc; 756 uint32_t bit; 757 uint32_t newval, oldval; 758 759 CRC32(crc, macaddr, ETHERADDRL, -1U, crc32_table); 760 crc %= AFE_MCHASH; 761 762 /* bit within a 32-bit word */ 763 index = crc / 32; 764 bit = (1 << (crc % 32)); 765 766 mutex_enter(&afep->afe_intrlock); 767 mutex_enter(&afep->afe_xmtlock); 768 newval = oldval = afep->afe_mctab[index]; 769 770 if (add) { 771 afep->afe_mccount[crc]++; 772 if (afep->afe_mccount[crc] == 1) 773 newval |= bit; 774 } else { 775 afep->afe_mccount[crc]--; 776 if (afep->afe_mccount[crc] == 0) 777 newval &= ~bit; 778 } 779 if (newval != oldval) { 780 afep->afe_mctab[index] = newval; 781 afe_setrxfilt(afep); 782 } 783 784 mutex_exit(&afep->afe_xmtlock); 785 mutex_exit(&afep->afe_intrlock); 786 787 return (0); 788 } 789 790 int 791 afe_m_promisc(void *arg, boolean_t on) 792 { 793 afe_t *afep = arg; 794 795 /* exclusive access to the card while we reprogram it */ 796 mutex_enter(&afep->afe_intrlock); 797 mutex_enter(&afep->afe_xmtlock); 798 /* save current promiscuous mode state for replay in resume */ 799 afep->afe_promisc = on; 800 801 afe_setrxfilt(afep); 802 mutex_exit(&afep->afe_xmtlock); 803 mutex_exit(&afep->afe_intrlock); 804 805 return (0); 806 } 807 808 int 809 afe_m_unicst(void *arg, const uint8_t *macaddr) 810 { 811 afe_t *afep = arg; 812 813 /* exclusive access to the card while we reprogram it */ 814 mutex_enter(&afep->afe_intrlock); 815 mutex_enter(&afep->afe_xmtlock); 816 817 bcopy(macaddr, afep->afe_curraddr, ETHERADDRL); 818 afe_setrxfilt(afep); 819 820 mutex_exit(&afep->afe_xmtlock); 821 mutex_exit(&afep->afe_intrlock); 822 823 return (0); 824 } 825 826 mblk_t * 827 afe_m_tx(void *arg, mblk_t *mp) 828 { 829 afe_t *afep = arg; 830 mblk_t *nmp; 831 832 mutex_enter(&afep->afe_xmtlock); 833 834 if (afep->afe_flags & AFE_SUSPENDED) { 835 while ((nmp = mp) != NULL) { 836 afep->afe_carrier_errors++; 837 mp = mp->b_next; 838 freemsg(nmp); 839 } 840 mutex_exit(&afep->afe_xmtlock); 841 return (NULL); 842 } 843 844 while (mp != NULL) { 845 nmp = mp->b_next; 846 mp->b_next = NULL; 847 848 if (!afe_send(afep, mp)) { 849 mp->b_next = nmp; 850 break; 851 } 852 mp = nmp; 853 } 854 mutex_exit(&afep->afe_xmtlock); 855 856 return (mp); 857 } 858 859 /* 860 * Hardware management. 861 */ 862 static boolean_t 863 afe_initialize(afe_t *afep) 864 { 865 int i; 866 unsigned val; 867 uint32_t par, nar; 868 869 ASSERT(mutex_owned(&afep->afe_intrlock)); 870 ASSERT(mutex_owned(&afep->afe_xmtlock)); 871 872 DBG(DCHATTY, "resetting!"); 873 SETBIT(afep, CSR_PAR, PAR_RESET); 874 for (i = 1; i < 10; i++) { 875 drv_usecwait(5); 876 val = GETCSR(afep, CSR_PAR); 877 if (!(val & PAR_RESET)) { 878 break; 879 } 880 } 881 if (i == 10) { 882 afe_error(afep->afe_dip, "timed out waiting for reset!"); 883 return (B_FALSE); 884 } 885 886 /* 887 * Updated Centaur data sheets show that the Comet and Centaur are 888 * alike here (contrary to earlier versions of the data sheet). 889 */ 890 /* XXX:? chip problems */ 891 /* par = PAR_MRLE | PAR_MRME | PAR_MWIE; */ 892 par = 0; 893 switch (afep->afe_cachesize) { 894 case 8: 895 par |= PAR_CALIGN_8 | PAR_BURST_8; 896 break; 897 case 16: 898 par |= PAR_CALIGN_16 | PAR_BURST_16; 899 break; 900 case 32: 901 par |= PAR_CALIGN_32 | PAR_BURST_32; 902 break; 903 default: 904 par |= PAR_BURST_32; 905 par &= ~(PAR_MWIE | PAR_MRLE | PAR_MRME); 906 break; 907 908 } 909 910 PUTCSR(afep, CSR_PAR, par); 911 912 /* enable transmit underrun auto-recovery */ 913 SETBIT(afep, CSR_CR, CR_TXURAUTOR); 914 915 afe_resetrings(afep); 916 917 /* clear the lost packet counter (cleared on read) */ 918 (void) GETCSR(afep, CSR_LPC); 919 920 nar = GETCSR(afep, CSR_NAR); 921 nar &= ~NAR_TR; /* clear tx threshold */ 922 nar |= NAR_SF; /* store-and-forward */ 923 nar |= NAR_HBD; /* disable SQE test */ 924 PUTCSR(afep, CSR_NAR, nar); 925 926 afe_setrxfilt(afep); 927 928 return (B_TRUE); 929 } 930 931 /* 932 * Serial EEPROM access - inspired by the FreeBSD implementation. 933 */ 934 935 uint8_t 936 afe_sromwidth(afe_t *afep) 937 { 938 int i; 939 uint32_t eeread; 940 uint8_t addrlen = 8; 941 942 eeread = SPR_SROM_READ | SPR_SROM_SEL | SPR_SROM_CHIP; 943 944 PUTCSR(afep, CSR_SPR, eeread & ~SPR_SROM_CHIP); 945 drv_usecwait(1); 946 PUTCSR(afep, CSR_SPR, eeread); 947 948 /* command bits first */ 949 for (i = 4; i != 0; i >>= 1) { 950 unsigned val = (SROM_READCMD & i) ? SPR_SROM_DIN : 0; 951 952 PUTCSR(afep, CSR_SPR, eeread | val); 953 drv_usecwait(1); 954 PUTCSR(afep, CSR_SPR, eeread | val | SPR_SROM_CLOCK); 955 drv_usecwait(1); 956 } 957 958 PUTCSR(afep, CSR_SPR, eeread); 959 960 for (addrlen = 1; addrlen <= 12; addrlen++) { 961 PUTCSR(afep, CSR_SPR, eeread | SPR_SROM_CLOCK); 962 drv_usecwait(1); 963 if (!(GETCSR(afep, CSR_SPR) & SPR_SROM_DOUT)) { 964 PUTCSR(afep, CSR_SPR, eeread); 965 drv_usecwait(1); 966 break; 967 } 968 PUTCSR(afep, CSR_SPR, eeread); 969 drv_usecwait(1); 970 } 971 972 /* turn off accesses to the EEPROM */ 973 PUTCSR(afep, CSR_SPR, eeread &~ SPR_SROM_CHIP); 974 975 DBG(DSROM, "detected srom width = %d bits", addrlen); 976 977 return ((addrlen < 4 || addrlen > 12) ? 6 : addrlen); 978 } 979 980 /* 981 * The words in EEPROM are stored in little endian order. We 982 * shift bits out in big endian order, though. This requires 983 * a byte swap on some platforms. 984 */ 985 uint16_t 986 afe_readsromword(afe_t *afep, unsigned romaddr) 987 { 988 int i; 989 uint16_t word = 0; 990 uint16_t retval; 991 int eeread; 992 uint8_t addrlen; 993 int readcmd; 994 uchar_t *ptr; 995 996 eeread = SPR_SROM_READ | SPR_SROM_SEL | SPR_SROM_CHIP; 997 addrlen = afep->afe_sromwidth; 998 readcmd = (SROM_READCMD << addrlen) | romaddr; 999 1000 if (romaddr >= (1 << addrlen)) { 1001 /* too big to fit! */ 1002 return (0); 1003 } 1004 1005 PUTCSR(afep, CSR_SPR, eeread & ~SPR_SROM_CHIP); 1006 PUTCSR(afep, CSR_SPR, eeread); 1007 1008 /* command and address bits */ 1009 for (i = 4 + addrlen; i >= 0; i--) { 1010 short val = (readcmd & (1 << i)) ? SPR_SROM_DIN : 0; 1011 1012 PUTCSR(afep, CSR_SPR, eeread | val); 1013 drv_usecwait(1); 1014 PUTCSR(afep, CSR_SPR, eeread | val | SPR_SROM_CLOCK); 1015 drv_usecwait(1); 1016 } 1017 1018 PUTCSR(afep, CSR_SPR, eeread); 1019 1020 for (i = 0; i < 16; i++) { 1021 PUTCSR(afep, CSR_SPR, eeread | SPR_SROM_CLOCK); 1022 drv_usecwait(1); 1023 word <<= 1; 1024 if (GETCSR(afep, CSR_SPR) & SPR_SROM_DOUT) { 1025 word |= 1; 1026 } 1027 PUTCSR(afep, CSR_SPR, eeread); 1028 drv_usecwait(1); 1029 } 1030 1031 /* turn off accesses to the EEPROM */ 1032 PUTCSR(afep, CSR_SPR, eeread &~ SPR_SROM_CHIP); 1033 1034 /* 1035 * Fix up the endianness thing. Note that the values 1036 * are stored in little endian format on the SROM. 1037 */ 1038 ptr = (uchar_t *)&word; 1039 retval = (ptr[1] << 8) | ptr[0]; 1040 return (retval); 1041 } 1042 1043 void 1044 afe_readsrom(afe_t *afep, unsigned romaddr, unsigned len, char *dest) 1045 { 1046 int i; 1047 uint16_t word; 1048 uint16_t *ptr = (uint16_t *)((void *)dest); 1049 for (i = 0; i < len; i++) { 1050 word = afe_readsromword(afep, romaddr + i); 1051 *ptr = word; 1052 ptr++; 1053 } 1054 } 1055 1056 void 1057 afe_getfactaddr(afe_t *afep, uchar_t *eaddr) 1058 { 1059 afe_readsrom(afep, SROM_ENADDR, ETHERADDRL / 2, (char *)eaddr); 1060 1061 DBG(DMACID, 1062 "factory ethernet address = %02x:%02x:%02x:%02x:%02x:%02x", 1063 eaddr[0], eaddr[1], eaddr[2], eaddr[3], eaddr[4], eaddr[5]); 1064 } 1065 1066 /* 1067 * MII management. 1068 */ 1069 void 1070 afe_startphy(afe_t *afep) 1071 { 1072 unsigned phyaddr; 1073 unsigned bmcr; 1074 unsigned bmsr; 1075 unsigned anar; 1076 unsigned phyidr1; 1077 unsigned phyidr2; 1078 unsigned nosqe = 0; 1079 int retries; 1080 int force; 1081 int fiber; 1082 int cnt; 1083 1084 /* ADMtek devices just use the PHY at address 1 */ 1085 afep->afe_phyaddr = phyaddr = 1; 1086 1087 phyidr1 = afe_miiread(afep, phyaddr, MII_PHYIDH); 1088 phyidr2 = afe_miiread(afep, phyaddr, MII_PHYIDL); 1089 if ((phyidr1 == 0x0022) && 1090 ((phyidr2 & 0xfff0) == 0x5410)) { 1091 nosqe = 1; 1092 /* only 983B has fiber support */ 1093 afep->afe_flags |= AFE_HASFIBER; 1094 } 1095 afep->afe_phyid = (phyidr1 << 16) | phyidr2; 1096 1097 DBG(DPHY, "phy at %d: %x,%x", phyaddr, phyidr1, phyidr2); 1098 DBG(DPHY, "bmsr = %x", afe_miiread(afep, 1099 afep->afe_phyaddr, MII_STATUS)); 1100 DBG(DPHY, "anar = %x", afe_miiread(afep, 1101 afep->afe_phyaddr, MII_AN_ADVERT)); 1102 DBG(DPHY, "anlpar = %x", afe_miiread(afep, 1103 afep->afe_phyaddr, MII_AN_LPABLE)); 1104 DBG(DPHY, "aner = %x", afe_miiread(afep, 1105 afep->afe_phyaddr, MII_AN_EXPANSION)); 1106 1107 DBG(DPHY, "resetting phy"); 1108 1109 /* we reset the phy block */ 1110 afe_miiwrite(afep, phyaddr, MII_CONTROL, MII_CONTROL_RESET); 1111 /* 1112 * wait for it to complete -- 500usec is still to short to 1113 * bother getting the system clock involved. 1114 */ 1115 drv_usecwait(500); 1116 for (retries = 0; retries < 10; retries++) { 1117 if (afe_miiread(afep, phyaddr, MII_CONTROL) & 1118 MII_CONTROL_RESET) { 1119 drv_usecwait(500); 1120 continue; 1121 } 1122 break; 1123 } 1124 if (retries == 100) { 1125 afe_error(afep->afe_dip, "timeout waiting on phy to reset"); 1126 return; 1127 } 1128 1129 DBG(DPHY, "phy reset complete"); 1130 1131 bmsr = afe_miiread(afep, phyaddr, MII_STATUS); 1132 anar = afe_miiread(afep, phyaddr, MII_AN_ADVERT); 1133 1134 anar &= ~(MII_ABILITY_100BASE_T4 | 1135 MII_ABILITY_100BASE_TX_FD | MII_ABILITY_100BASE_TX | 1136 MII_ABILITY_10BASE_T_FD | MII_ABILITY_10BASE_T); 1137 1138 force = 0; 1139 fiber = 0; 1140 1141 /* if fiber is being forced, and device supports fiber... */ 1142 if (afep->afe_flags & AFE_HASFIBER) { 1143 1144 uint16_t mcr; 1145 1146 DBG(DPHY, "device supports 100BaseFX"); 1147 mcr = afe_miiread(afep, phyaddr, PHY_MCR); 1148 switch (afep->afe_forcefiber) { 1149 case 0: 1150 /* UTP Port */ 1151 DBG(DPHY, "forcing twpair"); 1152 mcr &= ~MCR_FIBER; 1153 fiber = 0; 1154 break; 1155 case 1: 1156 /* Fiber Port */ 1157 force = 1; 1158 DBG(DPHY, "forcing 100BaseFX"); 1159 mcr |= MCR_FIBER; 1160 bmcr = (MII_CONTROL_100MB | MII_CONTROL_FDUPLEX); 1161 fiber = 1; 1162 break; 1163 default: 1164 DBG(DPHY, "checking for 100BaseFX link"); 1165 /* fiber is 100 Mb FDX */ 1166 afe_miiwrite(afep, phyaddr, MII_CONTROL, 1167 MII_CONTROL_100MB | MII_CONTROL_FDUPLEX); 1168 drv_usecwait(50); 1169 1170 mcr = afe_miiread(afep, phyaddr, PHY_MCR); 1171 mcr |= MCR_FIBER; 1172 afe_miiwrite(afep, phyaddr, PHY_MCR, mcr); 1173 drv_usecwait(500); 1174 1175 /* if fiber is active, use it */ 1176 if ((afe_miiread(afep, phyaddr, MII_STATUS) & 1177 MII_STATUS_LINKUP)) { 1178 bmcr = MII_CONTROL_100MB | MII_CONTROL_FDUPLEX; 1179 fiber = 1; 1180 } else { 1181 mcr &= ~MCR_FIBER; 1182 fiber = 0; 1183 } 1184 break; 1185 } 1186 afe_miiwrite(afep, phyaddr, PHY_MCR, mcr); 1187 drv_usecwait(500); 1188 } 1189 1190 if (fiber) { 1191 /* fiber only supports 100FDX(?) */ 1192 bmsr &= ~(MII_STATUS_100_BASE_T4 | 1193 MII_STATUS_100_BASEX | MII_STATUS_10_FD | MII_STATUS_10); 1194 bmsr |= MII_STATUS_100_BASEX_FD; 1195 } 1196 1197 /* disable modes not supported in hardware */ 1198 if (!(bmsr & MII_STATUS_100_BASEX_FD)) { 1199 afep->afe_adv_100fdx = 0; 1200 } 1201 if (!(bmsr & MII_STATUS_100_BASE_T4)) { 1202 afep->afe_adv_100T4 = 0; 1203 } 1204 if (!(bmsr & MII_STATUS_100_BASEX)) { 1205 afep->afe_adv_100hdx = 0; 1206 } 1207 if (!(bmsr & MII_STATUS_10_FD)) { 1208 afep->afe_adv_10fdx = 0; 1209 } 1210 if (!(bmsr & MII_STATUS_10)) { 1211 afep->afe_adv_10hdx = 0; 1212 } 1213 if (!(bmsr & MII_STATUS_CANAUTONEG)) { 1214 afep->afe_adv_aneg = 0; 1215 force = 1; 1216 } 1217 1218 cnt = 0; 1219 if (afep->afe_adv_100fdx) { 1220 anar |= MII_ABILITY_100BASE_TX_FD; 1221 cnt++; 1222 } 1223 if (afep->afe_adv_100T4) { 1224 anar |= MII_ABILITY_100BASE_T4; 1225 cnt++; 1226 } 1227 if (afep->afe_adv_100hdx) { 1228 anar |= MII_ABILITY_100BASE_TX; 1229 cnt++; 1230 } 1231 if (afep->afe_adv_10fdx) { 1232 anar |= MII_ABILITY_10BASE_T_FD; 1233 cnt++; 1234 } 1235 if (afep->afe_adv_10hdx) { 1236 anar |= MII_ABILITY_10BASE_T; 1237 cnt++; 1238 } 1239 1240 /* 1241 * Make certain at least one valid link mode is selected. 1242 */ 1243 if (!cnt) { 1244 afe_error(afep->afe_dip, "No valid link mode selected."); 1245 afe_error(afep->afe_dip, "Powering down PHY."); 1246 afe_stopphy(afep); 1247 afep->afe_linkup = LINK_STATE_DOWN; 1248 if (afep->afe_flags & AFE_RUNNING) 1249 afe_reportlink(afep); 1250 return; 1251 } 1252 1253 if (fiber) { 1254 bmcr = MII_CONTROL_100MB | MII_CONTROL_FDUPLEX; 1255 } else if ((afep->afe_adv_aneg) && (bmsr & MII_STATUS_CANAUTONEG)) { 1256 DBG(DPHY, "using autoneg mode"); 1257 bmcr = (MII_CONTROL_ANE | MII_CONTROL_RSAN); 1258 } else { 1259 DBG(DPHY, "using forced mode"); 1260 force = 1; 1261 if (afep->afe_adv_100fdx) { 1262 bmcr = (MII_CONTROL_100MB | MII_CONTROL_FDUPLEX); 1263 } else if (afep->afe_adv_100hdx) { 1264 bmcr = MII_CONTROL_100MB; 1265 } else if (afep->afe_adv_10fdx) { 1266 bmcr = MII_CONTROL_FDUPLEX; 1267 } else { 1268 /* 10HDX */ 1269 bmcr = 0; 1270 } 1271 } 1272 1273 afep->afe_forcephy = force; 1274 1275 DBG(DPHY, "programming anar to 0x%x", anar); 1276 afe_miiwrite(afep, phyaddr, MII_AN_ADVERT, anar); 1277 DBG(DPHY, "programming bmcr to 0x%x", bmcr); 1278 afe_miiwrite(afep, phyaddr, MII_CONTROL, bmcr); 1279 1280 if (nosqe) { 1281 uint16_t pilr; 1282 /* 1283 * work around for errata 983B_0416 -- duplex light flashes 1284 * in 10 HDX. we just disable SQE testing on the device. 1285 */ 1286 pilr = afe_miiread(afep, phyaddr, PHY_PILR); 1287 pilr |= PILR_NOSQE; 1288 afe_miiwrite(afep, phyaddr, PHY_PILR, pilr); 1289 } 1290 1291 /* 1292 * schedule a query of the link status 1293 */ 1294 PUTCSR(afep, CSR_TIMER, TIMER_LOOP | 1295 (AFE_LINKTIMER * 1000 / TIMER_USEC)); 1296 } 1297 1298 void 1299 afe_stopphy(afe_t *afep) 1300 { 1301 /* stop the phy timer */ 1302 PUTCSR(afep, CSR_TIMER, 0); 1303 1304 /* 1305 * phy in isolate & powerdown mode... 1306 */ 1307 afe_miiwrite(afep, afep->afe_phyaddr, MII_CONTROL, 1308 MII_CONTROL_PWRDN | MII_CONTROL_ISOLATE); 1309 1310 /* 1311 * mark the link state unknown 1312 */ 1313 if (!afep->afe_resetting) { 1314 afep->afe_linkup = LINK_STATE_UNKNOWN; 1315 afep->afe_ifspeed = 0; 1316 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1317 if (afep->afe_flags & AFE_RUNNING) 1318 afe_reportlink(afep); 1319 } 1320 } 1321 1322 void 1323 afe_reportlink(afe_t *afep) 1324 { 1325 int changed = 0; 1326 1327 if (afep->afe_ifspeed != afep->afe_lastifspeed) { 1328 afep->afe_lastifspeed = afep->afe_ifspeed; 1329 changed++; 1330 } 1331 if (afep->afe_duplex != afep->afe_lastduplex) { 1332 afep->afe_lastduplex = afep->afe_duplex; 1333 changed++; 1334 } 1335 if (changed) 1336 mac_link_update(afep->afe_mh, afep->afe_linkup); 1337 } 1338 1339 void 1340 afe_checklink(afe_t *afep) 1341 { 1342 if ((afep->afe_flags & AFE_RUNNING) == 0) 1343 return; 1344 1345 if ((afep->afe_txstall_time != 0) && 1346 (gethrtime() > afep->afe_txstall_time) && 1347 (afep->afe_txavail != AFE_TXRING)) { 1348 afep->afe_txstall_time = 0; 1349 afe_error(afep->afe_dip, "TX stall detected!"); 1350 afe_resetall(afep); 1351 return; 1352 } 1353 1354 switch (AFE_MODEL(afep)) { 1355 case MODEL_COMET: 1356 afe_checklinkcomet(afep); 1357 break; 1358 case MODEL_CENTAUR: 1359 afe_checklinkcentaur(afep); 1360 break; 1361 } 1362 } 1363 1364 void 1365 afe_checklinkcomet(afe_t *afep) 1366 { 1367 uint16_t xciis; 1368 int reinit = 0; 1369 1370 xciis = GETCSR16(afep, CSR_XCIIS); 1371 if (xciis & XCIIS_PDF) { 1372 afe_error(afep->afe_dip, "Parallel detection fault detected!"); 1373 } 1374 if (xciis & XCIIS_RF) { 1375 afe_error(afep->afe_dip, "Remote fault detected."); 1376 } 1377 if (xciis & XCIIS_LFAIL) { 1378 if (afep->afe_linkup == LINK_STATE_UP) { 1379 reinit++; 1380 } 1381 afep->afe_ifspeed = 0; 1382 afep->afe_linkup = LINK_STATE_DOWN; 1383 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1384 afe_reportlink(afep); 1385 if (reinit) { 1386 afe_startphy(afep); 1387 } 1388 return; 1389 } 1390 1391 afep->afe_linkup = LINK_STATE_UP; 1392 afep->afe_ifspeed = (xciis & XCIIS_SPEED) ? 100000000 : 10000000; 1393 if (xciis & XCIIS_DUPLEX) { 1394 afep->afe_duplex = LINK_DUPLEX_FULL; 1395 } else { 1396 afep->afe_duplex = LINK_DUPLEX_HALF; 1397 } 1398 1399 afe_reportlink(afep); 1400 } 1401 1402 void 1403 afe_checklinkcentaur(afe_t *afep) 1404 { 1405 unsigned opmode; 1406 int reinit = 0; 1407 1408 opmode = GETCSR(afep, CSR_OPM); 1409 if ((opmode & OPM_MODE) == OPM_MACONLY) { 1410 DBG(DPHY, "Centaur running in MAC-only mode"); 1411 afe_checklinkmii(afep); 1412 return; 1413 } 1414 DBG(DPHY, "Centaur running in single chip mode"); 1415 if ((opmode & OPM_LINK) == 0) { 1416 if (afep->afe_linkup == LINK_STATE_UP) { 1417 reinit++; 1418 } 1419 afep->afe_ifspeed = 0; 1420 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1421 afep->afe_linkup = LINK_STATE_DOWN; 1422 afe_reportlink(afep); 1423 if (reinit) { 1424 afe_startphy(afep); 1425 } 1426 return; 1427 } 1428 1429 afep->afe_linkup = LINK_STATE_UP; 1430 afep->afe_ifspeed = (opmode & OPM_SPEED) ? 100000000 : 10000000; 1431 if (opmode & OPM_DUPLEX) { 1432 afep->afe_duplex = LINK_DUPLEX_FULL; 1433 } else { 1434 afep->afe_duplex = LINK_DUPLEX_HALF; 1435 } 1436 afe_reportlink(afep); 1437 } 1438 1439 void 1440 afe_checklinkmii(afe_t *afep) 1441 { 1442 /* read MII state registers */ 1443 uint16_t bmsr; 1444 uint16_t bmcr; 1445 uint16_t anar; 1446 uint16_t anlpar; 1447 int reinit = 0; 1448 1449 /* read this twice, to clear latched link state */ 1450 bmsr = afe_miiread(afep, afep->afe_phyaddr, MII_STATUS); 1451 bmsr = afe_miiread(afep, afep->afe_phyaddr, MII_STATUS); 1452 bmcr = afe_miiread(afep, afep->afe_phyaddr, MII_CONTROL); 1453 anar = afe_miiread(afep, afep->afe_phyaddr, MII_AN_ADVERT); 1454 anlpar = afe_miiread(afep, afep->afe_phyaddr, MII_AN_LPABLE); 1455 1456 if (bmsr & MII_STATUS_REMFAULT) { 1457 afe_error(afep->afe_dip, "Remote fault detected."); 1458 } 1459 if (bmsr & MII_STATUS_JABBERING) { 1460 afe_error(afep->afe_dip, "Jabber condition detected."); 1461 } 1462 if ((bmsr & MII_STATUS_LINKUP) == 0) { 1463 /* no link */ 1464 if (afep->afe_linkup) { 1465 reinit = 1; 1466 } 1467 afep->afe_ifspeed = 0; 1468 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1469 afep->afe_linkup = LINK_STATE_DOWN; 1470 afe_reportlink(afep); 1471 if (reinit) { 1472 afe_startphy(afep); 1473 } 1474 return; 1475 } 1476 1477 DBG(DCHATTY, "link up!"); 1478 afep->afe_linkup = LINK_STATE_UP; 1479 1480 if (!(bmcr & MII_CONTROL_ANE)) { 1481 /* forced mode */ 1482 if (bmcr & MII_CONTROL_100MB) { 1483 afep->afe_ifspeed = 100000000; 1484 } else { 1485 afep->afe_ifspeed = 10000000; 1486 } 1487 if (bmcr & MII_CONTROL_FDUPLEX) { 1488 afep->afe_duplex = LINK_DUPLEX_FULL; 1489 } else { 1490 afep->afe_duplex = LINK_DUPLEX_HALF; 1491 } 1492 } else if ((!(bmsr & MII_STATUS_CANAUTONEG)) || 1493 (!(bmsr & MII_STATUS_ANDONE))) { 1494 afep->afe_ifspeed = 0; 1495 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1496 } else if (anar & anlpar & MII_ABILITY_100BASE_TX_FD) { 1497 afep->afe_ifspeed = 100000000; 1498 afep->afe_duplex = LINK_DUPLEX_FULL; 1499 } else if (anar & anlpar & MII_ABILITY_100BASE_T4) { 1500 afep->afe_ifspeed = 100000000; 1501 afep->afe_duplex = LINK_DUPLEX_HALF; 1502 } else if (anar & anlpar & MII_ABILITY_100BASE_TX) { 1503 afep->afe_ifspeed = 100000000; 1504 afep->afe_duplex = LINK_DUPLEX_HALF; 1505 } else if (anar & anlpar & MII_ABILITY_10BASE_T_FD) { 1506 afep->afe_ifspeed = 10000000; 1507 afep->afe_duplex = LINK_DUPLEX_FULL; 1508 } else if (anar & anlpar & MII_ABILITY_10BASE_T) { 1509 afep->afe_ifspeed = 10000000; 1510 afep->afe_duplex = LINK_DUPLEX_HALF; 1511 } else { 1512 afep->afe_ifspeed = 0; 1513 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1514 } 1515 1516 afe_reportlink(afep); 1517 } 1518 1519 void 1520 afe_miitristate(afe_t *afep) 1521 { 1522 unsigned val = SPR_SROM_WRITE | SPR_MII_CTRL; 1523 PUTCSR(afep, CSR_SPR, val); 1524 drv_usecwait(1); 1525 PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK); 1526 drv_usecwait(1); 1527 } 1528 1529 void 1530 afe_miiwritebit(afe_t *afep, int bit) 1531 { 1532 unsigned val = bit ? SPR_MII_DOUT : 0; 1533 PUTCSR(afep, CSR_SPR, val); 1534 drv_usecwait(1); 1535 PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK); 1536 drv_usecwait(1); 1537 } 1538 1539 int 1540 afe_miireadbit(afe_t *afep) 1541 { 1542 unsigned val = SPR_MII_CTRL | SPR_SROM_READ; 1543 int bit; 1544 PUTCSR(afep, CSR_SPR, val); 1545 drv_usecwait(1); 1546 bit = (GETCSR(afep, CSR_SPR) & SPR_MII_DIN) ? 1 : 0; 1547 PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK); 1548 drv_usecwait(1); 1549 return (bit); 1550 } 1551 1552 unsigned 1553 afe_miiread(afe_t *afep, int phy, int reg) 1554 { 1555 /* 1556 * ADMtek bugs ignore address decode bits -- they only 1557 * support PHY at 1. 1558 */ 1559 if (phy != 1) { 1560 return (0xffff); 1561 } 1562 switch (AFE_MODEL(afep)) { 1563 case MODEL_COMET: 1564 return (afe_miireadcomet(afep, phy, reg)); 1565 case MODEL_CENTAUR: 1566 return (afe_miireadgeneral(afep, phy, reg)); 1567 } 1568 return (0xffff); 1569 } 1570 1571 unsigned 1572 afe_miireadgeneral(afe_t *afep, int phy, int reg) 1573 { 1574 unsigned value = 0; 1575 int i; 1576 1577 /* send the 32 bit preamble */ 1578 for (i = 0; i < 32; i++) { 1579 afe_miiwritebit(afep, 1); 1580 } 1581 1582 /* send the start code - 01b */ 1583 afe_miiwritebit(afep, 0); 1584 afe_miiwritebit(afep, 1); 1585 1586 /* send the opcode for read, - 10b */ 1587 afe_miiwritebit(afep, 1); 1588 afe_miiwritebit(afep, 0); 1589 1590 /* next we send the 5 bit phy address */ 1591 for (i = 0x10; i > 0; i >>= 1) { 1592 afe_miiwritebit(afep, (phy & i) ? 1 : 0); 1593 } 1594 1595 /* the 5 bit register address goes next */ 1596 for (i = 0x10; i > 0; i >>= 1) { 1597 afe_miiwritebit(afep, (reg & i) ? 1 : 0); 1598 } 1599 1600 /* turnaround - tristate followed by logic 0 */ 1601 afe_miitristate(afep); 1602 afe_miiwritebit(afep, 0); 1603 1604 /* read the 16 bit register value */ 1605 for (i = 0x8000; i > 0; i >>= 1) { 1606 value <<= 1; 1607 value |= afe_miireadbit(afep); 1608 } 1609 afe_miitristate(afep); 1610 return (value); 1611 } 1612 1613 unsigned 1614 afe_miireadcomet(afe_t *afep, int phy, int reg) 1615 { 1616 if (phy != 1) { 1617 return (0xffff); 1618 } 1619 switch (reg) { 1620 case MII_CONTROL: 1621 reg = CSR_BMCR; 1622 break; 1623 case MII_STATUS: 1624 reg = CSR_BMSR; 1625 break; 1626 case MII_PHYIDH: 1627 reg = CSR_PHYIDR1; 1628 break; 1629 case MII_PHYIDL: 1630 reg = CSR_PHYIDR2; 1631 break; 1632 case MII_AN_ADVERT: 1633 reg = CSR_ANAR; 1634 break; 1635 case MII_AN_LPABLE: 1636 reg = CSR_ANLPAR; 1637 break; 1638 case MII_AN_EXPANSION: 1639 reg = CSR_ANER; 1640 break; 1641 default: 1642 return (0); 1643 } 1644 return (GETCSR16(afep, reg) & 0xFFFF); 1645 } 1646 1647 void 1648 afe_miiwrite(afe_t *afep, int phy, int reg, uint16_t val) 1649 { 1650 /* 1651 * ADMtek bugs ignore address decode bits -- they only 1652 * support PHY at 1. 1653 */ 1654 if (phy != 1) { 1655 return; 1656 } 1657 switch (AFE_MODEL(afep)) { 1658 case MODEL_COMET: 1659 afe_miiwritecomet(afep, phy, reg, val); 1660 break; 1661 case MODEL_CENTAUR: 1662 afe_miiwritegeneral(afep, phy, reg, val); 1663 break; 1664 } 1665 } 1666 1667 void 1668 afe_miiwritegeneral(afe_t *afep, int phy, int reg, uint16_t val) 1669 { 1670 int i; 1671 1672 /* send the 32 bit preamble */ 1673 for (i = 0; i < 32; i++) { 1674 afe_miiwritebit(afep, 1); 1675 } 1676 1677 /* send the start code - 01b */ 1678 afe_miiwritebit(afep, 0); 1679 afe_miiwritebit(afep, 1); 1680 1681 /* send the opcode for write, - 01b */ 1682 afe_miiwritebit(afep, 0); 1683 afe_miiwritebit(afep, 1); 1684 1685 /* next we send the 5 bit phy address */ 1686 for (i = 0x10; i > 0; i >>= 1) { 1687 afe_miiwritebit(afep, (phy & i) ? 1 : 0); 1688 } 1689 1690 /* the 5 bit register address goes next */ 1691 for (i = 0x10; i > 0; i >>= 1) { 1692 afe_miiwritebit(afep, (reg & i) ? 1 : 0); 1693 } 1694 1695 /* turnaround - tristate followed by logic 0 */ 1696 afe_miitristate(afep); 1697 afe_miiwritebit(afep, 0); 1698 1699 /* now write out our data (16 bits) */ 1700 for (i = 0x8000; i > 0; i >>= 1) { 1701 afe_miiwritebit(afep, (val & i) ? 1 : 0); 1702 } 1703 1704 /* idle mode */ 1705 afe_miitristate(afep); 1706 } 1707 1708 void 1709 afe_miiwritecomet(afe_t *afep, int phy, int reg, uint16_t val) 1710 { 1711 if (phy != 1) { 1712 return; 1713 } 1714 switch (reg) { 1715 case MII_CONTROL: 1716 reg = CSR_BMCR; 1717 break; 1718 case MII_STATUS: 1719 reg = CSR_BMSR; 1720 break; 1721 case MII_PHYIDH: 1722 reg = CSR_PHYIDR1; 1723 break; 1724 case MII_PHYIDL: 1725 reg = CSR_PHYIDR2; 1726 break; 1727 case MII_AN_ADVERT: 1728 reg = CSR_ANAR; 1729 break; 1730 case MII_AN_LPABLE: 1731 reg = CSR_ANLPAR; 1732 break; 1733 case MII_AN_EXPANSION: 1734 reg = CSR_ANER; 1735 break; 1736 default: 1737 return; 1738 } 1739 PUTCSR16(afep, reg, val); 1740 } 1741 1742 int 1743 afe_m_start(void *arg) 1744 { 1745 afe_t *afep = arg; 1746 1747 /* grab exclusive access to the card */ 1748 mutex_enter(&afep->afe_intrlock); 1749 mutex_enter(&afep->afe_xmtlock); 1750 1751 afe_startall(afep); 1752 afep->afe_flags |= AFE_RUNNING; 1753 1754 mutex_exit(&afep->afe_xmtlock); 1755 mutex_exit(&afep->afe_intrlock); 1756 return (0); 1757 } 1758 1759 void 1760 afe_m_stop(void *arg) 1761 { 1762 afe_t *afep = arg; 1763 1764 /* exclusive access to the hardware! */ 1765 mutex_enter(&afep->afe_intrlock); 1766 mutex_enter(&afep->afe_xmtlock); 1767 1768 afe_stopall(afep); 1769 afep->afe_flags &= ~AFE_RUNNING; 1770 1771 mutex_exit(&afep->afe_xmtlock); 1772 mutex_exit(&afep->afe_intrlock); 1773 } 1774 1775 void 1776 afe_startmac(afe_t *afep) 1777 { 1778 /* verify exclusive access to the card */ 1779 ASSERT(mutex_owned(&afep->afe_intrlock)); 1780 ASSERT(mutex_owned(&afep->afe_xmtlock)); 1781 1782 /* start the card */ 1783 SETBIT(afep, CSR_NAR, NAR_TX_ENABLE | NAR_RX_ENABLE); 1784 1785 if (afep->afe_txavail != AFE_TXRING) 1786 PUTCSR(afep, CSR_TDR, 0); 1787 1788 /* tell the mac that we are ready to go! */ 1789 if (afep->afe_flags & AFE_RUNNING) 1790 mac_tx_update(afep->afe_mh); 1791 } 1792 1793 void 1794 afe_stopmac(afe_t *afep) 1795 { 1796 int i; 1797 1798 /* exclusive access to the hardware! */ 1799 ASSERT(mutex_owned(&afep->afe_intrlock)); 1800 ASSERT(mutex_owned(&afep->afe_xmtlock)); 1801 1802 CLRBIT(afep, CSR_NAR, NAR_TX_ENABLE | NAR_RX_ENABLE); 1803 1804 /* 1805 * A 1518 byte frame at 10Mbps takes about 1.2 msec to drain. 1806 * We just add up to the nearest msec (2), which should be 1807 * plenty to complete. 1808 * 1809 * Note that some chips never seem to indicate the transition to 1810 * the stopped state properly. Experience shows that we can safely 1811 * proceed anyway, after waiting the requisite timeout. 1812 */ 1813 for (i = 2000; i != 0; i -= 10) { 1814 if ((GETCSR(afep, CSR_SR) & (SR_TX_STATE | SR_RX_STATE)) == 0) 1815 break; 1816 drv_usecwait(10); 1817 } 1818 1819 /* prevent an interrupt */ 1820 PUTCSR(afep, CSR_SR2, INT_RXSTOPPED | INT_TXSTOPPED); 1821 } 1822 1823 void 1824 afe_resetrings(afe_t *afep) 1825 { 1826 int i; 1827 1828 /* now we need to reset the pointers... */ 1829 PUTCSR(afep, CSR_RDB, 0); 1830 PUTCSR(afep, CSR_TDB, 0); 1831 1832 /* reset the descriptor ring pointers */ 1833 afep->afe_rxhead = 0; 1834 afep->afe_txreclaim = 0; 1835 afep->afe_txsend = 0; 1836 afep->afe_txavail = AFE_TXRING; 1837 1838 /* set up transmit descriptor ring */ 1839 for (i = 0; i < AFE_TXRING; i++) { 1840 afe_desc_t *tmdp = &afep->afe_txdescp[i]; 1841 unsigned control = 0; 1842 if (i == (AFE_TXRING - 1)) { 1843 control |= TXCTL_ENDRING; 1844 } 1845 PUTTXDESC(afep, tmdp->desc_status, 0); 1846 PUTTXDESC(afep, tmdp->desc_control, control); 1847 PUTTXDESC(afep, tmdp->desc_buffer1, 0); 1848 PUTTXDESC(afep, tmdp->desc_buffer2, 0); 1849 SYNCTXDESC(afep, i, DDI_DMA_SYNC_FORDEV); 1850 } 1851 PUTCSR(afep, CSR_TDB, afep->afe_txdesc_paddr); 1852 1853 /* make the receive buffers available */ 1854 for (i = 0; i < AFE_RXRING; i++) { 1855 afe_rxbuf_t *rxb = afep->afe_rxbufs[i]; 1856 afe_desc_t *rmdp = &afep->afe_rxdescp[i]; 1857 unsigned control; 1858 1859 control = AFE_BUFSZ & RXCTL_BUFLEN1; 1860 if (i == (AFE_RXRING - 1)) { 1861 control |= RXCTL_ENDRING; 1862 } 1863 PUTRXDESC(afep, rmdp->desc_buffer1, rxb->rxb_paddr); 1864 PUTRXDESC(afep, rmdp->desc_buffer2, 0); 1865 PUTRXDESC(afep, rmdp->desc_control, control); 1866 PUTRXDESC(afep, rmdp->desc_status, RXSTAT_OWN); 1867 SYNCRXDESC(afep, i, DDI_DMA_SYNC_FORDEV); 1868 } 1869 PUTCSR(afep, CSR_RDB, afep->afe_rxdesc_paddr); 1870 } 1871 1872 void 1873 afe_stopall(afe_t *afep) 1874 { 1875 afe_disableinterrupts(afep); 1876 1877 afe_stopmac(afep); 1878 1879 /* stop the phy */ 1880 afe_stopphy(afep); 1881 } 1882 1883 void 1884 afe_startall(afe_t *afep) 1885 { 1886 ASSERT(mutex_owned(&afep->afe_intrlock)); 1887 ASSERT(mutex_owned(&afep->afe_xmtlock)); 1888 1889 /* make sure interrupts are disabled to begin */ 1890 afe_disableinterrupts(afep); 1891 1892 /* initialize the chip */ 1893 (void) afe_initialize(afep); 1894 1895 /* now we can enable interrupts */ 1896 afe_enableinterrupts(afep); 1897 1898 /* start up the phy */ 1899 afe_startphy(afep); 1900 1901 /* start up the mac */ 1902 afe_startmac(afep); 1903 } 1904 1905 void 1906 afe_resetall(afe_t *afep) 1907 { 1908 afep->afe_resetting = B_TRUE; 1909 afe_stopall(afep); 1910 afep->afe_resetting = B_FALSE; 1911 afe_startall(afep); 1912 } 1913 1914 afe_txbuf_t * 1915 afe_alloctxbuf(afe_t *afep) 1916 { 1917 ddi_dma_cookie_t dmac; 1918 unsigned ncookies; 1919 afe_txbuf_t *txb; 1920 size_t len; 1921 1922 txb = kmem_zalloc(sizeof (*txb), KM_SLEEP); 1923 1924 if (ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_txattr, 1925 DDI_DMA_SLEEP, NULL, &txb->txb_dmah) != DDI_SUCCESS) { 1926 return (NULL); 1927 } 1928 1929 if (ddi_dma_mem_alloc(txb->txb_dmah, AFE_BUFSZ, &afe_bufattr, 1930 DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, &txb->txb_buf, &len, 1931 &txb->txb_acch) != DDI_SUCCESS) { 1932 return (NULL); 1933 } 1934 if (ddi_dma_addr_bind_handle(txb->txb_dmah, NULL, txb->txb_buf, 1935 len, DDI_DMA_WRITE | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, 1936 &dmac, &ncookies) != DDI_DMA_MAPPED) { 1937 return (NULL); 1938 } 1939 txb->txb_paddr = dmac.dmac_address; 1940 1941 return (txb); 1942 } 1943 1944 void 1945 afe_destroytxbuf(afe_txbuf_t *txb) 1946 { 1947 if (txb != NULL) { 1948 if (txb->txb_paddr) 1949 (void) ddi_dma_unbind_handle(txb->txb_dmah); 1950 if (txb->txb_acch) 1951 ddi_dma_mem_free(&txb->txb_acch); 1952 if (txb->txb_dmah) 1953 ddi_dma_free_handle(&txb->txb_dmah); 1954 kmem_free(txb, sizeof (*txb)); 1955 } 1956 } 1957 1958 afe_rxbuf_t * 1959 afe_allocrxbuf(afe_t *afep) 1960 { 1961 afe_rxbuf_t *rxb; 1962 size_t len; 1963 unsigned ccnt; 1964 ddi_dma_cookie_t dmac; 1965 1966 rxb = kmem_zalloc(sizeof (*rxb), KM_SLEEP); 1967 1968 if (ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_attr, 1969 DDI_DMA_SLEEP, NULL, &rxb->rxb_dmah) != DDI_SUCCESS) { 1970 kmem_free(rxb, sizeof (*rxb)); 1971 return (NULL); 1972 } 1973 if (ddi_dma_mem_alloc(rxb->rxb_dmah, AFE_BUFSZ, &afe_bufattr, 1974 DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, &rxb->rxb_buf, &len, 1975 &rxb->rxb_acch) != DDI_SUCCESS) { 1976 ddi_dma_free_handle(&rxb->rxb_dmah); 1977 kmem_free(rxb, sizeof (*rxb)); 1978 return (NULL); 1979 } 1980 if (ddi_dma_addr_bind_handle(rxb->rxb_dmah, NULL, rxb->rxb_buf, len, 1981 DDI_DMA_READ | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, &dmac, 1982 &ccnt) != DDI_DMA_MAPPED) { 1983 ddi_dma_mem_free(&rxb->rxb_acch); 1984 ddi_dma_free_handle(&rxb->rxb_dmah); 1985 kmem_free(rxb, sizeof (*rxb)); 1986 return (NULL); 1987 } 1988 rxb->rxb_paddr = dmac.dmac_address; 1989 1990 return (rxb); 1991 } 1992 1993 void 1994 afe_destroyrxbuf(afe_rxbuf_t *rxb) 1995 { 1996 if (rxb) { 1997 (void) ddi_dma_unbind_handle(rxb->rxb_dmah); 1998 ddi_dma_mem_free(&rxb->rxb_acch); 1999 ddi_dma_free_handle(&rxb->rxb_dmah); 2000 kmem_free(rxb, sizeof (*rxb)); 2001 } 2002 } 2003 2004 /* 2005 * Allocate receive resources. 2006 */ 2007 int 2008 afe_allocrxring(afe_t *afep) 2009 { 2010 int rval; 2011 int i; 2012 size_t size; 2013 size_t len; 2014 ddi_dma_cookie_t dmac; 2015 unsigned ncookies; 2016 caddr_t kaddr; 2017 2018 size = AFE_RXRING * sizeof (afe_desc_t); 2019 2020 rval = ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_attr, 2021 DDI_DMA_SLEEP, NULL, &afep->afe_rxdesc_dmah); 2022 if (rval != DDI_SUCCESS) { 2023 afe_error(afep->afe_dip, 2024 "unable to allocate DMA handle for rx descriptors"); 2025 return (DDI_FAILURE); 2026 } 2027 2028 rval = ddi_dma_mem_alloc(afep->afe_rxdesc_dmah, size, &afe_devattr, 2029 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &kaddr, &len, 2030 &afep->afe_rxdesc_acch); 2031 if (rval != DDI_SUCCESS) { 2032 afe_error(afep->afe_dip, 2033 "unable to allocate DMA memory for rx descriptors"); 2034 return (DDI_FAILURE); 2035 } 2036 2037 rval = ddi_dma_addr_bind_handle(afep->afe_rxdesc_dmah, NULL, kaddr, 2038 size, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2039 &dmac, &ncookies); 2040 if (rval != DDI_DMA_MAPPED) { 2041 afe_error(afep->afe_dip, 2042 "unable to bind DMA for rx descriptors"); 2043 return (DDI_FAILURE); 2044 } 2045 2046 /* because of afe_dma_attr */ 2047 ASSERT(ncookies == 1); 2048 2049 /* we take the 32-bit physical address out of the cookie */ 2050 afep->afe_rxdesc_paddr = dmac.dmac_address; 2051 afep->afe_rxdescp = (void *)kaddr; 2052 2053 /* allocate buffer pointers (not the buffers themselves, yet) */ 2054 afep->afe_rxbufs = kmem_zalloc(AFE_RXRING * sizeof (afe_rxbuf_t *), 2055 KM_SLEEP); 2056 2057 /* now allocate rx buffers */ 2058 for (i = 0; i < AFE_RXRING; i++) { 2059 afe_rxbuf_t *rxb = afe_allocrxbuf(afep); 2060 if (rxb == NULL) 2061 return (DDI_FAILURE); 2062 afep->afe_rxbufs[i] = rxb; 2063 } 2064 2065 return (DDI_SUCCESS); 2066 } 2067 2068 /* 2069 * Allocate transmit resources. 2070 */ 2071 int 2072 afe_alloctxring(afe_t *afep) 2073 { 2074 int rval; 2075 int i; 2076 size_t size; 2077 size_t len; 2078 ddi_dma_cookie_t dmac; 2079 unsigned ncookies; 2080 caddr_t kaddr; 2081 2082 size = AFE_TXRING * sizeof (afe_desc_t); 2083 2084 rval = ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_attr, 2085 DDI_DMA_SLEEP, NULL, &afep->afe_txdesc_dmah); 2086 if (rval != DDI_SUCCESS) { 2087 afe_error(afep->afe_dip, 2088 "unable to allocate DMA handle for tx descriptors"); 2089 return (DDI_FAILURE); 2090 } 2091 2092 rval = ddi_dma_mem_alloc(afep->afe_txdesc_dmah, size, &afe_devattr, 2093 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &kaddr, &len, 2094 &afep->afe_txdesc_acch); 2095 if (rval != DDI_SUCCESS) { 2096 afe_error(afep->afe_dip, 2097 "unable to allocate DMA memory for tx descriptors"); 2098 return (DDI_FAILURE); 2099 } 2100 2101 rval = ddi_dma_addr_bind_handle(afep->afe_txdesc_dmah, NULL, kaddr, 2102 size, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2103 &dmac, &ncookies); 2104 if (rval != DDI_DMA_MAPPED) { 2105 afe_error(afep->afe_dip, 2106 "unable to bind DMA for tx descriptors"); 2107 return (DDI_FAILURE); 2108 } 2109 2110 /* because of afe_dma_attr */ 2111 ASSERT(ncookies == 1); 2112 2113 /* we take the 32-bit physical address out of the cookie */ 2114 afep->afe_txdesc_paddr = dmac.dmac_address; 2115 afep->afe_txdescp = (void *)kaddr; 2116 2117 /* allocate buffer pointers (not the buffers themselves, yet) */ 2118 afep->afe_txbufs = kmem_zalloc(AFE_TXRING * sizeof (afe_txbuf_t *), 2119 KM_SLEEP); 2120 2121 /* now allocate tx buffers */ 2122 for (i = 0; i < AFE_TXRING; i++) { 2123 afe_txbuf_t *txb = afe_alloctxbuf(afep); 2124 if (txb == NULL) 2125 return (DDI_FAILURE); 2126 afep->afe_txbufs[i] = txb; 2127 } 2128 2129 return (DDI_SUCCESS); 2130 } 2131 2132 void 2133 afe_freerxring(afe_t *afep) 2134 { 2135 int i; 2136 2137 for (i = 0; i < AFE_RXRING; i++) { 2138 afe_destroyrxbuf(afep->afe_rxbufs[i]); 2139 } 2140 2141 if (afep->afe_rxbufs) { 2142 kmem_free(afep->afe_rxbufs, 2143 AFE_RXRING * sizeof (afe_rxbuf_t *)); 2144 } 2145 2146 if (afep->afe_rxdesc_paddr) 2147 (void) ddi_dma_unbind_handle(afep->afe_rxdesc_dmah); 2148 if (afep->afe_rxdesc_acch) 2149 ddi_dma_mem_free(&afep->afe_rxdesc_acch); 2150 if (afep->afe_rxdesc_dmah) 2151 ddi_dma_free_handle(&afep->afe_rxdesc_dmah); 2152 } 2153 2154 void 2155 afe_freetxring(afe_t *afep) 2156 { 2157 int i; 2158 2159 for (i = 0; i < AFE_TXRING; i++) { 2160 afe_destroytxbuf(afep->afe_txbufs[i]); 2161 } 2162 2163 if (afep->afe_txbufs) { 2164 kmem_free(afep->afe_txbufs, 2165 AFE_TXRING * sizeof (afe_txbuf_t *)); 2166 } 2167 if (afep->afe_txdesc_paddr) 2168 (void) ddi_dma_unbind_handle(afep->afe_txdesc_dmah); 2169 if (afep->afe_txdesc_acch) 2170 ddi_dma_mem_free(&afep->afe_txdesc_acch); 2171 if (afep->afe_txdesc_dmah) 2172 ddi_dma_free_handle(&afep->afe_txdesc_dmah); 2173 } 2174 2175 /* 2176 * Interrupt service routine. 2177 */ 2178 unsigned 2179 afe_intr(caddr_t arg) 2180 { 2181 afe_t *afep = (void *)arg; 2182 uint32_t status; 2183 mblk_t *mp = NULL; 2184 2185 mutex_enter(&afep->afe_intrlock); 2186 2187 if (afep->afe_flags & AFE_SUSPENDED) { 2188 /* we cannot receive interrupts! */ 2189 mutex_exit(&afep->afe_intrlock); 2190 return (DDI_INTR_UNCLAIMED); 2191 } 2192 2193 /* check interrupt status bits, did we interrupt? */ 2194 status = GETCSR(afep, CSR_SR2) & INT_ALL; 2195 2196 if (status == 0) { 2197 KIOIP->intrs[KSTAT_INTR_SPURIOUS]++; 2198 mutex_exit(&afep->afe_intrlock); 2199 return (DDI_INTR_UNCLAIMED); 2200 } 2201 /* ack the interrupt */ 2202 PUTCSR(afep, CSR_SR2, status); 2203 KIOIP->intrs[KSTAT_INTR_HARD]++; 2204 2205 if (!(afep->afe_flags & AFE_RUNNING)) { 2206 /* not running, don't touch anything */ 2207 mutex_exit(&afep->afe_intrlock); 2208 return (DDI_INTR_CLAIMED); 2209 } 2210 2211 if (status & (INT_RXOK|INT_RXNOBUF)) { 2212 /* receive packets */ 2213 mp = afe_receive(afep); 2214 if (status & INT_RXNOBUF) 2215 PUTCSR(afep, CSR_RDR, 0); /* wake up chip */ 2216 } 2217 2218 if (status & INT_TXOK) { 2219 /* transmit completed */ 2220 mutex_enter(&afep->afe_xmtlock); 2221 afe_reclaim(afep); 2222 mutex_exit(&afep->afe_xmtlock); 2223 } 2224 2225 if (status & (INT_LINKCHG|INT_TIMER)) { 2226 mutex_enter(&afep->afe_xmtlock); 2227 afe_checklink(afep); 2228 mutex_exit(&afep->afe_xmtlock); 2229 } 2230 2231 if (status & (INT_RXSTOPPED|INT_TXSTOPPED| 2232 INT_RXJABBER|INT_TXJABBER|INT_TXUNDERFLOW)) { 2233 2234 if (status & (INT_RXJABBER | INT_TXJABBER)) { 2235 afep->afe_jabber++; 2236 } 2237 DBG(DWARN, "resetting mac, status %x", status); 2238 mutex_enter(&afep->afe_xmtlock); 2239 afe_resetall(afep); 2240 mutex_exit(&afep->afe_xmtlock); 2241 } 2242 2243 if (status & INT_BUSERR) { 2244 switch (GETCSR(afep, CSR_SR) & SR_BERR_TYPE) { 2245 case SR_BERR_PARITY: 2246 afe_error(afep->afe_dip, "PCI parity error"); 2247 break; 2248 case SR_BERR_TARGET_ABORT: 2249 afe_error(afep->afe_dip, "PCI target abort"); 2250 break; 2251 case SR_BERR_MASTER_ABORT: 2252 afe_error(afep->afe_dip, "PCI master abort"); 2253 break; 2254 default: 2255 afe_error(afep->afe_dip, "Unknown PCI error"); 2256 break; 2257 } 2258 2259 /* reset the chip in an attempt to fix things */ 2260 mutex_enter(&afep->afe_xmtlock); 2261 afe_resetall(afep); 2262 mutex_exit(&afep->afe_xmtlock); 2263 } 2264 2265 mutex_exit(&afep->afe_intrlock); 2266 2267 /* 2268 * Send up packets. We do this outside of the intrlock. 2269 */ 2270 if (mp) { 2271 mac_rx(afep->afe_mh, NULL, mp); 2272 } 2273 2274 return (DDI_INTR_CLAIMED); 2275 } 2276 2277 void 2278 afe_enableinterrupts(afe_t *afep) 2279 { 2280 unsigned mask = INT_WANTED; 2281 2282 if (afep->afe_wantw) 2283 mask |= INT_TXOK; 2284 2285 PUTCSR(afep, CSR_IER2, mask); 2286 2287 if (AFE_MODEL(afep) == MODEL_COMET) { 2288 /* 2289 * On the Comet, this is the internal transceiver 2290 * interrupt. We program the Comet's built-in PHY to 2291 * enable certain interrupts. 2292 */ 2293 PUTCSR16(afep, CSR_XIE, XIE_LDE | XIE_ANCE); 2294 } 2295 } 2296 2297 void 2298 afe_disableinterrupts(afe_t *afep) 2299 { 2300 /* disable further interrupts */ 2301 PUTCSR(afep, CSR_IER2, INT_NONE); 2302 2303 /* clear any pending interrupts */ 2304 PUTCSR(afep, CSR_SR2, INT_ALL); 2305 } 2306 2307 boolean_t 2308 afe_send(afe_t *afep, mblk_t *mp) 2309 { 2310 size_t len; 2311 afe_txbuf_t *txb; 2312 afe_desc_t *tmd; 2313 uint32_t control; 2314 int txsend; 2315 2316 ASSERT(mutex_owned(&afep->afe_xmtlock)); 2317 ASSERT(mp != NULL); 2318 2319 len = msgsize(mp); 2320 if (len > ETHERVLANMTU) { 2321 DBG(DXMIT, "frame too long: %d", len); 2322 afep->afe_macxmt_errors++; 2323 freemsg(mp); 2324 return (B_TRUE); 2325 } 2326 2327 if (afep->afe_txavail < AFE_TXRECLAIM) 2328 afe_reclaim(afep); 2329 2330 if (afep->afe_txavail == 0) { 2331 /* no more tmds */ 2332 afep->afe_wantw = B_TRUE; 2333 /* enable TX interrupt */ 2334 afe_enableinterrupts(afep); 2335 return (B_FALSE); 2336 } 2337 2338 txsend = afep->afe_txsend; 2339 2340 /* 2341 * For simplicity, we just do a copy into a preallocated 2342 * DMA buffer. 2343 */ 2344 2345 txb = afep->afe_txbufs[txsend]; 2346 mcopymsg(mp, txb->txb_buf); /* frees mp! */ 2347 2348 /* 2349 * Statistics. 2350 */ 2351 afep->afe_opackets++; 2352 afep->afe_obytes += len; 2353 if (txb->txb_buf[0] & 0x1) { 2354 if (bcmp(txb->txb_buf, afe_broadcast, ETHERADDRL) != 0) 2355 afep->afe_multixmt++; 2356 else 2357 afep->afe_brdcstxmt++; 2358 } 2359 2360 /* note len is already known to be a small unsigned */ 2361 control = len | TXCTL_FIRST | TXCTL_LAST | TXCTL_INTCMPLTE; 2362 2363 if (txsend == (AFE_TXRING - 1)) 2364 control |= TXCTL_ENDRING; 2365 2366 tmd = &afep->afe_txdescp[txsend]; 2367 2368 SYNCTXBUF(txb, len, DDI_DMA_SYNC_FORDEV); 2369 PUTTXDESC(afep, tmd->desc_control, control); 2370 PUTTXDESC(afep, tmd->desc_buffer1, txb->txb_paddr); 2371 PUTTXDESC(afep, tmd->desc_buffer2, 0); 2372 PUTTXDESC(afep, tmd->desc_status, TXSTAT_OWN); 2373 /* sync the descriptor out to the device */ 2374 SYNCTXDESC(afep, txsend, DDI_DMA_SYNC_FORDEV); 2375 2376 /* 2377 * Note the new values of txavail and txsend. 2378 */ 2379 afep->afe_txavail--; 2380 afep->afe_txsend = (txsend + 1) % AFE_TXRING; 2381 2382 /* 2383 * It should never, ever take more than 5 seconds to drain 2384 * the ring. If it happens, then we are stuck! 2385 */ 2386 afep->afe_txstall_time = gethrtime() + (5 * 1000000000ULL); 2387 2388 /* 2389 * wake up the chip ... inside the lock to protect against DR suspend, 2390 * etc. 2391 */ 2392 PUTCSR(afep, CSR_TDR, 0); 2393 2394 return (B_TRUE); 2395 } 2396 2397 /* 2398 * Reclaim buffers that have completed transmission. 2399 */ 2400 void 2401 afe_reclaim(afe_t *afep) 2402 { 2403 afe_desc_t *tmdp; 2404 2405 while (afep->afe_txavail != AFE_TXRING) { 2406 uint32_t status; 2407 uint32_t control; 2408 int index = afep->afe_txreclaim; 2409 2410 tmdp = &afep->afe_txdescp[index]; 2411 2412 /* sync it before we read it */ 2413 SYNCTXDESC(afep, index, DDI_DMA_SYNC_FORKERNEL); 2414 2415 control = GETTXDESC(afep, tmdp->desc_control); 2416 status = GETTXDESC(afep, tmdp->desc_status); 2417 2418 if (status & TXSTAT_OWN) { 2419 /* chip is still working on it, we're done */ 2420 break; 2421 } 2422 2423 afep->afe_txavail++; 2424 afep->afe_txreclaim = (index + 1) % AFE_TXRING; 2425 2426 /* in the most common successful case, all bits are clear */ 2427 if (status == 0) 2428 continue; 2429 2430 if ((control & TXCTL_LAST) == 0) 2431 continue; 2432 2433 if (status & TXSTAT_TXERR) { 2434 afep->afe_errxmt++; 2435 2436 if (status & TXSTAT_JABBER) { 2437 /* transmit jabber timeout */ 2438 afep->afe_macxmt_errors++; 2439 } 2440 if (status & 2441 (TXSTAT_CARRLOST | TXSTAT_NOCARR)) { 2442 afep->afe_carrier_errors++; 2443 } 2444 if (status & TXSTAT_UFLOW) { 2445 afep->afe_underflow++; 2446 } 2447 if (status & TXSTAT_LATECOL) { 2448 afep->afe_tx_late_collisions++; 2449 } 2450 if (status & TXSTAT_EXCOLL) { 2451 afep->afe_ex_collisions++; 2452 afep->afe_collisions += 16; 2453 } 2454 } 2455 2456 if (status & TXSTAT_DEFER) { 2457 afep->afe_defer_xmts++; 2458 } 2459 2460 /* collision counting */ 2461 if (TXCOLLCNT(status) == 1) { 2462 afep->afe_collisions++; 2463 afep->afe_first_collisions++; 2464 } else if (TXCOLLCNT(status)) { 2465 afep->afe_collisions += TXCOLLCNT(status); 2466 afep->afe_multi_collisions += TXCOLLCNT(status); 2467 } 2468 } 2469 2470 if (afep->afe_txavail >= AFE_TXRESCHED) { 2471 if (afep->afe_wantw) { 2472 /* 2473 * we were able to reclaim some packets, so 2474 * disable tx interrupts 2475 */ 2476 afep->afe_wantw = B_FALSE; 2477 afe_enableinterrupts(afep); 2478 mac_tx_update(afep->afe_mh); 2479 } 2480 } 2481 } 2482 2483 mblk_t * 2484 afe_receive(afe_t *afep) 2485 { 2486 unsigned len; 2487 afe_rxbuf_t *rxb; 2488 afe_desc_t *rmd; 2489 uint32_t status; 2490 mblk_t *mpchain, **mpp, *mp; 2491 int head, cnt; 2492 2493 mpchain = NULL; 2494 mpp = &mpchain; 2495 head = afep->afe_rxhead; 2496 2497 /* limit the number of packets we process to a half ring size */ 2498 for (cnt = 0; cnt < AFE_RXRING / 2; cnt++) { 2499 2500 DBG(DRECV, "receive at index %d", head); 2501 2502 rmd = &afep->afe_rxdescp[head]; 2503 rxb = afep->afe_rxbufs[head]; 2504 2505 SYNCRXDESC(afep, head, DDI_DMA_SYNC_FORKERNEL); 2506 status = GETRXDESC(afep, rmd->desc_status); 2507 if (status & RXSTAT_OWN) { 2508 /* chip is still chewing on it */ 2509 break; 2510 } 2511 2512 /* discard the ethernet frame checksum */ 2513 len = RXLENGTH(status) - ETHERFCSL; 2514 2515 DBG(DRECV, "recv length %d, status %x", len, status); 2516 2517 if ((status & (RXSTAT_ERRS | RXSTAT_FIRST | RXSTAT_LAST)) != 2518 (RXSTAT_FIRST | RXSTAT_LAST)) { 2519 2520 afep->afe_errrcv++; 2521 2522 /* 2523 * Abnormal status bits detected, analyze further. 2524 */ 2525 if ((status & (RXSTAT_LAST|RXSTAT_FIRST)) != 2526 (RXSTAT_LAST|RXSTAT_FIRST)) { 2527 DBG(DRECV, "rx packet overspill"); 2528 if (status & RXSTAT_FIRST) { 2529 afep->afe_toolong_errors++; 2530 } 2531 } else if (status & RXSTAT_DESCERR) { 2532 afep->afe_macrcv_errors++; 2533 2534 } else if (status & RXSTAT_RUNT) { 2535 afep->afe_runt++; 2536 2537 } else if (status & RXSTAT_COLLSEEN) { 2538 /* this should really be rx_late_collisions */ 2539 afep->afe_macrcv_errors++; 2540 2541 } else if (status & RXSTAT_DRIBBLE) { 2542 afep->afe_align_errors++; 2543 2544 } else if (status & RXSTAT_CRCERR) { 2545 afep->afe_fcs_errors++; 2546 2547 } else if (status & RXSTAT_OFLOW) { 2548 afep->afe_overflow++; 2549 } 2550 } 2551 2552 else if (len > ETHERVLANMTU) { 2553 afep->afe_errrcv++; 2554 afep->afe_toolong_errors++; 2555 } 2556 2557 /* 2558 * At this point, the chip thinks the packet is OK. 2559 */ 2560 else { 2561 mp = allocb(len + AFE_HEADROOM, 0); 2562 if (mp == NULL) { 2563 afep->afe_errrcv++; 2564 afep->afe_norcvbuf++; 2565 goto skip; 2566 } 2567 2568 /* sync the buffer before we look at it */ 2569 SYNCRXBUF(rxb, len, DDI_DMA_SYNC_FORKERNEL); 2570 mp->b_rptr += AFE_HEADROOM; 2571 mp->b_wptr = mp->b_rptr + len; 2572 bcopy((char *)rxb->rxb_buf, mp->b_rptr, len); 2573 2574 afep->afe_ipackets++; 2575 afep->afe_rbytes += len; 2576 if (status & RXSTAT_GROUP) { 2577 if (bcmp(mp->b_rptr, afe_broadcast, 2578 ETHERADDRL) == 0) 2579 afep->afe_brdcstrcv++; 2580 else 2581 afep->afe_multircv++; 2582 } 2583 *mpp = mp; 2584 mpp = &mp->b_next; 2585 } 2586 2587 skip: 2588 /* return ring entry to the hardware */ 2589 PUTRXDESC(afep, rmd->desc_status, RXSTAT_OWN); 2590 SYNCRXDESC(afep, head, DDI_DMA_SYNC_FORDEV); 2591 2592 /* advance to next RMD */ 2593 head = (head + 1) % AFE_RXRING; 2594 } 2595 2596 afep->afe_rxhead = head; 2597 2598 return (mpchain); 2599 } 2600 2601 int 2602 afe_getmiibit(afe_t *afep, uint16_t reg, uint16_t bit) 2603 { 2604 unsigned val; 2605 2606 mutex_enter(&afep->afe_xmtlock); 2607 if (afep->afe_flags & AFE_SUSPENDED) { 2608 mutex_exit(&afep->afe_xmtlock); 2609 /* device is suspended */ 2610 return (0); 2611 } 2612 val = afe_miiread(afep, afep->afe_phyaddr, reg); 2613 mutex_exit(&afep->afe_xmtlock); 2614 2615 return (val & bit ? 1 : 0); 2616 } 2617 #define GETMIIBIT(reg, bit) afe_getmiibit(afep, reg, bit) 2618 2619 int 2620 afe_m_stat(void *arg, uint_t stat, uint64_t *val) 2621 { 2622 afe_t *afep = arg; 2623 2624 mutex_enter(&afep->afe_xmtlock); 2625 if ((afep->afe_flags & (AFE_RUNNING|AFE_SUSPENDED)) == AFE_RUNNING) 2626 afe_reclaim(afep); 2627 mutex_exit(&afep->afe_xmtlock); 2628 2629 switch (stat) { 2630 case MAC_STAT_IFSPEED: 2631 *val = afep->afe_ifspeed; 2632 break; 2633 2634 case MAC_STAT_MULTIRCV: 2635 *val = afep->afe_multircv; 2636 break; 2637 2638 case MAC_STAT_BRDCSTRCV: 2639 *val = afep->afe_brdcstrcv; 2640 break; 2641 2642 case MAC_STAT_MULTIXMT: 2643 *val = afep->afe_multixmt; 2644 break; 2645 2646 case MAC_STAT_BRDCSTXMT: 2647 *val = afep->afe_brdcstxmt; 2648 break; 2649 2650 case MAC_STAT_IPACKETS: 2651 *val = afep->afe_ipackets; 2652 break; 2653 2654 case MAC_STAT_RBYTES: 2655 *val = afep->afe_rbytes; 2656 break; 2657 2658 case MAC_STAT_OPACKETS: 2659 *val = afep->afe_opackets; 2660 break; 2661 2662 case MAC_STAT_OBYTES: 2663 *val = afep->afe_obytes; 2664 break; 2665 2666 case MAC_STAT_NORCVBUF: 2667 *val = afep->afe_norcvbuf; 2668 break; 2669 2670 case MAC_STAT_NOXMTBUF: 2671 *val = 0; 2672 break; 2673 2674 case MAC_STAT_COLLISIONS: 2675 *val = afep->afe_collisions; 2676 break; 2677 2678 case MAC_STAT_IERRORS: 2679 *val = afep->afe_errrcv; 2680 break; 2681 2682 case MAC_STAT_OERRORS: 2683 *val = afep->afe_errxmt; 2684 break; 2685 2686 case ETHER_STAT_LINK_DUPLEX: 2687 *val = afep->afe_duplex; 2688 break; 2689 2690 case ETHER_STAT_ALIGN_ERRORS: 2691 *val = afep->afe_align_errors; 2692 break; 2693 2694 case ETHER_STAT_FCS_ERRORS: 2695 *val = afep->afe_fcs_errors; 2696 break; 2697 2698 case ETHER_STAT_SQE_ERRORS: 2699 *val = afep->afe_sqe_errors; 2700 break; 2701 2702 case ETHER_STAT_DEFER_XMTS: 2703 *val = afep->afe_defer_xmts; 2704 break; 2705 2706 case ETHER_STAT_FIRST_COLLISIONS: 2707 *val = afep->afe_first_collisions; 2708 break; 2709 2710 case ETHER_STAT_MULTI_COLLISIONS: 2711 *val = afep->afe_multi_collisions; 2712 break; 2713 2714 case ETHER_STAT_TX_LATE_COLLISIONS: 2715 *val = afep->afe_tx_late_collisions; 2716 break; 2717 2718 case ETHER_STAT_EX_COLLISIONS: 2719 *val = afep->afe_ex_collisions; 2720 break; 2721 2722 case ETHER_STAT_MACXMT_ERRORS: 2723 *val = afep->afe_macxmt_errors; 2724 break; 2725 2726 case ETHER_STAT_CARRIER_ERRORS: 2727 *val = afep->afe_carrier_errors; 2728 break; 2729 2730 case ETHER_STAT_TOOLONG_ERRORS: 2731 *val = afep->afe_toolong_errors; 2732 break; 2733 2734 case ETHER_STAT_MACRCV_ERRORS: 2735 *val = afep->afe_macrcv_errors; 2736 break; 2737 2738 case MAC_STAT_OVERFLOWS: 2739 *val = afep->afe_overflow; 2740 break; 2741 2742 case MAC_STAT_UNDERFLOWS: 2743 *val = afep->afe_underflow; 2744 break; 2745 2746 case ETHER_STAT_TOOSHORT_ERRORS: 2747 *val = afep->afe_runt; 2748 break; 2749 2750 case ETHER_STAT_JABBER_ERRORS: 2751 *val = afep->afe_jabber; 2752 break; 2753 2754 case ETHER_STAT_CAP_100T4: 2755 *val = GETMIIBIT(MII_STATUS, MII_STATUS_100_BASE_T4); 2756 break; 2757 2758 case ETHER_STAT_CAP_100FDX: 2759 *val = GETMIIBIT(MII_STATUS, MII_STATUS_100_BASEX_FD); 2760 break; 2761 2762 case ETHER_STAT_CAP_100HDX: 2763 *val = GETMIIBIT(MII_STATUS, MII_STATUS_100_BASEX); 2764 break; 2765 2766 case ETHER_STAT_CAP_10FDX: 2767 *val = GETMIIBIT(MII_STATUS, MII_STATUS_10_FD); 2768 break; 2769 2770 case ETHER_STAT_CAP_10HDX: 2771 *val = GETMIIBIT(MII_STATUS, MII_STATUS_10); 2772 break; 2773 2774 case ETHER_STAT_CAP_AUTONEG: 2775 *val = GETMIIBIT(MII_STATUS, MII_STATUS_CANAUTONEG); 2776 break; 2777 2778 case ETHER_STAT_LINK_AUTONEG: 2779 *val = ((afep->afe_adv_aneg != 0) && 2780 (GETMIIBIT(MII_AN_LPABLE, MII_AN_EXP_LPCANAN) != 0)); 2781 break; 2782 2783 case ETHER_STAT_ADV_CAP_100T4: 2784 *val = afep->afe_adv_100T4; 2785 break; 2786 2787 case ETHER_STAT_ADV_CAP_100FDX: 2788 *val = afep->afe_adv_100fdx; 2789 break; 2790 2791 case ETHER_STAT_ADV_CAP_100HDX: 2792 *val = afep->afe_adv_100hdx; 2793 break; 2794 2795 case ETHER_STAT_ADV_CAP_10FDX: 2796 *val = afep->afe_adv_10fdx; 2797 break; 2798 2799 case ETHER_STAT_ADV_CAP_10HDX: 2800 *val = afep->afe_adv_10hdx; 2801 break; 2802 2803 case ETHER_STAT_ADV_CAP_AUTONEG: 2804 *val = afep->afe_adv_aneg; 2805 break; 2806 2807 case ETHER_STAT_LP_CAP_100T4: 2808 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_100BASE_T4); 2809 break; 2810 2811 case ETHER_STAT_LP_CAP_100FDX: 2812 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_100BASE_TX_FD); 2813 break; 2814 2815 case ETHER_STAT_LP_CAP_100HDX: 2816 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_100BASE_TX); 2817 break; 2818 2819 case ETHER_STAT_LP_CAP_10FDX: 2820 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_10BASE_T_FD); 2821 break; 2822 2823 case ETHER_STAT_LP_CAP_10HDX: 2824 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_10BASE_T); 2825 break; 2826 2827 case ETHER_STAT_LP_CAP_AUTONEG: 2828 *val = GETMIIBIT(MII_AN_EXPANSION, MII_AN_EXP_LPCANAN); 2829 break; 2830 2831 case ETHER_STAT_XCVR_ADDR: 2832 *val = afep->afe_phyaddr; 2833 break; 2834 2835 case ETHER_STAT_XCVR_ID: 2836 *val = afep->afe_phyid; 2837 break; 2838 2839 default: 2840 return (ENOTSUP); 2841 } 2842 return (0); 2843 } 2844 2845 /* 2846 * NDD support. 2847 */ 2848 afe_nd_t * 2849 afe_ndfind(afe_t *afep, char *name) 2850 { 2851 afe_nd_t *ndp; 2852 2853 for (ndp = afep->afe_ndp; ndp != NULL; ndp = ndp->nd_next) { 2854 if (strcmp(name, ndp->nd_name) == 0) { 2855 break; 2856 } 2857 } 2858 return (ndp); 2859 } 2860 2861 void 2862 afe_ndadd(afe_t *afep, char *name, afe_nd_pf_t get, afe_nd_pf_t set, 2863 intptr_t arg1, intptr_t arg2) 2864 { 2865 afe_nd_t *newndp; 2866 afe_nd_t **ndpp; 2867 2868 newndp = (afe_nd_t *)kmem_alloc(sizeof (afe_nd_t), KM_SLEEP); 2869 newndp->nd_next = NULL; 2870 newndp->nd_name = name; 2871 newndp->nd_get = get; 2872 newndp->nd_set = set; 2873 newndp->nd_arg1 = arg1; 2874 newndp->nd_arg2 = arg2; 2875 2876 /* seek to the end of the list */ 2877 for (ndpp = &afep->afe_ndp; *ndpp; ndpp = &(*ndpp)->nd_next) { 2878 } 2879 2880 *ndpp = newndp; 2881 } 2882 2883 void 2884 afe_ndempty(mblk_t *mp) 2885 { 2886 while (mp != NULL) { 2887 mp->b_rptr = mp->b_datap->db_base; 2888 mp->b_wptr = mp->b_rptr; 2889 mp = mp->b_cont; 2890 } 2891 } 2892 2893 void 2894 afe_ndget(afe_t *afep, queue_t *wq, mblk_t *mp) 2895 { 2896 mblk_t *nmp = mp->b_cont; 2897 afe_nd_t *ndp; 2898 int rv; 2899 char name[128]; 2900 2901 /* assumption, name will fit in first mblk of chain */ 2902 if ((nmp == NULL) || (nmp->b_wptr <= nmp->b_rptr)) { 2903 miocnak(wq, mp, 0, EINVAL); 2904 return; 2905 } 2906 2907 if (afe_ndparselen(nmp) >= sizeof (name)) { 2908 miocnak(wq, mp, 0, EINVAL); 2909 return; 2910 } 2911 afe_ndparsestring(nmp, name, sizeof (name)); 2912 2913 /* locate variable */ 2914 if ((ndp = afe_ndfind(afep, name)) == NULL) { 2915 miocnak(wq, mp, 0, EINVAL); 2916 return; 2917 } 2918 2919 /* locate get callback */ 2920 if (ndp->nd_get == NULL) { 2921 miocnak(wq, mp, 0, EACCES); 2922 return; 2923 } 2924 2925 /* clear the result buffer */ 2926 afe_ndempty(nmp); 2927 2928 rv = (*ndp->nd_get)(afep, nmp, ndp); 2929 if (rv == 0) { 2930 /* add final null bytes */ 2931 rv = afe_ndaddbytes(nmp, "\0", 1); 2932 } 2933 2934 if (rv == 0) { 2935 miocack(wq, mp, msgsize(nmp), 0); 2936 } else { 2937 miocnak(wq, mp, 0, rv); 2938 } 2939 } 2940 2941 void 2942 afe_ndset(afe_t *afep, queue_t *wq, mblk_t *mp) 2943 { 2944 struct iocblk *iocp = (void *)mp->b_rptr; 2945 mblk_t *nmp = mp->b_cont; 2946 afe_nd_t *ndp; 2947 int rv; 2948 char name[128]; 2949 2950 /* enforce policy */ 2951 if ((rv = priv_getbyname(PRIV_SYS_NET_CONFIG, 0)) < 0) { 2952 /* priv_getbyname returns a negative errno */ 2953 miocnak(wq, mp, 0, -rv); 2954 return; 2955 } 2956 if ((rv = priv_policy(iocp->ioc_cr, rv, B_FALSE, EPERM, NULL)) != 0) { 2957 miocnak(wq, mp, 0, rv); 2958 return; 2959 } 2960 2961 /* assumption, name will fit in first mblk of chain */ 2962 if ((nmp == NULL) || (nmp->b_wptr <= nmp->b_rptr)) { 2963 miocnak(wq, mp, 0, EINVAL); 2964 return; 2965 } 2966 2967 if (afe_ndparselen(nmp) >= sizeof (name)) { 2968 miocnak(wq, mp, 0, EINVAL); 2969 return; 2970 } 2971 afe_ndparsestring(nmp, name, sizeof (name)); 2972 2973 /* locate variable */ 2974 if ((ndp = afe_ndfind(afep, name)) == NULL) { 2975 miocnak(wq, mp, 0, EINVAL); 2976 return; 2977 } 2978 2979 /* locate set callback */ 2980 if (ndp->nd_set == NULL) { 2981 miocnak(wq, mp, 0, EACCES); 2982 return; 2983 } 2984 2985 rv = (*ndp->nd_set)(afep, nmp, ndp); 2986 2987 if (rv == 0) { 2988 miocack(wq, mp, 0, 0); 2989 } else { 2990 miocnak(wq, mp, 0, rv); 2991 } 2992 } 2993 2994 int 2995 afe_ndaddbytes(mblk_t *mp, char *bytes, int cnt) 2996 { 2997 int index; 2998 2999 for (index = 0; index < cnt; index++) { 3000 while (mp && (mp->b_wptr >= DB_LIM(mp))) { 3001 mp = mp->b_cont; 3002 } 3003 if (mp == NULL) { 3004 return (ENOSPC); 3005 } 3006 *(mp->b_wptr) = *bytes; 3007 mp->b_wptr++; 3008 bytes++; 3009 } 3010 return (0); 3011 } 3012 3013 int 3014 afe_ndaddstr(mblk_t *mp, char *str, int addnull) 3015 { 3016 /* store the string, plus the terminating null */ 3017 return (afe_ndaddbytes(mp, str, strlen(str) + (addnull ? 1 : 0))); 3018 } 3019 3020 int 3021 afe_ndparselen(mblk_t *mp) 3022 { 3023 int len = 0; 3024 int done = 0; 3025 uchar_t *ptr; 3026 3027 while (mp && !done) { 3028 for (ptr = mp->b_rptr; ptr < mp->b_wptr; ptr++) { 3029 if (!(*ptr)) { 3030 done = 1; 3031 break; 3032 } 3033 len++; 3034 } 3035 mp = mp->b_cont; 3036 } 3037 return (len); 3038 } 3039 3040 int 3041 afe_ndparseint(mblk_t *mp) 3042 { 3043 int done = 0; 3044 int val = 0; 3045 while (mp && !done) { 3046 while (mp->b_rptr < mp->b_wptr) { 3047 uchar_t ch = *(mp->b_rptr); 3048 mp->b_rptr++; 3049 if ((ch >= '0') && (ch <= '9')) { 3050 val *= 10; 3051 val += ch - '0'; 3052 } else if (ch == 0) { 3053 return (val); 3054 } else { 3055 /* parse error, put back rptr */ 3056 mp->b_rptr--; 3057 return (val); 3058 } 3059 } 3060 mp = mp->b_cont; 3061 } 3062 return (val); 3063 } 3064 3065 void 3066 afe_ndparsestring(mblk_t *mp, char *buf, int maxlen) 3067 { 3068 int done = 0; 3069 int len = 0; 3070 3071 /* ensure null termination */ 3072 buf[maxlen - 1] = 0; 3073 while (mp && !done) { 3074 while (mp->b_rptr < mp->b_wptr) { 3075 char ch = *((char *)mp->b_rptr); 3076 mp->b_rptr++; 3077 buf[len++] = ch; 3078 if ((ch == 0) || (len == maxlen)) { 3079 return; 3080 } 3081 } 3082 mp = mp->b_cont; 3083 } 3084 } 3085 3086 int 3087 afe_ndquestion(afe_t *afep, mblk_t *mp, afe_nd_t *ndp) 3088 { 3089 for (ndp = afep->afe_ndp; ndp; ndp = ndp->nd_next) { 3090 int rv; 3091 char *s; 3092 if ((rv = afe_ndaddstr(mp, ndp->nd_name, 0)) != 0) { 3093 return (rv); 3094 } 3095 if (ndp->nd_get && ndp->nd_set) { 3096 s = " (read and write)"; 3097 } else if (ndp->nd_get) { 3098 s = " (read only)"; 3099 } else if (ndp->nd_set) { 3100 s = " (write only)"; 3101 } else { 3102 s = " (no read or write)"; 3103 } 3104 if ((rv = afe_ndaddstr(mp, s, 1)) != 0) { 3105 return (rv); 3106 } 3107 } 3108 return (0); 3109 } 3110 3111 /*ARGSUSED*/ 3112 int 3113 afe_ndgetint(afe_t *afep, mblk_t *mp, afe_nd_t *ndp) 3114 { 3115 int val; 3116 char buf[16]; 3117 3118 val = *(int *)ndp->nd_arg1; 3119 3120 (void) snprintf(buf, sizeof (buf), "%d", val); 3121 return (afe_ndaddstr(mp, buf, 1)); 3122 } 3123 3124 int 3125 afe_ndgetmiibit(afe_t *afep, mblk_t *mp, afe_nd_t *ndp) 3126 { 3127 unsigned val; 3128 unsigned mask; 3129 int reg; 3130 3131 reg = (int)ndp->nd_arg1; 3132 mask = (unsigned)ndp->nd_arg2; 3133 3134 mutex_enter(&afep->afe_xmtlock); 3135 if (afep->afe_flags & AFE_SUSPENDED) { 3136 mutex_exit(&afep->afe_xmtlock); 3137 /* device is suspended */ 3138 return (EIO); 3139 } 3140 val = afe_miiread(afep, afep->afe_phyaddr, reg); 3141 mutex_exit(&afep->afe_xmtlock); 3142 3143 return (afe_ndaddstr(mp, val & mask ? "1" : "0", 1)); 3144 } 3145 3146 int 3147 afe_ndsetadv(afe_t *afep, mblk_t *mp, afe_nd_t *ndp) 3148 { 3149 unsigned *ptr = (unsigned *)ndp->nd_arg1; 3150 unsigned oldval, newval; 3151 3152 newval = afe_ndparseint(mp) ? 1 : 0; 3153 3154 mutex_enter(&afep->afe_intrlock); 3155 mutex_enter(&afep->afe_xmtlock); 3156 3157 oldval = *ptr; 3158 if (oldval != newval) { 3159 *ptr = newval; 3160 if ((afep->afe_flags & (AFE_RUNNING|AFE_SUSPENDED)) == 3161 AFE_RUNNING) { 3162 /* 3163 * This re-initializes the phy, but it also 3164 * restarts transmit and receive rings. 3165 * Needless to say, changing the link 3166 * parameters is destructive to traffic in 3167 * progress. 3168 */ 3169 afe_resetall(afep); 3170 } 3171 } 3172 mutex_exit(&afep->afe_xmtlock); 3173 mutex_exit(&afep->afe_intrlock); 3174 3175 return (0); 3176 } 3177 3178 void 3179 afe_ndfini(afe_t *afep) 3180 { 3181 afe_nd_t *ndp; 3182 3183 while ((ndp = afep->afe_ndp) != NULL) { 3184 afep->afe_ndp = ndp->nd_next; 3185 kmem_free(ndp, sizeof (afe_nd_t)); 3186 } 3187 } 3188 3189 void 3190 afe_ndinit(afe_t *afep) 3191 { 3192 afe_ndadd(afep, "?", afe_ndquestion, NULL, 0, 0); 3193 afe_ndadd(afep, "link_status", afe_ndgetint, NULL, 3194 (intptr_t)&afep->afe_linkup, 0); 3195 afe_ndadd(afep, "link_speed", afe_ndgetint, NULL, 3196 (intptr_t)&afep->afe_ifspeed, 0); 3197 afe_ndadd(afep, "link_duplex", afe_ndgetint, NULL, 3198 (intptr_t)&afep->afe_duplex, 0); 3199 afe_ndadd(afep, "adv_autoneg_cap", afe_ndgetint, afe_ndsetadv, 3200 (intptr_t)&afep->afe_adv_aneg, 0); 3201 afe_ndadd(afep, "adv_100T4_cap", afe_ndgetint, afe_ndsetadv, 3202 (intptr_t)&afep->afe_adv_100T4, 0); 3203 afe_ndadd(afep, "adv_100fdx_cap", afe_ndgetint, afe_ndsetadv, 3204 (intptr_t)&afep->afe_adv_100fdx, 0); 3205 afe_ndadd(afep, "adv_100hdx_cap", afe_ndgetint, afe_ndsetadv, 3206 (intptr_t)&afep->afe_adv_100hdx, 0); 3207 afe_ndadd(afep, "adv_10fdx_cap", afe_ndgetint, afe_ndsetadv, 3208 (intptr_t)&afep->afe_adv_10fdx, 0); 3209 afe_ndadd(afep, "adv_10hdx_cap", afe_ndgetint, afe_ndsetadv, 3210 (intptr_t)&afep->afe_adv_10hdx, 0); 3211 afe_ndadd(afep, "autoneg_cap", afe_ndgetmiibit, NULL, 3212 MII_STATUS, MII_STATUS_CANAUTONEG); 3213 afe_ndadd(afep, "100T4_cap", afe_ndgetmiibit, NULL, 3214 MII_STATUS, MII_STATUS_100_BASE_T4); 3215 afe_ndadd(afep, "100fdx_cap", afe_ndgetmiibit, NULL, 3216 MII_STATUS, MII_STATUS_100_BASEX_FD); 3217 afe_ndadd(afep, "100hdx_cap", afe_ndgetmiibit, NULL, 3218 MII_STATUS, MII_STATUS_100_BASEX); 3219 afe_ndadd(afep, "10fdx_cap", afe_ndgetmiibit, NULL, 3220 MII_STATUS, MII_STATUS_10_FD); 3221 afe_ndadd(afep, "10hdx_cap", afe_ndgetmiibit, NULL, 3222 MII_STATUS, MII_STATUS_10); 3223 afe_ndadd(afep, "lp_autoneg_cap", afe_ndgetmiibit, NULL, 3224 MII_AN_EXPANSION, MII_AN_EXP_LPCANAN); 3225 afe_ndadd(afep, "lp_100T4_cap", afe_ndgetmiibit, NULL, 3226 MII_AN_LPABLE, MII_ABILITY_100BASE_T4); 3227 afe_ndadd(afep, "lp_100fdx_cap", afe_ndgetmiibit, NULL, 3228 MII_AN_LPABLE, MII_ABILITY_100BASE_TX_FD); 3229 afe_ndadd(afep, "lp_100hdx_cap", afe_ndgetmiibit, NULL, 3230 MII_AN_LPABLE, MII_ABILITY_100BASE_TX); 3231 afe_ndadd(afep, "lp_10fdx_cap", afe_ndgetmiibit, NULL, 3232 MII_AN_LPABLE, MII_ABILITY_10BASE_T_FD); 3233 afe_ndadd(afep, "lp_10hdx_cap", afe_ndgetmiibit, NULL, 3234 MII_AN_LPABLE, MII_ABILITY_10BASE_T); 3235 } 3236 3237 /* 3238 * Debugging and error reporting. 3239 */ 3240 void 3241 afe_error(dev_info_t *dip, char *fmt, ...) 3242 { 3243 va_list ap; 3244 char buf[256]; 3245 3246 va_start(ap, fmt); 3247 (void) vsnprintf(buf, sizeof (buf), fmt, ap); 3248 va_end(ap); 3249 3250 if (dip) { 3251 cmn_err(CE_WARN, "%s%d: %s", 3252 ddi_driver_name(dip), ddi_get_instance(dip), buf); 3253 } else { 3254 cmn_err(CE_WARN, "afe: %s", buf); 3255 } 3256 } 3257 3258 #ifdef DEBUG 3259 3260 void 3261 afe_dprintf(afe_t *afep, const char *func, int level, char *fmt, ...) 3262 { 3263 va_list ap; 3264 3265 va_start(ap, fmt); 3266 if (afe_debug & level) { 3267 char tag[64]; 3268 char buf[256]; 3269 3270 if (afep && afep->afe_dip) { 3271 (void) snprintf(tag, sizeof (tag), "%s%d", 3272 ddi_driver_name(afep->afe_dip), 3273 ddi_get_instance(afep->afe_dip)); 3274 } else { 3275 (void) snprintf(tag, sizeof (tag), "afe"); 3276 } 3277 3278 (void) snprintf(buf, sizeof (buf), "%s: %s: %s\n", 3279 tag, func, fmt); 3280 3281 vcmn_err(CE_CONT, buf, ap); 3282 } 3283 va_end(ap); 3284 } 3285 3286 #endif 3287