1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2000-2001, 2003 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_HPC3130_DAK_H 28 #define _SYS_HPC3130_DAK_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined(_KERNEL) 37 38 #include <sys/i2c/clients/i2c_client.h> 39 40 /* masks */ 41 42 #define HPC3130_PROTECT_ON 0x01 /* (R/W) protection enable mechanism */ 43 #define HPC3130_SYSM66STAT 0x02 /* (R) indicates bus runs at 66Mhz */ 44 #define HPC3130_SEQUENCING 0x0c /* (R/W) hotplug sequencing mode */ 45 #define HPC3130_MANUAL_SEQ 0x00 /* controle with idividual register calls */ 46 #define HPC3130_AUTO1_SEQ 0x04 /* enable CBT before disable RST# */ 47 #define HPC3130_AUTO2_SEQ 0x08 /* enable CBT after disable RST# */ 48 49 #define HPC3130_GCR 0x00 50 #define HPC3130_STATUS 0x01 51 #define HPC3130_CONTROL 0x02 52 #define HPC3130_ATTEN 0x03 53 #define HPC3130_EVENT_STATUS 0x06 54 #define HPC3130_INTERRUPT 0x07 55 #define HPC3130_NO_REGISTER 0xff 56 57 /* 58 * masks 59 */ 60 #define HPC3130_PRSNT1 0x01 /* (R) Logic level of PRSNT1# signal */ 61 #define HPC3130_PRSNT2 0x02 /* (R) Logic level of PRSNT2# signal */ 62 #define HPC3130_DETECT0 0x04 /* (R) Logic level of DETECT0# signal */ 63 #define HPC3130_DETECT1 0x08 /* (R) Logic level of DETECT1# signal */ 64 #define HPC3130_PWRFAULT 0x10 /* (R) Logic level of PWRFAULT# signal */ 65 #define HPC3130_PWRGOOD 0x20 /* (R) Logic level of PWRGOOD# signal */ 66 #define HPC3130_M66EN 0x40 /* (R) Logic level of M66EN terminal */ 67 #define HPC3130_BUSON 0x80 /* (R) Logic level of BUSON# signal */ 68 69 70 /* 71 * more masks 72 */ 73 /* (R/W) Logical level of SLOTRST# (used to reset a slot) */ 74 #define HPC3130_SLOTRST 0x01 75 /* (R/W) Logical level of CLKON# (used to control clock signal) */ 76 #define HPC3130_CLKON 0x02 77 /* (R/W) Logical level of REQ64ON# signal */ 78 #define HPC3130_REQ64 0x04 79 /* (R/W) Logical level of SLOTREQ64# signal */ 80 #define HPC3130_SLOTREQ64 0x08 81 /* (R/W) Bus control (for auto sequence level==1?disconnect:connect */ 82 #define HPC3130_BUS_CTL 0x10 83 /* (R/W) Logical level of power control on the slot */ 84 #define HPC3130_SLTPWRCTL 0x20 85 86 87 #define HPC3130_ATTN0 0x00 88 #define HPC3130_ATTN1 0x01 89 90 #define HPC3130_LED_FAULT HPC3130_ATTN1 91 #define HPC3130_LED_OK2REM HPC3130_ATTN0 92 93 #define HPC3130_ATTN_MASK(led) (3<<(HPC3130_ATTN_SHIFT(led))) /* 3 or c */ 94 #define HPC3130_ATTN_SHIFT(led) (led<<1) /* 0 or 2 */ 95 96 #define HPC3130_ATTN_OFF 0x00 97 #define HPC3130_ATTN_SLO 0x01 /* not used by Daktari */ 98 #define HPC3130_ATTN_FST 0x02 99 #define HPC3130_ATTN_ON 0x03 100 101 /* 102 * These two macros map between the Hot Plug Services LED constants 103 * (cf. uts/common/sys/hotplug/hpctrl.h) and the values used by the 104 * HPC3130 hardware. 105 */ 106 107 static char hpc3130_to_hpc_led_map[] = { 108 HPC_LED_OFF, HPC_LED_BLINK, HPC_LED_BLINK, HPC_LED_ON 109 }; 110 static char hpc3130_from_hpc_led_map[] = { 111 HPC3130_ATTN_OFF, HPC3130_ATTN_ON, HPC3130_ATTN_FST 112 }; 113 #define HPC3130_TO_HPC_LED(val) (hpc3130_to_hpc_led_map[val]) 114 #define HPC3130_FROM_HPC_LED(val) (hpc3130_from_hpc_led_map[val]) 115 116 #define HPC3130_MAX_SLOT 0x4 117 118 #define HPC3130_TABLE_COLUMNS 3 /* number of colums in slot-table property */ 119 #define HPC3130_DEBOUNCE_COUNT 2 /* consecutive equal readings == debounced */ 120 #define HPC3130_DEBOUNCE_LIMIT 1000 /* hard upper limit on debouce code */ 121 #define HPC3130_POWER_TRIES 3 /* Try this may times to connect/disconnect */ 122 #define HPC3130_ADEQUATE_PAUSE 25000 /* usec delay for connect sequence */ 123 124 /* 125 * This structure defines an element of the controller's 126 * slot table array 127 */ 128 129 typedef struct hpc3130_slot_table_entry hpc3130_slot_table_entry_t; 130 typedef struct hpc3130_callback_arg hpc3130_callback_arg_t; 131 132 struct hpc3130_callback_arg { 133 caddr_t handle; 134 caddr_t statep; 135 uint8_t offset; 136 }; 137 138 struct hpc3130_slot_table_entry { 139 hpc_slot_info_t hpc3130_slot_info; 140 hpc_slot_t hpc3130_slot_handle; 141 char nexus[MAXNAMELEN]; 142 hpc3130_callback_arg_t callback_info; 143 }; 144 145 /* 146 * The soft state structure 147 */ 148 struct hpc3130_unit { 149 150 dev_info_t *dip; 151 152 hpc_slot_ops_t *hpc3130_slot_ops; 153 154 /* 155 * the following fields hold the value of the "slot-table" 156 * property for this controller 157 */ 158 caddr_t hpc3130_slot_table_data; 159 int hpc3130_slot_table_size; 160 161 /* 162 * the following fields represent the array of hot-plug 163 * slots derived from the "slot-table" property 164 */ 165 hpc3130_slot_table_entry_t *hpc3130_slot_table; 166 int hpc3130_slot_table_length; 167 168 /* 169 * Mutex associated with this structure 170 */ 171 kmutex_t hpc3130_mutex; 172 173 /* 174 * Trap interrupt cookie 175 */ 176 ddi_iblock_cookie_t ic_trap_cookie; 177 178 /* 179 * Open flag 180 */ 181 int hpc3130_oflag; 182 183 /* 184 * An integer field describing the type 185 * of slots (PCI/SBD). 186 */ 187 hpc3130_slot_type_t slots_are; 188 189 /* 190 * A place to put the name of this driver 191 * What gets put here is "hpc3130n" - where 192 * n is the instance number. 193 */ 194 char hpc3130_name[16]; 195 196 /* 197 * The handle within the I2C nexus that this instance 198 * represents. 199 */ 200 i2c_client_hdl_t hpc3130_hdl; 201 202 /* 203 * condition variable used to throttle power OK signal 204 */ 205 kcondvar_t hpc3130_cond; 206 207 /* 208 * Present vector - if B_TRUE there is a card in the corresponding 209 * slot. 210 */ 211 boolean_t present[HPC3130_MAX_SLOT]; 212 213 /* 214 * Power vector - if B_TRUE, then power is applied to the slot 215 */ 216 boolean_t power[HPC3130_MAX_SLOT]; 217 218 /* 219 * Enable vector - if B_TRUE the slot is enabled. 220 */ 221 boolean_t enabled[HPC3130_MAX_SLOT]; 222 223 /* 224 * LED state indicators. 225 */ 226 char fault_led[HPC3130_MAX_SLOT]; 227 char ok2rem_led[HPC3130_MAX_SLOT]; 228 229 /* For poll(9e)/ioctl(HPC3130_GET_SOFT_EVENT */ 230 uint_t events[HPC3130_MAX_SLOT]; 231 pollhead_t pollhead[HPC3130_MAX_SLOT]; 232 }; 233 234 typedef struct hpc3130_unit hpc3130_unit_t; 235 236 #endif /* _KERNEL */ 237 238 #ifdef __cplusplus 239 } 240 #endif 241 242 #endif /* _SYS_HPC3130_DAK_H */ 243