1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_MACHLOCK_H 28 #define _SYS_MACHLOCK_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifndef _ASM 33 #include <sys/types.h> 34 #include <sys/time.h> 35 #endif /* _ASM */ 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 #ifndef _ASM 42 43 #ifdef _KERNEL 44 45 extern void lock_set(lock_t *lp); 46 extern int lock_try(lock_t *lp); 47 extern int lock_spin_try(lock_t *lp); 48 extern int ulock_try(lock_t *lp); 49 extern void lock_clear(lock_t *lp); 50 extern void ulock_clear(lock_t *lp); 51 extern void lock_set_spl(lock_t *lp, int new_pil, ushort_t *old_pil); 52 extern void lock_clear_splx(lock_t *lp, int s); 53 54 #endif /* _KERNEL */ 55 56 #define LOCK_HELD_VALUE 0xff 57 #define LOCK_INIT_CLEAR(lp) (*(lp) = 0) 58 #define LOCK_INIT_HELD(lp) (*(lp) = LOCK_HELD_VALUE) 59 #define LOCK_HELD(lp) (*(volatile lock_t *)(lp) != 0) 60 61 typedef lock_t disp_lock_t; /* dispatcher lock type */ 62 63 /* 64 * SPIN_LOCK() macro indicates whether lock is implemented as a spin lock or 65 * an adaptive mutex, depending on what interrupt levels use it. 66 */ 67 #define SPIN_LOCK(pl) ((pl) > ipltospl(LOCK_LEVEL)) 68 69 /* 70 * Macro to control loops which spin on a lock and then check state 71 * periodically. Its passed an integer, and returns a boolean value 72 * that if true indicates its a good time to get the scheduler lock and 73 * check the state of the current owner of the lock. 74 */ 75 #define LOCK_SAMPLE_INTERVAL(i) (((i) & 0xff) == 0) 76 77 /* 78 * Externs for CLOCK_LOCK and clock resolution 79 */ 80 #ifdef __STDC__ 81 extern volatile int hres_lock; 82 #else 83 extern int hres_lock; 84 #endif 85 extern hrtime_t hrtime_base; 86 extern int clock_res; 87 88 #endif /* _ASM */ 89 90 /* 91 * The definitions of the symbolic interrupt levels: 92 * 93 * CLOCK_LEVEL => The level at which one must be to block the clock. 94 * 95 * LOCK_LEVEL => The highest level at which one may block (and thus the 96 * highest level at which one may acquire adaptive locks) 97 * Also the highest level at which one may be preempted. 98 * 99 * DISP_LEVEL => The level at which one must be to perform dispatcher 100 * operations. 101 * 102 * The constraints on the platform: 103 * 104 * - CLOCK_LEVEL must be less than or equal to LOCK_LEVEL 105 * - LOCK_LEVEL must be less than DISP_LEVEL 106 * - DISP_LEVEL should be as close to LOCK_LEVEL as possible 107 * 108 * Note that LOCK_LEVEL and CLOCK_LEVEL have historically always been equal; 109 * changing this relationship is probably possible but not advised. 110 * 111 */ 112 113 #define PIL_MAX 15 114 115 #define CLOCK_LEVEL 10 116 #define LOCK_LEVEL 10 117 #define DISP_LEVEL (LOCK_LEVEL + 1) 118 119 #define HIGH_LEVELS (PIL_MAX - LOCK_LEVEL) 120 121 /* 122 * The following mask is for the cpu_intr_actv bits corresponding to 123 * high-level PILs. It should equal: 124 * ((((1 << PIL_MAX + 1) - 1) >> LOCK_LEVEL + 1) << LOCK_LEVEL + 1) 125 */ 126 #define CPU_INTR_ACTV_HIGH_LEVEL_MASK 0xF800 127 128 /* 129 * The semaphore code depends on being able to represent a lock plus 130 * owner in a single 32-bit word. (Mutexes used to have a similar 131 * dependency, but no longer.) Thus the owner must contain at most 132 * 24 significant bits. At present only threads and semaphores 133 * must be aware of this vile constraint. Different ISAs may handle this 134 * differently depending on their capabilities (e.g. compare-and-swap) 135 * and limitations (e.g. constraints on alignment and/or KERNELBASE). 136 */ 137 #define PTR24_LSB 5 /* lower bits all zero */ 138 #define PTR24_MSB (PTR24_LSB + 24) /* upper bits all one */ 139 #define PTR24_ALIGN 32 /* minimum alignment (1 << lsb) */ 140 #define PTR24_BASE 0xe0000000 /* minimum ptr value (-1 >> (32-msb)) */ 141 142 #ifdef __cplusplus 143 } 144 #endif 145 146 #endif /* _SYS_MACHLOCK_H */ 147