xref: /titanic_44/usr/src/uts/intel/io/pci/pci_boot.c (revision a60349c89adffc0902b2353230891d8e7f2b24d9)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23  * Copyright 2016 Joyent, Inc.
24  */
25 
26 #include <sys/types.h>
27 #include <sys/stat.h>
28 #include <sys/sysmacros.h>
29 #include <sys/sunndi.h>
30 #include <sys/pci.h>
31 #include <sys/pci_impl.h>
32 #include <sys/pcie_impl.h>
33 #include <sys/memlist.h>
34 #include <sys/bootconf.h>
35 #include <io/pci/mps_table.h>
36 #include <sys/pci_cfgacc.h>
37 #include <sys/pci_cfgspace.h>
38 #include <sys/pci_cfgspace_impl.h>
39 #include <sys/psw.h>
40 #include "../../../../common/pci/pci_strings.h"
41 #include <sys/apic.h>
42 #include <io/pciex/pcie_nvidia.h>
43 #include <sys/hotplug/pci/pciehpc_acpi.h>
44 #include <sys/acpi/acpi.h>
45 #include <sys/acpica.h>
46 #include <sys/iommulib.h>
47 #include <sys/devcache.h>
48 #include <sys/pci_cfgacc_x86.h>
49 
50 #define	pci_getb	(*pci_getb_func)
51 #define	pci_getw	(*pci_getw_func)
52 #define	pci_getl	(*pci_getl_func)
53 #define	pci_putb	(*pci_putb_func)
54 #define	pci_putw	(*pci_putw_func)
55 #define	pci_putl	(*pci_putl_func)
56 #define	dcmn_err	if (pci_boot_debug) cmn_err
57 
58 #define	CONFIG_INFO	0
59 #define	CONFIG_UPDATE	1
60 #define	CONFIG_NEW	2
61 #define	CONFIG_FIX	3
62 #define	COMPAT_BUFSIZE	512
63 
64 #define	PPB_IO_ALIGNMENT	0x1000		/* 4K aligned */
65 #define	PPB_MEM_ALIGNMENT	0x100000	/* 1M aligned */
66 /* round down to nearest power of two */
67 #define	P2LE(align)					\
68 	{						\
69 		int i = 0;				\
70 		while (align >>= 1)			\
71 			i ++;				\
72 		align = 1 << i;				\
73 	}						\
74 
75 /* for is_vga and list_is_vga_only */
76 
77 enum io_mem {
78 	IO,
79 	MEM
80 };
81 
82 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */
83 #define	LPC_IO_CONTROL_REG_1	0x40
84 #define	AMD8111_ENABLENMI	(uint8_t)0x80
85 #define	DEVID_AMD8111_LPC	0x7468
86 
87 struct pci_fixundo {
88 	uint8_t			bus;
89 	uint8_t			dev;
90 	uint8_t			fn;
91 	void			(*undofn)(uint8_t, uint8_t, uint8_t);
92 	struct pci_fixundo	*next;
93 };
94 
95 struct pci_devfunc {
96 	struct pci_devfunc *next;
97 	dev_info_t *dip;
98 	uchar_t dev;
99 	uchar_t func;
100 	boolean_t reprogram;	/* this device needs to be reprogrammed */
101 };
102 
103 extern int apic_nvidia_io_max;
104 extern int pseudo_isa;
105 extern int pci_bios_maxbus;
106 static uchar_t max_dev_pci = 32;	/* PCI standard */
107 int pci_boot_debug = 0;
108 extern struct memlist *find_bus_res(int, int);
109 static struct pci_fixundo *undolist = NULL;
110 static int num_root_bus = 0;	/* count of root buses */
111 extern volatile int acpi_resource_discovery;
112 extern uint64_t mcfg_mem_base;
113 extern void pci_cfgacc_add_workaround(uint16_t, uchar_t, uchar_t);
114 extern dev_info_t *pcie_get_rc_dip(dev_info_t *);
115 
116 /*
117  * Module prototypes
118  */
119 static void enumerate_bus_devs(uchar_t bus, int config_op);
120 static void create_root_bus_dip(uchar_t bus);
121 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t,
122     ushort_t, int);
123 static void add_compatible(dev_info_t *, ushort_t, ushort_t,
124     ushort_t, ushort_t, uchar_t, uint_t, int);
125 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int);
126 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int,
127     ushort_t);
128 static void add_model_prop(dev_info_t *, uint_t);
129 static void add_bus_range_prop(int);
130 static void add_bus_slot_names_prop(int);
131 static void add_ranges_prop(int, int);
132 static void add_bus_available_prop(int);
133 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id);
134 static void fix_ppb_res(uchar_t, boolean_t);
135 static void alloc_res_array();
136 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
137     ushort_t deviceid);
138 static void pciex_slot_names_prop(dev_info_t *, ushort_t);
139 static void populate_bus_res(uchar_t bus);
140 static void memlist_remove_list(struct memlist **list,
141     struct memlist *remove_list);
142 static void ck804_fix_aer_ptr(dev_info_t *, pcie_req_id_t);
143 
144 static void pci_scan_bbn(void);
145 static int pci_unitaddr_cache_valid(void);
146 static int pci_bus_unitaddr(int);
147 static void pci_unitaddr_cache_create(void);
148 
149 static int pci_cache_unpack_nvlist(nvf_handle_t, nvlist_t *, char *);
150 static int pci_cache_pack_nvlist(nvf_handle_t, nvlist_t **);
151 static void pci_cache_free_list(nvf_handle_t);
152 
153 extern int pci_slot_names_prop(int, char *, int);
154 
155 /* set non-zero to force PCI peer-bus renumbering */
156 int pci_bus_always_renumber = 0;
157 
158 /*
159  * used to register ISA resource usage which must not be made
160  * "available" from other PCI node' resource maps
161  */
162 static struct {
163 	struct memlist *io_used;
164 	struct memlist *mem_used;
165 } isa_res;
166 
167 /*
168  * PCI unit-address cache management
169  */
170 static nvf_ops_t pci_unitaddr_cache_ops = {
171 	"/etc/devices/pci_unitaddr_persistent",	/* path to cache */
172 	pci_cache_unpack_nvlist,		/* read in nvlist form */
173 	pci_cache_pack_nvlist,			/* convert to nvlist form */
174 	pci_cache_free_list,			/* free data list */
175 	NULL					/* write complete callback */
176 };
177 
178 typedef struct {
179 	list_node_t	pua_nodes;
180 	int		pua_index;
181 	int		pua_addr;
182 } pua_node_t;
183 
184 nvf_handle_t	puafd_handle;
185 int		pua_cache_valid = 0;
186 
187 
188 /*ARGSUSED*/
189 static ACPI_STATUS
190 pci_process_acpi_device(ACPI_HANDLE hdl, UINT32 level, void *ctx, void **rv)
191 {
192 	ACPI_BUFFER	rb;
193 	ACPI_OBJECT	ro;
194 	ACPI_DEVICE_INFO *adi;
195 	int		busnum;
196 
197 	/*
198 	 * Use AcpiGetObjectInfo() to find the device _HID
199 	 * If not a PCI root-bus, ignore this device and continue
200 	 * the walk
201 	 */
202 	if (ACPI_FAILURE(AcpiGetObjectInfo(hdl, &adi)))
203 		return (AE_OK);
204 
205 	if (!(adi->Valid & ACPI_VALID_HID)) {
206 		AcpiOsFree(adi);
207 		return (AE_OK);
208 	}
209 
210 	if (strncmp(adi->HardwareId.String, PCI_ROOT_HID_STRING,
211 	    sizeof (PCI_ROOT_HID_STRING)) &&
212 	    strncmp(adi->HardwareId.String, PCI_EXPRESS_ROOT_HID_STRING,
213 	    sizeof (PCI_EXPRESS_ROOT_HID_STRING))) {
214 		AcpiOsFree(adi);
215 		return (AE_OK);
216 	}
217 
218 	AcpiOsFree(adi);
219 
220 	/*
221 	 * XXX: ancient Big Bear broken _BBN will result in two
222 	 * bus 0 _BBNs being found, so we need to handle duplicate
223 	 * bus 0 gracefully.  However, broken _BBN does not
224 	 * hide a childless root-bridge so no need to work-around it
225 	 * here
226 	 */
227 	rb.Pointer = &ro;
228 	rb.Length = sizeof (ro);
229 	if (ACPI_SUCCESS(AcpiEvaluateObjectTyped(hdl, "_BBN",
230 	    NULL, &rb, ACPI_TYPE_INTEGER))) {
231 		busnum = ro.Integer.Value;
232 
233 		/*
234 		 * Ignore invalid _BBN return values here (rather
235 		 * than panic) and emit a warning; something else
236 		 * may suffer failure as a result of the broken BIOS.
237 		 */
238 		if ((busnum < 0) || (busnum > pci_bios_maxbus)) {
239 			dcmn_err(CE_NOTE,
240 			    "pci_process_acpi_device: invalid _BBN 0x%x\n",
241 			    busnum);
242 			return (AE_CTRL_DEPTH);
243 		}
244 
245 		/* PCI with valid _BBN */
246 		if (pci_bus_res[busnum].par_bus == (uchar_t)-1 &&
247 		    pci_bus_res[busnum].dip == NULL)
248 			create_root_bus_dip((uchar_t)busnum);
249 		return (AE_CTRL_DEPTH);
250 	}
251 
252 	/* PCI and no _BBN, continue walk */
253 	return (AE_OK);
254 }
255 
256 /*
257  * Scan the ACPI namespace for all top-level instances of _BBN
258  * in order to discover childless root-bridges (which enumeration
259  * may not find; root-bridges are inferred by the existence of
260  * children).  This scan should find all root-bridges that have
261  * been enumerated, and any childless root-bridges not enumerated.
262  * Root-bridge for bus 0 may not have a _BBN object.
263  */
264 static void
265 pci_scan_bbn()
266 {
267 	void *rv;
268 
269 	(void) AcpiGetDevices(NULL, pci_process_acpi_device, NULL, &rv);
270 }
271 
272 static void
273 pci_unitaddr_cache_init(void)
274 {
275 
276 	puafd_handle = nvf_register_file(&pci_unitaddr_cache_ops);
277 	ASSERT(puafd_handle);
278 
279 	list_create(nvf_list(puafd_handle), sizeof (pua_node_t),
280 	    offsetof(pua_node_t, pua_nodes));
281 
282 	rw_enter(nvf_lock(puafd_handle), RW_WRITER);
283 	(void) nvf_read_file(puafd_handle);
284 	rw_exit(nvf_lock(puafd_handle));
285 }
286 
287 /*
288  * Format of /etc/devices/pci_unitaddr_persistent:
289  *
290  * The persistent record of unit-address assignments contains
291  * a list of name/value pairs, where name is a string representation
292  * of the "index value" of the PCI root-bus and the value is
293  * the assigned unit-address.
294  *
295  * The "index value" is simply the zero-based index of the PCI
296  * root-buses ordered by physical bus number; first PCI bus is 0,
297  * second is 1, and so on.
298  */
299 
300 /*ARGSUSED*/
301 static int
302 pci_cache_unpack_nvlist(nvf_handle_t hdl, nvlist_t *nvl, char *name)
303 {
304 	long		index;
305 	int32_t		value;
306 	nvpair_t	*np;
307 	pua_node_t	*node;
308 
309 	np = NULL;
310 	while ((np = nvlist_next_nvpair(nvl, np)) != NULL) {
311 		/* name of nvpair is index value */
312 		if (ddi_strtol(nvpair_name(np), NULL, 10, &index) != 0)
313 			continue;
314 
315 		if (nvpair_value_int32(np, &value) != 0)
316 			continue;
317 
318 		node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP);
319 		node->pua_index = index;
320 		node->pua_addr = value;
321 		list_insert_tail(nvf_list(hdl), node);
322 	}
323 
324 	pua_cache_valid = 1;
325 	return (DDI_SUCCESS);
326 }
327 
328 static int
329 pci_cache_pack_nvlist(nvf_handle_t hdl, nvlist_t **ret_nvl)
330 {
331 	int		rval;
332 	nvlist_t	*nvl, *sub_nvl;
333 	list_t		*listp;
334 	pua_node_t	*pua;
335 	char		buf[13];
336 
337 	ASSERT(RW_WRITE_HELD(nvf_lock(hdl)));
338 
339 	rval = nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP);
340 	if (rval != DDI_SUCCESS) {
341 		nvf_error("%s: nvlist alloc error %d\n",
342 		    nvf_cache_name(hdl), rval);
343 		return (DDI_FAILURE);
344 	}
345 
346 	sub_nvl = NULL;
347 	rval = nvlist_alloc(&sub_nvl, NV_UNIQUE_NAME, KM_SLEEP);
348 	if (rval != DDI_SUCCESS)
349 		goto error;
350 
351 	listp = nvf_list(hdl);
352 	for (pua = list_head(listp); pua != NULL;
353 	    pua = list_next(listp, pua)) {
354 		(void) snprintf(buf, sizeof (buf), "%d", pua->pua_index);
355 		rval = nvlist_add_int32(sub_nvl, buf, pua->pua_addr);
356 		if (rval != DDI_SUCCESS)
357 			goto error;
358 	}
359 
360 	rval = nvlist_add_nvlist(nvl, "table", sub_nvl);
361 	if (rval != DDI_SUCCESS)
362 		goto error;
363 	nvlist_free(sub_nvl);
364 
365 	*ret_nvl = nvl;
366 	return (DDI_SUCCESS);
367 
368 error:
369 	if (sub_nvl)
370 		nvlist_free(sub_nvl);
371 	ASSERT(nvl);
372 	nvlist_free(nvl);
373 	*ret_nvl = NULL;
374 	return (DDI_FAILURE);
375 }
376 
377 static void
378 pci_cache_free_list(nvf_handle_t hdl)
379 {
380 	list_t		*listp;
381 	pua_node_t	*pua;
382 
383 	ASSERT(RW_WRITE_HELD(nvf_lock(hdl)));
384 
385 	listp = nvf_list(hdl);
386 	for (pua = list_head(listp); pua != NULL;
387 	    pua = list_next(listp, pua)) {
388 		list_remove(listp, pua);
389 		kmem_free(pua, sizeof (pua_node_t));
390 	}
391 }
392 
393 
394 static int
395 pci_unitaddr_cache_valid(void)
396 {
397 
398 	/* read only, no need for rw lock */
399 	return (pua_cache_valid);
400 }
401 
402 
403 static int
404 pci_bus_unitaddr(int index)
405 {
406 	pua_node_t	*pua;
407 	list_t		*listp;
408 	int		addr;
409 
410 	rw_enter(nvf_lock(puafd_handle), RW_READER);
411 
412 	addr = -1;	/* default return if no match */
413 	listp = nvf_list(puafd_handle);
414 	for (pua = list_head(listp); pua != NULL;
415 	    pua = list_next(listp, pua)) {
416 		if (pua->pua_index == index) {
417 			addr = pua->pua_addr;
418 			break;
419 		}
420 	}
421 
422 	rw_exit(nvf_lock(puafd_handle));
423 	return (addr);
424 }
425 
426 static void
427 pci_unitaddr_cache_create(void)
428 {
429 	int		i, index;
430 	pua_node_t	*node;
431 	list_t		*listp;
432 
433 	rw_enter(nvf_lock(puafd_handle), RW_WRITER);
434 
435 	index = 0;
436 	listp = nvf_list(puafd_handle);
437 	for (i = 0; i <= pci_bios_maxbus; i++) {
438 		/* skip non-root (peer) PCI busses */
439 		if ((pci_bus_res[i].par_bus != (uchar_t)-1) ||
440 		    (pci_bus_res[i].dip == NULL))
441 			continue;
442 		node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP);
443 		node->pua_index = index++;
444 		node->pua_addr = pci_bus_res[i].root_addr;
445 		list_insert_tail(listp, node);
446 	}
447 
448 	(void) nvf_mark_dirty(puafd_handle);
449 	rw_exit(nvf_lock(puafd_handle));
450 	nvf_wake_daemon();
451 }
452 
453 
454 /*
455  * Enumerate all PCI devices
456  */
457 void
458 pci_setup_tree(void)
459 {
460 	uint_t i, root_bus_addr = 0;
461 
462 	alloc_res_array();
463 	for (i = 0; i <= pci_bios_maxbus; i++) {
464 		pci_bus_res[i].par_bus = (uchar_t)-1;
465 		pci_bus_res[i].root_addr = (uchar_t)-1;
466 		pci_bus_res[i].sub_bus = i;
467 	}
468 
469 	pci_bus_res[0].root_addr = root_bus_addr++;
470 	create_root_bus_dip(0);
471 	enumerate_bus_devs(0, CONFIG_INFO);
472 
473 	/*
474 	 * Now enumerate peer busses
475 	 *
476 	 * We loop till pci_bios_maxbus. On most systems, there is
477 	 * one more bus at the high end, which implements the ISA
478 	 * compatibility bus. We don't care about that.
479 	 *
480 	 * Note: In the old (bootconf) enumeration, the peer bus
481 	 *	address did not use the bus number, and there were
482 	 *	too many peer busses created. The root_bus_addr is
483 	 *	used to maintain the old peer bus address assignment.
484 	 *	However, we stop enumerating phantom peers with no
485 	 *	device below.
486 	 */
487 	for (i = 1; i <= pci_bios_maxbus; i++) {
488 		if (pci_bus_res[i].dip == NULL) {
489 			pci_bus_res[i].root_addr = root_bus_addr++;
490 		}
491 		enumerate_bus_devs(i, CONFIG_INFO);
492 
493 		/* add slot-names property for named pci hot-plug slots */
494 		add_bus_slot_names_prop(i);
495 	}
496 }
497 
498 /*
499  * >0 = present, 0 = not present, <0 = error
500  */
501 static int
502 pci_bbn_present(int bus)
503 {
504 	ACPI_HANDLE	hdl;
505 	int	rv;
506 
507 	/* no dip means no _BBN */
508 	if (pci_bus_res[bus].dip == NULL)
509 		return (0);
510 
511 	rv = -1;	/* default return value in case of error below */
512 	if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) {
513 		switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) {
514 		case AE_OK:
515 			rv = 1;
516 			break;
517 		case AE_NOT_FOUND:
518 			rv = 0;
519 			break;
520 		default:
521 			break;
522 		}
523 	}
524 
525 	return (rv);
526 }
527 
528 /*
529  * Return non-zero if any PCI bus in the system has an associated
530  * _BBN object, 0 otherwise.
531  */
532 static int
533 pci_roots_have_bbn(void)
534 {
535 	int	i;
536 
537 	/*
538 	 * Scan the PCI busses and look for at least 1 _BBN
539 	 */
540 	for (i = 0; i <= pci_bios_maxbus; i++) {
541 		/* skip non-root (peer) PCI busses */
542 		if (pci_bus_res[i].par_bus != (uchar_t)-1)
543 			continue;
544 
545 		if (pci_bbn_present(i) > 0)
546 			return (1);
547 	}
548 	return (0);
549 
550 }
551 
552 /*
553  * return non-zero if the machine is one on which we renumber
554  * the internal pci unit-addresses
555  */
556 static int
557 pci_bus_renumber()
558 {
559 	ACPI_TABLE_HEADER *fadt;
560 
561 	if (pci_bus_always_renumber)
562 		return (1);
563 
564 	/* get the FADT */
565 	if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) !=
566 	    AE_OK)
567 		return (0);
568 
569 	/* compare OEM Table ID to "SUNm31" */
570 	if (strncmp("SUNm31", fadt->OemId, 6))
571 		return (0);
572 	else
573 		return (1);
574 }
575 
576 /*
577  * Initial enumeration of the physical PCI bus hierarchy can
578  * leave 'gaps' in the order of peer PCI bus unit-addresses.
579  * Systems with more than one peer PCI bus *must* have an ACPI
580  * _BBN object associated with each peer bus; use the presence
581  * of this object to remove gaps in the numbering of the peer
582  * PCI bus unit-addresses - only peer busses with an associated
583  * _BBN are counted.
584  */
585 static void
586 pci_renumber_root_busses(void)
587 {
588 	int pci_regs[] = {0, 0, 0};
589 	int	i, root_addr = 0;
590 
591 	/*
592 	 * Currently, we only enable the re-numbering on specific
593 	 * Sun machines; this is a work-around for the more complicated
594 	 * issue of upgrade changing physical device paths
595 	 */
596 	if (!pci_bus_renumber())
597 		return;
598 
599 	/*
600 	 * If we find no _BBN objects at all, we either don't need
601 	 * to do anything or can't do anything anyway
602 	 */
603 	if (!pci_roots_have_bbn())
604 		return;
605 
606 	for (i = 0; i <= pci_bios_maxbus; i++) {
607 		/* skip non-root (peer) PCI busses */
608 		if (pci_bus_res[i].par_bus != (uchar_t)-1)
609 			continue;
610 
611 		if (pci_bbn_present(i) < 1) {
612 			pci_bus_res[i].root_addr = (uchar_t)-1;
613 			continue;
614 		}
615 
616 		ASSERT(pci_bus_res[i].dip != NULL);
617 		if (pci_bus_res[i].root_addr != root_addr) {
618 			/* update reg property for node */
619 			pci_bus_res[i].root_addr = root_addr;
620 			pci_regs[0] = pci_bus_res[i].root_addr;
621 			(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
622 			    pci_bus_res[i].dip, "reg", (int *)pci_regs, 3);
623 		}
624 		root_addr++;
625 	}
626 }
627 
628 void
629 pci_register_isa_resources(int type, uint32_t base, uint32_t size)
630 {
631 	(void) memlist_insert(
632 	    (type == 1) ?  &isa_res.io_used : &isa_res.mem_used,
633 	    base, size);
634 }
635 
636 /*
637  * Remove the resources which are already used by devices under a subtractive
638  * bridge from the bus's resources lists, because they're not available, and
639  * shouldn't be allocated to other buses.  This is necessary because tracking
640  * resources for subtractive bridges is not complete.  (Subtractive bridges only
641  * track some of their claimed resources, not "the rest of the address space" as
642  * they should, so that allocation to peer non-subtractive PPBs is easier.  We
643  * need a fully-capable global resource allocator).
644  */
645 static void
646 remove_subtractive_res()
647 {
648 	int i, j;
649 	struct memlist *list;
650 
651 	for (i = 0; i <= pci_bios_maxbus; i++) {
652 		if (pci_bus_res[i].subtractive) {
653 			/* remove used io ports */
654 			list = pci_bus_res[i].io_used;
655 			while (list) {
656 				for (j = 0; j <= pci_bios_maxbus; j++)
657 					(void) memlist_remove(
658 					    &pci_bus_res[j].io_avail,
659 					    list->ml_address, list->ml_size);
660 				list = list->ml_next;
661 			}
662 			/* remove used mem resource */
663 			list = pci_bus_res[i].mem_used;
664 			while (list) {
665 				for (j = 0; j <= pci_bios_maxbus; j++) {
666 					(void) memlist_remove(
667 					    &pci_bus_res[j].mem_avail,
668 					    list->ml_address, list->ml_size);
669 					(void) memlist_remove(
670 					    &pci_bus_res[j].pmem_avail,
671 					    list->ml_address, list->ml_size);
672 				}
673 				list = list->ml_next;
674 			}
675 			/* remove used prefetchable mem resource */
676 			list = pci_bus_res[i].pmem_used;
677 			while (list) {
678 				for (j = 0; j <= pci_bios_maxbus; j++) {
679 					(void) memlist_remove(
680 					    &pci_bus_res[j].pmem_avail,
681 					    list->ml_address, list->ml_size);
682 					(void) memlist_remove(
683 					    &pci_bus_res[j].mem_avail,
684 					    list->ml_address, list->ml_size);
685 				}
686 				list = list->ml_next;
687 			}
688 		}
689 	}
690 }
691 
692 /*
693  * Set up (or complete the setup of) the bus_avail resource list
694  */
695 static void
696 setup_bus_res(int bus)
697 {
698 	uchar_t par_bus;
699 
700 	if (pci_bus_res[bus].dip == NULL)	/* unused bus */
701 		return;
702 
703 	/*
704 	 * Set up bus_avail if not already filled in by populate_bus_res()
705 	 */
706 	if (pci_bus_res[bus].bus_avail == NULL) {
707 		ASSERT(pci_bus_res[bus].sub_bus >= bus);
708 		memlist_insert(&pci_bus_res[bus].bus_avail, bus,
709 		    pci_bus_res[bus].sub_bus - bus + 1);
710 	}
711 
712 	ASSERT(pci_bus_res[bus].bus_avail != NULL);
713 
714 	/*
715 	 * Remove resources from parent bus node if this is not a
716 	 * root bus.
717 	 */
718 	par_bus = pci_bus_res[bus].par_bus;
719 	if (par_bus != (uchar_t)-1) {
720 		ASSERT(pci_bus_res[par_bus].bus_avail != NULL);
721 		memlist_remove_list(&pci_bus_res[par_bus].bus_avail,
722 		    pci_bus_res[bus].bus_avail);
723 	}
724 
725 	/* remove self from bus_avail */;
726 	(void) memlist_remove(&pci_bus_res[bus].bus_avail, bus, 1);
727 }
728 
729 static uint64_t
730 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
731 {
732 	uint64_t addr = 0;
733 	uchar_t res_bus;
734 
735 	/*
736 	 * Skip root(peer) buses in multiple-root-bus systems when
737 	 * ACPI resource discovery was not successfully done.
738 	 */
739 	if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) &&
740 	    (num_root_bus > 1) && (acpi_resource_discovery <= 0))
741 		return (0);
742 
743 	res_bus = parbus;
744 	while (pci_bus_res[res_bus].subtractive) {
745 		if (pci_bus_res[res_bus].io_avail)
746 			break;
747 		res_bus = pci_bus_res[res_bus].par_bus;
748 		if (res_bus == (uchar_t)-1)
749 			break; /* root bus already */
750 	}
751 
752 	if (pci_bus_res[res_bus].io_avail) {
753 		addr = memlist_find(&pci_bus_res[res_bus].io_avail,
754 		    size, align);
755 		if (addr) {
756 			memlist_insert(&pci_bus_res[res_bus].io_used,
757 			    addr, size);
758 
759 			/* free the old resource */
760 			memlist_free_all(&pci_bus_res[bus].io_avail);
761 			memlist_free_all(&pci_bus_res[bus].io_used);
762 
763 			/* add the new resource */
764 			memlist_insert(&pci_bus_res[bus].io_avail, addr, size);
765 		}
766 	}
767 
768 	return (addr);
769 }
770 
771 static uint64_t
772 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
773 {
774 	uint64_t addr = 0;
775 	uchar_t res_bus;
776 
777 	/*
778 	 * Skip root(peer) buses in multiple-root-bus systems when
779 	 * ACPI resource discovery was not successfully done.
780 	 */
781 	if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) &&
782 	    (num_root_bus > 1) && (acpi_resource_discovery <= 0))
783 		return (0);
784 
785 	res_bus = parbus;
786 	while (pci_bus_res[res_bus].subtractive) {
787 		if (pci_bus_res[res_bus].mem_avail)
788 			break;
789 		res_bus = pci_bus_res[res_bus].par_bus;
790 		if (res_bus == (uchar_t)-1)
791 			break; /* root bus already */
792 	}
793 
794 	if (pci_bus_res[res_bus].mem_avail) {
795 		addr = memlist_find(&pci_bus_res[res_bus].mem_avail,
796 		    size, align);
797 		if (addr) {
798 			memlist_insert(&pci_bus_res[res_bus].mem_used,
799 			    addr, size);
800 			(void) memlist_remove(&pci_bus_res[res_bus].pmem_avail,
801 			    addr, size);
802 
803 			/* free the old resource */
804 			memlist_free_all(&pci_bus_res[bus].mem_avail);
805 			memlist_free_all(&pci_bus_res[bus].mem_used);
806 
807 			/* add the new resource */
808 			memlist_insert(&pci_bus_res[bus].mem_avail, addr, size);
809 		}
810 	}
811 
812 	return (addr);
813 }
814 
815 /*
816  * given a cap_id, return its cap_id location in config space
817  */
818 static int
819 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id)
820 {
821 	uint8_t curcap, cap_id_loc;
822 	uint16_t status;
823 	int location = -1;
824 
825 	/*
826 	 * Need to check the Status register for ECP support first.
827 	 * Also please note that for type 1 devices, the
828 	 * offset could change. Should support type 1 next.
829 	 */
830 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
831 	if (!(status & PCI_STAT_CAP)) {
832 		return (-1);
833 	}
834 	cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
835 
836 	/* Walk the list of capabilities */
837 	while (cap_id_loc && cap_id_loc != (uint8_t)-1) {
838 		curcap = pci_getb(bus, dev, func, cap_id_loc);
839 
840 		if (curcap == cap_id) {
841 			location = cap_id_loc;
842 			break;
843 		}
844 		cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1);
845 	}
846 	return (location);
847 }
848 
849 /*
850  * Does this resource element live in the legacy VGA range?
851  */
852 
853 int
854 is_vga(struct memlist *elem, enum io_mem io)
855 {
856 
857 	if (io == IO) {
858 		if ((elem->ml_address == 0x3b0 && elem->ml_size == 0xc) ||
859 		    (elem->ml_address == 0x3c0 && elem->ml_size == 0x20))
860 			return (1);
861 	} else {
862 		if (elem->ml_address == 0xa0000 && elem->ml_size == 0x20000)
863 			return (1);
864 	}
865 	return (0);
866 }
867 
868 /*
869  * Does this entire resource list consist only of legacy VGA resources?
870  */
871 
872 int
873 list_is_vga_only(struct memlist *l, enum io_mem io)
874 {
875 	do {
876 		if (!is_vga(l, io))
877 			return (0);
878 	} while ((l = l->ml_next) != NULL);
879 	return (1);
880 }
881 
882 /*
883  * Assign valid resources to unconfigured pci(e) bridges. We are trying
884  * to reprogram the bridge when its
885  * 		i)   SECBUS == SUBBUS	||
886  * 		ii)  IOBASE > IOLIM	||
887  * 		iii) MEMBASE > MEMLIM
888  * This must be done after one full pass through the PCI tree to collect
889  * all BIOS-configured resources, so that we know what resources are
890  * free and available to assign to the unconfigured PPBs.
891  */
892 static void
893 fix_ppb_res(uchar_t secbus, boolean_t prog_sub)
894 {
895 	uchar_t bus, dev, func;
896 	uchar_t parbus, subbus;
897 	uint_t io_base, io_limit, mem_base, mem_limit;
898 	uint_t io_size, mem_size, io_align, mem_align;
899 	uint64_t addr = 0;
900 	int *regp = NULL;
901 	uint_t reglen;
902 	int rv, cap_ptr, physhi;
903 	dev_info_t *dip;
904 	uint16_t cmd_reg;
905 	struct memlist *list, *scratch_list;
906 
907 	/* skip root (peer) PCI busses */
908 	if (pci_bus_res[secbus].par_bus == (uchar_t)-1)
909 		return;
910 
911 	/* skip subtractive PPB when prog_sub is not TRUE */
912 	if (pci_bus_res[secbus].subtractive && !prog_sub)
913 		return;
914 
915 	/* some entries may be empty due to discontiguous bus numbering */
916 	dip = pci_bus_res[secbus].dip;
917 	if (dip == NULL)
918 		return;
919 
920 	rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
921 	    "reg", &regp, &reglen);
922 	if (rv != DDI_PROP_SUCCESS || reglen == 0)
923 		return;
924 	physhi = regp[0];
925 	ddi_prop_free(regp);
926 
927 	func = (uchar_t)PCI_REG_FUNC_G(physhi);
928 	dev = (uchar_t)PCI_REG_DEV_G(physhi);
929 	bus = (uchar_t)PCI_REG_BUS_G(physhi);
930 
931 	/*
932 	 * If pcie bridge, check to see if link is enabled
933 	 */
934 	cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E);
935 	if (cap_ptr != -1) {
936 		cmd_reg = pci_getw(bus, dev, func,
937 		    (uint16_t)cap_ptr + PCIE_LINKCTL);
938 		if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) {
939 			dcmn_err(CE_NOTE,
940 			    "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n",
941 			    bus, dev, func);
942 			return;
943 		}
944 	}
945 
946 	subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
947 	parbus = pci_bus_res[secbus].par_bus;
948 	ASSERT(parbus == bus);
949 	cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM);
950 
951 	/*
952 	 * If we have a Cardbus bridge, but no bus space
953 	 */
954 	if (pci_bus_res[secbus].num_cbb != 0 &&
955 	    pci_bus_res[secbus].bus_avail == NULL) {
956 		uchar_t range;
957 
958 		/* normally there are 2 buses under a cardbus bridge */
959 		range = pci_bus_res[secbus].num_cbb * 2;
960 
961 		/*
962 		 * Try to find and allocate a bus-range starting at subbus+1
963 		 * from the parent of the PPB.
964 		 */
965 		for (; range != 0; range--) {
966 			if (memlist_find_with_startaddr(
967 			    &pci_bus_res[parbus].bus_avail,
968 			    subbus + 1, range, 1) != NULL)
969 				break; /* find bus range resource at parent */
970 		}
971 		if (range != 0) {
972 			memlist_insert(&pci_bus_res[secbus].bus_avail,
973 			    subbus + 1, range);
974 			subbus = subbus + range;
975 			pci_bus_res[secbus].sub_bus = subbus;
976 			pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus);
977 			add_bus_range_prop(secbus);
978 
979 			cmn_err(CE_NOTE, "!reprogram bus-range on ppb"
980 			    "[%x/%x/%x]: %x ~ %x\n", bus, dev, func,
981 			    secbus, subbus);
982 		}
983 	}
984 
985 	/*
986 	 * Calculate required IO size and alignment
987 	 * If bus io_size is zero, we are going to assign 512 bytes per bus,
988 	 * otherwise, we'll choose the maximum value of such calculation and
989 	 * bus io_size. The size needs to be 4K aligned.
990 	 *
991 	 * We calculate alignment as the largest power of two less than the
992 	 * the sum of all children's IO size requirements, because this will
993 	 * align to the size of the largest child request within that size
994 	 * (which is always a power of two).
995 	 */
996 	io_size = (subbus - secbus + 1) * 0x200;
997 	if (io_size <  pci_bus_res[secbus].io_size)
998 		io_size = pci_bus_res[secbus].io_size;
999 	io_size = P2ROUNDUP(io_size, PPB_IO_ALIGNMENT);
1000 	io_align = io_size;
1001 	P2LE(io_align);
1002 
1003 	/*
1004 	 * Calculate required MEM size and alignment
1005 	 * If bus mem_size is zero, we are going to assign 1M bytes per bus,
1006 	 * otherwise, we'll choose the maximum value of such calculation and
1007 	 * bus mem_size. The size needs to be 1M aligned.
1008 	 *
1009 	 * For the alignment, refer to the I/O comment above.
1010 	 */
1011 	mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT;
1012 	if (mem_size < pci_bus_res[secbus].mem_size) {
1013 		mem_size = pci_bus_res[secbus].mem_size;
1014 		mem_size = P2ROUNDUP(mem_size, PPB_MEM_ALIGNMENT);
1015 	}
1016 	mem_align = mem_size;
1017 	P2LE(mem_align);
1018 
1019 	/* Subtractive bridge */
1020 	if (pci_bus_res[secbus].subtractive && prog_sub) {
1021 		/*
1022 		 * We program an arbitrary amount of I/O and memory resource
1023 		 * for the subtractive bridge so that child dynamic-resource-
1024 		 * allocating devices (such as Cardbus bridges) have a chance
1025 		 * of success.  Until we have full-tree resource rebalancing,
1026 		 * dynamic resource allocation (thru busra) only looks at the
1027 		 * parent bridge, so all PPBs must have some allocatable
1028 		 * resource.  For non-subtractive bridges, the resources come
1029 		 * from the base/limit register "windows", but subtractive
1030 		 * bridges often don't program those (since they don't need to).
1031 		 * If we put all the remaining resources on the subtractive
1032 		 * bridge, then peer non-subtractive bridges can't allocate
1033 		 * more space (even though this is probably most correct).
1034 		 * If we put the resources only on the parent, then allocations
1035 		 * from children of subtractive bridges will fail without
1036 		 * special-case code for bypassing the subtractive bridge.
1037 		 * This solution is the middle-ground temporary solution until
1038 		 * we have fully-capable resource allocation.
1039 		 */
1040 
1041 		/*
1042 		 * Add an arbitrary I/O resource to the subtractive PPB
1043 		 */
1044 		if (pci_bus_res[secbus].io_avail == NULL) {
1045 			addr = get_parbus_io_res(parbus, secbus, io_size,
1046 			    io_align);
1047 			if (addr) {
1048 				add_ranges_prop(secbus, 1);
1049 				pci_bus_res[secbus].io_reprogram =
1050 				    pci_bus_res[parbus].io_reprogram;
1051 
1052 				cmn_err(CE_NOTE, "!add io-range on subtractive"
1053 				    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
1054 				    bus, dev, func, (uint32_t)addr,
1055 				    (uint32_t)addr + io_size - 1);
1056 			}
1057 		}
1058 		/*
1059 		 * Add an arbitrary memory resource to the subtractive PPB
1060 		 */
1061 		if (pci_bus_res[secbus].mem_avail == NULL) {
1062 			addr = get_parbus_mem_res(parbus, secbus, mem_size,
1063 			    mem_align);
1064 			if (addr) {
1065 				add_ranges_prop(secbus, 1);
1066 				pci_bus_res[secbus].mem_reprogram =
1067 				    pci_bus_res[parbus].mem_reprogram;
1068 
1069 				cmn_err(CE_NOTE, "!add mem-range on "
1070 				    "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
1071 				    bus, dev, func, (uint32_t)addr,
1072 				    (uint32_t)addr + mem_size - 1);
1073 			}
1074 		}
1075 
1076 		goto cmd_enable;
1077 	}
1078 
1079 	/*
1080 	 * Check to see if we need to reprogram I/O space, either because the
1081 	 * parent bus needed reprogramming and so do we, or because I/O space is
1082 	 * disabled in base/limit or command register.
1083 	 */
1084 	io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
1085 	io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
1086 	io_base = (io_base & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT;
1087 	io_limit = ((io_limit & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT) | 0xfff;
1088 	if ((io_base & PCI_BCNF_ADDR_MASK) == PCI_BCNF_IO_32BIT) {
1089 		uint16_t io_base_hi, io_limit_hi;
1090 		io_base_hi = pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI);
1091 		io_limit_hi = pci_getw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI);
1092 
1093 		io_base |= (uint_t)io_base_hi << 16;
1094 		io_limit |= (uint_t)io_limit_hi << 16;
1095 	}
1096 
1097 	/* Form list of all resources passed (avail + used) */
1098 	scratch_list = memlist_dup(pci_bus_res[secbus].io_avail);
1099 	memlist_merge(&pci_bus_res[secbus].io_used, &scratch_list);
1100 
1101 	if ((pci_bus_res[parbus].io_reprogram ||
1102 	    (io_base > io_limit) ||
1103 	    (!(cmd_reg & PCI_COMM_IO))) &&
1104 	    !list_is_vga_only(scratch_list, IO)) {
1105 		if (pci_bus_res[secbus].io_used) {
1106 			memlist_subsume(&pci_bus_res[secbus].io_used,
1107 			    &pci_bus_res[secbus].io_avail);
1108 		}
1109 		if (pci_bus_res[secbus].io_avail &&
1110 		    (!pci_bus_res[parbus].io_reprogram) &&
1111 		    (!pci_bus_res[parbus].subtractive)) {
1112 			/* rechoose old io ports info */
1113 			list = pci_bus_res[secbus].io_avail;
1114 			io_base = 0;
1115 			do {
1116 				if (is_vga(list, IO))
1117 					continue;
1118 				if (!io_base) {
1119 					io_base = (uint_t)list->ml_address;
1120 					io_limit = (uint_t)list->ml_address +
1121 					    list->ml_size - 1;
1122 					io_base =
1123 					    P2ALIGN(io_base, PPB_IO_ALIGNMENT);
1124 				} else {
1125 					if (list->ml_address + list->ml_size >
1126 					    io_limit) {
1127 						io_limit = (uint_t)
1128 						    (list->ml_address +
1129 						    list->ml_size - 1);
1130 					}
1131 				}
1132 			} while ((list = list->ml_next) != NULL);
1133 			/* 4K aligned */
1134 			io_limit = P2ROUNDUP(io_limit, PPB_IO_ALIGNMENT) - 1;
1135 			io_size = io_limit - io_base + 1;
1136 			ASSERT(io_base <= io_limit);
1137 			memlist_free_all(&pci_bus_res[secbus].io_avail);
1138 			memlist_insert(&pci_bus_res[secbus].io_avail,
1139 			    io_base, io_size);
1140 			memlist_insert(&pci_bus_res[parbus].io_used,
1141 			    io_base, io_size);
1142 			(void) memlist_remove(&pci_bus_res[parbus].io_avail,
1143 			    io_base, io_size);
1144 			pci_bus_res[secbus].io_reprogram = B_TRUE;
1145 		} else {
1146 			/* get new io ports from parent bus */
1147 			addr = get_parbus_io_res(parbus, secbus, io_size,
1148 			    io_align);
1149 			if (addr) {
1150 				io_base = addr;
1151 				io_limit = addr + io_size - 1;
1152 				pci_bus_res[secbus].io_reprogram = B_TRUE;
1153 			}
1154 		}
1155 		if (pci_bus_res[secbus].io_reprogram) {
1156 			/* reprogram PPB regs */
1157 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
1158 			    (uchar_t)((io_base>>8) & 0xf0));
1159 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
1160 			    (uchar_t)((io_limit>>8) & 0xf0));
1161 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
1162 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
1163 			add_ranges_prop(secbus, 1);
1164 
1165 			cmn_err(CE_NOTE, "!reprogram io-range on"
1166 			    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
1167 			    bus, dev, func, io_base, io_limit);
1168 		}
1169 	}
1170 	memlist_free_all(&scratch_list);
1171 
1172 	/*
1173 	 * Check memory space as we did I/O space.
1174 	 */
1175 	mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
1176 	mem_base = (mem_base & 0xfff0) << 16;
1177 	mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
1178 	mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff;
1179 
1180 	scratch_list = memlist_dup(pci_bus_res[secbus].mem_avail);
1181 	memlist_merge(&pci_bus_res[secbus].mem_used, &scratch_list);
1182 
1183 	if ((pci_bus_res[parbus].mem_reprogram ||
1184 	    (mem_base > mem_limit) ||
1185 	    (!(cmd_reg & PCI_COMM_MAE))) &&
1186 	    !list_is_vga_only(scratch_list, MEM)) {
1187 		if (pci_bus_res[secbus].mem_used) {
1188 			memlist_subsume(&pci_bus_res[secbus].mem_used,
1189 			    &pci_bus_res[secbus].mem_avail);
1190 		}
1191 		if (pci_bus_res[secbus].mem_avail &&
1192 		    (!pci_bus_res[parbus].mem_reprogram) &&
1193 		    (!pci_bus_res[parbus].subtractive)) {
1194 			/* rechoose old mem resource */
1195 			list = pci_bus_res[secbus].mem_avail;
1196 			mem_base = 0;
1197 			do {
1198 				if (is_vga(list, MEM))
1199 					continue;
1200 				if (mem_base == 0) {
1201 					mem_base = (uint_t)list->ml_address;
1202 					mem_base = P2ALIGN(mem_base,
1203 					    PPB_MEM_ALIGNMENT);
1204 					mem_limit = (uint_t)(list->ml_address +
1205 					    list->ml_size - 1);
1206 				} else {
1207 					if ((list->ml_address + list->ml_size) >
1208 					    mem_limit) {
1209 						mem_limit = (uint_t)
1210 						    (list->ml_address +
1211 						    list->ml_size - 1);
1212 					}
1213 				}
1214 			} while ((list = list->ml_next) != NULL);
1215 			mem_limit = P2ROUNDUP(mem_limit, PPB_MEM_ALIGNMENT) - 1;
1216 			mem_size = mem_limit + 1 - mem_base;
1217 			ASSERT(mem_base <= mem_limit);
1218 			memlist_free_all(&pci_bus_res[secbus].mem_avail);
1219 			memlist_insert(&pci_bus_res[secbus].mem_avail,
1220 			    mem_base, mem_size);
1221 			memlist_insert(&pci_bus_res[parbus].mem_used,
1222 			    mem_base, mem_size);
1223 			(void) memlist_remove(&pci_bus_res[parbus].mem_avail,
1224 			    mem_base, mem_size);
1225 			pci_bus_res[secbus].mem_reprogram = B_TRUE;
1226 		} else {
1227 			/* get new mem resource from parent bus */
1228 			addr = get_parbus_mem_res(parbus, secbus, mem_size,
1229 			    mem_align);
1230 			if (addr) {
1231 				mem_base = addr;
1232 				mem_limit = addr + mem_size - 1;
1233 				pci_bus_res[secbus].mem_reprogram = B_TRUE;
1234 			}
1235 		}
1236 
1237 		if (pci_bus_res[secbus].mem_reprogram) {
1238 			/* reprogram PPB MEM regs */
1239 			pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE,
1240 			    (uint16_t)((mem_base>>16) & 0xfff0));
1241 			pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT,
1242 			    (uint16_t)((mem_limit>>16) & 0xfff0));
1243 			/*
1244 			 * Disable PMEM window by setting base > limit.
1245 			 * We currently don't reprogram the PMEM like we've
1246 			 * done for I/O and MEM. (Devices that support prefetch
1247 			 * can use non-prefetch MEM.) Anyway, if the MEM access
1248 			 * bit is initially disabled by BIOS, we disable the
1249 			 * PMEM window manually by setting PMEM base > PMEM
1250 			 * limit here, in case there are incorrect values in
1251 			 * them from BIOS, so that we won't get in trouble once
1252 			 * the MEM access bit is enabled at the end of this
1253 			 * function.
1254 			 */
1255 			if (!(cmd_reg & PCI_COMM_MAE)) {
1256 				pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW,
1257 				    0xfff0);
1258 				pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW,
1259 				    0x0);
1260 				pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH,
1261 				    0xffffffff);
1262 				pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH,
1263 				    0x0);
1264 			}
1265 
1266 			add_ranges_prop(secbus, 1);
1267 
1268 			cmn_err(CE_NOTE, "!reprogram mem-range on"
1269 			    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
1270 			    bus, dev, func, mem_base, mem_limit);
1271 		}
1272 	}
1273 	memlist_free_all(&scratch_list);
1274 
1275 cmd_enable:
1276 	if (pci_bus_res[secbus].io_avail)
1277 		cmd_reg |= PCI_COMM_IO | PCI_COMM_ME;
1278 	if (pci_bus_res[secbus].mem_avail)
1279 		cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME;
1280 	pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg);
1281 }
1282 
1283 void
1284 pci_reprogram(void)
1285 {
1286 	int i, pci_reconfig = 1;
1287 	char *onoff;
1288 	int bus;
1289 
1290 	/*
1291 	 * Scan ACPI namespace for _BBN objects, make sure that
1292 	 * childless root-bridges appear in devinfo tree
1293 	 */
1294 	pci_scan_bbn();
1295 	pci_unitaddr_cache_init();
1296 
1297 	/*
1298 	 * Fix-up unit-address assignments if cache is available
1299 	 */
1300 	if (pci_unitaddr_cache_valid()) {
1301 		int pci_regs[] = {0, 0, 0};
1302 		int	new_addr;
1303 		int	index = 0;
1304 
1305 		for (bus = 0; bus <= pci_bios_maxbus; bus++) {
1306 			/* skip non-root (peer) PCI busses */
1307 			if ((pci_bus_res[bus].par_bus != (uchar_t)-1) ||
1308 			    (pci_bus_res[bus].dip == NULL))
1309 				continue;
1310 
1311 			new_addr = pci_bus_unitaddr(index);
1312 			if (pci_bus_res[bus].root_addr != new_addr) {
1313 				/* update reg property for node */
1314 				pci_regs[0] = pci_bus_res[bus].root_addr =
1315 				    new_addr;
1316 				(void) ndi_prop_update_int_array(
1317 				    DDI_DEV_T_NONE, pci_bus_res[bus].dip,
1318 				    "reg", (int *)pci_regs, 3);
1319 			}
1320 			index++;
1321 		}
1322 	} else {
1323 		/* perform legacy processing */
1324 		pci_renumber_root_busses();
1325 		pci_unitaddr_cache_create();
1326 	}
1327 
1328 	/*
1329 	 * Do root-bus resource discovery
1330 	 */
1331 	for (bus = 0; bus <= pci_bios_maxbus; bus++) {
1332 		/* skip non-root (peer) PCI busses */
1333 		if (pci_bus_res[bus].par_bus != (uchar_t)-1)
1334 			continue;
1335 
1336 		/*
1337 		 * 1. find resources associated with this root bus
1338 		 */
1339 		populate_bus_res(bus);
1340 
1341 
1342 		/*
1343 		 * 2. Remove used PCI and ISA resources from bus resource map
1344 		 */
1345 
1346 		memlist_remove_list(&pci_bus_res[bus].io_avail,
1347 		    pci_bus_res[bus].io_used);
1348 		memlist_remove_list(&pci_bus_res[bus].mem_avail,
1349 		    pci_bus_res[bus].mem_used);
1350 		memlist_remove_list(&pci_bus_res[bus].pmem_avail,
1351 		    pci_bus_res[bus].pmem_used);
1352 		memlist_remove_list(&pci_bus_res[bus].mem_avail,
1353 		    pci_bus_res[bus].pmem_used);
1354 		memlist_remove_list(&pci_bus_res[bus].pmem_avail,
1355 		    pci_bus_res[bus].mem_used);
1356 
1357 		memlist_remove_list(&pci_bus_res[bus].io_avail,
1358 		    isa_res.io_used);
1359 		memlist_remove_list(&pci_bus_res[bus].mem_avail,
1360 		    isa_res.mem_used);
1361 
1362 		/*
1363 		 * 3. Exclude <1M address range here in case below reserved
1364 		 * ranges for BIOS data area, ROM area etc are wrongly reported
1365 		 * in ACPI resource producer entries for PCI root bus.
1366 		 * 	00000000 - 000003FF	RAM
1367 		 * 	00000400 - 000004FF	BIOS data area
1368 		 * 	00000500 - 0009FFFF	RAM
1369 		 * 	000A0000 - 000BFFFF	VGA RAM
1370 		 * 	000C0000 - 000FFFFF	ROM area
1371 		 */
1372 		(void) memlist_remove(&pci_bus_res[bus].mem_avail, 0, 0x100000);
1373 		(void) memlist_remove(&pci_bus_res[bus].pmem_avail,
1374 		    0, 0x100000);
1375 	}
1376 
1377 	memlist_free_all(&isa_res.io_used);
1378 	memlist_free_all(&isa_res.mem_used);
1379 
1380 	/* add bus-range property for root/peer bus nodes */
1381 	for (i = 0; i <= pci_bios_maxbus; i++) {
1382 		/* create bus-range property on root/peer buses */
1383 		if (pci_bus_res[i].par_bus == (uchar_t)-1)
1384 			add_bus_range_prop(i);
1385 
1386 		/* setup bus range resource on each bus */
1387 		setup_bus_res(i);
1388 	}
1389 
1390 	if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(),
1391 	    DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) {
1392 		if (strcmp(onoff, "off") == 0) {
1393 			pci_reconfig = 0;
1394 			cmn_err(CE_NOTE, "pci device reprogramming disabled");
1395 		}
1396 		ddi_prop_free(onoff);
1397 	}
1398 
1399 	remove_subtractive_res();
1400 
1401 	/* reprogram the non-subtractive PPB */
1402 	if (pci_reconfig)
1403 		for (i = 0; i <= pci_bios_maxbus; i++)
1404 			fix_ppb_res(i, B_FALSE);
1405 
1406 	for (i = 0; i <= pci_bios_maxbus; i++) {
1407 		/* configure devices not configured by BIOS */
1408 		if (pci_reconfig) {
1409 			/*
1410 			 * Reprogram the subtractive PPB. At this time, all its
1411 			 * siblings should have got their resources already.
1412 			 */
1413 			if (pci_bus_res[i].subtractive)
1414 				fix_ppb_res(i, B_TRUE);
1415 			enumerate_bus_devs(i, CONFIG_NEW);
1416 		}
1417 	}
1418 
1419 	/* All dev programmed, so we can create available prop */
1420 	for (i = 0; i <= pci_bios_maxbus; i++)
1421 		add_bus_available_prop(i);
1422 }
1423 
1424 /*
1425  * populate bus resources
1426  */
1427 static void
1428 populate_bus_res(uchar_t bus)
1429 {
1430 
1431 	/* scan BIOS structures */
1432 	pci_bus_res[bus].pmem_avail = find_bus_res(bus, PREFETCH_TYPE);
1433 	pci_bus_res[bus].mem_avail = find_bus_res(bus, MEM_TYPE);
1434 	pci_bus_res[bus].io_avail = find_bus_res(bus, IO_TYPE);
1435 	pci_bus_res[bus].bus_avail = find_bus_res(bus, BUSRANGE_TYPE);
1436 
1437 	/*
1438 	 * attempt to initialize sub_bus from the largest range-end
1439 	 * in the bus_avail list
1440 	 */
1441 	if (pci_bus_res[bus].bus_avail != NULL) {
1442 		struct memlist *entry;
1443 		int current;
1444 
1445 		entry = pci_bus_res[bus].bus_avail;
1446 		while (entry != NULL) {
1447 			current = entry->ml_address + entry->ml_size - 1;
1448 			if (current > pci_bus_res[bus].sub_bus)
1449 				pci_bus_res[bus].sub_bus = current;
1450 			entry = entry->ml_next;
1451 		}
1452 	}
1453 
1454 	if (bus == 0) {
1455 		/*
1456 		 * Special treatment of bus 0:
1457 		 * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy
1458 		 * pcimem from boot and make I/O space the entire range
1459 		 * starting at 0x100.
1460 		 */
1461 		if (pci_bus_res[0].mem_avail == NULL)
1462 			pci_bus_res[0].mem_avail =
1463 			    memlist_dup(bootops->boot_mem->pcimem);
1464 		/* Exclude 0x00 to 0xff of the I/O space, used by all PCs */
1465 		if (pci_bus_res[0].io_avail == NULL)
1466 			memlist_insert(&pci_bus_res[0].io_avail, 0x100, 0xffff);
1467 	}
1468 
1469 	/*
1470 	 * Create 'ranges' property here before any resources are
1471 	 * removed from the resource lists
1472 	 */
1473 	add_ranges_prop(bus, 0);
1474 }
1475 
1476 
1477 /*
1478  * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0...
1479  */
1480 static void
1481 create_root_bus_dip(uchar_t bus)
1482 {
1483 	int pci_regs[] = {0, 0, 0};
1484 	dev_info_t *dip;
1485 
1486 	ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1);
1487 
1488 	num_root_bus++;
1489 	ndi_devi_alloc_sleep(ddi_root_node(), "pci",
1490 	    (pnode_t)DEVI_SID_NODEID, &dip);
1491 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1492 	    "#address-cells", 3);
1493 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1494 	    "#size-cells", 2);
1495 	pci_regs[0] = pci_bus_res[bus].root_addr;
1496 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1497 	    "reg", (int *)pci_regs, 3);
1498 
1499 	/*
1500 	 * If system has PCIe bus, then create different properties
1501 	 */
1502 	if (create_pcie_root_bus(bus, dip) == B_FALSE)
1503 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1504 		    "device_type", "pci");
1505 
1506 	(void) ndi_devi_bind_driver(dip, 0);
1507 	pci_bus_res[bus].dip = dip;
1508 }
1509 
1510 /*
1511  * For any fixed configuration (often compatability) pci devices
1512  * and those with their own expansion rom, create device nodes
1513  * to hold the already configured device details.
1514  */
1515 void
1516 enumerate_bus_devs(uchar_t bus, int config_op)
1517 {
1518 	uchar_t dev, func, nfunc, header;
1519 	ushort_t venid;
1520 	struct pci_devfunc *devlist = NULL, *entry;
1521 
1522 	if (config_op == CONFIG_NEW) {
1523 		dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus);
1524 	} else if (config_op == CONFIG_FIX) {
1525 		dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus);
1526 	} else
1527 		dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus);
1528 
1529 	if (config_op == CONFIG_NEW) {
1530 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
1531 		while (devlist) {
1532 			entry = devlist;
1533 			devlist = entry->next;
1534 			if (entry->reprogram ||
1535 			    pci_bus_res[bus].io_reprogram ||
1536 			    pci_bus_res[bus].mem_reprogram) {
1537 				/* reprogram device(s) */
1538 				(void) add_reg_props(entry->dip, bus,
1539 				    entry->dev, entry->func, CONFIG_NEW, 0);
1540 			}
1541 			kmem_free(entry, sizeof (*entry));
1542 		}
1543 		pci_bus_res[bus].privdata = NULL;
1544 		return;
1545 	}
1546 
1547 	for (dev = 0; dev < max_dev_pci; dev++) {
1548 		nfunc = 1;
1549 		for (func = 0; func < nfunc; func++) {
1550 
1551 			dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x",
1552 			    dev, func);
1553 
1554 			venid = pci_getw(bus, dev, func, PCI_CONF_VENID);
1555 
1556 			if ((venid == 0xffff) || (venid == 0)) {
1557 				/* no function at this address */
1558 				continue;
1559 			}
1560 
1561 			header = pci_getb(bus, dev, func, PCI_CONF_HEADER);
1562 			if (header == 0xff) {
1563 				continue; /* illegal value */
1564 			}
1565 
1566 			/*
1567 			 * according to some mail from Microsoft posted
1568 			 * to the pci-drivers alias, their only requirement
1569 			 * for a multifunction device is for the 1st
1570 			 * function to have to PCI_HEADER_MULTI bit set.
1571 			 */
1572 			if ((func == 0) && (header & PCI_HEADER_MULTI)) {
1573 				nfunc = 8;
1574 			}
1575 
1576 			if (config_op == CONFIG_FIX ||
1577 			    config_op == CONFIG_INFO) {
1578 				/*
1579 				 * Create the node, unconditionally, on the
1580 				 * first pass only.  It may still need
1581 				 * resource assignment, which will be
1582 				 * done on the second, CONFIG_NEW, pass.
1583 				 */
1584 				process_devfunc(bus, dev, func, header,
1585 				    venid, config_op);
1586 
1587 			}
1588 		}
1589 	}
1590 
1591 	/* percolate bus used resources up through parents to root */
1592 	if (config_op == CONFIG_INFO) {
1593 		int	par_bus;
1594 
1595 		par_bus = pci_bus_res[bus].par_bus;
1596 		while (par_bus != (uchar_t)-1) {
1597 			pci_bus_res[par_bus].io_size +=
1598 			    pci_bus_res[bus].io_size;
1599 			pci_bus_res[par_bus].mem_size +=
1600 			    pci_bus_res[bus].mem_size;
1601 
1602 			if (pci_bus_res[bus].io_used)
1603 				memlist_merge(&pci_bus_res[bus].io_used,
1604 				    &pci_bus_res[par_bus].io_used);
1605 
1606 			if (pci_bus_res[bus].mem_used)
1607 				memlist_merge(&pci_bus_res[bus].mem_used,
1608 				    &pci_bus_res[par_bus].mem_used);
1609 
1610 			if (pci_bus_res[bus].pmem_used)
1611 				memlist_merge(&pci_bus_res[bus].pmem_used,
1612 				    &pci_bus_res[par_bus].pmem_used);
1613 
1614 			bus = par_bus;
1615 			par_bus = pci_bus_res[par_bus].par_bus;
1616 		}
1617 	}
1618 }
1619 
1620 static int
1621 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid,
1622     ushort_t subvenid, ushort_t subdevid)
1623 {
1624 	static int prop_exist = -1;
1625 	static char *pciide_str;
1626 	char compat[32];
1627 
1628 	if (prop_exist == -1) {
1629 		prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY,
1630 		    ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide",
1631 		    &pciide_str) == DDI_SUCCESS);
1632 	}
1633 
1634 	if (!prop_exist)
1635 		return (0);
1636 
1637 	/* compare property value against various forms of compatible */
1638 	if (subvenid) {
1639 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x",
1640 		    venid, devid, subvenid, subdevid, revid);
1641 		if (strcmp(pciide_str, compat) == 0)
1642 			return (1);
1643 
1644 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x",
1645 		    venid, devid, subvenid, subdevid);
1646 		if (strcmp(pciide_str, compat) == 0)
1647 			return (1);
1648 
1649 		(void) snprintf(compat, sizeof (compat), "pci%x,%x",
1650 		    subvenid, subdevid);
1651 		if (strcmp(pciide_str, compat) == 0)
1652 			return (1);
1653 	}
1654 	(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x",
1655 	    venid, devid, revid);
1656 	if (strcmp(pciide_str, compat) == 0)
1657 		return (1);
1658 
1659 	(void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid);
1660 	if (strcmp(pciide_str, compat) == 0)
1661 		return (1);
1662 
1663 	return (0);
1664 }
1665 
1666 static int
1667 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid,
1668     ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid)
1669 {
1670 	struct ide_table {	/* table for PCI_MASS_OTHER */
1671 		ushort_t venid;
1672 		ushort_t devid;
1673 	} *entry;
1674 
1675 	/* XXX SATA and other devices: need a way to add dynamically */
1676 	static struct ide_table ide_other[] = {
1677 		{0x1095, 0x3112},
1678 		{0x1095, 0x3114},
1679 		{0x1095, 0x3512},
1680 		{0x1095, 0x680},	/* Sil0680 */
1681 		{0x1283, 0x8211},	/* ITE 8211F is subcl PCI_MASS_OTHER */
1682 		{0, 0}
1683 	};
1684 
1685 	if (basecl != PCI_CLASS_MASS)
1686 		return (0);
1687 
1688 	if (subcl == PCI_MASS_IDE) {
1689 		return (1);
1690 	}
1691 
1692 	if (check_pciide_prop(revid, venid, devid, subvenid, subdevid))
1693 		return (1);
1694 
1695 	if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) {
1696 		return (0);
1697 	}
1698 
1699 	entry = &ide_other[0];
1700 	while (entry->venid) {
1701 		if (entry->venid == venid && entry->devid == devid)
1702 			return (1);
1703 		entry++;
1704 	}
1705 	return (0);
1706 }
1707 
1708 static int
1709 is_display(uint_t classcode)
1710 {
1711 	static uint_t disp_classes[] = {
1712 		0x000100,
1713 		0x030000,
1714 		0x030001
1715 	};
1716 	int i, nclasses = sizeof (disp_classes) / sizeof (uint_t);
1717 
1718 	for (i = 0; i < nclasses; i++) {
1719 		if (classcode == disp_classes[i])
1720 			return (1);
1721 	}
1722 	return (0);
1723 }
1724 
1725 static void
1726 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn,
1727     void (*undofn)(uint8_t, uint8_t, uint8_t))
1728 {
1729 	struct pci_fixundo *newundo;
1730 
1731 	newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP);
1732 
1733 	/*
1734 	 * Adding an item to this list means that we must turn its NMIENABLE
1735 	 * bit back on at a later time.
1736 	 */
1737 	newundo->bus = bus;
1738 	newundo->dev = dev;
1739 	newundo->fn = fn;
1740 	newundo->undofn = undofn;
1741 	newundo->next = undolist;
1742 
1743 	/* add to the undo list in LIFO order */
1744 	undolist = newundo;
1745 }
1746 
1747 void
1748 add_pci_fixes(void)
1749 {
1750 	int i;
1751 
1752 	for (i = 0; i <= pci_bios_maxbus; i++) {
1753 		/*
1754 		 * For each bus, apply needed fixes to the appropriate devices.
1755 		 * This must be done before the main enumeration loop because
1756 		 * some fixes must be applied to devices normally encountered
1757 		 * later in the pci scan (e.g. if a fix to device 7 must be
1758 		 * applied before scanning device 6, applying fixes in the
1759 		 * normal enumeration loop would obviously be too late).
1760 		 */
1761 		enumerate_bus_devs(i, CONFIG_FIX);
1762 	}
1763 }
1764 
1765 void
1766 undo_pci_fixes(void)
1767 {
1768 	struct pci_fixundo *nextundo;
1769 	uint8_t bus, dev, fn;
1770 
1771 	/*
1772 	 * All fixes in the undo list are performed unconditionally.  Future
1773 	 * fixes may require selective undo.
1774 	 */
1775 	while (undolist != NULL) {
1776 
1777 		bus = undolist->bus;
1778 		dev = undolist->dev;
1779 		fn = undolist->fn;
1780 
1781 		(*(undolist->undofn))(bus, dev, fn);
1782 
1783 		nextundo = undolist->next;
1784 		kmem_free(undolist, sizeof (struct pci_fixundo));
1785 		undolist = nextundo;
1786 	}
1787 }
1788 
1789 static void
1790 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn)
1791 {
1792 	uint8_t val8;
1793 
1794 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1795 	/*
1796 	 * The NMIONERR bit is turned back on to allow the SMM BIOS
1797 	 * to handle more critical PCI errors (e.g. PERR#).
1798 	 */
1799 	val8 |= AMD8111_ENABLENMI;
1800 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1801 }
1802 
1803 static void
1804 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn)
1805 {
1806 	uint8_t val8;
1807 
1808 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1809 
1810 	if ((val8 & AMD8111_ENABLENMI) == 0)
1811 		return;
1812 
1813 	/*
1814 	 * We reset NMIONERR in the LPC because master-abort on the PCI
1815 	 * bridge side of the 8111 will cause NMI, which might cause SMI,
1816 	 * which sometimes prevents all devices from being enumerated.
1817 	 */
1818 	val8 &= ~AMD8111_ENABLENMI;
1819 
1820 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1821 
1822 	add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix);
1823 }
1824 
1825 static void
1826 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func)
1827 {
1828 	uint16_t status;
1829 	uint8_t header;
1830 	uint8_t cap_ptr;
1831 	uint8_t cap_id;
1832 	uint16_t pmcsr;
1833 
1834 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
1835 	if (!(status & PCI_STAT_CAP))
1836 		return;	/* No capabilities list */
1837 
1838 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
1839 	if (header == PCI_HEADER_CARDBUS)
1840 		cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR);
1841 	else
1842 		cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
1843 	/*
1844 	 * Walk the capabilities list searching for a PM entry.
1845 	 */
1846 	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) {
1847 		cap_ptr &= PCI_CAP_PTR_MASK;
1848 		cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID);
1849 		if (cap_id == PCI_CAP_ID_PM) {
1850 			pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR);
1851 			pmcsr &= ~(PCI_PMCSR_STATE_MASK);
1852 			pmcsr |= PCI_PMCSR_D0; /* D0 state */
1853 			pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr);
1854 			break;
1855 		}
1856 		cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR);
1857 	}
1858 
1859 }
1860 
1861 #define	is_isa(bc, sc)	\
1862 	(((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA))
1863 
1864 static void
1865 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header,
1866     ushort_t vendorid, int config_op)
1867 {
1868 	char nodename[32], unitaddr[5];
1869 	dev_info_t *dip;
1870 	uchar_t basecl, subcl, progcl, intr, revid;
1871 	ushort_t subvenid, subdevid, status;
1872 	ushort_t slot_num;
1873 	uint_t classcode, revclass;
1874 	int reprogram = 0, pciide = 0;
1875 	int power[2] = {1, 1};
1876 	int pciex = 0;
1877 	ushort_t is_pci_bridge = 0;
1878 	struct pci_devfunc *devlist = NULL, *entry = NULL;
1879 	boolean_t slot_valid;
1880 	gfx_entry_t *gfxp;
1881 	pcie_req_id_t bdf;
1882 
1883 	ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID);
1884 
1885 	switch (header & PCI_HEADER_TYPE_M) {
1886 	case PCI_HEADER_ZERO:
1887 		subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID);
1888 		subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID);
1889 		break;
1890 	case PCI_HEADER_CARDBUS:
1891 		subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID);
1892 		subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID);
1893 		/* Record the # of cardbus bridges found on the bus */
1894 		if (config_op == CONFIG_INFO)
1895 			pci_bus_res[bus].num_cbb++;
1896 		break;
1897 	default:
1898 		subvenid = 0;
1899 		subdevid = 0;
1900 		break;
1901 	}
1902 
1903 	if (config_op == CONFIG_FIX) {
1904 		if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) {
1905 			pci_fix_amd8111(bus, dev, func);
1906 		}
1907 		return;
1908 	}
1909 
1910 	/* XXX should be use generic names? derive from class? */
1911 	revclass = pci_getl(bus, dev, func, PCI_CONF_REVID);
1912 	classcode = revclass >> 8;
1913 	revid = revclass & 0xff;
1914 
1915 	/* figure out if this is pci-ide */
1916 	basecl = classcode >> 16;
1917 	subcl = (classcode >> 8) & 0xff;
1918 	progcl = classcode & 0xff;
1919 
1920 
1921 	if (is_display(classcode))
1922 		(void) snprintf(nodename, sizeof (nodename), "display");
1923 	else if (!pseudo_isa && is_isa(basecl, subcl))
1924 		(void) snprintf(nodename, sizeof (nodename), "isa");
1925 	else if (subvenid != 0)
1926 		(void) snprintf(nodename, sizeof (nodename),
1927 		    "pci%x,%x", subvenid, subdevid);
1928 	else
1929 		(void) snprintf(nodename, sizeof (nodename),
1930 		    "pci%x,%x", vendorid, deviceid);
1931 
1932 	/* make sure parent bus dip has been created */
1933 	if (pci_bus_res[bus].dip == NULL)
1934 		create_root_bus_dip(bus);
1935 
1936 	ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename,
1937 	    DEVI_SID_NODEID, &dip);
1938 
1939 	if (check_if_device_is_pciex(dip, bus, dev, func, &slot_valid,
1940 	    &slot_num, &is_pci_bridge) == B_TRUE)
1941 		pciex = 1;
1942 
1943 	bdf = PCI_GETBDF(bus, dev, func);
1944 	/*
1945 	 * Record BAD AMD bridges which don't support MMIO config access.
1946 	 */
1947 	if (IS_BAD_AMD_NTBRIDGE(vendorid, deviceid) ||
1948 	    IS_AMD_8132_CHIP(vendorid, deviceid)) {
1949 		uchar_t secbus = 0;
1950 		uchar_t subbus = 0;
1951 
1952 		if ((basecl == PCI_CLASS_BRIDGE) &&
1953 		    (subcl == PCI_BRIDGE_PCI)) {
1954 			secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
1955 			subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
1956 		}
1957 		pci_cfgacc_add_workaround(bdf, secbus, subbus);
1958 	}
1959 
1960 	/*
1961 	 * Only populate bus_t if this device is sitting under a PCIE root
1962 	 * complex.  Some particular machines have both a PCIE root complex and
1963 	 * a PCI hostbridge, in which case only devices under the PCIE root
1964 	 * complex will have their bus_t populated.
1965 	 */
1966 	if (pcie_get_rc_dip(dip) != NULL) {
1967 		ck804_fix_aer_ptr(dip, bdf);
1968 		(void) pcie_init_bus(dip, bdf, PCIE_BUS_INITIAL);
1969 	}
1970 
1971 	/* add properties */
1972 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid);
1973 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid);
1974 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid);
1975 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1976 	    "class-code", classcode);
1977 	if (func == 0)
1978 		(void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev);
1979 	else
1980 		(void) snprintf(unitaddr, sizeof (unitaddr),
1981 		    "%x,%x", dev, func);
1982 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1983 	    "unit-address", unitaddr);
1984 
1985 	/* add device_type for display nodes */
1986 	if (is_display(classcode)) {
1987 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1988 		    "device_type", "display");
1989 	}
1990 	/* add special stuff for header type */
1991 	if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) {
1992 		uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G);
1993 		uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L);
1994 
1995 		if (subvenid != 0) {
1996 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1997 			    "subsystem-id", subdevid);
1998 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1999 			    "subsystem-vendor-id", subvenid);
2000 		}
2001 		if (!pciex)
2002 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2003 			    "min-grant", mingrant);
2004 		if (!pciex)
2005 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2006 			    "max-latency", maxlatency);
2007 	}
2008 
2009 	/* interrupt, record if not 0 */
2010 	intr = pci_getb(bus, dev, func, PCI_CONF_IPIN);
2011 	if (intr != 0)
2012 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2013 		    "interrupts", intr);
2014 
2015 	/*
2016 	 * Add support for 133 mhz pci eventually
2017 	 */
2018 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
2019 
2020 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2021 	    "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9);
2022 	if (!pciex && (status & PCI_STAT_FBBC))
2023 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
2024 		    "fast-back-to-back");
2025 	if (!pciex && (status & PCI_STAT_66MHZ))
2026 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
2027 		    "66mhz-capable");
2028 	if (status & PCI_STAT_UDF)
2029 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
2030 		    "udf-supported");
2031 	if (pciex && slot_valid) {
2032 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2033 		    "physical-slot#", slot_num);
2034 		if (!is_pci_bridge)
2035 			pciex_slot_names_prop(dip, slot_num);
2036 	}
2037 
2038 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
2039 	    "power-consumption", power, 2);
2040 
2041 	/* Set the device PM state to D0 */
2042 	set_devpm_d0(bus, dev, func);
2043 
2044 	if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI))
2045 		add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge);
2046 	else {
2047 		/*
2048 		 * Record the non-PPB devices on the bus for possible
2049 		 * reprogramming at 2nd bus enumeration.
2050 		 * Note: PPB reprogramming is done in fix_ppb_res()
2051 		 */
2052 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
2053 		entry = kmem_zalloc(sizeof (*entry), KM_SLEEP);
2054 		entry->dip = dip;
2055 		entry->dev = dev;
2056 		entry->func = func;
2057 		entry->next = devlist;
2058 		pci_bus_res[bus].privdata = entry;
2059 	}
2060 
2061 	if (IS_CLASS_IOAPIC(basecl, subcl, progcl)) {
2062 		create_ioapic_node(bus, dev, func, vendorid, deviceid);
2063 	}
2064 
2065 	/* check for NVIDIA CK8-04/MCP55 based LPC bridge */
2066 	if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) &&
2067 	    (func == 0)) {
2068 		add_nvidia_isa_bridge_props(dip, bus, dev, func);
2069 		/* each LPC bridge has an integrated IOAPIC */
2070 		apic_nvidia_io_max++;
2071 	}
2072 
2073 	if (pciex && is_pci_bridge)
2074 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
2075 		    (char *)"PCIe-PCI bridge");
2076 	else
2077 		add_model_prop(dip, classcode);
2078 
2079 	add_compatible(dip, subvenid, subdevid, vendorid, deviceid,
2080 	    revid, classcode, pciex);
2081 
2082 	/*
2083 	 * See if this device is a controller that advertises
2084 	 * itself to be a standard ATA task file controller, or one that
2085 	 * has been hard coded.
2086 	 *
2087 	 * If it is, check if any other higher precedence driver listed in
2088 	 * driver_aliases will claim the node by calling
2089 	 * ddi_compatibile_driver_major.  If so, clear pciide and do not
2090 	 * create a pci-ide node or any other special handling.
2091 	 *
2092 	 * If another driver does not bind, set the node name to pci-ide
2093 	 * and then let the special pci-ide handling for registers and
2094 	 * child pci-ide nodes proceed below.
2095 	 */
2096 	if (is_pciide(basecl, subcl, revid, vendorid, deviceid,
2097 	    subvenid, subdevid) == 1) {
2098 		if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) {
2099 			(void) ndi_devi_set_nodename(dip, "pci-ide", 0);
2100 			pciide = 1;
2101 		}
2102 	}
2103 
2104 	DEVI_SET_PCI(dip);
2105 	reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide);
2106 	(void) ndi_devi_bind_driver(dip, 0);
2107 
2108 	/* special handling for pci-ide */
2109 	if (pciide) {
2110 		dev_info_t *cdip;
2111 
2112 		/*
2113 		 * Create properties specified by P1275 Working Group
2114 		 * Proposal #414 Version 1
2115 		 */
2116 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
2117 		    "device_type", "pci-ide");
2118 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2119 		    "#address-cells", 1);
2120 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2121 		    "#size-cells", 0);
2122 
2123 		/* allocate two child nodes */
2124 		ndi_devi_alloc_sleep(dip, "ide",
2125 		    (pnode_t)DEVI_SID_NODEID, &cdip);
2126 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
2127 		    "reg", 0);
2128 		(void) ndi_devi_bind_driver(cdip, 0);
2129 		ndi_devi_alloc_sleep(dip, "ide",
2130 		    (pnode_t)DEVI_SID_NODEID, &cdip);
2131 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
2132 		    "reg", 1);
2133 		(void) ndi_devi_bind_driver(cdip, 0);
2134 
2135 		reprogram = 0;	/* don't reprogram pci-ide bridge */
2136 	}
2137 
2138 	if (is_display(classcode)) {
2139 		gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP);
2140 		gfxp->g_dip = dip;
2141 		gfxp->g_prev = NULL;
2142 		gfxp->g_next = gfx_devinfo_list;
2143 		gfx_devinfo_list = gfxp;
2144 		if (gfxp->g_next)
2145 			gfxp->g_next->g_prev = gfxp;
2146 	}
2147 
2148 	/* special handling for isa */
2149 	if (!pseudo_isa && is_isa(basecl, subcl)) {
2150 		/* add device_type */
2151 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
2152 		    "device_type", "isa");
2153 	}
2154 
2155 	if (reprogram && (entry != NULL))
2156 		entry->reprogram = B_TRUE;
2157 
2158 }
2159 
2160 /*
2161  * Some vendors do not use unique subsystem IDs in their products, which
2162  * makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate.
2163  * Allow for these compatible forms to be excluded on a per-device basis.
2164  */
2165 /*ARGSUSED*/
2166 static boolean_t
2167 subsys_compat_exclude(ushort_t venid, ushort_t devid, ushort_t subvenid,
2168     ushort_t subdevid, uchar_t revid, uint_t classcode)
2169 {
2170 	/* Nvidia display adapters */
2171 	if ((venid == 0x10de) && (is_display(classcode)))
2172 		return (B_TRUE);
2173 
2174 	return (B_FALSE);
2175 }
2176 
2177 /*
2178  * Set the compatible property to a value compliant with
2179  * rev 2.1 of the IEEE1275 PCI binding.
2180  * (Also used for PCI-Express devices).
2181  *
2182  *   pciVVVV,DDDD.SSSS.ssss.RR	(0)
2183  *   pciVVVV,DDDD.SSSS.ssss	(1)
2184  *   pciSSSS,ssss		(2)
2185  *   pciVVVV,DDDD.RR		(3)
2186  *   pciVVVV,DDDD		(4)
2187  *   pciclass,CCSSPP		(5)
2188  *   pciclass,CCSS		(6)
2189  *
2190  * The Subsystem (SSSS) forms are not inserted if
2191  * subsystem-vendor-id is 0.
2192  *
2193  * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above
2194  * property 2 is not created as per "1275 bindings for PCI Express Interconnect"
2195  *
2196  * Set with setprop and \x00 between each
2197  * to generate the encoded string array form.
2198  */
2199 void
2200 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid,
2201     ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode,
2202     int pciex)
2203 {
2204 	int i = 0;
2205 	int size = COMPAT_BUFSIZE;
2206 	char *compat[13];
2207 	char *buf, *curr;
2208 
2209 	curr = buf = kmem_alloc(size, KM_SLEEP);
2210 
2211 	if (pciex) {
2212 		if (subvenid) {
2213 			compat[i++] = curr;	/* form 0 */
2214 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x",
2215 			    vendorid, deviceid, subvenid, subdevid, revid);
2216 			size -= strlen(curr) + 1;
2217 			curr += strlen(curr) + 1;
2218 
2219 			compat[i++] = curr;	/* form 1 */
2220 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x",
2221 			    vendorid, deviceid, subvenid, subdevid);
2222 			size -= strlen(curr) + 1;
2223 			curr += strlen(curr) + 1;
2224 
2225 		}
2226 		compat[i++] = curr;	/* form 3 */
2227 		(void) snprintf(curr, size, "pciex%x,%x.%x",
2228 		    vendorid, deviceid, revid);
2229 		size -= strlen(curr) + 1;
2230 		curr += strlen(curr) + 1;
2231 
2232 		compat[i++] = curr;	/* form 4 */
2233 		(void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid);
2234 		size -= strlen(curr) + 1;
2235 		curr += strlen(curr) + 1;
2236 
2237 		compat[i++] = curr;	/* form 5 */
2238 		(void) snprintf(curr, size, "pciexclass,%06x", classcode);
2239 		size -= strlen(curr) + 1;
2240 		curr += strlen(curr) + 1;
2241 
2242 		compat[i++] = curr;	/* form 6 */
2243 		(void) snprintf(curr, size, "pciexclass,%04x",
2244 		    (classcode >> 8));
2245 		size -= strlen(curr) + 1;
2246 		curr += strlen(curr) + 1;
2247 	}
2248 
2249 	if (subvenid) {
2250 		compat[i++] = curr;	/* form 0 */
2251 		(void) snprintf(curr, size, "pci%x,%x.%x.%x.%x",
2252 		    vendorid, deviceid, subvenid, subdevid, revid);
2253 		size -= strlen(curr) + 1;
2254 		curr += strlen(curr) + 1;
2255 
2256 		compat[i++] = curr;	/* form 1 */
2257 		(void) snprintf(curr, size, "pci%x,%x.%x.%x",
2258 		    vendorid, deviceid, subvenid, subdevid);
2259 		size -= strlen(curr) + 1;
2260 		curr += strlen(curr) + 1;
2261 
2262 		if (subsys_compat_exclude(vendorid, deviceid, subvenid,
2263 		    subdevid, revid, classcode) == B_FALSE) {
2264 			compat[i++] = curr;	/* form 2 */
2265 			(void) snprintf(curr, size, "pci%x,%x", subvenid,
2266 			    subdevid);
2267 			size -= strlen(curr) + 1;
2268 			curr += strlen(curr) + 1;
2269 		}
2270 	}
2271 	compat[i++] = curr;	/* form 3 */
2272 	(void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid);
2273 	size -= strlen(curr) + 1;
2274 	curr += strlen(curr) + 1;
2275 
2276 	compat[i++] = curr;	/* form 4 */
2277 	(void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid);
2278 	size -= strlen(curr) + 1;
2279 	curr += strlen(curr) + 1;
2280 
2281 	compat[i++] = curr;	/* form 5 */
2282 	(void) snprintf(curr, size, "pciclass,%06x", classcode);
2283 	size -= strlen(curr) + 1;
2284 	curr += strlen(curr) + 1;
2285 
2286 	compat[i++] = curr;	/* form 6 */
2287 	(void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8));
2288 	size -= strlen(curr) + 1;
2289 	curr += strlen(curr) + 1;
2290 
2291 	(void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip,
2292 	    "compatible", compat, i);
2293 	kmem_free(buf, COMPAT_BUFSIZE);
2294 }
2295 
2296 /*
2297  * Adjust the reg properties for a dual channel PCI-IDE device.
2298  *
2299  * NOTE: don't do anything that changes the order of the hard-decodes
2300  * and programmed BARs. The kernel driver depends on these values
2301  * being in this order regardless of whether they're for a 'native'
2302  * mode BAR or not.
2303  */
2304 /*
2305  * config info for pci-ide devices
2306  */
2307 static struct {
2308 	uchar_t  native_mask;	/* 0 == 'compatibility' mode, 1 == native */
2309 	uchar_t  bar_offset;	/* offset for alt status register */
2310 	ushort_t addr;		/* compatibility mode base address */
2311 	ushort_t length;	/* number of ports for this BAR */
2312 } pciide_bar[] = {
2313 	{ 0x01, 0, 0x1f0, 8 },	/* primary lower BAR */
2314 	{ 0x01, 2, 0x3f6, 1 },	/* primary upper BAR */
2315 	{ 0x04, 0, 0x170, 8 },	/* secondary lower BAR */
2316 	{ 0x04, 2, 0x376, 1 }	/* secondary upper BAR */
2317 };
2318 
2319 static int
2320 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp)
2321 {
2322 	int hard_decode = 0;
2323 
2324 	/*
2325 	 * Adjust the base and len for the BARs of the PCI-IDE
2326 	 * device's primary and secondary controllers. The first
2327 	 * two BARs are for the primary controller and the next
2328 	 * two BARs are for the secondary controller. The fifth
2329 	 * and sixth bars are never adjusted.
2330 	 */
2331 	if (index >= 0 && index <= 3) {
2332 		*lenp = pciide_bar[index].length;
2333 
2334 		if (progcl & pciide_bar[index].native_mask) {
2335 			*basep += pciide_bar[index].bar_offset;
2336 		} else {
2337 			*basep = pciide_bar[index].addr;
2338 			hard_decode = 1;
2339 		}
2340 	}
2341 
2342 	/*
2343 	 * if either base or len is zero make certain both are zero
2344 	 */
2345 	if (*basep == 0 || *lenp == 0) {
2346 		*basep = 0;
2347 		*lenp = 0;
2348 		hard_decode = 0;
2349 	}
2350 
2351 	return (hard_decode);
2352 }
2353 
2354 
2355 /*
2356  * Add the "reg" and "assigned-addresses" property
2357  */
2358 static int
2359 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
2360     int config_op, int pciide)
2361 {
2362 	uchar_t baseclass, subclass, progclass, header;
2363 	ushort_t bar_sz;
2364 	uint_t value = 0, len, devloc;
2365 	uint_t base, base_hi, type;
2366 	ushort_t offset, end;
2367 	int max_basereg, j, reprogram = 0;
2368 	uint_t phys_hi;
2369 	struct memlist **io_avail, **io_used;
2370 	struct memlist **mem_avail, **mem_used;
2371 	struct memlist **pmem_avail, **pmem_used;
2372 	uchar_t res_bus;
2373 
2374 	pci_regspec_t regs[16] = {{0}};
2375 	pci_regspec_t assigned[15] = {{0}};
2376 	int nreg, nasgn;
2377 
2378 	io_avail = &pci_bus_res[bus].io_avail;
2379 	io_used = &pci_bus_res[bus].io_used;
2380 	mem_avail = &pci_bus_res[bus].mem_avail;
2381 	mem_used = &pci_bus_res[bus].mem_used;
2382 	pmem_avail = &pci_bus_res[bus].pmem_avail;
2383 	pmem_used = &pci_bus_res[bus].pmem_used;
2384 
2385 	devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8;
2386 	regs[0].pci_phys_hi = devloc;
2387 	nreg = 1;	/* rest of regs[0] is all zero */
2388 	nasgn = 0;
2389 
2390 	baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS);
2391 	subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS);
2392 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
2393 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
2394 
2395 	switch (header) {
2396 	case PCI_HEADER_ZERO:
2397 		max_basereg = PCI_BASE_NUM;
2398 		break;
2399 	case PCI_HEADER_PPB:
2400 		max_basereg = PCI_BCNF_BASE_NUM;
2401 		break;
2402 	case PCI_HEADER_CARDBUS:
2403 		max_basereg = PCI_CBUS_BASE_NUM;
2404 		reprogram = 1;
2405 		break;
2406 	default:
2407 		max_basereg = 0;
2408 		break;
2409 	}
2410 
2411 	/*
2412 	 * Create the register property by saving the current
2413 	 * value of the base register. Write 0xffffffff to the
2414 	 * base register.  Read the value back to determine the
2415 	 * required size of the address space.  Restore the base
2416 	 * register contents.
2417 	 *
2418 	 * Do not disable I/O and memory access for bridges; this
2419 	 * has the side-effect of making the bridge transparent to
2420 	 * secondary-bus activity (see sections 4.1-4.3 of the
2421 	 * PCI-PCI Bridge Spec V1.2).  For non-bridges, disable
2422 	 * I/O and memory access to avoid difficulty with USB
2423 	 * emulation (see OHCI spec1.0a appendix B
2424 	 * "Host Controller Mapping")
2425 	 */
2426 	end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t);
2427 	for (j = 0, offset = PCI_CONF_BASE0; offset < end;
2428 	    j++, offset += bar_sz) {
2429 		uint_t	command;
2430 
2431 		/* determine the size of the address space */
2432 		base = pci_getl(bus, dev, func, offset);
2433 		if (baseclass != PCI_CLASS_BRIDGE) {
2434 			command = (uint_t)pci_getw(bus, dev, func,
2435 			    PCI_CONF_COMM);
2436 			pci_putw(bus, dev, func, PCI_CONF_COMM,
2437 			    command & ~(PCI_COMM_MAE | PCI_COMM_IO));
2438 		}
2439 		pci_putl(bus, dev, func, offset, 0xffffffff);
2440 		value = pci_getl(bus, dev, func, offset);
2441 		pci_putl(bus, dev, func, offset, base);
2442 		if (baseclass != PCI_CLASS_BRIDGE)
2443 			pci_putw(bus, dev, func, PCI_CONF_COMM, command);
2444 
2445 		/* construct phys hi,med.lo, size hi, lo */
2446 		if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) {
2447 			int hard_decode = 0;
2448 
2449 			/* i/o space */
2450 			bar_sz = PCI_BAR_SZ_32;
2451 			value &= PCI_BASE_IO_ADDR_M;
2452 			len = ((value ^ (value-1)) + 1) >> 1;
2453 
2454 			/* XXX Adjust first 4 IDE registers */
2455 			if (pciide) {
2456 				if (subclass != PCI_MASS_IDE)
2457 					progclass = (PCI_IDE_IF_NATIVE_PRI |
2458 					    PCI_IDE_IF_NATIVE_SEC);
2459 				hard_decode = pciIdeAdjustBAR(progclass, j,
2460 				    &base, &len);
2461 			} else if (value == 0) {
2462 				/* skip base regs with size of 0 */
2463 				continue;
2464 			}
2465 
2466 			regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc |
2467 			    (hard_decode ? PCI_RELOCAT_B : offset);
2468 			regs[nreg].pci_phys_low = hard_decode ?
2469 			    base & PCI_BASE_IO_ADDR_M : 0;
2470 			assigned[nasgn].pci_phys_hi =
2471 			    PCI_RELOCAT_B | regs[nreg].pci_phys_hi;
2472 			regs[nreg].pci_size_low =
2473 			    assigned[nasgn].pci_size_low = len;
2474 			type = base & (~PCI_BASE_IO_ADDR_M);
2475 			base &= PCI_BASE_IO_ADDR_M;
2476 			/*
2477 			 * A device under a subtractive PPB can allocate
2478 			 * resources from its parent bus if there is no resource
2479 			 * available on its own bus.
2480 			 */
2481 			if ((config_op == CONFIG_NEW) && (*io_avail == NULL)) {
2482 				res_bus = bus;
2483 				while (pci_bus_res[res_bus].subtractive) {
2484 					res_bus = pci_bus_res[res_bus].par_bus;
2485 					if (res_bus == (uchar_t)-1)
2486 						break; /* root bus already */
2487 					if (pci_bus_res[res_bus].io_avail) {
2488 						io_avail = &pci_bus_res
2489 						    [res_bus].io_avail;
2490 						break;
2491 					}
2492 				}
2493 			}
2494 
2495 			/*
2496 			 * first pass - gather what's there
2497 			 * update/second pass - adjust/allocate regions
2498 			 *	config - allocate regions
2499 			 */
2500 			if (config_op == CONFIG_INFO) {	/* first pass */
2501 				/* take out of the resource map of the bus */
2502 				if (base != 0) {
2503 					(void) memlist_remove(io_avail, base,
2504 					    len);
2505 					memlist_insert(io_used, base, len);
2506 				} else {
2507 					reprogram = 1;
2508 				}
2509 				pci_bus_res[bus].io_size += len;
2510 			} else if ((*io_avail && base == 0) ||
2511 			    pci_bus_res[bus].io_reprogram) {
2512 				base = (uint_t)memlist_find(io_avail, len, len);
2513 				if (base != 0) {
2514 					memlist_insert(io_used, base, len);
2515 					/* XXX need to worry about 64-bit? */
2516 					pci_putl(bus, dev, func, offset,
2517 					    base | type);
2518 					base = pci_getl(bus, dev, func, offset);
2519 					base &= PCI_BASE_IO_ADDR_M;
2520 				}
2521 				if (base == 0) {
2522 					cmn_err(CE_WARN, "failed to program"
2523 					    " IO space [%d/%d/%d] BAR@0x%x"
2524 					    " length 0x%x",
2525 					    bus, dev, func, offset, len);
2526 				}
2527 			}
2528 			assigned[nasgn].pci_phys_low = base;
2529 			nreg++, nasgn++;
2530 
2531 		} else {
2532 			/* memory space */
2533 			if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) {
2534 				bar_sz = PCI_BAR_SZ_64;
2535 				base_hi = pci_getl(bus, dev, func, offset + 4);
2536 				phys_hi = PCI_ADDR_MEM64;
2537 			} else {
2538 				bar_sz = PCI_BAR_SZ_32;
2539 				base_hi = 0;
2540 				phys_hi = PCI_ADDR_MEM32;
2541 			}
2542 
2543 			/* skip base regs with size of 0 */
2544 			value &= PCI_BASE_M_ADDR_M;
2545 
2546 			if (value == 0)
2547 				continue;
2548 
2549 			len = ((value ^ (value-1)) + 1) >> 1;
2550 			regs[nreg].pci_size_low =
2551 			    assigned[nasgn].pci_size_low = len;
2552 
2553 			phys_hi |= (devloc | offset);
2554 			if (base & PCI_BASE_PREF_M)
2555 				phys_hi |= PCI_PREFETCH_B;
2556 
2557 			/*
2558 			 * A device under a subtractive PPB can allocate
2559 			 * resources from its parent bus if there is no resource
2560 			 * available on its own bus.
2561 			 */
2562 			if ((config_op == CONFIG_NEW) && (*mem_avail == NULL)) {
2563 				res_bus = bus;
2564 				while (pci_bus_res[res_bus].subtractive) {
2565 					res_bus = pci_bus_res[res_bus].par_bus;
2566 					if (res_bus == (uchar_t)-1)
2567 						break; /* root bus already */
2568 					mem_avail =
2569 					    &pci_bus_res[res_bus].mem_avail;
2570 					pmem_avail =
2571 					    &pci_bus_res [res_bus].pmem_avail;
2572 					/*
2573 					 * Break out as long as at least
2574 					 * mem_avail is available
2575 					 */
2576 					if ((*pmem_avail &&
2577 					    (phys_hi & PCI_PREFETCH_B)) ||
2578 					    *mem_avail)
2579 						break;
2580 				}
2581 			}
2582 
2583 			regs[nreg].pci_phys_hi =
2584 			    assigned[nasgn].pci_phys_hi = phys_hi;
2585 			assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B;
2586 			assigned[nasgn].pci_phys_mid = base_hi;
2587 			type = base & ~PCI_BASE_M_ADDR_M;
2588 			base &= PCI_BASE_M_ADDR_M;
2589 
2590 			if (config_op == CONFIG_INFO) {
2591 				/* take out of the resource map of the bus */
2592 				if (base != NULL) {
2593 					/* remove from PMEM and MEM space */
2594 					(void) memlist_remove(mem_avail,
2595 					    base, len);
2596 					(void) memlist_remove(pmem_avail,
2597 					    base, len);
2598 					/* only note as used in correct map */
2599 					if (phys_hi & PCI_PREFETCH_B)
2600 						memlist_insert(pmem_used,
2601 						    base, len);
2602 					else
2603 						memlist_insert(mem_used,
2604 						    base, len);
2605 				} else {
2606 					reprogram = 1;
2607 				}
2608 				pci_bus_res[bus].mem_size += len;
2609 			} else if ((*mem_avail && base == NULL) ||
2610 			    pci_bus_res[bus].mem_reprogram) {
2611 				/*
2612 				 * When desired, attempt a prefetchable
2613 				 * allocation first
2614 				 */
2615 				if (phys_hi & PCI_PREFETCH_B) {
2616 					base = (uint_t)memlist_find(pmem_avail,
2617 					    len, len);
2618 					if (base != NULL) {
2619 						memlist_insert(pmem_used,
2620 						    base, len);
2621 						(void) memlist_remove(mem_avail,
2622 						    base, len);
2623 					}
2624 				}
2625 				/*
2626 				 * If prefetchable allocation was not
2627 				 * desired, or failed, attempt ordinary
2628 				 * memory allocation
2629 				 */
2630 				if (base == NULL) {
2631 					base = (uint_t)memlist_find(mem_avail,
2632 					    len, len);
2633 					if (base != NULL) {
2634 						memlist_insert(mem_used,
2635 						    base, len);
2636 						(void) memlist_remove(
2637 						    pmem_avail, base, len);
2638 					}
2639 				}
2640 				if (base != NULL) {
2641 					pci_putl(bus, dev, func, offset,
2642 					    base | type);
2643 					base = pci_getl(bus, dev, func, offset);
2644 					base &= PCI_BASE_M_ADDR_M;
2645 				} else
2646 					cmn_err(CE_WARN, "failed to program "
2647 					    "mem space [%d/%d/%d] BAR@0x%x"
2648 					    " length 0x%x",
2649 					    bus, dev, func, offset, len);
2650 			}
2651 			assigned[nasgn].pci_phys_low = base;
2652 			nreg++, nasgn++;
2653 		}
2654 	}
2655 	switch (header) {
2656 	case PCI_HEADER_ZERO:
2657 		offset = PCI_CONF_ROM;
2658 		break;
2659 	case PCI_HEADER_PPB:
2660 		offset = PCI_BCNF_ROM;
2661 		break;
2662 	default: /* including PCI_HEADER_CARDBUS */
2663 		goto done;
2664 	}
2665 
2666 	/*
2667 	 * Add the expansion rom memory space
2668 	 * Determine the size of the ROM base reg; don't write reserved bits
2669 	 * ROM isn't in the PCI memory space.
2670 	 */
2671 	base = pci_getl(bus, dev, func, offset);
2672 	pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M);
2673 	value = pci_getl(bus, dev, func, offset);
2674 	pci_putl(bus, dev, func, offset, base);
2675 	if (value & PCI_BASE_ROM_ENABLE)
2676 		value &= PCI_BASE_ROM_ADDR_M;
2677 	else
2678 		value = 0;
2679 
2680 	if (value != 0) {
2681 		regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset;
2682 		assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B |
2683 		    PCI_ADDR_MEM32 | devloc) + offset;
2684 		base &= PCI_BASE_ROM_ADDR_M;
2685 		assigned[nasgn].pci_phys_low = base;
2686 		len = ((value ^ (value-1)) + 1) >> 1;
2687 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len;
2688 		nreg++, nasgn++;
2689 		/* take it out of the memory resource */
2690 		if (base != NULL) {
2691 			(void) memlist_remove(mem_avail, base, len);
2692 			memlist_insert(mem_used, base, len);
2693 			pci_bus_res[bus].mem_size += len;
2694 		}
2695 	}
2696 
2697 	/*
2698 	 * Account for "legacy" (alias) video adapter resources
2699 	 */
2700 
2701 	/* add the three hard-decode, aliased address spaces for VGA */
2702 	if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) ||
2703 	    (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) {
2704 
2705 		/* VGA hard decode 0x3b0-0x3bb */
2706 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2707 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2708 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0;
2709 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc;
2710 		nreg++, nasgn++;
2711 		(void) memlist_remove(io_avail, 0x3b0, 0xc);
2712 		memlist_insert(io_used, 0x3b0, 0xc);
2713 		pci_bus_res[bus].io_size += 0xc;
2714 
2715 		/* VGA hard decode 0x3c0-0x3df */
2716 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2717 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2718 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0;
2719 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20;
2720 		nreg++, nasgn++;
2721 		(void) memlist_remove(io_avail, 0x3c0, 0x20);
2722 		memlist_insert(io_used, 0x3c0, 0x20);
2723 		pci_bus_res[bus].io_size += 0x20;
2724 
2725 		/* Video memory */
2726 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2727 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_MEM32 | devloc);
2728 		regs[nreg].pci_phys_low =
2729 		    assigned[nasgn].pci_phys_low = 0xa0000;
2730 		regs[nreg].pci_size_low =
2731 		    assigned[nasgn].pci_size_low = 0x20000;
2732 		nreg++, nasgn++;
2733 		/* remove from MEM and PMEM space */
2734 		(void) memlist_remove(mem_avail, 0xa0000, 0x20000);
2735 		(void) memlist_remove(pmem_avail, 0xa0000, 0x20000);
2736 		memlist_insert(mem_used, 0xa0000, 0x20000);
2737 		pci_bus_res[bus].mem_size += 0x20000;
2738 	}
2739 
2740 	/* add the hard-decode, aliased address spaces for 8514 */
2741 	if ((baseclass == PCI_CLASS_DISPLAY) &&
2742 	    (subclass == PCI_DISPLAY_VGA) &&
2743 	    (progclass & PCI_DISPLAY_IF_8514)) {
2744 
2745 		/* hard decode 0x2e8 */
2746 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2747 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2748 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8;
2749 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1;
2750 		nreg++, nasgn++;
2751 		(void) memlist_remove(io_avail, 0x2e8, 0x1);
2752 		memlist_insert(io_used, 0x2e8, 0x1);
2753 		pci_bus_res[bus].io_size += 0x1;
2754 
2755 		/* hard decode 0x2ea-0x2ef */
2756 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2757 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2758 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea;
2759 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6;
2760 		nreg++, nasgn++;
2761 		(void) memlist_remove(io_avail, 0x2ea, 0x6);
2762 		memlist_insert(io_used, 0x2ea, 0x6);
2763 		pci_bus_res[bus].io_size += 0x6;
2764 	}
2765 
2766 done:
2767 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg",
2768 	    (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int));
2769 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
2770 	    "assigned-addresses",
2771 	    (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int));
2772 
2773 	return (reprogram);
2774 }
2775 
2776 static void
2777 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
2778     int pciex, ushort_t is_pci_bridge)
2779 {
2780 	char *dev_type;
2781 	int i;
2782 	uint_t val;
2783 	uint64_t io_range[2], mem_range[2], pmem_range[2];
2784 	uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
2785 	uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
2786 	uchar_t progclass;
2787 
2788 	ASSERT(secbus <= subbus);
2789 
2790 	/*
2791 	 * Check if it's a subtractive PPB.
2792 	 */
2793 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
2794 	if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE)
2795 		pci_bus_res[secbus].subtractive = B_TRUE;
2796 
2797 	/*
2798 	 * Some BIOSes lie about max pci busses, we allow for
2799 	 * such mistakes here
2800 	 */
2801 	if (subbus > pci_bios_maxbus) {
2802 		pci_bios_maxbus = subbus;
2803 		alloc_res_array();
2804 	}
2805 
2806 	ASSERT(pci_bus_res[secbus].dip == NULL);
2807 	pci_bus_res[secbus].dip = dip;
2808 	pci_bus_res[secbus].par_bus = bus;
2809 
2810 	dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci";
2811 
2812 	/* setup bus number hierarchy */
2813 	pci_bus_res[secbus].sub_bus = subbus;
2814 	/*
2815 	 * Keep track of the largest subordinate bus number (this is essential
2816 	 * for peer busses because there is no other way of determining its
2817 	 * subordinate bus number).
2818 	 */
2819 	if (subbus > pci_bus_res[bus].sub_bus)
2820 		pci_bus_res[bus].sub_bus = subbus;
2821 	/*
2822 	 * Loop through subordinate busses, initializing their parent bus
2823 	 * field to this bridge's parent.  The subordinate busses' parent
2824 	 * fields may very well be further refined later, as child bridges
2825 	 * are enumerated.  (The value is to note that the subordinate busses
2826 	 * are not peer busses by changing their par_bus fields to anything
2827 	 * other than -1.)
2828 	 */
2829 	for (i = secbus + 1; i <= subbus; i++)
2830 		pci_bus_res[i].par_bus = bus;
2831 
2832 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
2833 	    "device_type", dev_type);
2834 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2835 	    "#address-cells", 3);
2836 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2837 	    "#size-cells", 2);
2838 
2839 	/*
2840 	 * Collect bridge window specifications, and use them to populate
2841 	 * the "avail" resources for the bus.  Not all of those resources will
2842 	 * end up being available; this is done top-down, and so the initial
2843 	 * collection of windows populates the 'ranges' property for the
2844 	 * bus node.  Later, as children are found, resources are removed from
2845 	 * the 'avail' list, so that it becomes the freelist for
2846 	 * this point in the tree.  ranges may be set again after bridge
2847 	 * reprogramming in fix_ppb_res(), in which case it's set from
2848 	 * used + avail.
2849 	 *
2850 	 * According to PPB spec, the base register should be programmed
2851 	 * with a value bigger than the limit register when there are
2852 	 * no resources available. This applies to io, memory, and
2853 	 * prefetchable memory.
2854 	 */
2855 
2856 	/*
2857 	 * io range
2858 	 * We determine i/o windows that are left unconfigured by BIOS
2859 	 * through its i/o enable bit as Microsoft recommends OEMs to do.
2860 	 * If it is unset, we disable i/o and mark it for reconfiguration in
2861 	 * later passes by setting the base > limit
2862 	 */
2863 	val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM);
2864 	if (val & PCI_COMM_IO) {
2865 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
2866 		io_range[0] = ((val & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT);
2867 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
2868 		io_range[1]  = ((val & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT) |
2869 		    0xfff;
2870 		if ((io_range[0] & PCI_BCNF_ADDR_MASK) == PCI_BCNF_IO_32BIT) {
2871 			uint16_t io_base_hi, io_limit_hi;
2872 			io_base_hi = pci_getw(bus, dev, func,
2873 			    PCI_BCNF_IO_BASE_HI);
2874 			io_limit_hi = pci_getw(bus, dev, func,
2875 			    PCI_BCNF_IO_LIMIT_HI);
2876 
2877 			io_range[0] |= (uint32_t)io_base_hi << 16;
2878 			io_range[1] |= (uint32_t)io_limit_hi << 16;
2879 		}
2880 	} else {
2881 		io_range[0] = 0x9fff;
2882 		io_range[1] = 0x1000;
2883 		pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
2884 		    (uint8_t)((io_range[0] >> 8) & 0xf0));
2885 		pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
2886 		    (uint8_t)((io_range[1] >> 8) & 0xf0));
2887 		pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
2888 		pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
2889 	}
2890 
2891 	if (io_range[0] != 0 && io_range[0] < io_range[1]) {
2892 		memlist_insert(&pci_bus_res[secbus].io_avail,
2893 		    io_range[0], (io_range[1] - io_range[0] + 1));
2894 		memlist_insert(&pci_bus_res[bus].io_used,
2895 		    io_range[0], (io_range[1] - io_range[0] + 1));
2896 		if (pci_bus_res[bus].io_avail != NULL) {
2897 			(void) memlist_remove(&pci_bus_res[bus].io_avail,
2898 			    io_range[0], (io_range[1] - io_range[0] + 1));
2899 		}
2900 		dcmn_err(CE_NOTE, "bus %d io-range: 0x%" PRIx64 "-%" PRIx64,
2901 		    secbus, io_range[0], io_range[1]);
2902 	}
2903 
2904 	/* mem range */
2905 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
2906 	mem_range[0] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT);
2907 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
2908 	mem_range[1] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT) |
2909 	    0xfffff;
2910 	if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) {
2911 		memlist_insert(&pci_bus_res[secbus].mem_avail,
2912 		    (uint64_t)mem_range[0],
2913 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2914 		memlist_insert(&pci_bus_res[bus].mem_used,
2915 		    (uint64_t)mem_range[0],
2916 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2917 		/* remove from parent resource list */
2918 		(void) memlist_remove(&pci_bus_res[bus].mem_avail,
2919 		    (uint64_t)mem_range[0],
2920 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2921 		(void) memlist_remove(&pci_bus_res[bus].pmem_avail,
2922 		    (uint64_t)mem_range[0],
2923 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2924 		dcmn_err(CE_NOTE, "bus %d mem-range: 0x%" PRIx64 "-%" PRIx64,
2925 		    secbus, mem_range[0], mem_range[1]);
2926 	}
2927 
2928 	/* prefetchable memory range */
2929 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW);
2930 	pmem_range[0] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT);
2931 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW);
2932 	pmem_range[1] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT) |
2933 	    0xfffff;
2934 	if ((pmem_range[0] & PCI_BCNF_ADDR_MASK) == PCI_BCNF_PF_MEM_64BIT) {
2935 		uint32_t pf_addr_hi, pf_limit_hi;
2936 		pf_addr_hi = pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH);
2937 		pf_limit_hi = pci_getl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH);
2938 		pmem_range[0] |= (uint64_t)pf_addr_hi << 32;
2939 		pmem_range[1] |= (uint64_t)pf_limit_hi << 32;
2940 	}
2941 	if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) {
2942 		memlist_insert(&pci_bus_res[secbus].pmem_avail,
2943 		    (uint64_t)pmem_range[0],
2944 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2945 		memlist_insert(&pci_bus_res[bus].pmem_used,
2946 		    (uint64_t)pmem_range[0],
2947 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2948 		/* remove from parent resource list */
2949 		(void) memlist_remove(&pci_bus_res[bus].pmem_avail,
2950 		    (uint64_t)pmem_range[0],
2951 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2952 		(void) memlist_remove(&pci_bus_res[bus].mem_avail,
2953 		    (uint64_t)pmem_range[0],
2954 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2955 		dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%" PRIx64 "-%" PRIx64,
2956 		    secbus, pmem_range[0], pmem_range[1]);
2957 	}
2958 
2959 	/*
2960 	 * Add VGA legacy resources to the bridge's pci_bus_res if it
2961 	 * has VGA_ENABLE set.  Note that we put them in 'avail',
2962 	 * because that's used to populate the ranges prop; they'll be
2963 	 * removed from there by the VGA device once it's found.  Also,
2964 	 * remove them from the parent's available list and note them as
2965 	 * used in the parent.
2966 	 */
2967 
2968 	if (pci_getw(bus, dev, func, PCI_BCNF_BCNTRL) &
2969 	    PCI_BCNF_BCNTRL_VGA_ENABLE) {
2970 
2971 		memlist_insert(&pci_bus_res[secbus].io_avail, 0x3b0, 0xc);
2972 
2973 		memlist_insert(&pci_bus_res[bus].io_used, 0x3b0, 0xc);
2974 		if (pci_bus_res[bus].io_avail != NULL) {
2975 			(void) memlist_remove(&pci_bus_res[bus].io_avail,
2976 			    0x3b0, 0xc);
2977 		}
2978 
2979 		memlist_insert(&pci_bus_res[secbus].io_avail, 0x3c0, 0x20);
2980 
2981 		memlist_insert(&pci_bus_res[bus].io_used, 0x3c0, 0x20);
2982 		if (pci_bus_res[bus].io_avail != NULL) {
2983 			(void) memlist_remove(&pci_bus_res[bus].io_avail,
2984 			    0x3c0, 0x20);
2985 		}
2986 
2987 		memlist_insert(&pci_bus_res[secbus].mem_avail, 0xa0000,
2988 		    0x20000);
2989 
2990 		memlist_insert(&pci_bus_res[bus].mem_used, 0xa0000, 0x20000);
2991 		if (pci_bus_res[bus].mem_avail != NULL) {
2992 			(void) memlist_remove(&pci_bus_res[bus].mem_avail,
2993 			    0xa0000, 0x20000);
2994 		}
2995 	}
2996 	add_bus_range_prop(secbus);
2997 	add_ranges_prop(secbus, 1);
2998 }
2999 
3000 extern const struct pci_class_strings_s class_pci[];
3001 extern int class_pci_items;
3002 
3003 static void
3004 add_model_prop(dev_info_t *dip, uint_t classcode)
3005 {
3006 	const char *desc;
3007 	int i;
3008 	uchar_t baseclass = classcode >> 16;
3009 	uchar_t subclass = (classcode >> 8) & 0xff;
3010 	uchar_t progclass = classcode & 0xff;
3011 
3012 	if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) {
3013 		desc = "IDE controller";
3014 	} else {
3015 		for (desc = 0, i = 0; i < class_pci_items; i++) {
3016 			if ((baseclass == class_pci[i].base_class) &&
3017 			    (subclass == class_pci[i].sub_class) &&
3018 			    (progclass == class_pci[i].prog_class)) {
3019 				desc = class_pci[i].actual_desc;
3020 				break;
3021 			}
3022 		}
3023 		if (i == class_pci_items)
3024 			desc = "Unknown class of pci/pnpbios device";
3025 	}
3026 
3027 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
3028 	    (char *)desc);
3029 }
3030 
3031 static void
3032 add_bus_range_prop(int bus)
3033 {
3034 	int bus_range[2];
3035 
3036 	if (pci_bus_res[bus].dip == NULL)
3037 		return;
3038 	bus_range[0] = bus;
3039 	bus_range[1] = pci_bus_res[bus].sub_bus;
3040 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
3041 	    "bus-range", (int *)bus_range, 2);
3042 }
3043 
3044 /*
3045  * Add slot-names property for any named pci hot-plug slots
3046  */
3047 static void
3048 add_bus_slot_names_prop(int bus)
3049 {
3050 	char slotprop[256];
3051 	int len;
3052 	extern int pci_irq_nroutes;
3053 	char *slotcap_name;
3054 
3055 	/*
3056 	 * If no irq routing table, then go with the slot-names as set up
3057 	 * in pciex_slot_names_prop() from slot capability register (if any).
3058 	 */
3059 	if (pci_irq_nroutes == 0)
3060 		return;
3061 
3062 	/*
3063 	 * Otherise delete the slot-names we already have and use the irq
3064 	 * routing table values as returned by pci_slot_names_prop() instead,
3065 	 * but keep any property of value "pcie0" as that can't be represented
3066 	 * in the irq routing table.
3067 	 */
3068 	if (pci_bus_res[bus].dip != NULL) {
3069 		if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pci_bus_res[bus].dip,
3070 		    DDI_PROP_DONTPASS, "slot-names", &slotcap_name) !=
3071 		    DDI_SUCCESS || strcmp(slotcap_name, "pcie0") != 0)
3072 			(void) ndi_prop_remove(DDI_DEV_T_NONE,
3073 			    pci_bus_res[bus].dip, "slot-names");
3074 	}
3075 
3076 	len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop));
3077 	if (len > 0) {
3078 		/*
3079 		 * Only create a peer bus node if this bus may be a peer bus.
3080 		 * It may be a peer bus if the dip is NULL and if par_bus is
3081 		 * -1 (par_bus is -1 if this bus was not found to be
3082 		 * subordinate to any PCI-PCI bridge).
3083 		 * If it's not a peer bus, then the ACPI BBN-handling code
3084 		 * will remove it later.
3085 		 */
3086 		if (pci_bus_res[bus].par_bus == (uchar_t)-1 &&
3087 		    pci_bus_res[bus].dip == NULL) {
3088 
3089 			create_root_bus_dip(bus);
3090 		}
3091 		if (pci_bus_res[bus].dip != NULL) {
3092 			ASSERT((len % sizeof (int)) == 0);
3093 			(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
3094 			    pci_bus_res[bus].dip, "slot-names",
3095 			    (int *)slotprop, len / sizeof (int));
3096 		} else {
3097 			cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI "
3098 			    "IRQ routing table; Not adding slot-names "
3099 			    "property for incorrect bus %d", bus);
3100 		}
3101 	}
3102 }
3103 
3104 /*
3105  * Handle both PCI root and PCI-PCI bridge range properties;
3106  * non-zero 'ppb' argument select PCI-PCI bridges versus root.
3107  */
3108 static void
3109 memlist_to_ranges(void **rp, struct memlist *entry, uint_t type, int ppb)
3110 {
3111 	ppb_ranges_t *ppb_rp = *rp;
3112 	pci_ranges_t *pci_rp = *rp;
3113 
3114 	while (entry != NULL) {
3115 		uint_t atype = type;
3116 		if ((type & PCI_REG_ADDR_M) == PCI_ADDR_MEM32 &&
3117 		    (entry->ml_address >= UINT32_MAX ||
3118 		    entry->ml_size >= UINT32_MAX)) {
3119 			atype &= ~PCI_ADDR_MEM32;
3120 			atype |= PCI_ADDR_MEM64;
3121 		}
3122 		if (ppb) {
3123 			ppb_rp->child_high = ppb_rp->parent_high = atype;
3124 			ppb_rp->child_mid = ppb_rp->parent_mid =
3125 			    (uint32_t)(entry->ml_address >> 32);
3126 			ppb_rp->child_low = ppb_rp->parent_low =
3127 			    (uint32_t)entry->ml_address;
3128 			ppb_rp->size_high =
3129 			    (uint32_t)(entry->ml_size >> 32);
3130 			ppb_rp->size_low = (uint32_t)entry->ml_size;
3131 			*rp = ++ppb_rp;
3132 		} else {
3133 			pci_rp->child_high = atype;
3134 			pci_rp->child_mid = pci_rp->parent_high =
3135 			    (uint32_t)(entry->ml_address >> 32);
3136 			pci_rp->child_low = pci_rp->parent_low =
3137 			    (uint32_t)entry->ml_address;
3138 			pci_rp->size_high =
3139 			    (uint32_t)(entry->ml_size >> 32);
3140 			pci_rp->size_low = (uint32_t)entry->ml_size;
3141 			*rp = ++pci_rp;
3142 		}
3143 		entry = entry->ml_next;
3144 	}
3145 }
3146 
3147 static void
3148 add_ranges_prop(int bus, int ppb)
3149 {
3150 	int total, alloc_size;
3151 	void	*rp, *next_rp;
3152 	struct memlist *iolist, *memlist, *pmemlist;
3153 
3154 	/* no devinfo node - unused bus, return */
3155 	if (pci_bus_res[bus].dip == NULL)
3156 		return;
3157 
3158 	iolist = memlist = pmemlist = (struct memlist *)NULL;
3159 
3160 	memlist_merge(&pci_bus_res[bus].io_avail, &iolist);
3161 	memlist_merge(&pci_bus_res[bus].io_used, &iolist);
3162 	memlist_merge(&pci_bus_res[bus].mem_avail, &memlist);
3163 	memlist_merge(&pci_bus_res[bus].mem_used, &memlist);
3164 	memlist_merge(&pci_bus_res[bus].pmem_avail, &pmemlist);
3165 	memlist_merge(&pci_bus_res[bus].pmem_used, &pmemlist);
3166 
3167 	total = memlist_count(iolist);
3168 	total += memlist_count(memlist);
3169 	total += memlist_count(pmemlist);
3170 
3171 	/* no property is created if no ranges are present */
3172 	if (total == 0)
3173 		return;
3174 
3175 	alloc_size = total *
3176 	    (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t));
3177 
3178 	next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP);
3179 
3180 	memlist_to_ranges(&next_rp, iolist, PCI_ADDR_IO | PCI_REG_REL_M, ppb);
3181 	memlist_to_ranges(&next_rp, memlist,
3182 	    PCI_ADDR_MEM32 | PCI_REG_REL_M, ppb);
3183 	memlist_to_ranges(&next_rp, pmemlist,
3184 	    PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M, ppb);
3185 
3186 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
3187 	    "ranges", (int *)rp, alloc_size / sizeof (int));
3188 
3189 	kmem_free(rp, alloc_size);
3190 	memlist_free_all(&iolist);
3191 	memlist_free_all(&memlist);
3192 	memlist_free_all(&pmemlist);
3193 }
3194 
3195 static void
3196 memlist_remove_list(struct memlist **list, struct memlist *remove_list)
3197 {
3198 	while (list && *list && remove_list) {
3199 		(void) memlist_remove(list, remove_list->ml_address,
3200 		    remove_list->ml_size);
3201 		remove_list = remove_list->ml_next;
3202 	}
3203 }
3204 
3205 static int
3206 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type)
3207 {
3208 	int i = 0;
3209 
3210 	while (list) {
3211 		/* assume 32-bit addresses */
3212 		sp->pci_phys_hi = type;
3213 		sp->pci_phys_mid = 0;
3214 		sp->pci_phys_low = (uint32_t)list->ml_address;
3215 		sp->pci_size_hi = 0;
3216 		sp->pci_size_low = (uint32_t)list->ml_size;
3217 
3218 		list = list->ml_next;
3219 		sp++, i++;
3220 	}
3221 	return (i);
3222 }
3223 
3224 static void
3225 add_bus_available_prop(int bus)
3226 {
3227 	int i, count;
3228 	struct pci_phys_spec *sp;
3229 
3230 	/* no devinfo node - unused bus, return */
3231 	if (pci_bus_res[bus].dip == NULL)
3232 		return;
3233 
3234 	count = memlist_count(pci_bus_res[bus].io_avail) +
3235 	    memlist_count(pci_bus_res[bus].mem_avail) +
3236 	    memlist_count(pci_bus_res[bus].pmem_avail);
3237 
3238 	if (count == 0)		/* nothing available */
3239 		return;
3240 
3241 	sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP);
3242 	i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_avail,
3243 	    PCI_ADDR_IO | PCI_REG_REL_M);
3244 	i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_avail,
3245 	    PCI_ADDR_MEM32 | PCI_REG_REL_M);
3246 	i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_avail,
3247 	    PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M);
3248 	ASSERT(i == count);
3249 
3250 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
3251 	    "available", (int *)sp,
3252 	    i * sizeof (struct pci_phys_spec) / sizeof (int));
3253 	kmem_free(sp, count * sizeof (*sp));
3254 }
3255 
3256 static void
3257 alloc_res_array(void)
3258 {
3259 	static int array_size = 0;
3260 	int old_size;
3261 	void *old_res;
3262 
3263 	if (array_size > pci_bios_maxbus + 1)
3264 		return;	/* array is big enough */
3265 
3266 	old_size = array_size;
3267 	old_res = pci_bus_res;
3268 
3269 	if (array_size == 0)
3270 		array_size = 16;	/* start with a reasonable number */
3271 
3272 	while (array_size <= pci_bios_maxbus + 1)
3273 		array_size <<= 1;
3274 	pci_bus_res = (struct pci_bus_resource *)kmem_zalloc(
3275 	    array_size * sizeof (struct pci_bus_resource), KM_SLEEP);
3276 
3277 	if (old_res) {	/* copy content and free old array */
3278 		bcopy(old_res, pci_bus_res,
3279 		    old_size * sizeof (struct pci_bus_resource));
3280 		kmem_free(old_res, old_size * sizeof (struct pci_bus_resource));
3281 	}
3282 }
3283 
3284 static void
3285 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
3286     ushort_t deviceid)
3287 {
3288 	static dev_info_t *ioapicsnode = NULL;
3289 	static int numioapics = 0;
3290 	dev_info_t *ioapic_node;
3291 	uint64_t physaddr;
3292 	uint32_t lobase, hibase = 0;
3293 
3294 	/* BAR 0 contains the IOAPIC's memory-mapped I/O address */
3295 	lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0);
3296 
3297 	/* We (and the rest of the world) only support memory-mapped IOAPICs */
3298 	if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM)
3299 		return;
3300 
3301 	if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL)
3302 		hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4);
3303 
3304 	lobase &= PCI_BASE_M_ADDR_M;
3305 
3306 	physaddr = (((uint64_t)hibase) << 32) | lobase;
3307 
3308 	/*
3309 	 * Create a nexus node for all IOAPICs under the root node.
3310 	 */
3311 	if (ioapicsnode == NULL) {
3312 		if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME,
3313 		    (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) {
3314 			return;
3315 		}
3316 		(void) ndi_devi_online(ioapicsnode, 0);
3317 	}
3318 
3319 	/*
3320 	 * Create a child node for this IOAPIC
3321 	 */
3322 	ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME,
3323 	    DEVI_SID_NODEID, numioapics++);
3324 	if (ioapic_node == NULL) {
3325 		return;
3326 	}
3327 
3328 	/* Vendor and Device ID */
3329 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node,
3330 	    IOAPICS_PROP_VENID, vendorid);
3331 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node,
3332 	    IOAPICS_PROP_DEVID, deviceid);
3333 
3334 	/* device_type */
3335 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node,
3336 	    "device_type", IOAPICS_DEV_TYPE);
3337 
3338 	/* reg */
3339 	(void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node,
3340 	    "reg", physaddr);
3341 }
3342 
3343 /*
3344  * NOTE: For PCIe slots, the name is generated from the slot number
3345  * information obtained from Slot Capabilities register.
3346  * For non-PCIe slots, it is generated based on the slot number
3347  * information in the PCI IRQ table.
3348  */
3349 static void
3350 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num)
3351 {
3352 	char slotprop[256];
3353 	int len;
3354 
3355 	bzero(slotprop, sizeof (slotprop));
3356 
3357 	/* set mask to 1 as there is only one slot (i.e dev 0) */
3358 	*(uint32_t *)slotprop = 1;
3359 	len = 4;
3360 	(void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d",
3361 	    slot_num);
3362 	len += strlen(slotprop + len) + 1;
3363 	len += len % 4;
3364 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names",
3365 	    (int *)slotprop, len / sizeof (int));
3366 }
3367 
3368 /*
3369  * Enable reporting of AER capability next pointer.
3370  * This needs to be done only for CK8-04 devices
3371  * by setting NV_XVR_VEND_CYA1 (offset 0xf40) bit 13
3372  * NOTE: BIOS is disabling this, it needs to be enabled temporarily
3373  *
3374  * This function is adapted from npe_ck804_fix_aer_ptr(), and is
3375  * called from pci_boot.c.
3376  */
3377 static void
3378 ck804_fix_aer_ptr(dev_info_t *dip, pcie_req_id_t bdf)
3379 {
3380 	dev_info_t *rcdip;
3381 	ushort_t cya1;
3382 
3383 	rcdip = pcie_get_rc_dip(dip);
3384 	ASSERT(rcdip != NULL);
3385 
3386 	if ((pci_cfgacc_get16(rcdip, bdf, PCI_CONF_VENID) ==
3387 	    NVIDIA_VENDOR_ID) &&
3388 	    (pci_cfgacc_get16(rcdip, bdf, PCI_CONF_DEVID) ==
3389 	    NVIDIA_CK804_DEVICE_ID) &&
3390 	    (pci_cfgacc_get8(rcdip, bdf, PCI_CONF_REVID) >=
3391 	    NVIDIA_CK804_AER_VALID_REVID)) {
3392 		cya1 = pci_cfgacc_get16(rcdip, bdf, NVIDIA_CK804_VEND_CYA1_OFF);
3393 		if (!(cya1 & ~NVIDIA_CK804_VEND_CYA1_ERPT_MASK))
3394 			(void) pci_cfgacc_put16(rcdip, bdf,
3395 			    NVIDIA_CK804_VEND_CYA1_OFF,
3396 			    cya1 | NVIDIA_CK804_VEND_CYA1_ERPT_VAL);
3397 	}
3398 }
3399