1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/stat.h> 30 #include <sys/sunndi.h> 31 #include <sys/pci.h> 32 #include <sys/pci_impl.h> 33 #include <sys/pci_cfgspace.h> 34 #include <sys/memlist.h> 35 #include <sys/bootconf.h> 36 #include <io/pci/mps_table.h> 37 #include <sys/pci_cfgspace.h> 38 #include <sys/pci_cfgspace_impl.h> 39 #include <sys/psw.h> 40 #include "../../../../common/pci/pci_strings.h" 41 #include <sys/apic.h> 42 #include <io/pciex/pcie_nvidia.h> 43 #include <sys/acpi/acpi.h> 44 #include <sys/acpica.h> 45 46 #define pci_getb (*pci_getb_func) 47 #define pci_getw (*pci_getw_func) 48 #define pci_getl (*pci_getl_func) 49 #define pci_putb (*pci_putb_func) 50 #define pci_putw (*pci_putw_func) 51 #define pci_putl (*pci_putl_func) 52 #define dcmn_err if (pci_boot_debug) cmn_err 53 54 #define CONFIG_INFO 0 55 #define CONFIG_UPDATE 1 56 #define CONFIG_NEW 2 57 #define CONFIG_FIX 3 58 #define COMPAT_BUFSIZE 512 59 60 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 61 #define LPC_IO_CONTROL_REG_1 0x40 62 #define AMD8111_ENABLENMI (uint8_t)0x80 63 #define DEVID_AMD8111_LPC 0x7468 64 65 struct pci_fixundo { 66 uint8_t bus; 67 uint8_t dev; 68 uint8_t fn; 69 void (*undofn)(uint8_t, uint8_t, uint8_t); 70 struct pci_fixundo *next; 71 }; 72 73 extern int pci_bios_nbus; 74 static uchar_t max_dev_pci = 32; /* PCI standard */ 75 int pci_boot_debug = 0; 76 extern struct memlist *find_bus_res(int, int); 77 static struct pci_fixundo *undolist = NULL; 78 79 /* 80 * Module prototypes 81 */ 82 static void enumerate_bus_devs(uchar_t bus, int config_op); 83 static void create_root_bus_dip(uchar_t bus); 84 static dev_info_t *process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 85 ushort_t, int); 86 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 87 ushort_t, ushort_t, uchar_t, uint_t, int); 88 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 89 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int); 90 static void add_model_prop(dev_info_t *, uint_t); 91 static void add_bus_range_prop(int); 92 static void add_bus_slot_names_prop(int); 93 static void add_ppb_ranges_prop(int); 94 static void add_bus_available_prop(int); 95 static void alloc_res_array(); 96 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 97 ushort_t deviceid); 98 99 extern int pci_slot_names_prop(int, char *, int); 100 101 /* set to 1 to force PCI peer-bus renumbering, -1 to prevent it */ 102 int pci_bus_always_renumber = 0; 103 104 /* get the subordinate bus # for a root/peer bus */ 105 static int 106 pci_root_subbus(int bus, uchar_t *subbus) 107 { 108 ACPI_HANDLE hdl; 109 ACPI_BUFFER rb; 110 ACPI_RESOURCE *rp; 111 int rv; 112 113 if (pci_bus_res[bus].dip == NULL) { 114 /* non-used bus # */ 115 return (AE_ERROR); 116 } 117 if (acpica_find_pciobj(pci_bus_res[bus].dip, &hdl) != AE_OK) { 118 cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus); 119 return (AE_ERROR); 120 } 121 122 rb.Length = ACPI_ALLOCATE_BUFFER; 123 if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) { 124 cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus); 125 return (AE_ERROR); 126 } 127 128 rv = AE_ERROR; 129 130 for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG; 131 rp = ACPI_NEXT_RESOURCE(rp)) { 132 133 switch (rp->Type) { 134 case ACPI_RESOURCE_TYPE_ADDRESS16: 135 if (rp->Data.Address.ResourceType 136 != ACPI_BUS_NUMBER_RANGE) 137 continue; 138 *subbus = (uchar_t)rp->Data.Address16.Maximum; 139 dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus); 140 break; 141 case ACPI_RESOURCE_TYPE_ADDRESS32: 142 if (rp->Data.Address.ResourceType 143 != ACPI_BUS_NUMBER_RANGE) 144 continue; 145 *subbus = (uchar_t)rp->Data.Address32.Maximum; 146 dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus); 147 break; 148 case ACPI_RESOURCE_TYPE_ADDRESS64: 149 if (rp->Data.Address.ResourceType 150 != ACPI_BUS_NUMBER_RANGE) 151 continue; 152 *subbus = (uchar_t)rp->Data.Address64.Maximum; 153 dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus); 154 break; 155 case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64: 156 if (rp->Data.Address.ResourceType 157 != ACPI_BUS_NUMBER_RANGE) 158 continue; 159 *subbus = (uchar_t)rp->Data.ExtAddress64.Maximum; 160 dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus); 161 break; 162 default: 163 dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type); 164 continue; 165 } 166 167 /* found the bus-range resource */ 168 dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus); 169 rv = AE_OK; 170 171 /* This breaks out of the resource scanning loop */ 172 break; 173 } 174 175 AcpiOsFree(rb.Pointer); 176 if (rv != AE_OK) 177 cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus); 178 179 return (rv); 180 181 } 182 183 /* 184 * Enumerate all PCI devices 185 */ 186 void 187 pci_setup_tree() 188 { 189 uchar_t i, root_bus_addr = 0; 190 191 alloc_res_array(); 192 for (i = 0; i <= pci_bios_nbus; i++) { 193 pci_bus_res[i].par_bus = (uchar_t)-1; 194 pci_bus_res[i].root_addr = (uchar_t)-1; 195 pci_bus_res[i].sub_bus = i; 196 } 197 198 pci_bus_res[0].root_addr = root_bus_addr++; 199 create_root_bus_dip(0); 200 enumerate_bus_devs(0, CONFIG_INFO); 201 202 /* 203 * Now enumerate peer busses 204 * 205 * We loop till pci_bios_nbus. On most systems, there is 206 * one more bus at the high end, which implements the ISA 207 * compatibility bus. We don't care about that. 208 * 209 * Note: In the old (bootconf) enumeration, the peer bus 210 * address did not use the bus number, and there were 211 * too many peer busses created. The root_bus_addr is 212 * used to maintain the old peer bus address assignment. 213 * However, we stop enumerating phantom peers with no 214 * device below. 215 */ 216 for (i = 1; i <= pci_bios_nbus; i++) { 217 if (pci_bus_res[i].dip == NULL) { 218 pci_bus_res[i].root_addr = root_bus_addr++; 219 } 220 enumerate_bus_devs(i, CONFIG_INFO); 221 222 /* add slot-names property for named pci hot-plug slots */ 223 add_bus_slot_names_prop(i); 224 } 225 226 } 227 228 /* 229 * >0 = present, 0 = not present, <0 = error 230 */ 231 static int 232 pci_bbn_present(int bus) 233 { 234 ACPI_HANDLE hdl; 235 ACPI_BUFFER rb; 236 int rv; 237 238 /* no dip means no _BBN */ 239 if (pci_bus_res[bus].dip == NULL) 240 return (0); 241 242 rv = acpica_find_pciobj(pci_bus_res[bus].dip, &hdl); 243 if (rv != AE_OK) 244 return (-1); 245 246 rb.Length = ACPI_ALLOCATE_BUFFER; 247 248 rv = AcpiEvaluateObject(hdl, "_BBN", NULL, &rb); 249 250 if (rb.Length > 0) 251 AcpiOsFree(rb.Pointer); 252 253 if (rv == AE_OK) 254 return (1); 255 else if (rv == AE_NOT_FOUND) 256 return (0); 257 else 258 return (-1); 259 } 260 261 /* 262 * Return non-zero if any PCI bus in the system has an associated 263 * _BBN object, 0 otherwise. 264 */ 265 static int 266 pci_roots_have_bbn(void) 267 { 268 int i; 269 270 /* 271 * Scan the PCI busses and look for at least 1 _BBN 272 */ 273 for (i = 0; i <= pci_bios_nbus; i++) { 274 /* skip non-root (peer) PCI busses */ 275 if (pci_bus_res[i].par_bus != (uchar_t)-1) 276 continue; 277 278 if (pci_bbn_present(i) > 0) 279 return (1); 280 } 281 return (0); 282 283 } 284 285 /* 286 * return non-zero if the machine is one on which we renumber 287 * the internal pci unit-addresses 288 */ 289 static int 290 pci_bus_renumber() 291 { 292 char *bus_prop; 293 long val; 294 295 /* allow over-ride via patchable variable */ 296 if (pci_bus_always_renumber > 0) 297 return (1); 298 else if (pci_bus_always_renumber < 0) 299 return (0); 300 301 /* 302 * Get the "pci-renumber-buses" boot property 303 * This property is set-up during installation; 304 * upgraded systems disable re-numbering to avoid the 305 * complication of changing physical device paths. 306 * 307 * If the "pci-renumber-buses" property is not found, 308 * this suggests an incomplete BFU or failure during 309 * upgrade. In either case, default to "don't renumber" 310 * so that a botched BFU/upgrade doesn't render a system 311 * unbootable. 312 */ 313 val = 0; 314 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 315 DDI_PROP_DONTPASS, "pci-renumber-buses", &bus_prop) == 316 DDI_PROP_SUCCESS) { 317 (void) ddi_strtol(bus_prop, NULL, 0, &val); 318 ddi_prop_free(bus_prop); 319 } 320 return (val); 321 } 322 323 /* 324 * Initial enumeration of the physical PCI bus hierarchy can 325 * leave 'gaps' in the order of peer PCI bus unit-addresses. 326 * Systems with more than one peer PCI bus *must* have an ACPI 327 * _BBN object associated with each peer bus; use the presence 328 * of this object to remove gaps in the numbering of the peer 329 * PCI bus unit-addresses - only peer busses with an associated 330 * _BBN are counted. 331 */ 332 static void 333 pci_renumber_root_busses(void) 334 { 335 int pci_regs[] = {0, 0, 0}; 336 int i, root_addr = 0; 337 338 if (!pci_bus_renumber()) 339 return; 340 341 /* 342 * If we find no _BBN objects at all, we either don't need 343 * to do anything or can't do anything anyway 344 */ 345 if (!pci_roots_have_bbn()) 346 return; 347 348 for (i = 0; i <= pci_bios_nbus; i++) { 349 /* skip non-root (peer) PCI busses */ 350 if (pci_bus_res[i].par_bus != (uchar_t)-1) 351 continue; 352 353 if (pci_bbn_present(i) < 1) { 354 pci_bus_res[i].root_addr = (uchar_t)-1; 355 continue; 356 } 357 358 ASSERT(pci_bus_res[i].dip != NULL); 359 if (pci_bus_res[i].root_addr != root_addr) { 360 /* update reg property for node */ 361 pci_bus_res[i].root_addr = root_addr; 362 pci_regs[0] = pci_bus_res[i].root_addr; 363 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 364 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 365 } 366 root_addr++; 367 } 368 } 369 370 static void 371 remove_resource_range(struct memlist **list, int *ranges, int range_count) 372 { 373 struct range { 374 uint32_t base; 375 uint32_t len; 376 }; 377 int index; 378 379 for (index = 0; index < range_count; index++) { 380 /* all done if list is or has become empty */ 381 if (*list == NULL) 382 break; 383 (void) memlist_remove(list, 384 (uint64_t)((struct range *)ranges)[index].base, 385 (uint64_t)((struct range *)ranges)[index].len); 386 } 387 } 388 389 static void 390 remove_used_resources() 391 { 392 dev_info_t *used; 393 int *narray; 394 uint_t ncount; 395 int status; 396 int bus; 397 398 used = ddi_find_devinfo("used-resources", -1, 0); 399 if (used == NULL) 400 return; 401 402 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 403 DDI_PROP_DONTPASS, "io-space", &narray, &ncount); 404 if (status == DDI_PROP_SUCCESS) { 405 for (bus = 0; bus <= pci_bios_nbus; bus++) 406 remove_resource_range(&pci_bus_res[bus].io_ports, 407 narray, ncount / 2); 408 ddi_prop_free(narray); 409 } 410 411 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 412 DDI_PROP_DONTPASS, "device-memory", &narray, &ncount); 413 if (status == DDI_PROP_SUCCESS) { 414 for (bus = 0; bus <= pci_bios_nbus; bus++) 415 remove_resource_range(&pci_bus_res[bus].mem_space, 416 narray, ncount / 2); 417 ddi_prop_free(narray); 418 } 419 } 420 421 void 422 pci_reprogram(void) 423 { 424 int i, pci_reconfig = 1; 425 char *onoff; 426 427 /* 428 * Excise phantom roots if possible 429 */ 430 pci_renumber_root_busses(); 431 432 /* add bus-range property for root/peer bus nodes */ 433 for (i = 0; i <= pci_bios_nbus; i++) { 434 if (pci_bus_res[i].par_bus == (uchar_t)-1) { 435 uchar_t subbus; 436 if (pci_root_subbus(i, &subbus) == AE_OK) 437 pci_bus_res[i].sub_bus = subbus; 438 add_bus_range_prop(i); 439 } 440 } 441 442 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 443 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 444 if (strcmp(onoff, "off") == 0) { 445 pci_reconfig = 0; 446 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 447 } 448 ddi_prop_free(onoff); 449 } 450 451 /* remove used-resources from PCI resource maps */ 452 remove_used_resources(); 453 454 for (i = 0; i <= pci_bios_nbus; i++) { 455 /* configure devices not configured by bios */ 456 if (pci_reconfig) 457 enumerate_bus_devs(i, CONFIG_NEW); 458 /* All dev programmed, so we can create available prop */ 459 add_bus_available_prop(i); 460 } 461 } 462 463 /* 464 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 465 */ 466 static void 467 create_root_bus_dip(uchar_t bus) 468 { 469 int pci_regs[] = {0, 0, 0}; 470 dev_info_t *dip; 471 472 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 473 474 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 475 (pnode_t)DEVI_SID_NODEID, &dip); 476 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 477 "#address-cells", 3); 478 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 479 "#size-cells", 2); 480 pci_regs[0] = pci_bus_res[bus].root_addr; 481 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 482 "reg", (int *)pci_regs, 3); 483 484 /* 485 * If system has PCIe bus, then create different properties 486 */ 487 if (create_pcie_root_bus(bus, dip) == B_FALSE) 488 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 489 "device_type", "pci"); 490 491 (void) ndi_devi_bind_driver(dip, 0); 492 pci_bus_res[bus].dip = dip; 493 pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 494 pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 495 pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 496 497 if (bus != 0) 498 return; 499 500 /* 501 * Special treatment of bus 0: 502 * If no resource from MPSPEC/HRT, copy pcimem from boot 503 * and make I/O space the entire range starting at 0x100. There 504 * is no difference between prefetchable memory or not. 505 */ 506 if (pci_bus_res[0].mem_space == NULL) 507 pci_bus_res[0].mem_space = 508 memlist_dup(bootops->boot_mem->pcimem); 509 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 510 if (pci_bus_res[0].io_ports == NULL) 511 memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xff00); 512 } 513 514 /* 515 * For any fixed configuration (often compatability) pci devices 516 * and those with their own expansion rom, create device nodes 517 * to hold the already configured device details. 518 */ 519 void 520 enumerate_bus_devs(uchar_t bus, int config_op) 521 { 522 uchar_t dev, func, nfunc, header; 523 ushort_t venid; 524 dev_info_t *dip; 525 struct pci_devfunc { 526 struct pci_devfunc *next; 527 dev_info_t *dip; 528 uchar_t bus; 529 uchar_t dev; 530 uchar_t func; 531 } *devlist = NULL, *entry; 532 533 if (config_op == CONFIG_NEW) { 534 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 535 } else if (config_op == CONFIG_FIX) { 536 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 537 } else 538 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 539 540 for (dev = 0; dev < max_dev_pci; dev++) { 541 nfunc = 1; 542 for (func = 0; func < nfunc; func++) { 543 544 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 545 dev, func); 546 547 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 548 549 if ((venid == 0xffff) || (venid == 0)) { 550 /* no function at this address */ 551 continue; 552 } 553 554 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 555 if (header == 0xff) { 556 continue; /* illegal value */ 557 } 558 559 /* 560 * according to some mail from Microsoft posted 561 * to the pci-drivers alias, their only requirement 562 * for a multifunction device is for the 1st 563 * function to have to PCI_HEADER_MULTI bit set. 564 */ 565 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 566 nfunc = 8; 567 } 568 569 if (config_op == CONFIG_FIX) { 570 /* 571 * If we're processing PCI fixes, no dip 572 * will be returned. 573 */ 574 (void) process_devfunc(bus, dev, func, header, 575 venid, config_op); 576 577 } else if (config_op == CONFIG_INFO) { 578 /* 579 * Create the node, unconditionally, on the 580 * first pass only. It may still need 581 * resource assignment, which will be 582 * done on the second, CONFIG_NEW, pass. 583 */ 584 dip = process_devfunc(bus, dev, func, header, 585 venid, config_op); 586 /* 587 * If dip isn't null, put on a list to 588 * save for reprogramming when config_op 589 * is CONFIG_NEW. 590 */ 591 592 if (dip) { 593 entry = kmem_alloc(sizeof (*entry), 594 KM_SLEEP); 595 entry->dip = dip; 596 entry->dev = dev; 597 entry->func = func; 598 entry->next = devlist; 599 devlist = entry; 600 } 601 } 602 } 603 } 604 605 if (config_op == CONFIG_NEW) { 606 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 607 while (devlist) { 608 entry = devlist; 609 devlist = entry->next; 610 cmn_err(CE_NOTE, 611 "!reprogram pci device [%d/%d/%d] (%s)", 612 bus, entry->dev, entry->func, 613 ddi_driver_name(entry->dip)); 614 (void) add_reg_props(entry->dip, bus, entry->dev, 615 entry->func, CONFIG_UPDATE, 0); 616 kmem_free(entry, sizeof (*entry)); 617 } 618 pci_bus_res[bus].privdata = NULL; 619 } else if (config_op != CONFIG_FIX) { 620 pci_bus_res[bus].privdata = devlist; 621 } 622 } 623 624 static int 625 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 626 ushort_t subvenid, ushort_t subdevid) 627 { 628 static int prop_exist = -1; 629 static char *pciide_str; 630 char compat[32]; 631 632 if (prop_exist == -1) { 633 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 634 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 635 &pciide_str) == DDI_SUCCESS); 636 } 637 638 if (!prop_exist) 639 return (0); 640 641 /* compare property value against various forms of compatible */ 642 if (subvenid) { 643 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 644 venid, devid, subvenid, subdevid, revid); 645 if (strcmp(pciide_str, compat) == 0) 646 return (1); 647 648 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 649 venid, devid, subvenid, subdevid); 650 if (strcmp(pciide_str, compat) == 0) 651 return (1); 652 653 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 654 subvenid, subdevid); 655 if (strcmp(pciide_str, compat) == 0) 656 return (1); 657 } 658 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 659 venid, devid, revid); 660 if (strcmp(pciide_str, compat) == 0) 661 return (1); 662 663 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 664 if (strcmp(pciide_str, compat) == 0) 665 return (1); 666 667 return (0); 668 } 669 670 static int 671 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 672 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 673 { 674 struct ide_table { /* table for PCI_MASS_OTHER */ 675 ushort_t venid; 676 ushort_t devid; 677 } *entry; 678 679 /* XXX SATA devices: need a way to add dynamically */ 680 static struct ide_table ide_other[] = { 681 {0x1095, 0x3112}, 682 {0x1095, 0x3114}, 683 {0x1095, 0x3512}, 684 {0, 0} 685 }; 686 687 if (basecl != PCI_CLASS_MASS) 688 return (0); 689 690 if (subcl == PCI_MASS_IDE) { 691 return (1); 692 } 693 694 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 695 return (0); 696 } 697 698 entry = &ide_other[0]; 699 while (entry->venid) { 700 if (entry->venid == venid && entry->devid == devid) 701 return (1); 702 entry++; 703 } 704 return (check_pciide_prop(revid, venid, devid, subvenid, subdevid)); 705 } 706 707 static int 708 is_display(uint_t classcode) 709 { 710 static uint_t disp_classes[] = { 711 0x000100, 712 0x030000, 713 0x030001 714 }; 715 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 716 717 for (i = 0; i < nclasses; i++) { 718 if (classcode == disp_classes[i]) 719 return (1); 720 } 721 return (0); 722 } 723 724 static void 725 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 726 void (*undofn)(uint8_t, uint8_t, uint8_t)) 727 { 728 struct pci_fixundo *newundo; 729 730 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 731 732 /* 733 * Adding an item to this list means that we must turn its NMIENABLE 734 * bit back on at a later time. 735 */ 736 newundo->bus = bus; 737 newundo->dev = dev; 738 newundo->fn = fn; 739 newundo->undofn = undofn; 740 newundo->next = undolist; 741 742 /* add to the undo list in LIFO order */ 743 undolist = newundo; 744 } 745 746 void 747 add_pci_fixes(void) 748 { 749 int i; 750 751 for (i = 0; i <= pci_bios_nbus; i++) { 752 /* 753 * For each bus, apply needed fixes to the appropriate devices. 754 * This must be done before the main enumeration loop because 755 * some fixes must be applied to devices normally encountered 756 * later in the pci scan (e.g. if a fix to device 7 must be 757 * applied before scanning device 6, applying fixes in the 758 * normal enumeration loop would obviously be too late). 759 */ 760 enumerate_bus_devs(i, CONFIG_FIX); 761 } 762 } 763 764 void 765 undo_pci_fixes(void) 766 { 767 struct pci_fixundo *nextundo; 768 uint8_t bus, dev, fn; 769 770 /* 771 * All fixes in the undo list are performed unconditionally. Future 772 * fixes may require selective undo. 773 */ 774 while (undolist != NULL) { 775 776 bus = undolist->bus; 777 dev = undolist->dev; 778 fn = undolist->fn; 779 780 (*(undolist->undofn))(bus, dev, fn); 781 782 nextundo = undolist->next; 783 kmem_free(undolist, sizeof (struct pci_fixundo)); 784 undolist = nextundo; 785 } 786 } 787 788 static void 789 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 790 { 791 uint8_t val8; 792 793 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 794 /* 795 * The NMIONERR bit is turned back on to allow the SMM BIOS 796 * to handle more critical PCI errors (e.g. PERR#). 797 */ 798 val8 |= AMD8111_ENABLENMI; 799 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 800 } 801 802 static void 803 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 804 { 805 uint8_t val8; 806 807 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 808 809 if ((val8 & AMD8111_ENABLENMI) == 0) 810 return; 811 812 /* 813 * We reset NMIONERR in the LPC because master-abort on the PCI 814 * bridge side of the 8111 will cause NMI, which might cause SMI, 815 * which sometimes prevents all devices from being enumerated. 816 */ 817 val8 &= ~AMD8111_ENABLENMI; 818 819 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 820 821 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 822 } 823 824 static dev_info_t * 825 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 826 ushort_t vendorid, int config_op) 827 { 828 char nodename[32], unitaddr[5]; 829 dev_info_t *dip; 830 uchar_t basecl, subcl, progcl, intr, revid; 831 ushort_t subvenid, subdevid, status; 832 ushort_t slot_num; 833 uint_t classcode, revclass; 834 int reprogram = 0, pciide; 835 int power[2] = {1, 1}; 836 int pciex = 0; 837 ushort_t is_pci_bridge = 0; 838 839 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 840 841 switch (header & PCI_HEADER_TYPE_M) { 842 case PCI_HEADER_ZERO: 843 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 844 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 845 break; 846 case PCI_HEADER_CARDBUS: 847 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 848 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 849 break; 850 default: 851 subvenid = 0; 852 subdevid = 0; 853 break; 854 } 855 856 if (config_op == CONFIG_FIX) { 857 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 858 pci_fix_amd8111(bus, dev, func); 859 } 860 return (NULL); 861 } 862 863 /* XXX should be use generic names? derive from class? */ 864 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 865 classcode = revclass >> 8; 866 revid = revclass & 0xff; 867 868 /* figure out if this is pci-ide */ 869 basecl = classcode >> 16; 870 subcl = (classcode >> 8) & 0xff; 871 progcl = classcode & 0xff; 872 pciide = is_pciide(basecl, subcl, revid, vendorid, deviceid, 873 subvenid, subdevid); 874 875 if (pciide) 876 (void) snprintf(nodename, sizeof (nodename), "pci-ide"); 877 else if (is_display(classcode)) 878 (void) snprintf(nodename, sizeof (nodename), "display"); 879 else if (subvenid != 0) 880 (void) snprintf(nodename, sizeof (nodename), 881 "pci%x,%x", subvenid, subdevid); 882 else 883 (void) snprintf(nodename, sizeof (nodename), 884 "pci%x,%x", vendorid, deviceid); 885 886 /* make sure parent bus dip has been created */ 887 if (pci_bus_res[bus].dip == NULL) { 888 create_root_bus_dip(bus); 889 } 890 891 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 892 DEVI_SID_NODEID, &dip); 893 894 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 895 &is_pci_bridge) == B_TRUE) 896 pciex = 1; 897 898 /* add properties */ 899 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 900 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 901 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 902 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 903 "class-code", classcode); 904 if (func == 0) 905 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 906 else 907 (void) snprintf(unitaddr, sizeof (unitaddr), 908 "%x,%x", dev, func); 909 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 910 "unit-address", unitaddr); 911 912 /* add device_type for display nodes */ 913 if (is_display(classcode)) { 914 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 915 "device_type", "display"); 916 } 917 /* add special stuff for header type */ 918 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 919 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 920 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 921 922 if (subvenid != 0) { 923 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 924 "subsystem-id", subdevid); 925 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 926 "subsystem-vendor-id", subvenid); 927 } 928 if (!pciex) 929 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 930 "min-grant", mingrant); 931 if (!pciex) 932 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 933 "max-latency", maxlatency); 934 } 935 936 /* interrupt, record if not 0 */ 937 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 938 if (intr != 0) 939 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 940 "interrupts", intr); 941 942 /* 943 * Add support for 133 mhz pci eventually 944 */ 945 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 946 947 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 948 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 949 if (!pciex && (status & PCI_STAT_FBBC)) 950 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 951 "fast-back-to-back"); 952 if (!pciex && (status & PCI_STAT_66MHZ)) 953 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 954 "66mhz-capable"); 955 if (status & PCI_STAT_UDF) 956 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 957 "udf-supported"); 958 if (pciex && slot_num) 959 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 960 "physical-slot#", slot_num); 961 962 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 963 "power-consumption", power, 2); 964 965 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 966 add_ppb_props(dip, bus, dev, func, pciex); 967 968 if (config_op == CONFIG_INFO && 969 IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 970 create_ioapic_node(bus, dev, func, vendorid, deviceid); 971 } 972 973 /* check for ck8-04 based PCI ISA bridge only */ 974 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 975 (func == 0)) 976 add_nvidia_isa_bridge_props(dip, bus, dev, func); 977 978 if (pciex && is_pci_bridge) 979 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 980 (char *)"PCIe-PCI bridge"); 981 else 982 add_model_prop(dip, classcode); 983 984 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 985 revid, classcode, pciex); 986 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 987 (void) ndi_devi_bind_driver(dip, 0); 988 989 /* special handling for pci-ide */ 990 if (pciide) { 991 dev_info_t *cdip; 992 993 /* 994 * Create properties specified by P1275 Working Group 995 * Proposal #414 Version 1 996 */ 997 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 998 "device_type", "pci-ide"); 999 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1000 "#address-cells", 1); 1001 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1002 "#size-cells", 0); 1003 1004 /* allocate two child nodes */ 1005 ndi_devi_alloc_sleep(dip, "ide", 1006 (pnode_t)DEVI_SID_NODEID, &cdip); 1007 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1008 "reg", 0); 1009 (void) ndi_devi_bind_driver(cdip, 0); 1010 ndi_devi_alloc_sleep(dip, "ide", 1011 (pnode_t)DEVI_SID_NODEID, &cdip); 1012 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1013 "reg", 1); 1014 (void) ndi_devi_bind_driver(cdip, 0); 1015 1016 reprogram = 0; /* don't reprogram pci-ide bridge */ 1017 } 1018 1019 1020 if (reprogram) 1021 return (dip); 1022 return (NULL); 1023 } 1024 1025 /* 1026 * Set the compatible property to a value compliant with 1027 * rev 2.1 of the IEEE1275 PCI binding. 1028 * (Also used for PCI-Express devices). 1029 * 1030 * pciVVVV,DDDD.SSSS.ssss.RR (0) 1031 * pciVVVV,DDDD.SSSS.ssss (1) 1032 * pciSSSS,ssss (2) 1033 * pciVVVV,DDDD.RR (3) 1034 * pciVVVV,DDDD (4) 1035 * pciclass,CCSSPP (5) 1036 * pciclass,CCSS (6) 1037 * 1038 * The Subsystem (SSSS) forms are not inserted if 1039 * subsystem-vendor-id is 0. 1040 * 1041 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 1042 * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 1043 * 1044 * Set with setprop and \x00 between each 1045 * to generate the encoded string array form. 1046 */ 1047 void 1048 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 1049 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 1050 int pciex) 1051 { 1052 int i = 0; 1053 int size = COMPAT_BUFSIZE; 1054 char *compat[13]; 1055 char *buf, *curr; 1056 1057 curr = buf = kmem_alloc(size, KM_SLEEP); 1058 1059 if (pciex) { 1060 if (subvenid) { 1061 compat[i++] = curr; /* form 0 */ 1062 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 1063 vendorid, deviceid, subvenid, subdevid, revid); 1064 size -= strlen(curr) + 1; 1065 curr += strlen(curr) + 1; 1066 1067 compat[i++] = curr; /* form 1 */ 1068 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 1069 vendorid, deviceid, subvenid, subdevid); 1070 size -= strlen(curr) + 1; 1071 curr += strlen(curr) + 1; 1072 1073 } 1074 compat[i++] = curr; /* form 3 */ 1075 (void) snprintf(curr, size, "pciex%x,%x.%x", 1076 vendorid, deviceid, revid); 1077 size -= strlen(curr) + 1; 1078 curr += strlen(curr) + 1; 1079 1080 compat[i++] = curr; /* form 4 */ 1081 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 1082 size -= strlen(curr) + 1; 1083 curr += strlen(curr) + 1; 1084 1085 compat[i++] = curr; /* form 5 */ 1086 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 1087 size -= strlen(curr) + 1; 1088 curr += strlen(curr) + 1; 1089 1090 compat[i++] = curr; /* form 6 */ 1091 (void) snprintf(curr, size, "pciexclass,%04x", 1092 (classcode >> 8)); 1093 size -= strlen(curr) + 1; 1094 curr += strlen(curr) + 1; 1095 } 1096 1097 if (subvenid) { 1098 compat[i++] = curr; /* form 0 */ 1099 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 1100 vendorid, deviceid, subvenid, subdevid, revid); 1101 size -= strlen(curr) + 1; 1102 curr += strlen(curr) + 1; 1103 1104 compat[i++] = curr; /* form 1 */ 1105 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 1106 vendorid, deviceid, subvenid, subdevid); 1107 size -= strlen(curr) + 1; 1108 curr += strlen(curr) + 1; 1109 1110 compat[i++] = curr; /* form 2 */ 1111 (void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid); 1112 size -= strlen(curr) + 1; 1113 curr += strlen(curr) + 1; 1114 } 1115 compat[i++] = curr; /* form 3 */ 1116 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 1117 size -= strlen(curr) + 1; 1118 curr += strlen(curr) + 1; 1119 1120 compat[i++] = curr; /* form 4 */ 1121 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 1122 size -= strlen(curr) + 1; 1123 curr += strlen(curr) + 1; 1124 1125 compat[i++] = curr; /* form 5 */ 1126 (void) snprintf(curr, size, "pciclass,%06x", classcode); 1127 size -= strlen(curr) + 1; 1128 curr += strlen(curr) + 1; 1129 1130 compat[i++] = curr; /* form 6 */ 1131 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 1132 size -= strlen(curr) + 1; 1133 curr += strlen(curr) + 1; 1134 1135 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1136 "compatible", compat, i); 1137 kmem_free(buf, COMPAT_BUFSIZE); 1138 } 1139 1140 /* 1141 * Adjust the reg properties for a dual channel PCI-IDE device. 1142 * 1143 * NOTE: don't do anything that changes the order of the hard-decodes 1144 * and programmed BARs. The kernel driver depends on these values 1145 * being in this order regardless of whether they're for a 'native' 1146 * mode BAR or not. 1147 */ 1148 /* 1149 * config info for pci-ide devices 1150 */ 1151 static struct { 1152 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 1153 uchar_t bar_offset; /* offset for alt status register */ 1154 ushort_t addr; /* compatibility mode base address */ 1155 ushort_t length; /* number of ports for this BAR */ 1156 } pciide_bar[] = { 1157 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 1158 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 1159 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 1160 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 1161 }; 1162 1163 static int 1164 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 1165 { 1166 int hard_decode = 0; 1167 1168 /* 1169 * Adjust the base and len for the BARs of the PCI-IDE 1170 * device's primary and secondary controllers. The first 1171 * two BARs are for the primary controller and the next 1172 * two BARs are for the secondary controller. The fifth 1173 * and sixth bars are never adjusted. 1174 */ 1175 if (index >= 0 && index <= 3) { 1176 *lenp = pciide_bar[index].length; 1177 1178 if (progcl & pciide_bar[index].native_mask) { 1179 *basep += pciide_bar[index].bar_offset; 1180 } else { 1181 *basep = pciide_bar[index].addr; 1182 hard_decode = 1; 1183 } 1184 } 1185 1186 /* 1187 * if either base or len is zero make certain both are zero 1188 */ 1189 if (*basep == 0 || *lenp == 0) { 1190 *basep = 0; 1191 *lenp = 0; 1192 hard_decode = 0; 1193 } 1194 1195 return (hard_decode); 1196 } 1197 1198 1199 /* 1200 * Add the "reg" and "assigned-addresses" property 1201 */ 1202 static int 1203 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1204 int config_op, int pciide) 1205 { 1206 uchar_t baseclass, subclass, progclass, header; 1207 ushort_t bar_sz; 1208 uint_t value = 0, len, devloc; 1209 uint_t base, base_hi, type; 1210 ushort_t offset, end; 1211 int max_basereg, j, reprogram = 0; 1212 uint_t phys_hi; 1213 struct memlist **io_res, **mres, **mem_res, **pmem_res; 1214 uint16_t cmd_reg; 1215 1216 pci_regspec_t regs[16] = {{0}}; 1217 pci_regspec_t assigned[15] = {{0}}; 1218 int nreg, nasgn, enable = 0; 1219 1220 io_res = &pci_bus_res[bus].io_ports; 1221 mem_res = &pci_bus_res[bus].mem_space; 1222 if (bus == 0) /* for bus 0, there is only mem_space */ 1223 pmem_res = mem_res; 1224 else 1225 pmem_res = &pci_bus_res[bus].pmem_space; 1226 1227 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 1228 regs[0].pci_phys_hi = devloc; 1229 nreg = 1; /* rest of regs[0] is all zero */ 1230 nasgn = 0; 1231 1232 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 1233 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 1234 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 1235 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1236 1237 switch (header) { 1238 case PCI_HEADER_ZERO: 1239 max_basereg = PCI_BASE_NUM; 1240 break; 1241 case PCI_HEADER_PPB: 1242 max_basereg = PCI_BCNF_BASE_NUM; 1243 break; 1244 case PCI_HEADER_CARDBUS: 1245 max_basereg = PCI_CBUS_BASE_NUM; 1246 break; 1247 default: 1248 max_basereg = 0; 1249 break; 1250 } 1251 1252 /* 1253 * Create the register property by saving the current 1254 * value of the base register. Write 0xffffffff to the 1255 * base register. Read the value back to determine the 1256 * required size of the address space. Restore the base 1257 * register contents. 1258 * 1259 * Do not disable I/O and memory access; this isn't necessary 1260 * since no driver is yet attached to this device, and disabling 1261 * I/O and memory access has the side-effect of disabling PCI-PCI 1262 * bridge mappings, which makes the bridge transparent to secondary- 1263 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 1264 * Spec V1.2). 1265 */ 1266 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 1267 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 1268 j++, offset += bar_sz) { 1269 int hard_decode = 0; 1270 1271 /* determine the size of the address space */ 1272 base = pci_getl(bus, dev, func, offset); 1273 pci_putl(bus, dev, func, offset, 0xffffffff); 1274 value = pci_getl(bus, dev, func, offset); 1275 pci_putl(bus, dev, func, offset, base); 1276 1277 /* construct phys hi,med.lo, size hi, lo */ 1278 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 1279 /* i/o space */ 1280 bar_sz = PCI_BAR_SZ_32; 1281 value &= PCI_BASE_IO_ADDR_M; 1282 len = ((value ^ (value-1)) + 1) >> 1; 1283 1284 /* XXX Adjust first 4 IDE registers */ 1285 if (pciide) { 1286 if (subclass != PCI_MASS_IDE) 1287 progclass = (PCI_IDE_IF_NATIVE_PRI | 1288 PCI_IDE_IF_NATIVE_SEC); 1289 hard_decode = pciIdeAdjustBAR(progclass, j, 1290 &base, &len); 1291 } else if (value == 0) { 1292 /* skip base regs with size of 0 */ 1293 continue; 1294 } 1295 1296 regs[nreg].pci_size_low = 1297 assigned[nasgn].pci_size_low = len; 1298 if (!hard_decode) { 1299 regs[nreg].pci_phys_hi = 1300 (PCI_ADDR_IO | devloc) + offset; 1301 } else { 1302 regs[nreg].pci_phys_hi = 1303 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 1304 offset; 1305 regs[nreg].pci_phys_low = 1306 base & PCI_BASE_IO_ADDR_M; 1307 } 1308 assigned[nasgn].pci_phys_hi = 1309 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 1310 type = base & (~PCI_BASE_IO_ADDR_M); 1311 base &= PCI_BASE_IO_ADDR_M; 1312 1313 /* 1314 * first pass - gather what's there 1315 * update/second pass - adjust/allocate regions 1316 * config - allocate regions 1317 */ 1318 if (config_op == CONFIG_INFO) { /* first pass */ 1319 /* take out of the resource map of the bus */ 1320 if (*io_res && base != 0) 1321 (void) memlist_remove(io_res, 1322 (uint64_t)base, (uint64_t)len); 1323 else if (*io_res) 1324 reprogram = 1; 1325 } else if (*io_res && base == 0) { 1326 base = (uint_t)memlist_find(io_res, 1327 (uint64_t)len, (uint64_t)0x4); 1328 if (base != 0) { 1329 /* XXX need to worry about 64-bit? */ 1330 pci_putl(bus, dev, func, offset, 1331 base | type); 1332 base = pci_getl(bus, dev, func, offset); 1333 base &= PCI_BASE_IO_ADDR_M; 1334 } 1335 if (base == 0) { 1336 cmn_err(CE_WARN, "failed to program" 1337 " IO space [%d/%d/%d] BAR@0x%x" 1338 " length 0x%x", 1339 bus, dev, func, offset, len); 1340 } else 1341 enable |= PCI_COMM_IO; 1342 } 1343 assigned[nasgn].pci_phys_low = base; 1344 nreg++, nasgn++; 1345 1346 } else { 1347 /* memory space */ 1348 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 1349 bar_sz = PCI_BAR_SZ_64; 1350 base_hi = pci_getl(bus, dev, func, offset + 4); 1351 phys_hi = PCI_ADDR_MEM64; 1352 } else { 1353 bar_sz = PCI_BAR_SZ_32; 1354 base_hi = 0; 1355 phys_hi = PCI_ADDR_MEM32; 1356 } 1357 1358 /* skip base regs with size of 0 */ 1359 value &= PCI_BASE_M_ADDR_M; 1360 1361 if (value == 0) { 1362 continue; 1363 } 1364 len = ((value ^ (value-1)) + 1) >> 1; 1365 regs[nreg].pci_size_low = 1366 assigned[nasgn].pci_size_low = len; 1367 1368 phys_hi |= (devloc | offset); 1369 if (base & PCI_BASE_PREF_M) { 1370 mres = pmem_res; 1371 phys_hi |= PCI_PREFETCH_B; 1372 } else { 1373 mres = mem_res; 1374 } 1375 regs[nreg].pci_phys_hi = 1376 assigned[nasgn].pci_phys_hi = phys_hi; 1377 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 1378 assigned[nasgn].pci_phys_mid = base_hi; 1379 type = base & ~PCI_BASE_M_ADDR_M; 1380 base &= PCI_BASE_M_ADDR_M; 1381 1382 if (config_op == CONFIG_INFO) { 1383 /* take out of the resource map of the bus */ 1384 if (*mres && base != 0) { 1385 (void) memlist_remove(mres, 1386 (uint64_t)base, (uint64_t)len); 1387 } else if (*mres) 1388 reprogram = 1; 1389 } else if (*mres && base == 0) { 1390 base = (uint_t)memlist_find(mres, 1391 (uint64_t)len, (uint64_t)0x1000); 1392 if (base != NULL) { 1393 pci_putl(bus, dev, func, offset, 1394 base | type); 1395 base = pci_getl(bus, dev, func, offset); 1396 base &= PCI_BASE_M_ADDR_M; 1397 } 1398 1399 if (base == 0) { 1400 cmn_err(CE_WARN, "failed to program " 1401 "mem space [%d/%d/%d] BAR@0x%x" 1402 " length 0x%x", 1403 bus, dev, func, offset, len); 1404 } else 1405 enable |= PCI_COMM_MAE; 1406 } 1407 assigned[nasgn].pci_phys_low = base; 1408 nreg++, nasgn++; 1409 } 1410 } 1411 switch (header) { 1412 case PCI_HEADER_ZERO: 1413 offset = PCI_CONF_ROM; 1414 break; 1415 case PCI_HEADER_PPB: 1416 offset = PCI_BCNF_ROM; 1417 break; 1418 default: /* including PCI_HEADER_CARDBUS */ 1419 goto done; 1420 } 1421 1422 /* 1423 * Add the expansion rom memory space 1424 * Determine the size of the ROM base reg; don't write reserved bits 1425 * ROM isn't in the PCI memory space. 1426 */ 1427 base = pci_getl(bus, dev, func, offset); 1428 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 1429 value = pci_getl(bus, dev, func, offset); 1430 pci_putl(bus, dev, func, offset, base); 1431 if (value & PCI_BASE_ROM_ENABLE) 1432 value &= PCI_BASE_ROM_ADDR_M; 1433 else 1434 value = 0; 1435 1436 if (value != 0) { 1437 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 1438 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 1439 PCI_ADDR_MEM32 | devloc) + offset; 1440 base &= PCI_BASE_ROM_ADDR_M; 1441 assigned[nasgn].pci_phys_low = base; 1442 len = ((value ^ (value-1)) + 1) >> 1; 1443 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 1444 nreg++, nasgn++; 1445 /* take it out of the memory resource */ 1446 if (*mem_res && base != 0) 1447 (void) memlist_remove(mem_res, 1448 (uint64_t)base, (uint64_t)len); 1449 } 1450 1451 /* 1452 * The following are ISA resources. There are not part 1453 * of the PCI local bus resources. So don't attempt to 1454 * do resource accounting against PCI. 1455 */ 1456 1457 /* add the three hard-decode, aliased address spaces for VGA */ 1458 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 1459 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 1460 1461 /* VGA hard decode 0x3b0-0x3bb */ 1462 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1463 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1464 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 1465 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 1466 nreg++, nasgn++; 1467 1468 /* VGA hard decode 0x3c0-0x3df */ 1469 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1470 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1471 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 1472 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 1473 nreg++, nasgn++; 1474 1475 /* Video memory */ 1476 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1477 (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 1478 regs[nreg].pci_phys_low = 1479 assigned[nasgn].pci_phys_low = 0xa0000; 1480 regs[nreg].pci_size_low = 1481 assigned[nasgn].pci_size_low = 0x20000; 1482 nreg++, nasgn++; 1483 } 1484 1485 /* add the hard-decode, aliased address spaces for 8514 */ 1486 if ((baseclass == PCI_CLASS_DISPLAY) && 1487 (subclass == PCI_DISPLAY_VGA) && 1488 (progclass & PCI_DISPLAY_IF_8514)) { 1489 1490 /* hard decode 0x2e8 */ 1491 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1492 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1493 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 1494 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 1495 nreg++, nasgn++; 1496 1497 /* hard decode 0x2ea-0x2ef */ 1498 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1499 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1500 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 1501 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 1502 nreg++, nasgn++; 1503 } 1504 1505 done: 1506 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 1507 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 1508 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1509 "assigned-addresses", 1510 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 1511 if (config_op == CONFIG_NEW && enable) { 1512 cmn_err(CE_NOTE, 1513 "!enable PCI device [%d/%d/%d]", bus, dev, func); 1514 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 1515 cmd_reg |= (enable | PCI_COMM_ME); 1516 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 1517 } 1518 return (reprogram); 1519 } 1520 1521 static void 1522 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1523 int pciex) 1524 { 1525 char *dev_type; 1526 int i; 1527 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 1528 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1529 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1530 ASSERT(secbus <= subbus); 1531 1532 /* 1533 * Some BIOSes lie about max pci busses, we allow for 1534 * such mistakes here 1535 */ 1536 if (subbus > pci_bios_nbus) { 1537 pci_bios_nbus = subbus; 1538 alloc_res_array(); 1539 } 1540 1541 ASSERT(pci_bus_res[secbus].dip == NULL); 1542 pci_bus_res[secbus].dip = dip; 1543 pci_bus_res[secbus].par_bus = bus; 1544 1545 dev_type = pciex ? "pciex" : "pci"; 1546 1547 /* setup bus number hierarchy */ 1548 pci_bus_res[secbus].sub_bus = subbus; 1549 /* 1550 * Keep track of the largest subordinate bus number (this is essential 1551 * for peer busses because there is no other way of determining its 1552 * subordinate bus number). 1553 */ 1554 if (subbus > pci_bus_res[bus].sub_bus) 1555 pci_bus_res[bus].sub_bus = subbus; 1556 /* 1557 * Loop through subordinate busses, initializing their parent bus 1558 * field to this bridge's parent. The subordinate busses' parent 1559 * fields may very well be further refined later, as child bridges 1560 * are enumerated. (The value is to note that the subordinate busses 1561 * are not peer busses by changing their par_bus fields to anything 1562 * other than -1.) 1563 */ 1564 for (i = secbus + 1; i <= subbus; i++) 1565 pci_bus_res[i].par_bus = bus; 1566 1567 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1568 "device_type", dev_type); 1569 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1570 "#address-cells", 3); 1571 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1572 "#size-cells", 2); 1573 1574 /* 1575 * According to PPB spec, the base register should be programmed 1576 * with a value bigger than the limit register when there are 1577 * no resources available. This applies to io, memory, and 1578 * prefetchable memory. 1579 */ 1580 /* io range */ 1581 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 1582 io_range[0] = ((val & 0xf0) << 8); 1583 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 1584 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 1585 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 1586 memlist_insert(&pci_bus_res[secbus].io_ports, 1587 (uint64_t)io_range[0], 1588 (uint64_t)(io_range[1] - io_range[0] + 1)); 1589 if (pci_bus_res[bus].io_ports != NULL) { 1590 (void) memlist_remove(&pci_bus_res[bus].io_ports, 1591 (uint64_t)io_range[0], 1592 (uint64_t)(io_range[1] - io_range[0] + 1)); 1593 } 1594 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 1595 secbus, io_range[0], io_range[1]); 1596 /* if 32-bit supported, make sure upper bits are not set */ 1597 if ((val & 0xf) == 1 && 1598 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 1599 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 1600 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1601 } 1602 } 1603 1604 /* mem range */ 1605 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 1606 mem_range[0] = ((val & 0xFFF0) << 16); 1607 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1608 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1609 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 1610 memlist_insert(&pci_bus_res[secbus].mem_space, 1611 (uint64_t)mem_range[0], 1612 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1613 /* remove from parent resouce list */ 1614 if (pci_bus_res[bus].mem_space != NULL) { 1615 (void) memlist_remove(&pci_bus_res[bus].mem_space, 1616 (uint64_t)mem_range[0], 1617 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1618 } 1619 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 1620 secbus, mem_range[0], mem_range[1]); 1621 } 1622 1623 /* prefetchable memory range */ 1624 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 1625 pmem_range[0] = ((val & 0xFFF0) << 16); 1626 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 1627 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1628 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 1629 memlist_insert(&pci_bus_res[secbus].pmem_space, 1630 (uint64_t)pmem_range[0], 1631 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1632 if (pci_bus_res[bus].pmem_space != NULL) { 1633 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 1634 (uint64_t)pmem_range[0], 1635 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1636 } 1637 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 1638 secbus, pmem_range[0], pmem_range[1]); 1639 /* if 64-bit supported, make sure upper bits are not set */ 1640 if ((val & 0xf) == 1 && 1641 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 1642 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 1643 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1644 } 1645 } 1646 1647 add_bus_range_prop(secbus); 1648 add_ppb_ranges_prop(secbus); 1649 } 1650 1651 extern const struct pci_class_strings_s class_pci[]; 1652 extern int class_pci_items; 1653 1654 static void 1655 add_model_prop(dev_info_t *dip, uint_t classcode) 1656 { 1657 const char *desc; 1658 int i; 1659 uchar_t baseclass = classcode >> 16; 1660 uchar_t subclass = (classcode >> 8) & 0xff; 1661 uchar_t progclass = classcode & 0xff; 1662 1663 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 1664 desc = "IDE controller"; 1665 } else { 1666 for (desc = 0, i = 0; i < class_pci_items; i++) { 1667 if ((baseclass == class_pci[i].base_class) && 1668 (subclass == class_pci[i].sub_class) && 1669 (progclass == class_pci[i].prog_class)) { 1670 desc = class_pci[i].actual_desc; 1671 break; 1672 } 1673 } 1674 if (i == class_pci_items) 1675 desc = "Unknown class of pci/pnpbios device"; 1676 } 1677 1678 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1679 (char *)desc); 1680 } 1681 1682 static void 1683 add_bus_range_prop(int bus) 1684 { 1685 int bus_range[2]; 1686 1687 if (pci_bus_res[bus].dip == NULL) 1688 return; 1689 bus_range[0] = bus; 1690 bus_range[1] = pci_bus_res[bus].sub_bus; 1691 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1692 "bus-range", (int *)bus_range, 2); 1693 } 1694 1695 /* 1696 * Add slot-names property for any named pci hot-plug slots 1697 */ 1698 static void 1699 add_bus_slot_names_prop(int bus) 1700 { 1701 char slotprop[256]; 1702 int len; 1703 1704 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 1705 if (len > 0) { 1706 /* 1707 * Only create a peer bus node if this bus may be a peer bus. 1708 * It may be a peer bus if the dip is NULL and if par_bus is 1709 * -1 (par_bus is -1 if this bus was not found to be 1710 * subordinate to any PCI-PCI bridge). 1711 * If it's not a peer bus, then the ACPI BBN-handling code 1712 * will remove it later. 1713 */ 1714 if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 1715 pci_bus_res[bus].dip == NULL) { 1716 1717 create_root_bus_dip(bus); 1718 } 1719 if (pci_bus_res[bus].dip != NULL) { 1720 ASSERT((len % sizeof (int)) == 0); 1721 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1722 pci_bus_res[bus].dip, "slot-names", 1723 (int *)slotprop, len / sizeof (int)); 1724 } else { 1725 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 1726 "IRQ routing table; Not adding slot-names " 1727 "property for incorrect bus %d", bus); 1728 } 1729 } 1730 } 1731 1732 static int 1733 memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type) 1734 { 1735 if (entry == NULL) 1736 return (0); 1737 1738 /* assume 32-bit addresses */ 1739 rp->child_high = rp->parent_high = type; 1740 rp->child_mid = rp->parent_mid = 0; 1741 rp->child_low = rp->parent_low = (uint32_t)entry->address; 1742 rp->size_high = 0; 1743 rp->size_low = (uint32_t)entry->size; 1744 return (1); 1745 } 1746 1747 static void 1748 add_ppb_ranges_prop(int bus) 1749 { 1750 int i = 0; 1751 ppb_ranges_t *rp; 1752 1753 rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP); 1754 1755 i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports, 1756 PCI_ADDR_IO | PCI_REG_REL_M); 1757 i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space, 1758 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1759 i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space, 1760 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1761 1762 if (i != 0) 1763 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1764 pci_bus_res[bus].dip, "ranges", (int *)rp, 1765 i * sizeof (ppb_ranges_t) / sizeof (int)); 1766 kmem_free(rp, 3 * sizeof (*rp)); 1767 } 1768 1769 static int 1770 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 1771 { 1772 int i = 0; 1773 1774 while (list) { 1775 /* assume 32-bit addresses */ 1776 sp->pci_phys_hi = type; 1777 sp->pci_phys_mid = 0; 1778 sp->pci_phys_low = (uint32_t)list->address; 1779 sp->pci_size_hi = 0; 1780 sp->pci_size_low = (uint32_t)list->size; 1781 1782 list = list->next; 1783 sp++, i++; 1784 } 1785 return (i); 1786 } 1787 1788 static void 1789 add_bus_available_prop(int bus) 1790 { 1791 int i, count; 1792 struct pci_phys_spec *sp; 1793 1794 count = memlist_count(pci_bus_res[bus].io_ports) + 1795 memlist_count(pci_bus_res[bus].mem_space) + 1796 memlist_count(pci_bus_res[bus].pmem_space); 1797 1798 if (count == 0) /* nothing available */ 1799 return; 1800 1801 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 1802 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 1803 PCI_ADDR_IO | PCI_REG_REL_M); 1804 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 1805 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1806 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 1807 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1808 ASSERT(i == count); 1809 1810 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1811 "available", (int *)sp, 1812 i * sizeof (struct pci_phys_spec) / sizeof (int)); 1813 kmem_free(sp, count * sizeof (*sp)); 1814 } 1815 1816 static void 1817 alloc_res_array(void) 1818 { 1819 static int array_max = 0; 1820 int old_max; 1821 void *old_res; 1822 1823 if (array_max > pci_bios_nbus + 1) 1824 return; /* array is big enough */ 1825 1826 old_max = array_max; 1827 old_res = pci_bus_res; 1828 1829 if (array_max == 0) 1830 array_max = 16; /* start with a reasonable number */ 1831 1832 while (array_max < pci_bios_nbus + 1) 1833 array_max <<= 1; 1834 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 1835 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 1836 1837 if (old_res) { /* copy content and free old array */ 1838 bcopy(old_res, pci_bus_res, 1839 old_max * sizeof (struct pci_bus_resource)); 1840 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 1841 } 1842 } 1843 1844 static void 1845 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 1846 ushort_t deviceid) 1847 { 1848 static dev_info_t *ioapicsnode = NULL; 1849 static int numioapics = 0; 1850 dev_info_t *ioapic_node; 1851 uint64_t physaddr; 1852 uint32_t lobase, hibase = 0; 1853 1854 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 1855 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 1856 1857 /* We (and the rest of the world) only support memory-mapped IOAPICs */ 1858 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 1859 return; 1860 1861 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 1862 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 1863 1864 lobase &= PCI_BASE_M_ADDR_M; 1865 1866 physaddr = (((uint64_t)hibase) << 32) | lobase; 1867 1868 /* 1869 * Create a nexus node for all IOAPICs under the root node. 1870 */ 1871 if (ioapicsnode == NULL) { 1872 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 1873 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 1874 return; 1875 } 1876 (void) ndi_devi_online(ioapicsnode, 0); 1877 } 1878 1879 /* 1880 * Create a child node for this IOAPIC 1881 */ 1882 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 1883 DEVI_SID_NODEID, numioapics++); 1884 if (ioapic_node == NULL) { 1885 return; 1886 } 1887 1888 /* Vendor and Device ID */ 1889 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 1890 IOAPICS_PROP_VENID, vendorid); 1891 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 1892 IOAPICS_PROP_DEVID, deviceid); 1893 1894 /* device_type */ 1895 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 1896 "device_type", IOAPICS_DEV_TYPE); 1897 1898 /* reg */ 1899 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 1900 "reg", physaddr); 1901 } 1902