1 /* 2 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* BEGIN CSTYLED */ 7 8 /************************************************************************** 9 * 10 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 11 * All Rights Reserved. 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a 14 * copy of this software and associated documentation files (the 15 * "Software"), to deal in the Software without restriction, including 16 * without limitation the rights to use, copy, modify, merge, publish, 17 * distribute, sub license, and/or sell copies of the Software, and to 18 * permit persons to whom the Software is furnished to do so, subject to 19 * the following conditions: 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 26 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 28 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 29 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 30 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 31 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 32 * 33 **************************************************************************/ 34 35 #ifndef _I915_DRM_H 36 #define _I915_DRM_H 37 38 #pragma ident "%Z%%M% %I% %E% SMI" 39 40 /* Please note that modifications to all structs defined here are 41 * subject to backwards-compatibility constraints. 42 */ 43 44 #include "drm.h" 45 46 /* Each region is a minimum of 16k, and there are at most 255 of them. 47 */ 48 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 49 * of chars for next/prev indices */ 50 #define I915_LOG_MIN_TEX_REGION_SIZE 14 51 52 typedef struct _drm_i915_init { 53 enum { 54 I915_INIT_DMA = 0x01, 55 I915_CLEANUP_DMA = 0x02, 56 I915_RESUME_DMA = 0x03 57 } func; 58 unsigned int mmio_offset; 59 int sarea_priv_offset; 60 unsigned int ring_start; 61 unsigned int ring_end; 62 unsigned int ring_size; 63 unsigned int front_offset; 64 unsigned int back_offset; 65 unsigned int depth_offset; 66 unsigned int w; 67 unsigned int h; 68 unsigned int pitch; 69 unsigned int pitch_bits; 70 unsigned int back_pitch; 71 unsigned int depth_pitch; 72 unsigned int cpp; 73 unsigned int chipset; 74 } drm_i915_init_t; 75 76 typedef struct _drm_i915_sarea { 77 drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1]; 78 int last_upload; /* last time texture was uploaded */ 79 int last_enqueue; /* last time a buffer was enqueued */ 80 int last_dispatch; /* age of the most recently dispatched buffer */ 81 int ctxOwner; /* last context to upload state */ 82 int texAge; 83 int pf_enabled; /* is pageflipping allowed? */ 84 int pf_active; 85 int pf_current_page; /* which buffer is being displayed? */ 86 int perf_boxes; /* performance boxes to be displayed */ 87 } drm_i915_sarea_t; 88 89 /* Flags for perf_boxes 90 */ 91 #define I915_BOX_RING_EMPTY 0x1 92 #define I915_BOX_FLIP 0x2 93 #define I915_BOX_WAIT 0x4 94 #define I915_BOX_TEXTURE_LOAD 0x8 95 #define I915_BOX_LOST_CONTEXT 0x10 96 97 /* I915 specific ioctls 98 * The device specific ioctl range is 0x40 to 0x79. 99 */ 100 #define DRM_I915_INIT 0x00 101 #define DRM_I915_FLUSH 0x01 102 #define DRM_I915_FLIP 0x02 103 #define DRM_I915_BATCHBUFFER 0x03 104 #define DRM_I915_IRQ_EMIT 0x04 105 #define DRM_I915_IRQ_WAIT 0x05 106 #define DRM_I915_GETPARAM 0x06 107 #define DRM_I915_SETPARAM 0x07 108 #define DRM_I915_ALLOC 0x08 109 #define DRM_I915_FREE 0x09 110 #define DRM_I915_INIT_HEAP 0x0a 111 #define DRM_I915_CMDBUFFER 0x0b 112 113 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 114 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 115 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 116 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 117 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 118 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 119 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 120 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 121 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 122 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 123 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 124 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 125 126 /* Allow drivers to submit batchbuffers directly to hardware, relying 127 * on the security mechanisms provided by hardware. 128 */ 129 typedef struct _drm_i915_batchbuffer { 130 int start; /* agp offset */ 131 int used; /* nr bytes in use */ 132 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 133 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 134 int num_cliprects; /* mulitpass with multiple cliprects? */ 135 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */ 136 } drm_i915_batchbuffer_t; 137 138 typedef struct _drm_i915_batchbuffer32 { 139 int start; /* agp offset */ 140 int used; /* nr bytes in use */ 141 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 142 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 143 int num_cliprects; /* mulitpass with multiple cliprects? */ 144 caddr32_t cliprects; /* pointer to userspace cliprects */ 145 } drm_i915_batchbuffer32_t; 146 147 /* As above, but pass a pointer to userspace buffer which can be 148 * validated by the kernel prior to sending to hardware. 149 */ 150 typedef struct _drm_i915_cmdbuffer { 151 char __user *buf; /* pointer to userspace command buffer */ 152 int sz; /* nr bytes in buf */ 153 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 154 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 155 int num_cliprects; /* mulitpass with multiple cliprects? */ 156 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */ 157 } drm_i915_cmdbuffer_t; 158 159 typedef struct _drm_i915_cmdbuffer32 { 160 caddr32_t buf; /* pointer to userspace command buffer */ 161 int sz; /* nr bytes in buf */ 162 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 163 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 164 int num_cliprects; /* mulitpass with multiple cliprects? */ 165 caddr32_t cliprects; /* pointer to userspace cliprects */ 166 } drm_i915_cmdbuffer32_t; 167 168 /* Userspace can request & wait on irq's: 169 */ 170 typedef struct drm_i915_irq_emit { 171 int __user *irq_seq; 172 } drm_i915_irq_emit_t; 173 174 typedef struct drm_i915_irq_emit32 { 175 caddr32_t irq_seq; 176 } drm_i915_irq_emit32_t; 177 178 typedef struct drm_i915_irq_wait { 179 int irq_seq; 180 } drm_i915_irq_wait_t; 181 182 /* Ioctl to query kernel params: 183 */ 184 #define I915_PARAM_IRQ_ACTIVE 1 185 #define I915_PARAM_ALLOW_BATCHBUFFER 2 186 187 typedef struct drm_i915_getparam { 188 int param; 189 int __user *value; 190 } drm_i915_getparam_t; 191 192 typedef struct drm_i915_getparam32 { 193 int param; 194 caddr32_t value; 195 } drm_i915_getparam32_t; 196 197 /* Ioctl to set kernel params: 198 */ 199 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 200 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 201 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 202 203 typedef struct drm_i915_setparam { 204 int param; 205 int value; 206 } drm_i915_setparam_t; 207 208 /* A memory manager for regions of shared memory: 209 */ 210 #define I915_MEM_REGION_AGP 1 211 212 typedef struct drm_i915_mem_alloc { 213 int region; 214 int alignment; 215 int size; 216 int __user *region_offset; /* offset from start of fb or agp */ 217 } drm_i915_mem_alloc_t; 218 219 typedef struct drm_i915_mem_alloc32 { 220 int region; 221 int alignment; 222 int size; 223 caddr32_t region_offset; /* offset from start of fb or agp */ 224 } drm_i915_mem_alloc32_t; 225 226 typedef struct drm_i915_mem_free { 227 int region; 228 int region_offset; 229 } drm_i915_mem_free_t; 230 231 typedef struct drm_i915_mem_init_heap { 232 int region; 233 int size; 234 int start; 235 } drm_i915_mem_init_heap_t; 236 237 #endif /* _I915_DRM_H */ 238