1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 30 31 /* 32 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 33 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 34 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 35 * PSMI 1.5 extensions are supported in Solaris Nevada. 36 * PSMI 1.6 extensions are supported in Solaris Nevada. 37 * PSMI 1.7 extensions are supported in Solaris Nevada. 38 */ 39 #define PSMI_1_7 40 41 #include <sys/processor.h> 42 #include <sys/time.h> 43 #include <sys/psm.h> 44 #include <sys/smp_impldefs.h> 45 #include <sys/cram.h> 46 #include <sys/acpi/acpi.h> 47 #include <sys/acpica.h> 48 #include <sys/psm_common.h> 49 #include <sys/apic.h> 50 #include <sys/pit.h> 51 #include <sys/ddi.h> 52 #include <sys/sunddi.h> 53 #include <sys/ddi_impldefs.h> 54 #include <sys/pci.h> 55 #include <sys/promif.h> 56 #include <sys/x86_archext.h> 57 #include <sys/cpc_impl.h> 58 #include <sys/uadmin.h> 59 #include <sys/panic.h> 60 #include <sys/debug.h> 61 #include <sys/archsystm.h> 62 #include <sys/trap.h> 63 #include <sys/machsystm.h> 64 #include <sys/sysmacros.h> 65 #include <sys/cpuvar.h> 66 #include <sys/rm_platter.h> 67 #include <sys/privregs.h> 68 #include <sys/note.h> 69 #include <sys/pci_intr_lib.h> 70 #include <sys/spl.h> 71 #include <sys/clock.h> 72 #include <sys/dditypes.h> 73 #include <sys/sunddi.h> 74 #include <sys/x_call.h> 75 #include <sys/reboot.h> 76 #include <sys/hpet.h> 77 #include <sys/apic_common.h> 78 79 /* 80 * Local Function Prototypes 81 */ 82 static void apic_init_intr(void); 83 84 /* 85 * standard MP entries 86 */ 87 static int apic_probe(void); 88 static int apic_getclkirq(int ipl); 89 static uint_t apic_calibrate(volatile uint32_t *addr, 90 uint16_t *pit_ticks_adj); 91 static void apic_init(void); 92 static void apic_picinit(void); 93 static int apic_post_cpu_start(void); 94 static int apic_intr_enter(int ipl, int *vect); 95 static void apic_setspl(int ipl); 96 static void x2apic_setspl(int ipl); 97 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl); 98 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl); 99 static int apic_disable_intr(processorid_t cpun); 100 static void apic_enable_intr(processorid_t cpun); 101 static int apic_get_ipivect(int ipl, int type); 102 static void apic_post_cyclic_setup(void *arg); 103 104 /* 105 * The following vector assignments influence the value of ipltopri and 106 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program 107 * idle to 0 and IPL 0 to 0xf to differentiate idle in case 108 * we care to do so in future. Note some IPLs which are rarely used 109 * will share the vector ranges and heavily used IPLs (5 and 6) have 110 * a wide range. 111 * 112 * This array is used to initialize apic_ipls[] (in apic_init()). 113 * 114 * IPL Vector range. as passed to intr_enter 115 * 0 none. 116 * 1,2,3 0x20-0x2f 0x0-0xf 117 * 4 0x30-0x3f 0x10-0x1f 118 * 5 0x40-0x5f 0x20-0x3f 119 * 6 0x60-0x7f 0x40-0x5f 120 * 7,8,9 0x80-0x8f 0x60-0x6f 121 * 10 0x90-0x9f 0x70-0x7f 122 * 11 0xa0-0xaf 0x80-0x8f 123 * ... ... 124 * 15 0xe0-0xef 0xc0-0xcf 125 * 15 0xf0-0xff 0xd0-0xdf 126 */ 127 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = { 128 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15 129 }; 130 /* 131 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4] 132 * NOTE that this is vector as passed into intr_enter which is 133 * programmed vector - 0x20 (APIC_BASE_VECT) 134 */ 135 136 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */ 137 /* The taskpri to be programmed into apic to mask given ipl */ 138 139 #if defined(__amd64) 140 uchar_t apic_cr8pri[MAXIPL + 1]; /* unix ipl to cr8 pri */ 141 #endif 142 143 /* 144 * Correlation of the hardware vector to the IPL in use, initialized 145 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate 146 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines 147 * connected to errata-stricken IOAPICs 148 */ 149 uchar_t apic_ipls[APIC_AVAIL_VECTOR]; 150 151 /* 152 * Patchable global variables. 153 */ 154 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */ 155 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */ 156 157 /* 158 * Local static data 159 */ 160 static struct psm_ops apic_ops = { 161 apic_probe, 162 163 apic_init, 164 apic_picinit, 165 apic_intr_enter, 166 apic_intr_exit, 167 apic_setspl, 168 apic_addspl, 169 apic_delspl, 170 apic_disable_intr, 171 apic_enable_intr, 172 (int (*)(int))NULL, /* psm_softlvl_to_irq */ 173 (void (*)(int))NULL, /* psm_set_softintr */ 174 175 apic_set_idlecpu, 176 apic_unset_idlecpu, 177 178 apic_clkinit, 179 apic_getclkirq, 180 (void (*)(void))NULL, /* psm_hrtimeinit */ 181 apic_gethrtime, 182 183 apic_get_next_processorid, 184 apic_cpu_start, 185 apic_post_cpu_start, 186 apic_shutdown, 187 apic_get_ipivect, 188 apic_send_ipi, 189 190 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */ 191 (void (*)(int, char *))NULL, /* psm_notify_error */ 192 (void (*)(int))NULL, /* psm_notify_func */ 193 apic_timer_reprogram, 194 apic_timer_enable, 195 apic_timer_disable, 196 apic_post_cyclic_setup, 197 apic_preshutdown, 198 apic_intr_ops, /* Advanced DDI Interrupt framework */ 199 apic_state, /* save, restore apic state for S3 */ 200 apic_cpu_ops, /* CPU control interface. */ 201 }; 202 203 struct psm_ops *psmops = &apic_ops; 204 205 static struct psm_info apic_psm_info = { 206 PSM_INFO_VER01_7, /* version */ 207 PSM_OWN_EXCLUSIVE, /* ownership */ 208 (struct psm_ops *)&apic_ops, /* operation */ 209 APIC_PCPLUSMP_NAME, /* machine name */ 210 "pcplusmp v1.4 compatible", 211 }; 212 213 static void *apic_hdlp; 214 215 /* 216 * apic_let_idle_redistribute can have the following values: 217 * 0 - If clock decremented it from 1 to 0, clock has to call redistribute. 218 * apic_redistribute_lock prevents multiple idle cpus from redistributing 219 */ 220 int apic_num_idle_redistributions = 0; 221 static int apic_let_idle_redistribute = 0; 222 223 /* to gather intr data and redistribute */ 224 static void apic_redistribute_compute(void); 225 226 /* 227 * This is the loadable module wrapper 228 */ 229 230 int 231 _init(void) 232 { 233 if (apic_coarse_hrtime) 234 apic_ops.psm_gethrtime = &apic_gettime; 235 return (psm_mod_init(&apic_hdlp, &apic_psm_info)); 236 } 237 238 int 239 _fini(void) 240 { 241 return (psm_mod_fini(&apic_hdlp, &apic_psm_info)); 242 } 243 244 int 245 _info(struct modinfo *modinfop) 246 { 247 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop)); 248 } 249 250 static int 251 apic_probe(void) 252 { 253 /* check if apix is initialized */ 254 if (apix_enable && apix_loaded()) 255 return (PSM_FAILURE); 256 else 257 apix_enable = 0; /* continue using pcplusmp PSM */ 258 259 return (apic_probe_common(apic_psm_info.p_mach_idstring)); 260 } 261 262 static uchar_t 263 apic_xlate_vector_by_irq(uchar_t irq) 264 { 265 if (apic_irq_table[irq] == NULL) 266 return (0); 267 268 return (apic_irq_table[irq]->airq_vector); 269 } 270 271 void 272 apic_init(void) 273 { 274 int i; 275 int j = 1; 276 277 psm_get_ioapicid = apic_get_ioapicid; 278 psm_get_localapicid = apic_get_localapicid; 279 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq; 280 281 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */ 282 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) { 283 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) && 284 (apic_vectortoipl[i + 1] == apic_vectortoipl[i])) 285 /* get to highest vector at the same ipl */ 286 continue; 287 for (; j <= apic_vectortoipl[i]; j++) { 288 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + 289 APIC_BASE_VECT; 290 } 291 } 292 for (; j < MAXIPL + 1; j++) 293 /* fill up any empty ipltopri slots */ 294 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT; 295 apic_init_common(); 296 #if defined(__amd64) 297 /* 298 * Make cpu-specific interrupt info point to cr8pri vector 299 */ 300 for (i = 0; i <= MAXIPL; i++) 301 apic_cr8pri[i] = apic_ipltopri[i] >> APIC_IPL_SHIFT; 302 CPU->cpu_pri_data = apic_cr8pri; 303 #else 304 if (cpuid_have_cr8access(CPU)) 305 apic_have_32bit_cr8 = 1; 306 #endif /* __amd64 */ 307 } 308 309 static void 310 apic_init_intr(void) 311 { 312 processorid_t cpun = psm_get_cpu_id(); 313 uint_t nlvt; 314 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR; 315 316 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL); 317 318 if (apic_mode == LOCAL_APIC) { 319 /* 320 * We are running APIC in MMIO mode. 321 */ 322 if (apic_flat_model) { 323 apic_reg_ops->apic_write(APIC_FORMAT_REG, 324 APIC_FLAT_MODEL); 325 } else { 326 apic_reg_ops->apic_write(APIC_FORMAT_REG, 327 APIC_CLUSTER_MODEL); 328 } 329 330 apic_reg_ops->apic_write(APIC_DEST_REG, 331 AV_HIGH_ORDER >> cpun); 332 } 333 334 if (apic_directed_EOI_supported()) { 335 /* 336 * Setting the 12th bit in the Spurious Interrupt Vector 337 * Register suppresses broadcast EOIs generated by the local 338 * APIC. The suppression of broadcast EOIs happens only when 339 * interrupts are level-triggered. 340 */ 341 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI; 342 } 343 344 /* need to enable APIC before unmasking NMI */ 345 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr); 346 347 /* 348 * Presence of an invalid vector with delivery mode AV_FIXED can 349 * cause an error interrupt, even if the entry is masked...so 350 * write a valid vector to LVT entries along with the mask bit 351 */ 352 353 /* All APICs have timer and LINT0/1 */ 354 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ); 355 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ); 356 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */ 357 358 /* 359 * On integrated APICs, the number of LVT entries is 360 * 'Max LVT entry' + 1; on 82489DX's (non-integrated 361 * APICs), nlvt is "3" (LINT0, LINT1, and timer) 362 */ 363 364 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) { 365 nlvt = 3; 366 } else { 367 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) & 368 0xFF) + 1; 369 } 370 371 if (nlvt >= 5) { 372 /* Enable performance counter overflow interrupt */ 373 374 if ((x86_feature & X86_MSR) != X86_MSR) 375 apic_enable_cpcovf_intr = 0; 376 if (apic_enable_cpcovf_intr) { 377 if (apic_cpcovf_vect == 0) { 378 int ipl = APIC_PCINT_IPL; 379 int irq = apic_get_ipivect(ipl, -1); 380 381 ASSERT(irq != -1); 382 apic_cpcovf_vect = 383 apic_irq_table[irq]->airq_vector; 384 ASSERT(apic_cpcovf_vect); 385 (void) add_avintr(NULL, ipl, 386 (avfunc)kcpc_hw_overflow_intr, 387 "apic pcint", irq, NULL, NULL, NULL, NULL); 388 kcpc_hw_overflow_intr_installed = 1; 389 kcpc_hw_enable_cpc_intr = 390 apic_cpcovf_mask_clear; 391 } 392 apic_reg_ops->apic_write(APIC_PCINT_VECT, 393 apic_cpcovf_vect); 394 } 395 } 396 397 if (nlvt >= 6) { 398 /* Only mask TM intr if the BIOS apparently doesn't use it */ 399 400 uint32_t lvtval; 401 402 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT); 403 if (((lvtval & AV_MASK) == AV_MASK) || 404 ((lvtval & AV_DELIV_MODE) != AV_SMI)) { 405 apic_reg_ops->apic_write(APIC_THERM_VECT, 406 AV_MASK|APIC_RESV_IRQ); 407 } 408 } 409 410 /* Enable error interrupt */ 411 412 if (nlvt >= 4 && apic_enable_error_intr) { 413 if (apic_errvect == 0) { 414 int ipl = 0xf; /* get highest priority intr */ 415 int irq = apic_get_ipivect(ipl, -1); 416 417 ASSERT(irq != -1); 418 apic_errvect = apic_irq_table[irq]->airq_vector; 419 ASSERT(apic_errvect); 420 /* 421 * Not PSMI compliant, but we are going to merge 422 * with ON anyway 423 */ 424 (void) add_avintr((void *)NULL, ipl, 425 (avfunc)apic_error_intr, "apic error intr", 426 irq, NULL, NULL, NULL, NULL); 427 } 428 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect); 429 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 430 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 431 } 432 433 /* Enable CMCI interrupt */ 434 if (cmi_enable_cmci) { 435 436 mutex_enter(&cmci_cpu_setup_lock); 437 if (cmci_cpu_setup_registered == 0) { 438 mutex_enter(&cpu_lock); 439 register_cpu_setup_func(cmci_cpu_setup, NULL); 440 mutex_exit(&cpu_lock); 441 cmci_cpu_setup_registered = 1; 442 } 443 mutex_exit(&cmci_cpu_setup_lock); 444 445 if (apic_cmci_vect == 0) { 446 int ipl = 0x2; 447 int irq = apic_get_ipivect(ipl, -1); 448 449 ASSERT(irq != -1); 450 apic_cmci_vect = apic_irq_table[irq]->airq_vector; 451 ASSERT(apic_cmci_vect); 452 453 (void) add_avintr(NULL, ipl, 454 (avfunc)cmi_cmci_trap, 455 "apic cmci intr", irq, NULL, NULL, NULL, NULL); 456 } 457 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect); 458 } 459 } 460 461 static void 462 apic_picinit(void) 463 { 464 int i, j; 465 uint_t isr; 466 467 /* 468 * Initialize and enable interrupt remapping before apic 469 * hardware initialization 470 */ 471 apic_intrmap_init(apic_mode); 472 473 /* 474 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr 475 * bit on without clearing it with EOI. Since softint 476 * uses vector 0x20 to interrupt itself, so softint will 477 * not work on this machine. In order to fix this problem 478 * a check is made to verify all the isr bits are clear. 479 * If not, EOIs are issued to clear the bits. 480 */ 481 for (i = 7; i >= 1; i--) { 482 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4)); 483 if (isr != 0) 484 for (j = 0; ((j < 32) && (isr != 0)); j++) 485 if (isr & (1 << j)) { 486 apic_reg_ops->apic_write( 487 APIC_EOI_REG, 0); 488 isr &= ~(1 << j); 489 apic_error |= APIC_ERR_BOOT_EOI; 490 } 491 } 492 493 /* set a flag so we know we have run apic_picinit() */ 494 apic_picinit_called = 1; 495 LOCK_INIT_CLEAR(&apic_gethrtime_lock); 496 LOCK_INIT_CLEAR(&apic_ioapic_lock); 497 LOCK_INIT_CLEAR(&apic_error_lock); 498 LOCK_INIT_CLEAR(&apic_mode_switch_lock); 499 500 picsetup(); /* initialise the 8259 */ 501 502 /* add nmi handler - least priority nmi handler */ 503 LOCK_INIT_CLEAR(&apic_nmi_lock); 504 505 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr, 506 "pcplusmp NMI handler", (caddr_t)NULL)) 507 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler"); 508 509 /* 510 * Check for directed-EOI capability in the local APIC. 511 */ 512 if (apic_directed_EOI_supported() == 1) { 513 apic_set_directed_EOI_handler(); 514 } 515 516 apic_init_intr(); 517 518 /* enable apic mode if imcr present */ 519 if (apic_imcrp) { 520 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 521 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC); 522 } 523 524 ioapic_init_intr(IOAPIC_MASK); 525 } 526 527 #ifdef DEBUG 528 void 529 apic_break(void) 530 { 531 } 532 #endif /* DEBUG */ 533 534 /* 535 * platform_intr_enter 536 * 537 * Called at the beginning of the interrupt service routine to 538 * mask all level equal to and below the interrupt priority 539 * of the interrupting vector. An EOI should be given to 540 * the interrupt controller to enable other HW interrupts. 541 * 542 * Return -1 for spurious interrupts 543 * 544 */ 545 /*ARGSUSED*/ 546 static int 547 apic_intr_enter(int ipl, int *vectorp) 548 { 549 uchar_t vector; 550 int nipl; 551 int irq; 552 ulong_t iflag; 553 apic_cpus_info_t *cpu_infop; 554 555 /* 556 * The real vector delivered is (*vectorp + 0x20), but our caller 557 * subtracts 0x20 from the vector before passing it to us. 558 * (That's why APIC_BASE_VECT is 0x20.) 559 */ 560 vector = (uchar_t)*vectorp; 561 562 /* if interrupted by the clock, increment apic_nsec_since_boot */ 563 if (vector == apic_clkvect) { 564 if (!apic_oneshot) { 565 /* NOTE: this is not MT aware */ 566 apic_hrtime_stamp++; 567 apic_nsec_since_boot += apic_nsec_per_intr; 568 apic_hrtime_stamp++; 569 last_count_read = apic_hertz_count; 570 apic_redistribute_compute(); 571 } 572 573 /* We will avoid all the book keeping overhead for clock */ 574 nipl = apic_ipls[vector]; 575 576 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT]; 577 if (apic_mode == LOCAL_APIC) { 578 #if defined(__amd64) 579 setcr8((ulong_t)(apic_ipltopri[nipl] >> 580 APIC_IPL_SHIFT)); 581 #else 582 if (apic_have_32bit_cr8) 583 setcr8((ulong_t)(apic_ipltopri[nipl] >> 584 APIC_IPL_SHIFT)); 585 else 586 LOCAL_APIC_WRITE_REG(APIC_TASK_REG, 587 (uint32_t)apic_ipltopri[nipl]); 588 #endif 589 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0); 590 } else { 591 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]); 592 X2APIC_WRITE(APIC_EOI_REG, 0); 593 } 594 595 return (nipl); 596 } 597 598 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 599 600 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) { 601 cpu_infop->aci_spur_cnt++; 602 return (APIC_INT_SPURIOUS); 603 } 604 605 /* Check if the vector we got is really what we need */ 606 if (apic_revector_pending) { 607 /* 608 * Disable interrupts for the duration of 609 * the vector translation to prevent a self-race for 610 * the apic_revector_lock. This cannot be done 611 * in apic_xlate_vector because it is recursive and 612 * we want the vector translation to be atomic with 613 * respect to other (higher-priority) interrupts. 614 */ 615 iflag = intr_clear(); 616 vector = apic_xlate_vector(vector + APIC_BASE_VECT) - 617 APIC_BASE_VECT; 618 intr_restore(iflag); 619 } 620 621 nipl = apic_ipls[vector]; 622 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT]; 623 624 if (apic_mode == LOCAL_APIC) { 625 #if defined(__amd64) 626 setcr8((ulong_t)(apic_ipltopri[nipl] >> APIC_IPL_SHIFT)); 627 #else 628 if (apic_have_32bit_cr8) 629 setcr8((ulong_t)(apic_ipltopri[nipl] >> 630 APIC_IPL_SHIFT)); 631 else 632 LOCAL_APIC_WRITE_REG(APIC_TASK_REG, 633 (uint32_t)apic_ipltopri[nipl]); 634 #endif 635 } else { 636 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]); 637 } 638 639 cpu_infop->aci_current[nipl] = (uchar_t)irq; 640 cpu_infop->aci_curipl = (uchar_t)nipl; 641 cpu_infop->aci_ISR_in_progress |= 1 << nipl; 642 643 /* 644 * apic_level_intr could have been assimilated into the irq struct. 645 * but, having it as a character array is more efficient in terms of 646 * cache usage. So, we leave it as is. 647 */ 648 if (!apic_level_intr[irq]) { 649 if (apic_mode == LOCAL_APIC) { 650 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0); 651 } else { 652 X2APIC_WRITE(APIC_EOI_REG, 0); 653 } 654 } 655 656 #ifdef DEBUG 657 APIC_DEBUG_BUF_PUT(vector); 658 APIC_DEBUG_BUF_PUT(irq); 659 APIC_DEBUG_BUF_PUT(nipl); 660 APIC_DEBUG_BUF_PUT(psm_get_cpu_id()); 661 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl))) 662 drv_usecwait(apic_stretch_interrupts); 663 664 if (apic_break_on_cpu == psm_get_cpu_id()) 665 apic_break(); 666 #endif /* DEBUG */ 667 return (nipl); 668 } 669 670 /* 671 * This macro is a common code used by MMIO local apic and X2APIC 672 * local apic. 673 */ 674 #define APIC_INTR_EXIT() \ 675 { \ 676 cpu_infop = &apic_cpus[psm_get_cpu_id()]; \ 677 if (apic_level_intr[irq]) \ 678 apic_reg_ops->apic_send_eoi(irq); \ 679 cpu_infop->aci_curipl = (uchar_t)prev_ipl; \ 680 /* ISR above current pri could not be in progress */ \ 681 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; \ 682 } 683 684 /* 685 * Any changes made to this function must also change X2APIC 686 * version of intr_exit. 687 */ 688 void 689 apic_intr_exit(int prev_ipl, int irq) 690 { 691 apic_cpus_info_t *cpu_infop; 692 693 #if defined(__amd64) 694 setcr8((ulong_t)apic_cr8pri[prev_ipl]); 695 #else 696 if (apic_have_32bit_cr8) 697 setcr8((ulong_t)(apic_ipltopri[prev_ipl] >> APIC_IPL_SHIFT)); 698 else 699 apicadr[APIC_TASK_REG] = apic_ipltopri[prev_ipl]; 700 #endif 701 702 APIC_INTR_EXIT(); 703 } 704 705 /* 706 * Same as apic_intr_exit() except it uses MSR rather than MMIO 707 * to access local apic registers. 708 */ 709 void 710 x2apic_intr_exit(int prev_ipl, int irq) 711 { 712 apic_cpus_info_t *cpu_infop; 713 714 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[prev_ipl]); 715 APIC_INTR_EXIT(); 716 } 717 718 intr_exit_fn_t 719 psm_intr_exit_fn(void) 720 { 721 if (apic_mode == LOCAL_X2APIC) 722 return (x2apic_intr_exit); 723 724 return (apic_intr_exit); 725 } 726 727 /* 728 * Mask all interrupts below or equal to the given IPL. 729 * Any changes made to this function must also change X2APIC 730 * version of setspl. 731 */ 732 static void 733 apic_setspl(int ipl) 734 { 735 #if defined(__amd64) 736 setcr8((ulong_t)apic_cr8pri[ipl]); 737 #else 738 if (apic_have_32bit_cr8) 739 setcr8((ulong_t)(apic_ipltopri[ipl] >> APIC_IPL_SHIFT)); 740 else 741 apicadr[APIC_TASK_REG] = apic_ipltopri[ipl]; 742 #endif 743 744 /* interrupts at ipl above this cannot be in progress */ 745 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 746 /* 747 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts 748 * have enough time to come in before the priority is raised again 749 * during the idle() loop. 750 */ 751 if (apic_setspl_delay) 752 (void) apic_reg_ops->apic_get_pri(); 753 } 754 755 /* 756 * X2APIC version of setspl. 757 * Mask all interrupts below or equal to the given IPL 758 */ 759 static void 760 x2apic_setspl(int ipl) 761 { 762 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[ipl]); 763 764 /* interrupts at ipl above this cannot be in progress */ 765 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 766 } 767 768 /*ARGSUSED*/ 769 static int 770 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl) 771 { 772 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl)); 773 } 774 775 static int 776 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl) 777 { 778 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl)); 779 } 780 781 static int 782 apic_post_cpu_start(void) 783 { 784 int cpun; 785 static int cpus_started = 1; 786 787 /* We know this CPU + BSP started successfully. */ 788 cpus_started++; 789 790 /* 791 * On BSP we would have enabled X2APIC, if supported by processor, 792 * in acpi_probe(), but on AP we do it here. 793 * 794 * We enable X2APIC mode only if BSP is running in X2APIC & the 795 * local APIC mode of the current CPU is MMIO (xAPIC). 796 */ 797 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() && 798 apic_local_mode() == LOCAL_APIC) { 799 apic_enable_x2apic(); 800 } 801 802 /* 803 * Switch back to x2apic IPI sending method for performance when target 804 * CPU has entered x2apic mode. 805 */ 806 if (apic_mode == LOCAL_X2APIC) { 807 apic_switch_ipi_callback(B_FALSE); 808 } 809 810 splx(ipltospl(LOCK_LEVEL)); 811 apic_init_intr(); 812 813 /* 814 * since some systems don't enable the internal cache on the non-boot 815 * cpus, so we have to enable them here 816 */ 817 setcr0(getcr0() & ~(CR0_CD | CR0_NW)); 818 819 #ifdef DEBUG 820 APIC_AV_PENDING_SET(); 821 #else 822 if (apic_mode == LOCAL_APIC) 823 APIC_AV_PENDING_SET(); 824 #endif /* DEBUG */ 825 826 /* 827 * We may be booting, or resuming from suspend; aci_status will 828 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the 829 * APIC_CPU_ONLINE flag here rather than setting aci_status completely. 830 */ 831 cpun = psm_get_cpu_id(); 832 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE; 833 834 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init); 835 return (PSM_SUCCESS); 836 } 837 838 /* 839 * type == -1 indicates it is an internal request. Do not change 840 * resv_vector for these requests 841 */ 842 static int 843 apic_get_ipivect(int ipl, int type) 844 { 845 uchar_t vector; 846 int irq; 847 848 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) { 849 if (vector = apic_allocate_vector(ipl, irq, 1)) { 850 apic_irq_table[irq]->airq_mps_intr_index = 851 RESERVE_INDEX; 852 apic_irq_table[irq]->airq_vector = vector; 853 if (type != -1) { 854 apic_resv_vector[ipl] = vector; 855 } 856 return (irq); 857 } 858 } 859 apic_error |= APIC_ERR_GET_IPIVECT_FAIL; 860 return (-1); /* shouldn't happen */ 861 } 862 863 static int 864 apic_getclkirq(int ipl) 865 { 866 int irq; 867 868 if ((irq = apic_get_ipivect(ipl, -1)) == -1) 869 return (-1); 870 /* 871 * Note the vector in apic_clkvect for per clock handling. 872 */ 873 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT; 874 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n", 875 apic_clkvect)); 876 return (irq); 877 } 878 879 /* 880 * Try and disable all interrupts. We just assign interrupts to other 881 * processors based on policy. If any were bound by user request, we 882 * let them continue and return failure. We do not bother to check 883 * for cache affinity while rebinding. 884 */ 885 886 static int 887 apic_disable_intr(processorid_t cpun) 888 { 889 int bind_cpu = 0, i, hardbound = 0; 890 apic_irq_t *irq_ptr; 891 ulong_t iflag; 892 893 iflag = intr_clear(); 894 lock_set(&apic_ioapic_lock); 895 896 for (i = 0; i <= APIC_MAX_VECTOR; i++) { 897 if (apic_reprogram_info[i].done == B_FALSE) { 898 if (apic_reprogram_info[i].bindcpu == cpun) { 899 /* 900 * CPU is busy -- it's the target of 901 * a pending reprogramming attempt 902 */ 903 lock_clear(&apic_ioapic_lock); 904 intr_restore(iflag); 905 return (PSM_FAILURE); 906 } 907 } 908 } 909 910 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE; 911 912 apic_cpus[cpun].aci_curipl = 0; 913 914 i = apic_min_device_irq; 915 for (; i <= apic_max_device_irq; i++) { 916 /* 917 * If there are bound interrupts on this cpu, then 918 * rebind them to other processors. 919 */ 920 if ((irq_ptr = apic_irq_table[i]) != NULL) { 921 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) || 922 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) || 923 (apic_cpu_in_range(irq_ptr->airq_temp_cpu))); 924 925 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) { 926 hardbound = 1; 927 continue; 928 } 929 930 if (irq_ptr->airq_temp_cpu == cpun) { 931 do { 932 bind_cpu = 933 apic_find_cpu(APIC_CPU_INTR_ENABLE); 934 } while (apic_rebind_all(irq_ptr, bind_cpu)); 935 } 936 } 937 } 938 939 lock_clear(&apic_ioapic_lock); 940 intr_restore(iflag); 941 942 if (hardbound) { 943 cmn_err(CE_WARN, "Could not disable interrupts on %d" 944 "due to user bound interrupts", cpun); 945 return (PSM_FAILURE); 946 } 947 else 948 return (PSM_SUCCESS); 949 } 950 951 /* 952 * Bind interrupts to the CPU's local APIC. 953 * Interrupts should not be bound to a CPU's local APIC until the CPU 954 * is ready to receive interrupts. 955 */ 956 static void 957 apic_enable_intr(processorid_t cpun) 958 { 959 int i; 960 apic_irq_t *irq_ptr; 961 ulong_t iflag; 962 963 iflag = intr_clear(); 964 lock_set(&apic_ioapic_lock); 965 966 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE; 967 968 i = apic_min_device_irq; 969 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 970 if ((irq_ptr = apic_irq_table[i]) != NULL) { 971 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) { 972 (void) apic_rebind_all(irq_ptr, 973 irq_ptr->airq_cpu); 974 } 975 } 976 } 977 978 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) 979 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND; 980 981 lock_clear(&apic_ioapic_lock); 982 intr_restore(iflag); 983 } 984 985 /* 986 * If this module needs a periodic handler for the interrupt distribution, it 987 * can be added here. The argument to the periodic handler is not currently 988 * used, but is reserved for future. 989 */ 990 static void 991 apic_post_cyclic_setup(void *arg) 992 { 993 _NOTE(ARGUNUSED(arg)) 994 /* cpu_lock is held */ 995 /* set up a periodic handler for intr redistribution */ 996 997 /* 998 * In peridoc mode intr redistribution processing is done in 999 * apic_intr_enter during clk intr processing 1000 */ 1001 if (!apic_oneshot) 1002 return; 1003 /* 1004 * Register a periodical handler for the redistribution processing. 1005 * On X86, CY_LOW_LEVEL is mapped to the level 2 interrupt, so 1006 * DDI_IPL_2 should be passed to ddi_periodic_add() here. 1007 */ 1008 apic_periodic_id = ddi_periodic_add( 1009 (void (*)(void *))apic_redistribute_compute, NULL, 1010 apic_redistribute_sample_interval, DDI_IPL_2); 1011 } 1012 1013 static void 1014 apic_redistribute_compute(void) 1015 { 1016 int i, j, max_busy; 1017 1018 if (apic_enable_dynamic_migration) { 1019 if (++apic_nticks == apic_sample_factor_redistribution) { 1020 /* 1021 * Time to call apic_intr_redistribute(). 1022 * reset apic_nticks. This will cause max_busy 1023 * to be calculated below and if it is more than 1024 * apic_int_busy, we will do the whole thing 1025 */ 1026 apic_nticks = 0; 1027 } 1028 max_busy = 0; 1029 for (i = 0; i < apic_nproc; i++) { 1030 if (!apic_cpu_in_range(i)) 1031 continue; 1032 1033 /* 1034 * Check if curipl is non zero & if ISR is in 1035 * progress 1036 */ 1037 if (((j = apic_cpus[i].aci_curipl) != 0) && 1038 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) { 1039 1040 int irq; 1041 apic_cpus[i].aci_busy++; 1042 irq = apic_cpus[i].aci_current[j]; 1043 apic_irq_table[irq]->airq_busy++; 1044 } 1045 1046 if (!apic_nticks && 1047 (apic_cpus[i].aci_busy > max_busy)) 1048 max_busy = apic_cpus[i].aci_busy; 1049 } 1050 if (!apic_nticks) { 1051 if (max_busy > apic_int_busy_mark) { 1052 /* 1053 * We could make the following check be 1054 * skipped > 1 in which case, we get a 1055 * redistribution at half the busy mark (due to 1056 * double interval). Need to be able to collect 1057 * more empirical data to decide if that is a 1058 * good strategy. Punt for now. 1059 */ 1060 if (apic_skipped_redistribute) { 1061 apic_cleanup_busy(); 1062 apic_skipped_redistribute = 0; 1063 } else { 1064 apic_intr_redistribute(); 1065 } 1066 } else 1067 apic_skipped_redistribute++; 1068 } 1069 } 1070 } 1071 1072 1073 /* 1074 * The following functions are in the platform specific file so that they 1075 * can be different functions depending on whether we are running on 1076 * bare metal or a hypervisor. 1077 */ 1078 1079 /* 1080 * Check to make sure there are enough irq slots 1081 */ 1082 int 1083 apic_check_free_irqs(int count) 1084 { 1085 int i, avail; 1086 1087 avail = 0; 1088 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 1089 if ((apic_irq_table[i] == NULL) || 1090 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) { 1091 if (++avail >= count) 1092 return (PSM_SUCCESS); 1093 } 1094 } 1095 return (PSM_FAILURE); 1096 } 1097 1098 /* 1099 * This function allocates "count" MSI vector(s) for the given "dip/pri/type" 1100 */ 1101 int 1102 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri, 1103 int behavior) 1104 { 1105 int rcount, i; 1106 uchar_t start, irqno; 1107 uint32_t cpu; 1108 major_t major; 1109 apic_irq_t *irqptr; 1110 1111 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p " 1112 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n", 1113 (void *)dip, inum, pri, count, behavior)); 1114 1115 if (count > 1) { 1116 if (behavior == DDI_INTR_ALLOC_STRICT && 1117 apic_multi_msi_enable == 0) 1118 return (0); 1119 if (apic_multi_msi_enable == 0) 1120 count = 1; 1121 } 1122 1123 if ((rcount = apic_navail_vector(dip, pri)) > count) 1124 rcount = count; 1125 else if (rcount == 0 || (rcount < count && 1126 behavior == DDI_INTR_ALLOC_STRICT)) 1127 return (0); 1128 1129 /* if not ISP2, then round it down */ 1130 if (!ISP2(rcount)) 1131 rcount = 1 << (highbit(rcount) - 1); 1132 1133 mutex_enter(&airq_mutex); 1134 1135 for (start = 0; rcount > 0; rcount >>= 1) { 1136 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 || 1137 behavior == DDI_INTR_ALLOC_STRICT) 1138 break; 1139 } 1140 1141 if (start == 0) { 1142 /* no vector available */ 1143 mutex_exit(&airq_mutex); 1144 return (0); 1145 } 1146 1147 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 1148 /* not enough free irq slots available */ 1149 mutex_exit(&airq_mutex); 1150 return (0); 1151 } 1152 1153 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 1154 for (i = 0; i < rcount; i++) { 1155 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 1156 (uchar_t)-1) { 1157 /* 1158 * shouldn't happen because of the 1159 * apic_check_free_irqs() check earlier 1160 */ 1161 mutex_exit(&airq_mutex); 1162 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 1163 "apic_allocate_irq failed\n")); 1164 return (i); 1165 } 1166 apic_max_device_irq = max(irqno, apic_max_device_irq); 1167 apic_min_device_irq = min(irqno, apic_min_device_irq); 1168 irqptr = apic_irq_table[irqno]; 1169 #ifdef DEBUG 1170 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ) 1171 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 1172 "apic_vector_to_irq is not APIC_RESV_IRQ\n")); 1173 #endif 1174 apic_vector_to_irq[start + i] = (uchar_t)irqno; 1175 1176 irqptr->airq_vector = (uchar_t)(start + i); 1177 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */ 1178 irqptr->airq_intin_no = (uchar_t)rcount; 1179 irqptr->airq_ipl = pri; 1180 irqptr->airq_vector = start + i; 1181 irqptr->airq_origirq = (uchar_t)(inum + i); 1182 irqptr->airq_share_id = 0; 1183 irqptr->airq_mps_intr_index = MSI_INDEX; 1184 irqptr->airq_dip = dip; 1185 irqptr->airq_major = major; 1186 if (i == 0) /* they all bound to the same cpu */ 1187 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno, 1188 0xff, 0xff); 1189 else 1190 irqptr->airq_cpu = cpu; 1191 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x " 1192 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno, 1193 (void *)irqptr->airq_dip, irqptr->airq_vector, 1194 irqptr->airq_origirq, pri)); 1195 } 1196 mutex_exit(&airq_mutex); 1197 return (rcount); 1198 } 1199 1200 /* 1201 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type" 1202 */ 1203 int 1204 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri, 1205 int behavior) 1206 { 1207 int rcount, i; 1208 major_t major; 1209 1210 mutex_enter(&airq_mutex); 1211 1212 if ((rcount = apic_navail_vector(dip, pri)) > count) 1213 rcount = count; 1214 else if (rcount == 0 || (rcount < count && 1215 behavior == DDI_INTR_ALLOC_STRICT)) { 1216 rcount = 0; 1217 goto out; 1218 } 1219 1220 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 1221 /* not enough free irq slots available */ 1222 rcount = 0; 1223 goto out; 1224 } 1225 1226 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 1227 for (i = 0; i < rcount; i++) { 1228 uchar_t vector, irqno; 1229 apic_irq_t *irqptr; 1230 1231 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 1232 (uchar_t)-1) { 1233 /* 1234 * shouldn't happen because of the 1235 * apic_check_free_irqs() check earlier 1236 */ 1237 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 1238 "apic_allocate_irq failed\n")); 1239 rcount = i; 1240 goto out; 1241 } 1242 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) { 1243 /* 1244 * shouldn't happen because of the 1245 * apic_navail_vector() call earlier 1246 */ 1247 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 1248 "apic_allocate_vector failed\n")); 1249 rcount = i; 1250 goto out; 1251 } 1252 apic_max_device_irq = max(irqno, apic_max_device_irq); 1253 apic_min_device_irq = min(irqno, apic_min_device_irq); 1254 irqptr = apic_irq_table[irqno]; 1255 irqptr->airq_vector = (uchar_t)vector; 1256 irqptr->airq_ipl = pri; 1257 irqptr->airq_origirq = (uchar_t)(inum + i); 1258 irqptr->airq_share_id = 0; 1259 irqptr->airq_mps_intr_index = MSIX_INDEX; 1260 irqptr->airq_dip = dip; 1261 irqptr->airq_major = major; 1262 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff); 1263 } 1264 out: 1265 mutex_exit(&airq_mutex); 1266 return (rcount); 1267 } 1268 1269 /* 1270 * Allocate a free vector for irq at ipl. Takes care of merging of multiple 1271 * IPLs into a single APIC level as well as stretching some IPLs onto multiple 1272 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority 1273 * requests and allocated only when pri is set. 1274 */ 1275 uchar_t 1276 apic_allocate_vector(int ipl, int irq, int pri) 1277 { 1278 int lowest, highest, i; 1279 1280 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 1281 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL; 1282 1283 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */ 1284 lowest -= APIC_VECTOR_PER_IPL; 1285 1286 #ifdef DEBUG 1287 if (apic_restrict_vector) /* for testing shared interrupt logic */ 1288 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS; 1289 #endif /* DEBUG */ 1290 if (pri == 0) 1291 highest -= APIC_HI_PRI_VECTS; 1292 1293 for (i = lowest; i <= highest; i++) { 1294 if (APIC_CHECK_RESERVE_VECTORS(i)) 1295 continue; 1296 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) { 1297 apic_vector_to_irq[i] = (uchar_t)irq; 1298 return (i); 1299 } 1300 } 1301 1302 return (0); 1303 } 1304 1305 /* Mark vector as not being used by any irq */ 1306 void 1307 apic_free_vector(uchar_t vector) 1308 { 1309 apic_vector_to_irq[vector] = APIC_RESV_IRQ; 1310 } 1311 1312 /* 1313 * Call rebind to do the actual programming. 1314 * Must be called with interrupts disabled and apic_ioapic_lock held 1315 * 'p' is polymorphic -- if this function is called to process a deferred 1316 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which 1317 * the irq pointer is retrieved. If not doing deferred reprogramming, 1318 * p is of the type 'apic_irq_t *'. 1319 * 1320 * apic_ioapic_lock must be held across this call, as it protects apic_rebind 1321 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be 1322 * taken offline after a cpu is selected, but before apic_rebind is called to 1323 * bind interrupts to it. 1324 */ 1325 int 1326 apic_setup_io_intr(void *p, int irq, boolean_t deferred) 1327 { 1328 apic_irq_t *irqptr; 1329 struct ioapic_reprogram_data *drep = NULL; 1330 int rv; 1331 1332 if (deferred) { 1333 drep = (struct ioapic_reprogram_data *)p; 1334 ASSERT(drep != NULL); 1335 irqptr = drep->irqp; 1336 } else 1337 irqptr = (apic_irq_t *)p; 1338 1339 ASSERT(irqptr != NULL); 1340 1341 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep); 1342 if (rv) { 1343 /* 1344 * CPU is not up or interrupts are disabled. Fall back to 1345 * the first available CPU 1346 */ 1347 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE), 1348 drep); 1349 } 1350 1351 return (rv); 1352 } 1353 1354 1355 uchar_t 1356 apic_modify_vector(uchar_t vector, int irq) 1357 { 1358 apic_vector_to_irq[vector] = (uchar_t)irq; 1359 return (vector); 1360 } 1361 1362 char * 1363 apic_get_apic_type(void) 1364 { 1365 return (apic_psm_info.p_mach_idstring); 1366 } 1367 1368 void 1369 x2apic_update_psm(void) 1370 { 1371 struct psm_ops *pops = &apic_ops; 1372 1373 ASSERT(pops != NULL); 1374 1375 pops->psm_intr_exit = x2apic_intr_exit; 1376 pops->psm_setspl = x2apic_setspl; 1377 1378 pops->psm_send_ipi = x2apic_send_ipi; 1379 send_dirintf = pops->psm_send_ipi; 1380 1381 apic_mode = LOCAL_X2APIC; 1382 apic_change_ops(); 1383 } 1384