1 /* 2 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2008 Weongyo Jeong 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 21 * NO WARRANTY 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 25 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 26 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 27 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 30 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGES. 33 */ 34 35 #ifndef _URTW_REG_H 36 #define _URTW_REG_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /* 43 * Known hardware revisions. 44 */ 45 #define URTW_HWREV_8187 0x01 46 #define URTW_HWREV_8187_B 0x02 47 #define URTW_HWREV_8187_D 0x04 48 #define URTW_HWREV_8187B 0x08 49 #define URTW_HWREV_8187B_B 0x10 50 #define URTW_HWREV_8187B_D 0x20 51 #define URTW_HWREV_8187B_E 0x40 52 53 /* for 8187 */ 54 #define URTW_MAC0 0x0000 /* 1 byte */ 55 #define URTW_MAC1 0x0001 /* 1 byte */ 56 #define URTW_MAC2 0x0002 /* 1 byte */ 57 #define URTW_MAC3 0x0003 /* 1 byte */ 58 #define URTW_MAC4 0x0004 /* 1 byte */ 59 #define URTW_MAC5 0x0005 /* 1 byte */ 60 #define URTW_BRSR 0x002c /* 2 byte */ 61 #define URTW_BRSR_MBR_8185 (0x0fff) 62 #define URTW_8187B_EIFS 0x002d /* 1 byte */ 63 #define URTW_BSSID 0x002e /* 6 byte */ 64 #define URTW_RESP_RATE 0x0034 /* 1 byte */ 65 #define URTW_8187B_BRSR 0x0034 /* 2 byte */ 66 #define URTW_RESP_MAX_RATE_SHIFT (4) 67 #define URTW_RESP_MIN_RATE_SHIFT (0) 68 #define URTW_EIFS 0x0035 /* 1 byte */ 69 #define URTW_INTR_MASK 0x003c /* 2 byte */ 70 #define URTW_CMD 0x0037 /* 1 byte */ 71 #define URTW_CMD_TX_ENABLE (0x4) 72 #define URTW_CMD_RX_ENABLE (0x8) 73 #define URTW_CMD_RST (0x10) 74 #define URTW_TX_CONF 0x0040 /* 4 byte */ 75 76 #define URTW_TX_HWREV_MASK (7 << 25) 77 #define URTW_TX_HWREV_8187_D (5 << 25) 78 #define URTW_TX_HWREV_8187B_D (6 << 25) 79 #define URTW_TX_DURPROCMODE (1 << 30) 80 #define URTW_TX_DISREQQSIZE (1 << 28) 81 #define URTW_TX_SHORTRETRY (7 << 8) 82 #define URTW_TX_LONGRETRY (7 << 0) 83 84 #define URTW_TX_LOOPBACK_SHIFT (17) 85 #define URTW_TX_LOOPBACK_NONE (0 << URTW_TX_LOOPBACK_SHIFT) 86 #define URTW_TX_LOOPBACK_MAC (1 << URTW_TX_LOOPBACK_SHIFT) 87 #define URTW_TX_LOOPBACK_BASEBAND (2 << URTW_TX_LOOPBACK_SHIFT) 88 #define URTW_TX_LOOPBACK_CONTINUE (3 << URTW_TX_LOOPBACK_SHIFT) 89 #define URTW_TX_LOOPBACK_MASK (0x60000) 90 #define URTW_TX_DPRETRY_MASK (0xff00) 91 #define URTW_TX_RTSRETRY_MASK (0xff) 92 #define URTW_TX_DPRETRY_SHIFT (0) 93 #define URTW_TX_RTSRETRY_SHIFT (8) 94 #define URTW_TX_NOCRC (0x10000) 95 #define URTW_TX_MXDMA_MASK (0xe00000) 96 #define URTW_TX_MXDMA_1024 (6 << URTW_TX_MXDMA_SHIFT) 97 #define URTW_TX_MXDMA_2048 (7 << URTW_TX_MXDMA_SHIFT) 98 #define URTW_TX_MXDMA_SHIFT (21) 99 #define URTW_TX_CWMIN (0x80000000) 100 #define URTW_TX_DISCW (1 << 20) 101 #define URTW_TX_SWPLCPLEN (1 << 24) 102 #define URTW_TX_NOICV (0x80000) 103 #define URTW_RX 0x0044 /* 4 byte */ 104 #define URTW_RX_9356SEL (1 << 6) 105 #define URTW_RX_FILTER_MASK \ 106 (URTW_RX_FILTER_ALLMAC | URTW_RX_FILTER_NICMAC |\ 107 URTW_RX_FILTER_MCAST | \ 108 URTW_RX_FILTER_BCAST | URTW_RX_FILTER_CRCERR |\ 109 URTW_RX_FILTER_ICVERR | \ 110 URTW_RX_FILTER_DATA | URTW_RX_FILTER_CTL |\ 111 URTW_RX_FILTER_MNG | \ 112 (1 << 21) |\ 113 URTW_RX_FILTER_PWR | URTW_RX_CHECK_BSSID) 114 #define URTW_RX_FILTER_ALLMAC (0x00000001) 115 #define URTW_RX_FILTER_NICMAC (0x00000002) 116 #define URTW_RX_FILTER_MCAST (0x00000004) 117 #define URTW_RX_FILTER_BCAST (0x00000008) 118 #define URTW_RX_FILTER_CRCERR (0x00000020) 119 #define URTW_RX_FILTER_ICVERR (0x00001000) 120 #define URTW_RX_FILTER_DATA (0x00040000) 121 #define URTW_RX_FILTER_CTL (0x00080000) 122 #define URTW_RX_FILTER_MNG (0x00100000) 123 #define URTW_RX_FILTER_PWR (0x00400000) 124 #define URTW_RX_CHECK_BSSID (0x00800000) 125 #define URTW_RX_FIFO_THRESHOLD_MASK ((1 << 13) | (1 << 14) | (1 << 15)) 126 #define URTW_RX_FIFO_THRESHOLD_SHIFT (13) 127 #define URTW_RX_FIFO_THRESHOLD_128 (3) 128 #define URTW_RX_FIFO_THRESHOLD_256 (4) 129 #define URTW_RX_FIFO_THRESHOLD_512 (5) 130 #define URTW_RX_FIFO_THRESHOLD_1024 (6) 131 #define URTW_RX_FIFO_THRESHOLD_NONE (7 << URTW_RX_FIFO_THRESHOLD_SHIFT) 132 #define URTW_RX_AUTORESETPHY (1 << URTW_RX_AUTORESETPHY_SHIFT) 133 #define URTW_RX_AUTORESETPHY_SHIFT (28) 134 #define URTW_MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) 135 #define URTW_MAX_RX_DMA_2048 (0x1c00) 136 #define URTW_MAX_RX_DMA_1024 (6) 137 #define URTW_MAX_RX_DMA_SHIFT (10) 138 #define URTW_RCR_ONLYERLPKT (0x80000000) 139 #define URTW_INT_TIMEOUT 0x0048 /* 4 byte */ 140 #define URTW_EPROM_CMD 0x0050 /* 1 byte */ 141 #define URTW_EPROM_CMD_NORMAL (0x0) 142 #define URTW_EPROM_CMD_NORMAL_MODE \ 143 (URTW_EPROM_CMD_NORMAL << URTW_EPROM_CMD_SHIFT) 144 #define URTW_EPROM_CMD_LOAD (0x1) 145 #define URTW_EPROM_CMD_PROGRAM (0x2) 146 #define URTW_EPROM_CMD_PROGRAM_MODE \ 147 (URTW_EPROM_CMD_PROGRAM << URTW_EPROM_CMD_SHIFT) 148 #define URTW_EPROM_CMD_CONFIG (0x3) 149 #define URTW_EPROM_CMD_SHIFT (6) 150 #define URTW_EPROM_CMD_MASK ((1 << 7) | (1 << 6)) 151 #define URTW_EPROM_READBIT (0x1) 152 #define URTW_EPROM_WRITEBIT (0x2) 153 #define URTW_EPROM_CK (0x4) 154 #define URTW_EPROM_CS (0x8) 155 156 #define URTW_CONFIG1 0x0052 /* 1 byte */ 157 #define URTW_CONFIG2 0x0053 /* 1 byte */ 158 159 #define URTW_ANAPARAM 0x0054 /* 4 byte */ 160 #define URTW_8187_8225_ANAPARAM_ON (0xa0000a59) 161 #define URTW_8187B_8225_ANAPARAM_ON (0x45090658) 162 163 #define URTW_MSR 0x0058 /* 1 byte */ 164 #define URTW_MSR_LINK_MASK ((1 << 2) | (1 << 3)) 165 #define URTW_MSR_LINK_SHIFT (2) 166 #define URTW_MSR_LINK_NONE (0 << URTW_MSR_LINK_SHIFT) 167 #define URTW_MSR_LINK_ADHOC (1 << URTW_MSR_LINK_SHIFT) 168 #define URTW_MSR_LINK_STA (2 << URTW_MSR_LINK_SHIFT) 169 #define URTW_MSR_LINK_HOSTAP (3 << URTW_MSR_LINK_SHIFT) 170 #define URTW_MSR_LINK_ENEDCA (4 << URTW_MSR_LINK_SHIFT) 171 172 173 #define URTW_CONFIG3 0x0059 /* 1 byte */ 174 #define URTW_CONFIG3_ANAPARAM_WRITE (0x40) 175 #define URTW_CONFIG3_ANAPARAM_W_SHIFT (6) 176 #define URTW_CONFIG3_GNT_SELECT (0x80) 177 178 #define URTW_PSR 0x005e /* 1 byte */ 179 #define URTW_ANAPARAM2 0x0060 /* 4 byte */ 180 #define URTW_8187_8225_ANAPARAM2_ON (0x860c7312) 181 #define URTW_8187B_8225_ANAPARAM2_ON (0x727f3f52) 182 183 #define URTW_BEACON_INTERVAL 0x0070 /* 2 byte */ 184 #define URTW_ATIM_WND 0x0072 /* 2 byte */ 185 #define URTW_BEACON_INTERVAL_TIME 0x0074 /* 2 byte */ 186 #define URTW_ATIM_TR_ITV 0x0076 /* 2 byte */ 187 #define URTW_RF_PINS_OUTPUT 0x0080 /* 2 byte */ 188 #define URTW_BB_HOST_BANG_CLK (1 << 1) 189 #define URTW_BB_HOST_BANG_EN (1 << 2) 190 #define URTW_BB_HOST_BANG_RW (1 << 3) 191 #define URTW_RF_PINS_ENABLE 0x0082 /* 2 byte */ 192 #define URTW_RF_PINS_SELECT 0x0084 /* 2 byte */ 193 #define URTW_RF_PINS_INPUT 0x0086 /* 2 byte */ 194 #define URTW_RF_PARA 0x0088 /* 4 byte */ 195 #define URTW_RF_TIMING 0x008c /* 4 byte */ 196 #define URTW_GP_ENABLE 0x0090 /* 1 byte */ 197 #define URTW_GPIO 0x0091 /* 1 byte */ 198 #define URTW_HSSI_PARA 0x0094 199 200 #define URTW_TX_AGC_CTL 0x009c /* 1 byte */ 201 #define URTW_TX_AGC_CTL_PERPACKET_GAIN (0x1) 202 #define URTW_TX_AGC_CTL_PERPACKET_ANTSEL (0x2) 203 #define URTW_TX_AGC_CTL_FEEDBACK_ANT (0x4) 204 #define URTW_TX_GAIN_CCK 0x009d /* 1 byte */ 205 #define URTW_TX_GAIN_OFDM 0x009e /* 1 byte */ 206 #define URTW_TX_ANTENNA 0x009f /* 1 byte */ 207 #define URTW_WPA_CONFIG 0x00b0 /* 1 byte */ 208 #define URTW_SIFS 0x00b4 /* 1 byte */ 209 #define URTW_DIFS 0x00b5 /* 1 byte */ 210 #define URTW_SLOT 0x00b6 /* 1 byte */ 211 #define URTW_CW_CONF 0x00bc /* 1 byte */ 212 #define URTW_CW_CONF_PERPACKET_RETRY (0x2) 213 #define URTW_CW_CONF_PERPACKET_CW (0x1) 214 #define URTW_CW_VAL 0x00bd /* 1 byte */ 215 #define URTW_RATE_FALLBACK 0x00be /* 1 byte */ 216 217 #define URTW_RATE_FALLBACK_ENABLE (0x80) 218 #define URTW_ACM_CONTROL 0x00bf /* 1 byte */ 219 #define URTW_8187B_HWREV 0x00e1 /* 1 byte */ 220 #define URTW_8187B_HWREV_8187B_B (0x0) 221 #define URTW_8187B_HWREV_8187B_D (0x1) 222 #define URTW_8187B_HWREV_8187B_E (0x2) 223 #define URTW_INT_MIG 0x00e2 /* 2 byte */ 224 #define URTW_TID_AC_MAP 0x00e8 /* 2 byte */ 225 #define URTW_ANAPARAM3 0x00ee /* 4 byte */ 226 #define URTW_8187B_8225_ANAPARAM3_ON (0x0) 227 #define URTW_TALLY_SEL 0x00fc /* 1 byte */ 228 #define URTW_AC_VO 0x00f0 /* 1 byte */ 229 #define URTW_AC_VI 0x00f4 /* 1 byte */ 230 #define URTW_AC_BE 0x00f8 /* 1 byte */ 231 #define URTW_AC_BK 0x00fc /* 1 byte */ 232 #define URTW_FEMR 0x01d4 /* 2 byte */ 233 #define URTW_ARFR 0x01e0 /* 2 byte */ 234 #define URTW_RFSW_CTRL 0x0272 /* 2 byte */ 235 236 /* for EEPROM */ 237 #define URTW_EPROM_TXPW_BASE 0x05 238 #define URTW_EPROM_RFCHIPID 0x06 239 #define URTW_EPROM_RFCHIPID_RTL8225U (5) 240 #define URTW_EPROM_MACADDR 0x07 241 #define URTW_EPROM_TXPW0 0x16 242 #define URTW_EPROM_TXPW2 0x1b 243 #define URTW_EPROM_TXPW1 0x3d 244 #define URTW_EPROM_SWREV 0x3f 245 #define URTW_EPROM_CID_MASK (0xff) 246 #define URTW_EPROM_CID_RSVD0 (0x00) 247 #define URTW_EPROM_CID_RSVD1 (0xff) 248 #define URTW_EPROM_CID_ALPHA0 (0x01) 249 #define URTW_EPROM_CID_SERCOMM_PS (0x02) 250 #define URTW_EPROM_CID_HW_LED (0x03) 251 252 /* LED */ 253 #define URTW_CID_DEFAULT 0 254 #define URTW_CID_8187_ALPHA0 1 255 #define URTW_CID_8187_SERCOMM_PS 2 256 #define URTW_CID_8187_HW_LED 3 257 #define URTW_SW_LED_MODE0 0 258 #define URTW_SW_LED_MODE1 1 259 #define URTW_SW_LED_MODE2 2 260 #define URTW_SW_LED_MODE3 3 261 #define URTW_HW_LED 4 262 #define URTW_LED_CTL_POWER_ON 0 263 #define URTW_LED_CTL_LINK 2 264 #define URTW_LED_CTL_TX 4 265 #define URTW_LED_PIN_GPIO0 0 266 #define URTW_LED_PIN_LED0 1 267 #define URTW_LED_PIN_LED1 2 268 #define URTW_LED_UNKNOWN 0 269 #define URTW_LED_ON 1 270 #define URTW_LED_OFF 2 271 #define URTW_LED_BLINK_NORMAL 3 272 #define URTW_LED_BLINK_SLOWLY 4 273 #define URTW_LED_POWER_ON_BLINK 5 274 #define URTW_LED_SCAN_BLINK 6 275 #define URTW_LED_NO_LINK_BLINK 7 276 #define URTW_LED_BLINK_CM3 8 277 278 /* for extra area */ 279 #define URTW_EPROM_DISABLE 0 280 #define URTW_EPROM_ENABLE 1 281 #define URTW_EPROM_DELAY 10 282 #define URTW_8187_GETREGS_REQ 5 283 #define URTW_8187_SETREGS_REQ 5 284 #define URTW_8225_RF_MAX_SENS 6 285 #define URTW_8225_RF_DEF_SENS 4 286 #define URTW_DEFAULT_RTS_RETRY 7 287 #define URTW_DEFAULT_TX_RETRY 7 288 #define URTW_DEFAULT_RTS_THRESHOLD 2342U 289 290 #ifdef __cplusplus 291 } 292 #endif 293 294 #endif /* _URTW_REG_H */ 295