1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 /* 26 * Common x86 and SPARC PCI-E to PCI bus bridge nexus driver 27 */ 28 29 #include <sys/sysmacros.h> 30 #include <sys/conf.h> 31 #include <sys/kmem.h> 32 #include <sys/debug.h> 33 #include <sys/modctl.h> 34 #include <sys/autoconf.h> 35 #include <sys/ddi_impldefs.h> 36 #include <sys/pci.h> 37 #include <sys/ddi.h> 38 #include <sys/sunddi.h> 39 #include <sys/sunndi.h> 40 #include <sys/fm/util.h> 41 #include <sys/pci_cap.h> 42 #include <sys/pci_impl.h> 43 #include <sys/pcie_impl.h> 44 #include <sys/open.h> 45 #include <sys/stat.h> 46 #include <sys/file.h> 47 #include <sys/promif.h> /* prom_printf */ 48 #include <sys/disp.h> 49 #include <sys/pcie_pwr.h> 50 #include <sys/hotplug/pci/pcie_hp.h> 51 #include "pcieb.h" 52 #ifdef PX_PLX 53 #include <io/pciex/pcieb_plx.h> 54 #endif /* PX_PLX */ 55 56 /*LINTLIBRARY*/ 57 58 /* panic flag */ 59 int pcieb_die = PF_ERR_FATAL_FLAGS; 60 int pcieb_disable_41210_wkarnd = 0; 61 62 /* flag to turn on MSI support */ 63 int pcieb_enable_msi = 1; 64 65 #if defined(DEBUG) 66 uint_t pcieb_dbg_print = 0; 67 68 static char *pcieb_debug_sym [] = { /* same sequence as pcieb_debug_bit */ 69 /* 0 */ "attach", 70 /* 1 */ "pwr", 71 /* 2 */ "intr" 72 }; 73 #endif /* DEBUG */ 74 75 static int pcieb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *, off_t, 76 off_t, caddr_t *); 77 static int pcieb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t, void *, 78 void *); 79 static int pcieb_fm_init(pcieb_devstate_t *pcieb_p); 80 static void pcieb_fm_fini(pcieb_devstate_t *pcieb_p); 81 static int pcieb_fm_init_child(dev_info_t *dip, dev_info_t *cdip, int cap, 82 ddi_iblock_cookie_t *ibc_p); 83 static int pcieb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, 84 ddi_dma_attr_t *attr_p, int (*waitfp)(caddr_t), caddr_t arg, 85 ddi_dma_handle_t *handlep); 86 static int pcieb_dma_mctl(dev_info_t *dip, dev_info_t *rdip, 87 ddi_dma_handle_t handle, enum ddi_dma_ctlops cmd, off_t *offp, 88 size_t *lenp, caddr_t *objp, uint_t cache_flags); 89 static int pcieb_intr_ops(dev_info_t *dip, dev_info_t *rdip, 90 ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 91 92 static struct bus_ops pcieb_bus_ops = { 93 BUSO_REV, 94 pcieb_bus_map, 95 0, 96 0, 97 0, 98 i_ddi_map_fault, 99 ddi_dma_map, 100 pcieb_dma_allochdl, 101 ddi_dma_freehdl, 102 ddi_dma_bindhdl, 103 ddi_dma_unbindhdl, 104 ddi_dma_flush, 105 ddi_dma_win, 106 pcieb_dma_mctl, 107 pcieb_ctlops, 108 ddi_bus_prop_op, 109 ndi_busop_get_eventcookie, /* (*bus_get_eventcookie)(); */ 110 ndi_busop_add_eventcall, /* (*bus_add_eventcall)(); */ 111 ndi_busop_remove_eventcall, /* (*bus_remove_eventcall)(); */ 112 ndi_post_event, /* (*bus_post_event)(); */ 113 NULL, /* (*bus_intr_ctl)(); */ 114 NULL, /* (*bus_config)(); */ 115 NULL, /* (*bus_unconfig)(); */ 116 pcieb_fm_init_child, /* (*bus_fm_init)(); */ 117 NULL, /* (*bus_fm_fini)(); */ 118 i_ndi_busop_access_enter, /* (*bus_fm_access_enter)(); */ 119 i_ndi_busop_access_exit, /* (*bus_fm_access_exit)(); */ 120 pcie_bus_power, /* (*bus_power)(); */ 121 pcieb_intr_ops, /* (*bus_intr_op)(); */ 122 pcie_hp_common_ops /* (*bus_hp_op)(); */ 123 }; 124 125 static int pcieb_open(dev_t *, int, int, cred_t *); 126 static int pcieb_close(dev_t, int, int, cred_t *); 127 static int pcieb_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 128 static int pcieb_info(dev_info_t *, ddi_info_cmd_t, void *, void **); 129 static uint_t pcieb_intr_handler(caddr_t arg1, caddr_t arg2); 130 131 /* PM related functions */ 132 static int pcieb_pwr_setup(dev_info_t *dip); 133 static int pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p); 134 static void pcieb_pwr_teardown(dev_info_t *dip); 135 static int pcieb_pwr_disable(dev_info_t *dip); 136 137 /* Hotplug related functions */ 138 static void pcieb_id_props(pcieb_devstate_t *pcieb); 139 140 /* 141 * soft state pointer 142 */ 143 void *pcieb_state; 144 145 static struct cb_ops pcieb_cb_ops = { 146 pcieb_open, /* open */ 147 pcieb_close, /* close */ 148 nodev, /* strategy */ 149 nodev, /* print */ 150 nodev, /* dump */ 151 nodev, /* read */ 152 nodev, /* write */ 153 pcieb_ioctl, /* ioctl */ 154 nodev, /* devmap */ 155 nodev, /* mmap */ 156 nodev, /* segmap */ 157 nochpoll, /* poll */ 158 pcie_prop_op, /* cb_prop_op */ 159 NULL, /* streamtab */ 160 D_NEW | D_MP | D_HOTPLUG, /* Driver compatibility flag */ 161 CB_REV, /* rev */ 162 nodev, /* int (*cb_aread)() */ 163 nodev /* int (*cb_awrite)() */ 164 }; 165 166 static int pcieb_probe(dev_info_t *); 167 static int pcieb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd); 168 static int pcieb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 169 170 static struct dev_ops pcieb_ops = { 171 DEVO_REV, /* devo_rev */ 172 0, /* refcnt */ 173 pcieb_info, /* info */ 174 nulldev, /* identify */ 175 pcieb_probe, /* probe */ 176 pcieb_attach, /* attach */ 177 pcieb_detach, /* detach */ 178 nulldev, /* reset */ 179 &pcieb_cb_ops, /* driver operations */ 180 &pcieb_bus_ops, /* bus operations */ 181 pcie_power, /* power */ 182 ddi_quiesce_not_needed, /* quiesce */ 183 }; 184 185 /* 186 * Module linkage information for the kernel. 187 */ 188 189 static struct modldrv modldrv = { 190 &mod_driverops, /* Type of module */ 191 "PCIe bridge/switch driver", 192 &pcieb_ops, /* driver ops */ 193 }; 194 195 static struct modlinkage modlinkage = { 196 MODREV_1, 197 (void *)&modldrv, 198 NULL 199 }; 200 201 /* 202 * forward function declarations: 203 */ 204 static void pcieb_uninitchild(dev_info_t *); 205 static int pcieb_initchild(dev_info_t *child); 206 static void pcieb_create_ranges_prop(dev_info_t *, ddi_acc_handle_t); 207 static boolean_t pcieb_is_pcie_device_type(dev_info_t *dip); 208 209 /* interrupt related declarations */ 210 static int pcieb_msi_supported(dev_info_t *); 211 static int pcieb_intr_attach(pcieb_devstate_t *pcieb); 212 static int pcieb_intr_init(pcieb_devstate_t *pcieb_p, int intr_type); 213 static void pcieb_intr_fini(pcieb_devstate_t *pcieb_p); 214 215 int 216 _init(void) 217 { 218 int e; 219 220 if ((e = ddi_soft_state_init(&pcieb_state, sizeof (pcieb_devstate_t), 221 1)) == 0 && (e = mod_install(&modlinkage)) != 0) 222 ddi_soft_state_fini(&pcieb_state); 223 return (e); 224 } 225 226 int 227 _fini(void) 228 { 229 int e; 230 231 if ((e = mod_remove(&modlinkage)) == 0) { 232 ddi_soft_state_fini(&pcieb_state); 233 } 234 return (e); 235 } 236 237 int 238 _info(struct modinfo *modinfop) 239 { 240 return (mod_info(&modlinkage, modinfop)); 241 } 242 243 /* ARGSUSED */ 244 static int 245 pcieb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 246 { 247 minor_t minor = getminor((dev_t)arg); 248 int instance = PCI_MINOR_NUM_TO_INSTANCE(minor); 249 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, instance); 250 int ret = DDI_SUCCESS; 251 252 switch (infocmd) { 253 case DDI_INFO_DEVT2INSTANCE: 254 *result = (void *)(intptr_t)instance; 255 break; 256 case DDI_INFO_DEVT2DEVINFO: 257 if (pcieb == NULL) { 258 ret = DDI_FAILURE; 259 break; 260 } 261 262 *result = (void *)pcieb->pcieb_dip; 263 break; 264 default: 265 ret = DDI_FAILURE; 266 break; 267 } 268 269 return (ret); 270 } 271 272 273 /*ARGSUSED*/ 274 static int 275 pcieb_probe(dev_info_t *devi) 276 { 277 return (DDI_PROBE_SUCCESS); 278 } 279 280 /* 281 * This is a workaround for an undocumented HW erratum with the 282 * multi-function, F0 and F2, Intel 41210 PCIe-to-PCI bridge. When 283 * Fn (cdip) attaches, this workaround is called to initialize Fn's 284 * sibling (sdip) with MPS/MRRS if it isn't already configured. 285 * Doing so prevents a malformed TLP panic. 286 */ 287 static void 288 pcieb_41210_mps_wkrnd(dev_info_t *cdip) 289 { 290 dev_info_t *sdip; 291 ddi_acc_handle_t cfg_hdl; 292 uint16_t cdip_dev_ctrl, cdip_mrrs_mps; 293 pcie_bus_t *cdip_bus_p = PCIE_DIP2BUS(cdip); 294 295 /* Get cdip's MPS/MRRS already setup by pcie_initchild_mps() */ 296 ASSERT(cdip_bus_p); 297 cdip_dev_ctrl = PCIE_CAP_GET(16, cdip_bus_p, PCIE_DEVCTL); 298 cdip_mrrs_mps = cdip_dev_ctrl & 299 (PCIE_DEVCTL_MAX_READ_REQ_MASK | PCIE_DEVCTL_MAX_PAYLOAD_MASK); 300 301 /* Locate sdip and set its MPS/MRRS when applicable */ 302 for (sdip = ddi_get_child(ddi_get_parent(cdip)); sdip; 303 sdip = ddi_get_next_sibling(sdip)) { 304 uint16_t sdip_dev_ctrl, sdip_mrrs_mps, cap_ptr; 305 uint32_t bus_dev_ven_id; 306 307 if (sdip == cdip || pci_config_setup(sdip, &cfg_hdl) 308 != DDI_SUCCESS) 309 continue; 310 311 /* must be an Intel 41210 bridge */ 312 bus_dev_ven_id = pci_config_get32(cfg_hdl, PCI_CONF_VENID); 313 if (!PCIEB_IS_41210_BRIDGE(bus_dev_ven_id)) { 314 pci_config_teardown(&cfg_hdl); 315 continue; 316 } 317 318 if (PCI_CAP_LOCATE(cfg_hdl, PCI_CAP_ID_PCI_E, &cap_ptr) 319 != DDI_SUCCESS) { 320 pci_config_teardown(&cfg_hdl); 321 continue; 322 } 323 324 /* get sdip's MPS/MRRS to compare to cdip's */ 325 sdip_dev_ctrl = PCI_CAP_GET16(cfg_hdl, NULL, cap_ptr, 326 PCIE_DEVCTL); 327 sdip_mrrs_mps = sdip_dev_ctrl & 328 (PCIE_DEVCTL_MAX_READ_REQ_MASK | 329 PCIE_DEVCTL_MAX_PAYLOAD_MASK); 330 331 /* if sdip already attached then its MPS/MRRS is configured */ 332 if (i_ddi_devi_attached(sdip)) { 333 ASSERT(sdip_mrrs_mps == cdip_mrrs_mps); 334 pci_config_teardown(&cfg_hdl); 335 continue; 336 } 337 338 /* otherwise, update sdip's MPS/MRRS if different from cdip's */ 339 if (sdip_mrrs_mps != cdip_mrrs_mps) { 340 sdip_dev_ctrl = (sdip_dev_ctrl & 341 ~(PCIE_DEVCTL_MAX_READ_REQ_MASK | 342 PCIE_DEVCTL_MAX_PAYLOAD_MASK)) | cdip_mrrs_mps; 343 344 PCI_CAP_PUT16(cfg_hdl, NULL, cap_ptr, PCIE_DEVCTL, 345 sdip_dev_ctrl); 346 } 347 348 /* 349 * note: sdip's bus_mps will be updated by 350 * pcie_initchild_mps() 351 */ 352 353 pci_config_teardown(&cfg_hdl); 354 355 break; 356 } 357 } 358 359 static int 360 pcieb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd) 361 { 362 int instance; 363 char device_type[8]; 364 pcieb_devstate_t *pcieb; 365 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(devi); 366 ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl; 367 368 switch (cmd) { 369 case DDI_RESUME: 370 (void) pcie_pwr_resume(devi); 371 return (DDI_SUCCESS); 372 373 default: 374 return (DDI_FAILURE); 375 376 case DDI_ATTACH: 377 break; 378 } 379 380 if (!(PCIE_IS_BDG(bus_p))) { 381 PCIEB_DEBUG(DBG_ATTACH, devi, "This is not a switch or" 382 " bridge\n"); 383 return (DDI_FAILURE); 384 } 385 386 /* 387 * If PCIE_LINKCTL_LINK_DISABLE bit in the PCIe Config 388 * Space (PCIe Capability Link Control Register) is set, 389 * then do not bind the driver. 390 */ 391 if (PCIE_CAP_GET(16, bus_p, PCIE_LINKCTL) & PCIE_LINKCTL_LINK_DISABLE) 392 return (DDI_FAILURE); 393 394 /* 395 * Allocate and get soft state structure. 396 */ 397 instance = ddi_get_instance(devi); 398 if (ddi_soft_state_zalloc(pcieb_state, instance) != DDI_SUCCESS) 399 return (DDI_FAILURE); 400 pcieb = ddi_get_soft_state(pcieb_state, instance); 401 pcieb->pcieb_dip = devi; 402 403 if ((pcieb_fm_init(pcieb)) != DDI_SUCCESS) { 404 PCIEB_DEBUG(DBG_ATTACH, devi, "Failed in pcieb_fm_init\n"); 405 goto fail; 406 } 407 pcieb->pcieb_init_flags |= PCIEB_INIT_FM; 408 409 mutex_init(&pcieb->pcieb_mutex, NULL, MUTEX_DRIVER, NULL); 410 mutex_init(&pcieb->pcieb_err_mutex, NULL, MUTEX_DRIVER, 411 (void *)pcieb->pcieb_fm_ibc); 412 mutex_init(&pcieb->pcieb_peek_poke_mutex, NULL, MUTEX_DRIVER, 413 (void *)pcieb->pcieb_fm_ibc); 414 415 /* create special properties for device identification */ 416 pcieb_id_props(pcieb); 417 418 /* 419 * Power management setup. This also makes sure that switch/bridge 420 * is at D0 during attach. 421 */ 422 if (pwr_common_setup(devi) != DDI_SUCCESS) { 423 PCIEB_DEBUG(DBG_PWR, devi, "pwr_common_setup failed\n"); 424 goto fail; 425 } 426 427 if (pcieb_pwr_setup(devi) != DDI_SUCCESS) { 428 PCIEB_DEBUG(DBG_PWR, devi, "pxb_pwr_setup failed \n"); 429 goto fail; 430 } 431 432 /* 433 * Make sure the "device_type" property exists. 434 */ 435 if (pcieb_is_pcie_device_type(devi)) 436 (void) strcpy(device_type, "pciex"); 437 else 438 (void) strcpy(device_type, "pci"); 439 440 (void) ddi_prop_update_string(DDI_DEV_T_NONE, devi, 441 "device_type", device_type); 442 443 /* 444 * Check whether the "ranges" property is present. 445 * Otherwise create the ranges property by reading 446 * the configuration registers 447 */ 448 if (ddi_prop_exists(DDI_DEV_T_ANY, devi, DDI_PROP_DONTPASS, 449 "ranges") == 0) { 450 pcieb_create_ranges_prop(devi, config_handle); 451 } 452 453 if (PCIE_IS_PCI_BDG(bus_p)) 454 pcieb_set_pci_perf_parameters(devi, config_handle); 455 456 #ifdef PX_PLX 457 pcieb_attach_plx_workarounds(pcieb); 458 #endif /* PX_PLX */ 459 460 if (pcie_init(devi, NULL) != DDI_SUCCESS) 461 goto fail; 462 463 /* Intel PCIe-to-PCI 41210 bridge workaround -- if applicable */ 464 if (pcieb_disable_41210_wkarnd == 0 && 465 PCIEB_IS_41210_BRIDGE(bus_p->bus_dev_ven_id)) 466 pcieb_41210_mps_wkrnd(devi); 467 468 /* 469 * Initialize interrupt handlers. Ignore return value. 470 */ 471 (void) pcieb_intr_attach(pcieb); 472 473 (void) pcie_hpintr_enable(devi); 474 475 /* Do any platform specific workarounds needed at this time */ 476 pcieb_plat_attach_workaround(devi); 477 478 /* 479 * If this is a root port, determine and set the max payload size. 480 * Since this will involve scanning the fabric, all error enabling 481 * and sw workarounds should be in place before doing this. 482 */ 483 if (PCIE_IS_RP(bus_p)) 484 pcie_init_root_port_mps(devi); 485 486 ddi_report_dev(devi); 487 return (DDI_SUCCESS); 488 489 fail: 490 (void) pcieb_detach(devi, DDI_DETACH); 491 return (DDI_FAILURE); 492 } 493 494 static int 495 pcieb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 496 { 497 pcieb_devstate_t *pcieb; 498 int error = DDI_SUCCESS; 499 500 switch (cmd) { 501 case DDI_SUSPEND: 502 error = pcie_pwr_suspend(devi); 503 return (error); 504 505 case DDI_DETACH: 506 break; 507 508 default: 509 return (DDI_FAILURE); 510 } 511 512 pcieb = ddi_get_soft_state(pcieb_state, ddi_get_instance(devi)); 513 514 /* disable hotplug interrupt */ 515 (void) pcie_hpintr_disable(devi); 516 517 /* remove interrupt handlers */ 518 pcieb_intr_fini(pcieb); 519 520 /* uninitialize inband PCI-E HPC if present */ 521 (void) pcie_uninit(devi); 522 523 (void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type"); 524 525 (void) ndi_prop_remove(DDI_DEV_T_NONE, pcieb->pcieb_dip, 526 "pcie_ce_mask"); 527 528 if (pcieb->pcieb_init_flags & PCIEB_INIT_FM) 529 pcieb_fm_fini(pcieb); 530 531 pcieb_pwr_teardown(devi); 532 pwr_common_teardown(devi); 533 534 mutex_destroy(&pcieb->pcieb_peek_poke_mutex); 535 mutex_destroy(&pcieb->pcieb_err_mutex); 536 mutex_destroy(&pcieb->pcieb_mutex); 537 538 /* 539 * And finally free the per-pci soft state. 540 */ 541 ddi_soft_state_free(pcieb_state, ddi_get_instance(devi)); 542 543 return (DDI_SUCCESS); 544 } 545 546 static int 547 pcieb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 548 off_t offset, off_t len, caddr_t *vaddrp) 549 { 550 dev_info_t *pdip; 551 552 if (PCIE_IS_RP(PCIE_DIP2BUS(dip)) && mp->map_handlep != NULL) { 553 ddi_acc_impl_t *hdlp = 554 (ddi_acc_impl_t *)(mp->map_handlep)->ah_platform_private; 555 556 pcieb_set_prot_scan(dip, hdlp); 557 } 558 pdip = (dev_info_t *)DEVI(dip)->devi_parent; 559 return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map)(pdip, rdip, mp, 560 offset, len, vaddrp)); 561 } 562 563 static int 564 pcieb_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t ctlop, 565 void *arg, void *result) 566 { 567 pci_regspec_t *drv_regp; 568 int reglen; 569 int rn; 570 int totreg; 571 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, 572 ddi_get_instance(dip)); 573 struct detachspec *ds; 574 struct attachspec *as; 575 576 switch (ctlop) { 577 case DDI_CTLOPS_REPORTDEV: 578 if (rdip == (dev_info_t *)0) 579 return (DDI_FAILURE); 580 581 if (ddi_get_parent(rdip) == dip) { 582 cmn_err(CE_CONT, "?PCIE-device: %s@%s, %s%d\n", 583 ddi_node_name(rdip), ddi_get_name_addr(rdip), 584 ddi_driver_name(rdip), ddi_get_instance(rdip)); 585 } 586 587 /* Pass it up for fabric sync */ 588 (void) ddi_ctlops(dip, rdip, ctlop, arg, result); 589 return (DDI_SUCCESS); 590 591 case DDI_CTLOPS_INITCHILD: 592 return (pcieb_initchild((dev_info_t *)arg)); 593 594 case DDI_CTLOPS_UNINITCHILD: 595 pcieb_uninitchild((dev_info_t *)arg); 596 return (DDI_SUCCESS); 597 598 case DDI_CTLOPS_SIDDEV: 599 return (DDI_SUCCESS); 600 601 case DDI_CTLOPS_REGSIZE: 602 case DDI_CTLOPS_NREGS: 603 if (rdip == (dev_info_t *)0) 604 return (DDI_FAILURE); 605 break; 606 607 case DDI_CTLOPS_PEEK: 608 case DDI_CTLOPS_POKE: 609 return (pcieb_plat_peekpoke(dip, rdip, ctlop, arg, result)); 610 case DDI_CTLOPS_ATTACH: 611 if (!pcie_is_child(dip, rdip)) 612 return (DDI_SUCCESS); 613 614 as = (struct attachspec *)arg; 615 switch (as->when) { 616 case DDI_PRE: 617 if (as->cmd == DDI_RESUME) { 618 pcie_clear_errors(rdip); 619 if (pcieb_plat_ctlops(rdip, ctlop, arg) != 620 DDI_SUCCESS) 621 return (DDI_FAILURE); 622 } 623 624 if (as->cmd == DDI_ATTACH) 625 return (pcie_pm_hold(dip)); 626 627 return (DDI_SUCCESS); 628 629 case DDI_POST: 630 if (as->cmd == DDI_ATTACH && 631 as->result != DDI_SUCCESS) { 632 /* 633 * Attach failed for the child device. The child 634 * driver may have made PM calls before the 635 * attach failed. pcie_pm_remove_child() should 636 * cleanup PM state and holds (if any) 637 * associated with the child device. 638 */ 639 return (pcie_pm_remove_child(dip, rdip)); 640 } 641 642 if (as->result == DDI_SUCCESS) { 643 pf_init(rdip, (void *)pcieb->pcieb_fm_ibc, 644 as->cmd); 645 646 (void) pcieb_plat_ctlops(rdip, ctlop, arg); 647 } 648 649 /* 650 * For empty hotplug-capable slots, we should explicitly 651 * disable the errors, so that we won't panic upon 652 * unsupported hotplug messages. 653 */ 654 if ((!ddi_prop_exists(DDI_DEV_T_ANY, rdip, 655 DDI_PROP_DONTPASS, "hotplug-capable")) || 656 ddi_get_child(rdip)) { 657 (void) pcie_postattach_child(rdip); 658 return (DDI_SUCCESS); 659 } 660 661 pcie_disable_errors(rdip); 662 663 return (DDI_SUCCESS); 664 default: 665 break; 666 } 667 return (DDI_SUCCESS); 668 669 case DDI_CTLOPS_DETACH: 670 if (!pcie_is_child(dip, rdip)) 671 return (DDI_SUCCESS); 672 673 ds = (struct detachspec *)arg; 674 switch (ds->when) { 675 case DDI_PRE: 676 pf_fini(rdip, ds->cmd); 677 return (DDI_SUCCESS); 678 679 case DDI_POST: 680 if (pcieb_plat_ctlops(rdip, ctlop, arg) != DDI_SUCCESS) 681 return (DDI_FAILURE); 682 if (ds->cmd == DDI_DETACH && 683 ds->result == DDI_SUCCESS) { 684 return (pcie_pm_remove_child(dip, rdip)); 685 } 686 return (DDI_SUCCESS); 687 default: 688 break; 689 } 690 return (DDI_SUCCESS); 691 default: 692 return (ddi_ctlops(dip, rdip, ctlop, arg, result)); 693 } 694 695 *(int *)result = 0; 696 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, 697 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg", (caddr_t)&drv_regp, 698 ®len) != DDI_SUCCESS) 699 return (DDI_FAILURE); 700 701 totreg = reglen / sizeof (pci_regspec_t); 702 if (ctlop == DDI_CTLOPS_NREGS) 703 *(int *)result = totreg; 704 else if (ctlop == DDI_CTLOPS_REGSIZE) { 705 rn = *(int *)arg; 706 if (rn >= totreg) { 707 kmem_free(drv_regp, reglen); 708 return (DDI_FAILURE); 709 } 710 711 *(off_t *)result = drv_regp[rn].pci_size_low | 712 ((uint64_t)drv_regp[rn].pci_size_hi << 32); 713 } 714 715 kmem_free(drv_regp, reglen); 716 return (DDI_SUCCESS); 717 } 718 719 /* 720 * name_child 721 * 722 * This function is called from init_child to name a node. It is 723 * also passed as a callback for node merging functions. 724 * 725 * return value: DDI_SUCCESS, DDI_FAILURE 726 */ 727 static int 728 pcieb_name_child(dev_info_t *child, char *name, int namelen) 729 { 730 pci_regspec_t *pci_rp; 731 uint_t device, func; 732 char **unit_addr; 733 uint_t n; 734 735 /* 736 * For .conf nodes, use unit-address property as name 737 */ 738 if (ndi_dev_is_persistent_node(child) == 0) { 739 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child, 740 DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) != 741 DDI_PROP_SUCCESS) { 742 cmn_err(CE_WARN, 743 "cannot find unit-address in %s.conf", 744 ddi_driver_name(child)); 745 return (DDI_FAILURE); 746 } 747 if (n != 1 || *unit_addr == NULL || **unit_addr == 0) { 748 cmn_err(CE_WARN, "unit-address property in %s.conf" 749 " not well-formed", ddi_driver_name(child)); 750 ddi_prop_free(unit_addr); 751 return (DDI_FAILURE); 752 } 753 (void) snprintf(name, namelen, "%s", *unit_addr); 754 ddi_prop_free(unit_addr); 755 return (DDI_SUCCESS); 756 } 757 758 /* 759 * Get the address portion of the node name based on 760 * the function and device number. 761 */ 762 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, 763 DDI_PROP_DONTPASS, "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) { 764 return (DDI_FAILURE); 765 } 766 767 /* copy the device identifications */ 768 device = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi); 769 func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi); 770 771 if (pcie_ari_is_enabled(ddi_get_parent(child)) 772 == PCIE_ARI_FORW_ENABLED) { 773 func = (device << 3) | func; 774 device = 0; 775 } 776 777 if (func != 0) 778 (void) snprintf(name, namelen, "%x,%x", device, func); 779 else 780 (void) snprintf(name, namelen, "%x", device); 781 782 ddi_prop_free(pci_rp); 783 return (DDI_SUCCESS); 784 } 785 786 static int 787 pcieb_initchild(dev_info_t *child) 788 { 789 char name[MAXNAMELEN]; 790 int result = DDI_FAILURE; 791 pcieb_devstate_t *pcieb = 792 (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state, 793 ddi_get_instance(ddi_get_parent(child))); 794 795 /* 796 * Name the child 797 */ 798 if (pcieb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS) { 799 result = DDI_FAILURE; 800 goto done; 801 } 802 ddi_set_name_addr(child, name); 803 804 /* 805 * Pseudo nodes indicate a prototype node with per-instance 806 * properties to be merged into the real h/w device node. 807 * The interpretation of the unit-address is DD[,F] 808 * where DD is the device id and F is the function. 809 */ 810 if (ndi_dev_is_persistent_node(child) == 0) { 811 extern int pci_allow_pseudo_children; 812 813 /* 814 * Try to merge the properties from this prototype 815 * node into real h/w nodes. 816 */ 817 if (ndi_merge_node(child, pcieb_name_child) == DDI_SUCCESS) { 818 /* 819 * Merged ok - return failure to remove the node. 820 */ 821 ddi_set_name_addr(child, NULL); 822 result = DDI_FAILURE; 823 goto done; 824 } 825 826 /* workaround for ddivs to run under PCI-E */ 827 if (pci_allow_pseudo_children) { 828 result = DDI_SUCCESS; 829 goto done; 830 } 831 832 /* 833 * The child was not merged into a h/w node, 834 * but there's not much we can do with it other 835 * than return failure to cause the node to be removed. 836 */ 837 cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged", 838 ddi_driver_name(child), ddi_get_name_addr(child), 839 ddi_driver_name(child)); 840 ddi_set_name_addr(child, NULL); 841 result = DDI_NOT_WELL_FORMED; 842 goto done; 843 } 844 845 /* platform specific initchild */ 846 pcieb_plat_initchild(child); 847 848 if (pcie_pm_hold(pcieb->pcieb_dip) != DDI_SUCCESS) { 849 PCIEB_DEBUG(DBG_PWR, pcieb->pcieb_dip, 850 "INITCHILD: px_pm_hold failed\n"); 851 result = DDI_FAILURE; 852 goto done; 853 } 854 /* Any return from here must call pcie_pm_release */ 855 856 /* 857 * If configuration registers were previously saved by 858 * child (before it entered D3), then let the child do the 859 * restore to set up the config regs as it'll first need to 860 * power the device out of D3. 861 */ 862 if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 863 "config-regs-saved-by-child") == 1) { 864 PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child), 865 "INITCHILD: config regs to be restored by child" 866 " for %s@%s\n", ddi_node_name(child), 867 ddi_get_name_addr(child)); 868 869 result = DDI_SUCCESS; 870 goto cleanup; 871 } 872 873 PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child), 874 "INITCHILD: config regs setup for %s@%s\n", 875 ddi_node_name(child), ddi_get_name_addr(child)); 876 877 pcie_init_dom(child); 878 879 if (pcie_initchild(child) != DDI_SUCCESS) { 880 result = DDI_FAILURE; 881 pcie_fini_dom(child); 882 goto cleanup; 883 } 884 885 #ifdef PX_PLX 886 if (pcieb_init_plx_workarounds(pcieb, child) == DDI_FAILURE) { 887 result = DDI_FAILURE; 888 pcie_fini_dom(child); 889 goto cleanup; 890 } 891 #endif /* PX_PLX */ 892 893 result = DDI_SUCCESS; 894 cleanup: 895 pcie_pm_release(pcieb->pcieb_dip); 896 done: 897 return (result); 898 } 899 900 static void 901 pcieb_uninitchild(dev_info_t *dip) 902 { 903 904 pcie_uninitchild(dip); 905 906 pcieb_plat_uninitchild(dip); 907 908 ddi_set_name_addr(dip, NULL); 909 910 /* 911 * Strip the node to properly convert it back to prototype form 912 */ 913 ddi_remove_minor_node(dip, NULL); 914 915 ddi_prop_remove_all(dip); 916 } 917 918 static boolean_t 919 pcieb_is_pcie_device_type(dev_info_t *dip) 920 { 921 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 922 923 if (PCIE_IS_SW(bus_p) || PCIE_IS_RP(bus_p) || PCIE_IS_PCI2PCIE(bus_p)) 924 return (B_TRUE); 925 926 return (B_FALSE); 927 } 928 929 static int 930 pcieb_intr_attach(pcieb_devstate_t *pcieb) 931 { 932 int intr_types; 933 dev_info_t *dip = pcieb->pcieb_dip; 934 935 /* Allow platform specific code to do any initialization first */ 936 pcieb_plat_intr_attach(pcieb); 937 938 /* 939 * Initialize interrupt handlers. 940 * If both MSI and FIXED are supported, try to attach MSI first. 941 * If MSI fails for any reason, then try FIXED, but only allow one 942 * type to be attached. 943 */ 944 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 945 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_supported_types" 946 " failed\n"); 947 goto FAIL; 948 } 949 950 if ((intr_types & DDI_INTR_TYPE_MSI) && 951 (pcieb_msi_supported(dip) == DDI_SUCCESS)) { 952 if (pcieb_intr_init(pcieb, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) 953 intr_types = DDI_INTR_TYPE_MSI; 954 else { 955 PCIEB_DEBUG(DBG_ATTACH, dip, "Unable to attach MSI" 956 " handler\n"); 957 } 958 } 959 960 if (intr_types != DDI_INTR_TYPE_MSI) { 961 /* 962 * MSIs are not supported or MSI initialization failed. For Root 963 * Ports mark this so error handling might try to fallback to 964 * some other mechanism if available (machinecheck etc.). 965 */ 966 if (PCIE_IS_RP(PCIE_DIP2UPBUS(dip))) 967 pcieb->pcieb_no_aer_msi = B_TRUE; 968 } 969 970 if (intr_types & DDI_INTR_TYPE_FIXED) { 971 if (pcieb_intr_init(pcieb, DDI_INTR_TYPE_FIXED) != 972 DDI_SUCCESS) { 973 PCIEB_DEBUG(DBG_ATTACH, dip, 974 "Unable to attach INTx handler\n"); 975 goto FAIL; 976 } 977 } 978 return (DDI_SUCCESS); 979 980 FAIL: 981 return (DDI_FAILURE); 982 } 983 984 /* 985 * This function initializes internally generated interrupts only. 986 * It does not affect any interrupts generated by downstream devices 987 * or the forwarding of them. 988 * 989 * Enable Device Specific Interrupts or Hotplug features here. 990 * Enabling features may change how many interrupts are requested 991 * by the device. If features are not enabled first, the 992 * device might not ask for any interrupts. 993 */ 994 995 static int 996 pcieb_intr_init(pcieb_devstate_t *pcieb, int intr_type) 997 { 998 dev_info_t *dip = pcieb->pcieb_dip; 999 int nintrs, request, count, x; 1000 int intr_cap = 0; 1001 int inum = 0; 1002 int ret, hp_msi_off; 1003 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip); 1004 uint16_t vendorid = bus_p->bus_dev_ven_id & 0xFFFF; 1005 boolean_t is_hp = B_FALSE; 1006 boolean_t is_pme = B_FALSE; 1007 1008 PCIEB_DEBUG(DBG_ATTACH, dip, "pcieb_intr_init: Attaching %s handler\n", 1009 (intr_type == DDI_INTR_TYPE_MSI) ? "MSI" : "INTx"); 1010 1011 request = 0; 1012 if (PCIE_IS_HOTPLUG_ENABLED(dip)) { 1013 request++; 1014 is_hp = B_TRUE; 1015 } 1016 1017 /* 1018 * Hotplug and PME share the same MSI vector. If hotplug is not 1019 * supported check if MSI is needed for PME. 1020 */ 1021 if ((intr_type == DDI_INTR_TYPE_MSI) && PCIE_IS_RP(bus_p) && 1022 (vendorid == NVIDIA_VENDOR_ID)) { 1023 is_pme = B_TRUE; 1024 if (!is_hp) 1025 request++; 1026 } 1027 1028 /* 1029 * Setup MSI if this device is a Rootport and has AER. Currently no 1030 * SPARC Root Port supports fabric errors being reported through it. 1031 */ 1032 if (intr_type == DDI_INTR_TYPE_MSI) { 1033 if (PCIE_IS_RP(bus_p) && PCIE_HAS_AER(bus_p)) 1034 request++; 1035 } 1036 1037 if (request == 0) 1038 return (DDI_SUCCESS); 1039 1040 /* 1041 * Get number of supported interrupts. 1042 * 1043 * Several Bridges/Switches will not have this property set, resulting 1044 * in a FAILURE, if the device is not configured in a way that 1045 * interrupts are needed. (eg. hotplugging) 1046 */ 1047 ret = ddi_intr_get_nintrs(dip, intr_type, &nintrs); 1048 if ((ret != DDI_SUCCESS) || (nintrs == 0)) { 1049 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_nintrs ret:%d" 1050 " req:%d\n", ret, nintrs); 1051 return (DDI_FAILURE); 1052 } 1053 1054 PCIEB_DEBUG(DBG_ATTACH, dip, "bdf 0x%x: ddi_intr_get_nintrs: nintrs %d", 1055 " request %d\n", bus_p->bus_bdf, nintrs, request); 1056 1057 if (request > nintrs) 1058 request = nintrs; 1059 1060 /* Allocate an array of interrupt handlers */ 1061 pcieb->pcieb_htable_size = sizeof (ddi_intr_handle_t) * request; 1062 pcieb->pcieb_htable = kmem_zalloc(pcieb->pcieb_htable_size, 1063 KM_SLEEP); 1064 pcieb->pcieb_init_flags |= PCIEB_INIT_HTABLE; 1065 1066 ret = ddi_intr_alloc(dip, pcieb->pcieb_htable, intr_type, inum, 1067 request, &count, DDI_INTR_ALLOC_NORMAL); 1068 if ((ret != DDI_SUCCESS) || (count == 0)) { 1069 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_alloc() ret: %d ask: %d" 1070 " actual: %d\n", ret, request, count); 1071 goto FAIL; 1072 } 1073 pcieb->pcieb_init_flags |= PCIEB_INIT_ALLOC; 1074 1075 /* Save the actual number of interrupts allocated */ 1076 pcieb->pcieb_intr_count = count; 1077 if (count < request) { 1078 PCIEB_DEBUG(DBG_ATTACH, dip, "bdf 0%x: Requested Intr: %d" 1079 " Received: %d\n", bus_p->bus_bdf, request, count); 1080 } 1081 1082 /* 1083 * NVidia (MCP55 and other) chipsets have a errata that if the number 1084 * of requested MSI intrs is not allocated we have to fall back to INTx. 1085 */ 1086 if (intr_type == DDI_INTR_TYPE_MSI) { 1087 if (PCIE_IS_RP(bus_p) && (vendorid == NVIDIA_VENDOR_ID)) { 1088 if (request != count) 1089 goto FAIL; 1090 } 1091 } 1092 1093 /* Get interrupt priority */ 1094 ret = ddi_intr_get_pri(pcieb->pcieb_htable[0], 1095 &pcieb->pcieb_intr_priority); 1096 if (ret != DDI_SUCCESS) { 1097 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_pri() ret: %d\n", 1098 ret); 1099 goto FAIL; 1100 } 1101 1102 if (pcieb->pcieb_intr_priority >= LOCK_LEVEL) { 1103 pcieb->pcieb_intr_priority = LOCK_LEVEL - 1; 1104 ret = ddi_intr_set_pri(pcieb->pcieb_htable[0], 1105 pcieb->pcieb_intr_priority); 1106 if (ret != DDI_SUCCESS) { 1107 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_set_pri() ret:" 1108 " %d\n", ret); 1109 1110 goto FAIL; 1111 } 1112 } 1113 1114 mutex_init(&pcieb->pcieb_intr_mutex, NULL, MUTEX_DRIVER, NULL); 1115 1116 pcieb->pcieb_init_flags |= PCIEB_INIT_MUTEX; 1117 1118 for (count = 0; count < pcieb->pcieb_intr_count; count++) { 1119 ret = ddi_intr_add_handler(pcieb->pcieb_htable[count], 1120 pcieb_intr_handler, (caddr_t)pcieb, 1121 (caddr_t)(uintptr_t)(inum + count)); 1122 1123 if (ret != DDI_SUCCESS) { 1124 PCIEB_DEBUG(DBG_ATTACH, dip, "Cannot add " 1125 "interrupt(%d)\n", ret); 1126 break; 1127 } 1128 } 1129 1130 /* If unsucessful, remove the added handlers */ 1131 if (ret != DDI_SUCCESS) { 1132 for (x = 0; x < count; x++) { 1133 (void) ddi_intr_remove_handler(pcieb->pcieb_htable[x]); 1134 } 1135 goto FAIL; 1136 } 1137 1138 pcieb->pcieb_init_flags |= PCIEB_INIT_HANDLER; 1139 1140 (void) ddi_intr_get_cap(pcieb->pcieb_htable[0], &intr_cap); 1141 1142 /* 1143 * Get this intr lock because we are not quite ready to handle 1144 * interrupts immediately after enabling it. The MSI multi register 1145 * gets programmed in ddi_intr_enable after which we need to get the 1146 * MSI offsets for Hotplug/AER. 1147 */ 1148 mutex_enter(&pcieb->pcieb_intr_mutex); 1149 1150 if (intr_cap & DDI_INTR_FLAG_BLOCK) { 1151 (void) ddi_intr_block_enable(pcieb->pcieb_htable, 1152 pcieb->pcieb_intr_count); 1153 pcieb->pcieb_init_flags |= PCIEB_INIT_BLOCK; 1154 } else { 1155 for (count = 0; count < pcieb->pcieb_intr_count; count++) { 1156 (void) ddi_intr_enable(pcieb->pcieb_htable[count]); 1157 } 1158 } 1159 pcieb->pcieb_init_flags |= PCIEB_INIT_ENABLE; 1160 1161 /* Save the interrupt type */ 1162 pcieb->pcieb_intr_type = intr_type; 1163 1164 /* Get the MSI offset for hotplug/PME from the PCIe cap reg */ 1165 if (intr_type == DDI_INTR_TYPE_MSI) { 1166 hp_msi_off = PCI_CAP_GET16(bus_p->bus_cfg_hdl, NULL, 1167 bus_p->bus_pcie_off, PCIE_PCIECAP) & 1168 PCIE_PCIECAP_INT_MSG_NUM; 1169 1170 if (hp_msi_off >= count) { 1171 PCIEB_DEBUG(DBG_ATTACH, dip, "MSI number %d in PCIe " 1172 "cap > max allocated %d\n", hp_msi_off, count); 1173 mutex_exit(&pcieb->pcieb_intr_mutex); 1174 goto FAIL; 1175 } 1176 1177 if (is_hp) 1178 pcieb->pcieb_isr_tab[hp_msi_off] |= PCIEB_INTR_SRC_HP; 1179 1180 if (is_pme) 1181 pcieb->pcieb_isr_tab[hp_msi_off] |= PCIEB_INTR_SRC_PME; 1182 } else { 1183 /* INTx handles only Hotplug interrupts */ 1184 if (is_hp) 1185 pcieb->pcieb_isr_tab[0] |= PCIEB_INTR_SRC_HP; 1186 } 1187 1188 1189 /* 1190 * Get the MSI offset for errors from the AER Root Error status 1191 * register. 1192 */ 1193 if ((intr_type == DDI_INTR_TYPE_MSI) && PCIE_IS_RP(bus_p)) { 1194 if (PCIE_HAS_AER(bus_p)) { 1195 int aer_msi_off; 1196 aer_msi_off = (PCI_XCAP_GET32(bus_p->bus_cfg_hdl, NULL, 1197 bus_p->bus_aer_off, PCIE_AER_RE_STS) >> 1198 PCIE_AER_RE_STS_MSG_NUM_SHIFT) & 1199 PCIE_AER_RE_STS_MSG_NUM_MASK; 1200 1201 if (aer_msi_off >= count) { 1202 PCIEB_DEBUG(DBG_ATTACH, dip, "MSI number %d in" 1203 " AER cap > max allocated %d\n", 1204 aer_msi_off, count); 1205 mutex_exit(&pcieb->pcieb_intr_mutex); 1206 goto FAIL; 1207 } 1208 pcieb->pcieb_isr_tab[aer_msi_off] |= PCIEB_INTR_SRC_AER; 1209 } else { 1210 /* 1211 * This RP does not have AER. Fallback to the 1212 * SERR+Machinecheck approach if available. 1213 */ 1214 pcieb->pcieb_no_aer_msi = B_TRUE; 1215 } 1216 } 1217 1218 mutex_exit(&pcieb->pcieb_intr_mutex); 1219 return (DDI_SUCCESS); 1220 1221 FAIL: 1222 pcieb_intr_fini(pcieb); 1223 return (DDI_FAILURE); 1224 } 1225 1226 static void 1227 pcieb_intr_fini(pcieb_devstate_t *pcieb) 1228 { 1229 int x; 1230 int count = pcieb->pcieb_intr_count; 1231 int flags = pcieb->pcieb_init_flags; 1232 1233 if ((flags & PCIEB_INIT_ENABLE) && 1234 (flags & PCIEB_INIT_BLOCK)) { 1235 (void) ddi_intr_block_disable(pcieb->pcieb_htable, count); 1236 flags &= ~(PCIEB_INIT_ENABLE | 1237 PCIEB_INIT_BLOCK); 1238 } 1239 1240 if (flags & PCIEB_INIT_MUTEX) 1241 mutex_destroy(&pcieb->pcieb_intr_mutex); 1242 1243 for (x = 0; x < count; x++) { 1244 if (flags & PCIEB_INIT_ENABLE) 1245 (void) ddi_intr_disable(pcieb->pcieb_htable[x]); 1246 1247 if (flags & PCIEB_INIT_HANDLER) 1248 (void) ddi_intr_remove_handler(pcieb->pcieb_htable[x]); 1249 1250 if (flags & PCIEB_INIT_ALLOC) 1251 (void) ddi_intr_free(pcieb->pcieb_htable[x]); 1252 } 1253 1254 flags &= ~(PCIEB_INIT_ENABLE | PCIEB_INIT_HANDLER | PCIEB_INIT_ALLOC | 1255 PCIEB_INIT_MUTEX); 1256 1257 if (flags & PCIEB_INIT_HTABLE) 1258 kmem_free(pcieb->pcieb_htable, pcieb->pcieb_htable_size); 1259 1260 flags &= ~PCIEB_INIT_HTABLE; 1261 1262 pcieb->pcieb_init_flags &= flags; 1263 } 1264 1265 /* 1266 * Checks if this device needs MSIs enabled or not. 1267 */ 1268 /*ARGSUSED*/ 1269 static int 1270 pcieb_msi_supported(dev_info_t *dip) 1271 { 1272 return ((pcieb_enable_msi && pcieb_plat_msi_supported(dip)) ? 1273 DDI_SUCCESS: DDI_FAILURE); 1274 } 1275 1276 /*ARGSUSED*/ 1277 static int 1278 pcieb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap, 1279 ddi_iblock_cookie_t *ibc) 1280 { 1281 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, 1282 ddi_get_instance(dip)); 1283 1284 ASSERT(ibc != NULL); 1285 *ibc = pcieb->pcieb_fm_ibc; 1286 1287 return (DEVI(dip)->devi_fmhdl->fh_cap | DDI_FM_ACCCHK_CAPABLE | 1288 DDI_FM_DMACHK_CAPABLE); 1289 } 1290 1291 static int 1292 pcieb_fm_init(pcieb_devstate_t *pcieb_p) 1293 { 1294 dev_info_t *dip = pcieb_p->pcieb_dip; 1295 int fm_cap = DDI_FM_EREPORT_CAPABLE; 1296 1297 /* 1298 * Request our capability level and get our parents capability 1299 * and ibc. 1300 */ 1301 ddi_fm_init(dip, &fm_cap, &pcieb_p->pcieb_fm_ibc); 1302 1303 return (DDI_SUCCESS); 1304 } 1305 1306 /* 1307 * Breakdown our FMA resources 1308 */ 1309 static void 1310 pcieb_fm_fini(pcieb_devstate_t *pcieb_p) 1311 { 1312 /* 1313 * Clean up allocated fm structures 1314 */ 1315 ddi_fm_fini(pcieb_p->pcieb_dip); 1316 } 1317 1318 static int 1319 pcieb_open(dev_t *devp, int flags, int otyp, cred_t *credp) 1320 { 1321 int inst = PCI_MINOR_NUM_TO_INSTANCE(getminor(*devp)); 1322 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, inst); 1323 int rv; 1324 1325 if (pcieb == NULL) 1326 return (ENXIO); 1327 1328 mutex_enter(&pcieb->pcieb_mutex); 1329 rv = pcie_open(pcieb->pcieb_dip, devp, flags, otyp, credp); 1330 mutex_exit(&pcieb->pcieb_mutex); 1331 1332 return (rv); 1333 } 1334 1335 static int 1336 pcieb_close(dev_t dev, int flags, int otyp, cred_t *credp) 1337 { 1338 int inst = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev)); 1339 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, inst); 1340 int rv; 1341 1342 if (pcieb == NULL) 1343 return (ENXIO); 1344 1345 mutex_enter(&pcieb->pcieb_mutex); 1346 rv = pcie_close(pcieb->pcieb_dip, dev, flags, otyp, credp); 1347 mutex_exit(&pcieb->pcieb_mutex); 1348 1349 return (rv); 1350 } 1351 1352 static int 1353 pcieb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 1354 int *rvalp) 1355 { 1356 int inst = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev)); 1357 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, inst); 1358 int rv; 1359 1360 if (pcieb == NULL) 1361 return (ENXIO); 1362 1363 /* To handle devctl and hotplug related ioctls */ 1364 rv = pcie_ioctl(pcieb->pcieb_dip, dev, cmd, arg, mode, credp, rvalp); 1365 1366 return (rv); 1367 } 1368 1369 /* 1370 * Common interrupt handler for hotplug, PME and errors. 1371 */ 1372 static uint_t 1373 pcieb_intr_handler(caddr_t arg1, caddr_t arg2) 1374 { 1375 pcieb_devstate_t *pcieb_p = (pcieb_devstate_t *)arg1; 1376 dev_info_t *dip = pcieb_p->pcieb_dip; 1377 ddi_fm_error_t derr; 1378 int sts = 0; 1379 int ret = DDI_INTR_UNCLAIMED; 1380 int isrc; 1381 1382 if (!(pcieb_p->pcieb_init_flags & PCIEB_INIT_ENABLE)) 1383 goto FAIL; 1384 1385 mutex_enter(&pcieb_p->pcieb_intr_mutex); 1386 isrc = pcieb_p->pcieb_isr_tab[(int)(uintptr_t)arg2]; 1387 mutex_exit(&pcieb_p->pcieb_intr_mutex); 1388 1389 PCIEB_DEBUG(DBG_INTR, dip, "Received intr number %d\n", 1390 (int)(uintptr_t)arg2); 1391 1392 if (isrc == PCIEB_INTR_SRC_UNKNOWN) 1393 goto FAIL; 1394 1395 if (isrc & PCIEB_INTR_SRC_HP) 1396 ret = pcie_intr(dip); 1397 1398 if (isrc & PCIEB_INTR_SRC_PME) 1399 ret = DDI_INTR_CLAIMED; 1400 1401 /* AER Error */ 1402 if (isrc & PCIEB_INTR_SRC_AER) { 1403 /* 1404 * If MSI is shared with PME/hotplug then check Root Error 1405 * Status Reg before claiming it. For now it's ok since 1406 * we know we get 2 MSIs. 1407 */ 1408 ret = DDI_INTR_CLAIMED; 1409 bzero(&derr, sizeof (ddi_fm_error_t)); 1410 derr.fme_version = DDI_FME_VERSION; 1411 mutex_enter(&pcieb_p->pcieb_peek_poke_mutex); 1412 mutex_enter(&pcieb_p->pcieb_err_mutex); 1413 1414 pf_eh_enter(PCIE_DIP2BUS(dip)); 1415 PCIE_ROOT_EH_SRC(PCIE_DIP2PFD(dip))->intr_type = 1416 PF_INTR_TYPE_AER; 1417 1418 if ((DEVI(dip)->devi_fmhdl->fh_cap) & DDI_FM_EREPORT_CAPABLE) 1419 sts = pf_scan_fabric(dip, &derr, NULL); 1420 pf_eh_exit(PCIE_DIP2BUS(dip)); 1421 1422 mutex_exit(&pcieb_p->pcieb_err_mutex); 1423 mutex_exit(&pcieb_p->pcieb_peek_poke_mutex); 1424 if (pcieb_die & sts) 1425 fm_panic("%s-%d: PCI(-X) Express Fatal Error. (0x%x)", 1426 ddi_driver_name(dip), ddi_get_instance(dip), sts); 1427 } 1428 FAIL: 1429 return (ret); 1430 } 1431 1432 /* 1433 * Some PCI-X to PCI-E bridges do not support full 64-bit addressing on the 1434 * PCI-X side of the bridge. We build a special version of this driver for 1435 * those bridges, which uses PCIEB_ADDR_LIMIT_LO and/or PCIEB_ADDR_LIMIT_HI 1436 * to define the range of values which the chip can handle. The code below 1437 * then clamps the DMA address range supplied by the driver, preventing the 1438 * PCI-E nexus driver from allocating any memory the bridge can't deal 1439 * with. 1440 */ 1441 static int 1442 pcieb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, 1443 ddi_dma_attr_t *attr_p, int (*waitfp)(caddr_t), caddr_t arg, 1444 ddi_dma_handle_t *handlep) 1445 { 1446 int ret; 1447 #ifdef PCIEB_BCM 1448 uint64_t lim; 1449 1450 /* 1451 * If the leaf device's limits are outside than what the Broadcom 1452 * bridge can handle, we need to clip the values passed up the chain. 1453 */ 1454 lim = attr_p->dma_attr_addr_lo; 1455 attr_p->dma_attr_addr_lo = MAX(lim, PCIEB_ADDR_LIMIT_LO); 1456 1457 lim = attr_p->dma_attr_addr_hi; 1458 attr_p->dma_attr_addr_hi = MIN(lim, PCIEB_ADDR_LIMIT_HI); 1459 1460 #endif /* PCIEB_BCM */ 1461 1462 /* 1463 * This is a software workaround to fix the Broadcom 5714/5715 PCIe-PCI 1464 * bridge prefetch bug. Intercept the DMA alloc handle request and set 1465 * PX_DMAI_FLAGS_MAP_BUFZONE flag in the handle. If this flag is set, 1466 * the px nexus driver will allocate an extra page & make it valid one, 1467 * for any DVMA request that comes from any of the Broadcom bridge child 1468 * devices. 1469 */ 1470 if ((ret = ddi_dma_allochdl(dip, rdip, attr_p, waitfp, arg, 1471 handlep)) == DDI_SUCCESS) { 1472 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)*handlep; 1473 #ifdef PCIEB_BCM 1474 mp->dmai_inuse |= PX_DMAI_FLAGS_MAP_BUFZONE; 1475 #endif /* PCIEB_BCM */ 1476 /* 1477 * For a given rdip, update mp->dmai_bdf with the bdf value 1478 * of pcieb's immediate child or secondary bus-id of the 1479 * PCIe2PCI bridge. 1480 */ 1481 mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip); 1482 } 1483 1484 return (ret); 1485 } 1486 1487 /* 1488 * FDVMA feature is not supported for any child device of Broadcom 5714/5715 1489 * PCIe-PCI bridge due to prefetch bug. Return failure immediately, so that 1490 * these drivers will switch to regular DVMA path. 1491 */ 1492 /*ARGSUSED*/ 1493 static int 1494 pcieb_dma_mctl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 1495 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 1496 uint_t cache_flags) 1497 { 1498 int ret; 1499 1500 #ifdef PCIEB_BCM 1501 if (cmd == DDI_DMA_RESERVE) 1502 return (DDI_FAILURE); 1503 #endif /* PCIEB_BCM */ 1504 1505 if (((ret = ddi_dma_mctl(dip, rdip, handle, cmd, offp, lenp, objp, 1506 cache_flags)) == DDI_SUCCESS) && (cmd == DDI_DMA_RESERVE)) { 1507 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)*objp; 1508 1509 /* 1510 * For a given rdip, update mp->dmai_bdf with the bdf value 1511 * of pcieb's immediate child or secondary bus-id of the 1512 * PCIe2PCI bridge. 1513 */ 1514 mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip); 1515 } 1516 1517 return (ret); 1518 } 1519 1520 static int 1521 pcieb_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 1522 ddi_intr_handle_impl_t *hdlp, void *result) 1523 { 1524 return (pcieb_plat_intr_ops(dip, rdip, intr_op, hdlp, result)); 1525 1526 } 1527 1528 /* 1529 * Power management related initialization specific to pcieb. 1530 * Called by pcieb_attach() 1531 */ 1532 static int 1533 pcieb_pwr_setup(dev_info_t *dip) 1534 { 1535 char *comp_array[5]; 1536 int i; 1537 ddi_acc_handle_t conf_hdl; 1538 uint16_t pmcap, cap_ptr; 1539 pcie_pwr_t *pwr_p; 1540 1541 /* Some platforms/devices may choose to disable PM */ 1542 if (pcieb_plat_pwr_disable(dip)) { 1543 (void) pcieb_pwr_disable(dip); 1544 return (DDI_SUCCESS); 1545 } 1546 1547 ASSERT(PCIE_PMINFO(dip)); 1548 pwr_p = PCIE_NEXUS_PMINFO(dip); 1549 ASSERT(pwr_p); 1550 1551 /* Code taken from pci_pci driver */ 1552 if (pci_config_setup(dip, &pwr_p->pwr_conf_hdl) != DDI_SUCCESS) { 1553 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: pci_config_setup " 1554 "failed\n"); 1555 return (DDI_FAILURE); 1556 } 1557 conf_hdl = pwr_p->pwr_conf_hdl; 1558 1559 /* 1560 * Walk the capabilities searching for a PM entry. 1561 */ 1562 if ((PCI_CAP_LOCATE(conf_hdl, PCI_CAP_ID_PM, &cap_ptr)) == 1563 DDI_FAILURE) { 1564 PCIEB_DEBUG(DBG_PWR, dip, "switch/bridge does not support PM. " 1565 " PCI PM data structure not found in config header\n"); 1566 pci_config_teardown(&conf_hdl); 1567 return (DDI_SUCCESS); 1568 } 1569 /* 1570 * Save offset to pmcsr for future references. 1571 */ 1572 pwr_p->pwr_pmcsr_offset = cap_ptr + PCI_PMCSR; 1573 pmcap = PCI_CAP_GET16(conf_hdl, NULL, cap_ptr, PCI_PMCAP); 1574 if (pmcap & PCI_PMCAP_D1) { 1575 PCIEB_DEBUG(DBG_PWR, dip, "D1 state supported\n"); 1576 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D1; 1577 } 1578 if (pmcap & PCI_PMCAP_D2) { 1579 PCIEB_DEBUG(DBG_PWR, dip, "D2 state supported\n"); 1580 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D2; 1581 } 1582 1583 i = 0; 1584 comp_array[i++] = "NAME=PCIe switch/bridge PM"; 1585 comp_array[i++] = "0=Power Off (D3)"; 1586 if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D2) 1587 comp_array[i++] = "1=D2"; 1588 if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D1) 1589 comp_array[i++] = "2=D1"; 1590 comp_array[i++] = "3=Full Power D0"; 1591 1592 /* 1593 * Create pm-components property, if it does not exist already. 1594 */ 1595 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1596 "pm-components", comp_array, i) != DDI_PROP_SUCCESS) { 1597 PCIEB_DEBUG(DBG_PWR, dip, "could not create pm-components " 1598 " prop\n"); 1599 pci_config_teardown(&conf_hdl); 1600 return (DDI_FAILURE); 1601 } 1602 return (pcieb_pwr_init_and_raise(dip, pwr_p)); 1603 } 1604 1605 /* 1606 * undo whatever is done in pcieb_pwr_setup. called by pcieb_detach() 1607 */ 1608 static void 1609 pcieb_pwr_teardown(dev_info_t *dip) 1610 { 1611 pcie_pwr_t *pwr_p; 1612 1613 if (!PCIE_PMINFO(dip) || !(pwr_p = PCIE_NEXUS_PMINFO(dip))) 1614 return; 1615 1616 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 1617 if (pwr_p->pwr_conf_hdl) 1618 pci_config_teardown(&pwr_p->pwr_conf_hdl); 1619 } 1620 1621 /* 1622 * Initializes the power level and raise the power to D0, if it is 1623 * not at D0. 1624 */ 1625 static int 1626 pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p) 1627 { 1628 uint16_t pmcsr; 1629 int ret = DDI_SUCCESS; 1630 1631 /* 1632 * Intialize our power level from PMCSR. The common code initializes 1633 * this to UNKNOWN. There is no guarantee that we will be at full 1634 * power at attach. If we are not at D0, raise the power. 1635 */ 1636 pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl, pwr_p->pwr_pmcsr_offset); 1637 pmcsr &= PCI_PMCSR_STATE_MASK; 1638 switch (pmcsr) { 1639 case PCI_PMCSR_D0: 1640 pwr_p->pwr_func_lvl = PM_LEVEL_D0; 1641 break; 1642 1643 case PCI_PMCSR_D1: 1644 pwr_p->pwr_func_lvl = PM_LEVEL_D1; 1645 break; 1646 1647 case PCI_PMCSR_D2: 1648 pwr_p->pwr_func_lvl = PM_LEVEL_D2; 1649 break; 1650 1651 case PCI_PMCSR_D3HOT: 1652 pwr_p->pwr_func_lvl = PM_LEVEL_D3; 1653 break; 1654 1655 default: 1656 break; 1657 } 1658 1659 /* Raise the power to D0. */ 1660 if (pwr_p->pwr_func_lvl != PM_LEVEL_D0 && 1661 ((ret = pm_raise_power(dip, 0, PM_LEVEL_D0)) != DDI_SUCCESS)) { 1662 /* 1663 * Read PMCSR again. If it is at D0, ignore the return 1664 * value from pm_raise_power. 1665 */ 1666 pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl, 1667 pwr_p->pwr_pmcsr_offset); 1668 if ((pmcsr & PCI_PMCSR_STATE_MASK) == PCI_PMCSR_D0) 1669 ret = DDI_SUCCESS; 1670 else { 1671 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: could not " 1672 "raise power to D0 \n"); 1673 } 1674 } 1675 if (ret == DDI_SUCCESS) 1676 pwr_p->pwr_func_lvl = PM_LEVEL_D0; 1677 return (ret); 1678 } 1679 1680 /* 1681 * Disable PM for x86 and PLX 8532 switch. 1682 * For PLX Transitioning one port on this switch to low power causes links 1683 * on other ports on the same station to die. Due to PLX erratum #34, we 1684 * can't allow the downstream device go to non-D0 state. 1685 */ 1686 static int 1687 pcieb_pwr_disable(dev_info_t *dip) 1688 { 1689 pcie_pwr_t *pwr_p; 1690 1691 ASSERT(PCIE_PMINFO(dip)); 1692 pwr_p = PCIE_NEXUS_PMINFO(dip); 1693 ASSERT(pwr_p); 1694 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_disable: disabling PM\n"); 1695 pwr_p->pwr_func_lvl = PM_LEVEL_D0; 1696 pwr_p->pwr_flags = PCIE_NO_CHILD_PM; 1697 return (DDI_SUCCESS); 1698 } 1699 1700 #ifdef DEBUG 1701 int pcieb_dbg_intr_print = 0; 1702 void 1703 pcieb_dbg(uint_t bit, dev_info_t *dip, char *fmt, ...) 1704 { 1705 va_list ap; 1706 1707 if (!pcieb_dbg_print) 1708 return; 1709 1710 if (dip) 1711 prom_printf("%s(%d): %s", ddi_driver_name(dip), 1712 ddi_get_instance(dip), pcieb_debug_sym[bit]); 1713 1714 va_start(ap, fmt); 1715 if (servicing_interrupt()) { 1716 if (pcieb_dbg_intr_print) 1717 prom_vprintf(fmt, ap); 1718 } else { 1719 prom_vprintf(fmt, ap); 1720 } 1721 1722 va_end(ap); 1723 } 1724 #endif 1725 1726 static void 1727 pcieb_id_props(pcieb_devstate_t *pcieb) 1728 { 1729 uint64_t serialid = 0; /* 40b field of EUI-64 serial no. register */ 1730 uint16_t cap_ptr; 1731 uint8_t fic = 0; /* 1 = first in chassis device */ 1732 pcie_bus_t *bus_p = PCIE_DIP2BUS(pcieb->pcieb_dip); 1733 ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl; 1734 1735 /* 1736 * Identify first in chassis. In the special case of a Sun branded 1737 * PLX device, it obviously is first in chassis. Otherwise, in the 1738 * general case, look for an Expansion Slot Register and check its 1739 * first-in-chassis bit. 1740 */ 1741 #ifdef PX_PLX 1742 uint16_t vendor_id = bus_p->bus_dev_ven_id & 0xFFFF; 1743 uint16_t device_id = bus_p->bus_dev_ven_id >> 16; 1744 if ((vendor_id == PXB_VENDOR_SUN) && 1745 ((device_id == PXB_DEVICE_PLX_PCIX) || 1746 (device_id == PXB_DEVICE_PLX_PCIE))) { 1747 fic = 1; 1748 } 1749 #endif /* PX_PLX */ 1750 if ((fic == 0) && ((PCI_CAP_LOCATE(config_handle, 1751 PCI_CAP_ID_SLOT_ID, &cap_ptr)) != DDI_FAILURE)) { 1752 uint8_t esr = PCI_CAP_GET8(config_handle, NULL, 1753 cap_ptr, PCI_CAP_ID_REGS_OFF); 1754 if (PCI_CAPSLOT_FIC(esr)) 1755 fic = 1; 1756 } 1757 1758 if ((PCI_CAP_LOCATE(config_handle, 1759 PCI_CAP_XCFG_SPC(PCIE_EXT_CAP_ID_SER), &cap_ptr)) != DDI_FAILURE) { 1760 /* Serialid can be 0 thru a full 40b number */ 1761 serialid = PCI_XCAP_GET32(config_handle, NULL, 1762 cap_ptr, PCIE_SER_SID_UPPER_DW); 1763 serialid <<= 32; 1764 serialid |= PCI_XCAP_GET32(config_handle, NULL, 1765 cap_ptr, PCIE_SER_SID_LOWER_DW); 1766 } 1767 1768 if (fic) 1769 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, pcieb->pcieb_dip, 1770 "first-in-chassis"); 1771 if (serialid) 1772 (void) ddi_prop_update_int64(DDI_DEV_T_NONE, pcieb->pcieb_dip, 1773 "serialid#", serialid); 1774 } 1775 1776 static void 1777 pcieb_create_ranges_prop(dev_info_t *dip, 1778 ddi_acc_handle_t config_handle) 1779 { 1780 uint32_t base, limit; 1781 ppb_ranges_t ranges[PCIEB_RANGE_LEN]; 1782 uint8_t io_base_lo, io_limit_lo; 1783 uint16_t io_base_hi, io_limit_hi, mem_base, mem_limit; 1784 int i = 0, rangelen = sizeof (ppb_ranges_t)/sizeof (int); 1785 1786 io_base_lo = pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW); 1787 io_limit_lo = pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW); 1788 io_base_hi = pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI); 1789 io_limit_hi = pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI); 1790 mem_base = pci_config_get16(config_handle, PCI_BCNF_MEM_BASE); 1791 mem_limit = pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT); 1792 1793 /* 1794 * Create ranges for IO space 1795 */ 1796 ranges[i].size_low = ranges[i].size_high = 0; 1797 ranges[i].parent_mid = ranges[i].child_mid = ranges[i].parent_high = 0; 1798 ranges[i].child_high = ranges[i].parent_high |= 1799 (PCI_REG_REL_M | PCI_ADDR_IO); 1800 base = PCIEB_16bit_IOADDR(io_base_lo); 1801 limit = PCIEB_16bit_IOADDR(io_limit_lo); 1802 1803 if ((io_base_lo & 0xf) == PCIEB_32BIT_IO) { 1804 base = PCIEB_LADDR(base, io_base_hi); 1805 } 1806 if ((io_limit_lo & 0xf) == PCIEB_32BIT_IO) { 1807 limit = PCIEB_LADDR(limit, io_limit_hi); 1808 } 1809 1810 if ((io_base_lo & PCIEB_32BIT_IO) && (io_limit_hi > 0)) { 1811 base = PCIEB_LADDR(base, io_base_hi); 1812 limit = PCIEB_LADDR(limit, io_limit_hi); 1813 } 1814 1815 /* 1816 * Create ranges for 32bit memory space 1817 */ 1818 base = PCIEB_32bit_MEMADDR(mem_base); 1819 limit = PCIEB_32bit_MEMADDR(mem_limit); 1820 ranges[i].size_low = ranges[i].size_high = 0; 1821 ranges[i].parent_mid = ranges[i].child_mid = ranges[i].parent_high = 0; 1822 ranges[i].child_high = ranges[i].parent_high |= 1823 (PCI_REG_REL_M | PCI_ADDR_MEM32); 1824 ranges[i].child_low = ranges[i].parent_low = base; 1825 if (limit >= base) { 1826 ranges[i].size_low = limit - base + PCIEB_MEMGRAIN; 1827 i++; 1828 } 1829 1830 if (i) { 1831 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "ranges", 1832 (int *)ranges, i * rangelen); 1833 } 1834 } 1835 1836 /* 1837 * For PCI and PCI-X devices including PCIe2PCI bridge, initialize 1838 * cache-line-size and latency timer configuration registers. 1839 */ 1840 void 1841 pcieb_set_pci_perf_parameters(dev_info_t *dip, ddi_acc_handle_t cfg_hdl) 1842 { 1843 uint_t n; 1844 1845 /* Initialize cache-line-size configuration register if needed */ 1846 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1847 "cache-line-size", 0) == 0) { 1848 pci_config_put8(cfg_hdl, PCI_CONF_CACHE_LINESZ, 1849 PCIEB_CACHE_LINE_SIZE); 1850 n = pci_config_get8(cfg_hdl, PCI_CONF_CACHE_LINESZ); 1851 if (n != 0) { 1852 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1853 "cache-line-size", n); 1854 } 1855 } 1856 1857 /* Initialize latency timer configuration registers if needed */ 1858 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1859 "latency-timer", 0) == 0) { 1860 uchar_t min_gnt, latency_timer; 1861 uchar_t header_type; 1862 1863 /* Determine the configuration header type */ 1864 header_type = pci_config_get8(cfg_hdl, PCI_CONF_HEADER); 1865 1866 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) { 1867 latency_timer = PCIEB_LATENCY_TIMER; 1868 pci_config_put8(cfg_hdl, PCI_BCNF_LATENCY_TIMER, 1869 latency_timer); 1870 } else { 1871 min_gnt = pci_config_get8(cfg_hdl, PCI_CONF_MIN_G); 1872 latency_timer = min_gnt * 8; 1873 } 1874 1875 pci_config_put8(cfg_hdl, PCI_CONF_LATENCY_TIMER, 1876 latency_timer); 1877 n = pci_config_get8(cfg_hdl, PCI_CONF_LATENCY_TIMER); 1878 if (n != 0) { 1879 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1880 "latency-timer", n); 1881 } 1882 } 1883 } 1884